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JP3801334B2 - Semiconductor device mounting substrate and manufacturing method thereof - Google Patents

Semiconductor device mounting substrate and manufacturing method thereof Download PDF

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Publication number
JP3801334B2
JP3801334B2 JP34594797A JP34594797A JP3801334B2 JP 3801334 B2 JP3801334 B2 JP 3801334B2 JP 34594797 A JP34594797 A JP 34594797A JP 34594797 A JP34594797 A JP 34594797A JP 3801334 B2 JP3801334 B2 JP 3801334B2
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Prior art keywords
semiconductor element
wire bonding
mounting substrate
gold plating
element mounting
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JP34594797A
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JPH11176863A (en
Inventor
清 長谷川
昭男 高橋
昭士 中祖
良明 坪松
順雄 岩崎
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Resonac Corp
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Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
Resonac Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/8501—Cleaning, e.g. oxide removal step, desmearing
    • H01L2224/85013—Plasma cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子搭載用基板とその製造方法に関する。
【０００２】
【従来の技術】
プリント配線板は、近年高密度化が進んでおり、配線板に直接半導体チップを実装するＣＯＢ、ＭＣＭ等の半導体素子搭載用基板の需要が伸びている。
これらのチップ実装基板とチップの接続方法は、主にワイヤボンディングであり、実装基板側のワイヤボンディング接続部には、ワイヤボンディング用端子が形成されている。
このワイヤボンディング用端子の従来の構造は、基板上に形成した銅等の金属端子上にニッケル、金の皮膜を順次形成したものであり、端子の製造方法は無電解ニッケルめっき、置換金めっきのめっき皮膜を順次形成する方法と無電解ニッケルめっき、置換金めっき、無電解金めっきのめっき皮膜を順次形成する方法がある。
前者の方法は後者の方法に比べて短時間、かつ低価格な方法であり、置換金めっきは数分間めっき液に浸漬して得られ、金めっき膜厚が薄く、めっき液中の金イオンの減少も少なく、金めっき液の管理が簡便である。
一方、無電解金めっきは数十分から１時間程度めっき液に浸漬して得られ、金めっき膜厚が厚いため金イオン、還元剤等の主成分の濃度減少が大きく、成分濃度管理、安定性の制御等の問題があり、かつ金めっき皮膜が厚膜化するために、コスト高になる。
半導体素子搭載用基板にとって重要な特性であるワイヤボンディング強度は、置換金めっきだけの場合は低強度であり、置換金めっき・無電解金めっきの場合は高強度である。
【０００３】
そこで、製造方法の簡便さと低コストの両立のために、置換金めっき後のプラズマ処理により、金めっき表面を清浄化してからワイヤボンディングを行う方法が提案されており、適用されている。
この方法は、金めっき皮膜を形成して、プラズマ処理を行ったワイヤボンディング用端子を有する半導体素子搭載用基板に、半導体素子を、接着剤を用いて接着するというものであり、このときの接着に要する熱処理条件が、１５０〜２５０℃、３０〜１８０分の範囲であり、この後に、ワイヤボンディングを行う。
【０００４】
【発明が解決しようとする課題】
ところが、従来の技術のうち、ワイヤボンディング前にプラズマ処理を行うワイヤボンディング用端子に、置換金めっき皮膜を有するものは、熱処理が全くないかまたは低温度、短時間の熱処理でワイヤボンディングを行った場合は、良好な結果であるが、熱処理条件が厳しくなるとワイヤボンディングの際のワイヤが端子に付着しないという課題があることが分かった。
近年、生産性を向上させるために熱処理条件は、益々厳しくなりつつあり、この課題を解決することが重要になってきた。
また、半導体素子搭載用基板の基材が、膜厚２００μｍ以下のフレキシブルな樹脂材料の場合には、熱処理後のワイヤボンディングは非常に困難であるという課題もあった。
【０００５】
本発明は、ワイヤボンディング性に優れた半導体素子搭載用基板とその製造方法を提供することを目的とする。
【０００６】
【課題を解決するための手段】
本発明の半導体素子搭載用基板は、最外層が置換金めっき皮膜であるワイヤボンディング用端子を有し、ワイヤボンディング前にプラズマ処理を行われる半導体素子搭載用基板において、置換金めっき皮膜の下地に無電解パラジウムめっき皮膜を有することを特徴とする。
【０００７】
無電解パラジウムめっき皮膜の膜厚は、０．１μｍ〜１μｍの範囲であることが好ましく、０．１μｍ未満では、熱処理後のワイヤボンディングのときに、ワイヤが端子に付着しないという現象が発生し、１μｍを超えると、効果の改善がなく、経済的でない。
【０００８】
置換金めっき皮膜の膜厚は、０．００３μｍ〜０．１μｍの範囲であることが好ましく、０．００３μｍ未満であると、熱処理後のワイヤボンディングのときに、ワイヤが端子に付着しないという現象が発生し、０．１μｍを超えると、効果の改善がなく、経済的でない。
【０００９】
半導体素子搭載用基板の基材には、膜厚が２００μｍ以下のフレキシブルな樹脂材料を用いることができる。
【００１０】
このような半導体素子搭載用基板は、金属からなるワイヤボンディング用端子上に、無電解パラジウムめっき、置換金めっき皮膜を順次形成する工程と、ワイヤボンディング前にプラズマ処理を行う工程を有する方法によって製造することができる。
【００１１】
【発明の実施の形態】
本発明の無電解パラジウムめっきは、めっき液中のパラジウムイオンの還元剤の働きによって、ニッケル表面にパラジウムを析出させるものであれば良く、特に限定しない。
【００１２】
本発明の置換金めっきは、下地のパラジウムと溶液中の金イオンとの置換反応によって、パラジウム表面に金皮膜を形成するものであれば良く、特に限定しない。
【００１３】
本発明の基材の種類は、セラミック、半導体、樹脂基板等があるが特に限定するものではない。樹脂基板については、材料面ではフェノール、エポキシ、ポリイミド等のものがあり、構造面ではリジットとフレキシブル等のものがあるが、特に限定するものではないが、半導体素子搭載用基板の基材が、膜厚が２００μｍ以下のフレキシブルな樹脂材料である場合に効果的である。
【００１４】
本発明のワイヤボンディング用端子は、特に限定するものではないが、銅、タングステン、モリブデン等が一般的である。また、金属端子上に銅、ニッケル等のめっきをした場合でも良く、無電解パラジウムめっき前のめっき等の表面処理に関しては、特に限定するものではない。
【００１５】
【実施例】
実施例１
厚さ１００μｍのポリイミドフィルムを用いたフレキシブルな銅張り積層板であるエスパネックス（新日鐵化学株式会社製、商品名）に穴をあけ、スルーホールめっきを行い、エッチングレジストを形成して、不要な箇所の銅をエッチング除去し、ソルダーレジストを形成した後の導体パターンの露出したワイヤボンディング用端子上に以下の処理を行う。

Figure 0003801334
【００１６】
実施例２
厚さ１００μｍのポリイミドフィルムを用いたフレキシブル銅張り積層板であるエスパネックス（新日鐵化学株式会社製、商品名）に穴をあけ、スルーホールめっきを行い、エッチングレジストを形成し、不要な銅をエッチング除去し、ソルダーレジストを形成した後に、導体パターンの露出したワイヤボンディング用端子上に以下の処理を行う。
Figure 0003801334
【００１７】
比較例１
厚さ１００μｍのポリイミドフィルムを用いたフレキシブル銅張り積層板であるエスパネックス（新日鐵化学株式会社製、商品名）に穴をあけ、スルーホールめっきを行い、エッチングレジストを形成し、不要な銅をエッチング除去し、ソルダーレジストを形成した後に、導体パターンの露出したワイヤボンディング用端子上に以下の処理を行う。
Figure 0003801334
【００１８】
実施例１、２と比較例１で得た半導体素子搭載用基板を１８０℃、２時間熱処理後ワイヤボンディングを行った結果、実施例１、２のパラジウム皮膜を形成したものは付着率１００％であり、密着強度は９〜１３ｇ、比較例１の従来のものは付着率９０％であり、未付着が１０％、また、熱処理なしでは実施例１、２と比較例１ともに付着率は１００％であり、密着強度は９〜１３ｇであった。このように本発明の方法は、熱処理後のワイヤボンディング特性に優れている。
【００１９】
【発明の効果】
以上に説明したように、本発明によってワイヤボンディング性に優れた半導体素子搭載用基板とその製造方法を提供することができる。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element mounting substrate and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, the density of printed wiring boards has been increasing, and the demand for substrates for mounting semiconductor elements such as COB and MCM that directly mount semiconductor chips on the wiring boards has increased.
These chip mounting substrates and chips are connected mainly by wire bonding, and wire bonding terminals are formed at the wire bonding connection portion on the mounting substrate side.
In the conventional structure of this wire bonding terminal, a nickel and gold film is sequentially formed on a metal terminal such as copper formed on a substrate, and the manufacturing method of the terminal is electroless nickel plating or displacement gold plating. There are a method of sequentially forming a plating film and a method of sequentially forming a plating film of electroless nickel plating, displacement gold plating, and electroless gold plating.
The former method is a method that is shorter and less expensive than the latter method. The displacement gold plating is obtained by immersing in a plating solution for several minutes, the gold plating film thickness is thin, and the gold ions in the plating solution are reduced. There is little decrease, and management of the gold plating solution is simple.
On the other hand, electroless gold plating is obtained by immersing in a plating solution for several tens of minutes to 1 hour. Since the gold plating film is thick, the concentration of main components such as gold ions and reducing agents is greatly reduced, and the component concentration is controlled and stable. There is a problem such as control of the property, and the gold plating film becomes thick, so that the cost becomes high.
The wire bonding strength, which is an important characteristic for a semiconductor element mounting substrate, is low in the case of substitution gold plating alone, and high in the case of substitution gold plating / electroless gold plating.
[0003]
Therefore, in order to achieve both simplicity of the manufacturing method and low cost, a method of performing wire bonding after cleaning the gold plating surface by plasma treatment after substitution gold plating has been proposed and applied.
In this method, a gold plating film is formed, and a semiconductor element is bonded to a semiconductor element mounting substrate having a wire bonding terminal subjected to plasma treatment using an adhesive. The heat treatment conditions required for this are 150 to 250 ° C. and 30 to 180 minutes, and then wire bonding is performed.
[0004]
[Problems to be solved by the invention]
However, among the conventional techniques, the wire bonding terminals that perform plasma treatment before wire bonding have a displacement gold plating film, and there is no heat treatment or wire bonding is performed at a low temperature for a short time. In this case, it was found that there was a problem that the wire during wire bonding did not adhere to the terminal when the heat treatment conditions became severe, although the result was good.
In recent years, heat treatment conditions have become increasingly severe in order to improve productivity, and it has become important to solve this problem.
In addition, when the base material of the semiconductor element mounting substrate is a flexible resin material having a film thickness of 200 μm or less, there is a problem that wire bonding after the heat treatment is very difficult.
[0005]
An object of this invention is to provide the board | substrate for semiconductor element mounting excellent in wire bonding property, and its manufacturing method.
[0006]
[Means for Solving the Problems]
The substrate for mounting a semiconductor element of the present invention has a wire bonding terminal whose outermost layer is a displacement gold plating film, and is a substrate for a semiconductor element mounting that is subjected to plasma treatment before wire bonding. It has an electroless palladium plating film.
[0007]
The film thickness of the electroless palladium plating film is preferably in the range of 0.1 μm to 1 μm, and if it is less than 0.1 μm, a phenomenon that the wire does not adhere to the terminal occurs during wire bonding after heat treatment, If it exceeds 1 μm, the effect is not improved and it is not economical.
[0008]
The thickness of the displacement gold plating film is preferably in the range of 0.003 μm to 0.1 μm, and if it is less than 0.003 μm, there is a phenomenon that the wire does not adhere to the terminal during wire bonding after the heat treatment. If it exceeds 0.1 μm, the effect is not improved and it is not economical.
[0009]
A flexible resin material having a film thickness of 200 μm or less can be used as the base material of the semiconductor element mounting substrate.
[0010]
Such a semiconductor element mounting substrate is manufactured by a method having a step of sequentially forming electroless palladium plating and a displacement gold plating film on a wire bonding terminal made of metal, and a step of performing a plasma treatment before wire bonding. can do.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
The electroless palladium plating of the present invention is not particularly limited as long as palladium is deposited on the nickel surface by the action of a reducing agent of palladium ions in the plating solution.
[0012]
The displacement gold plating of the present invention is not particularly limited as long as it forms a gold film on the palladium surface by a substitution reaction between the underlying palladium and the gold ions in the solution.
[0013]
The type of the base material of the present invention includes, but is not limited to, ceramic, semiconductor, resin substrate and the like. For resin substrates, there are materials such as phenol, epoxy, polyimide, etc., and there are structures such as rigid and flexible, but there is no particular limitation, but the base material of the substrate for mounting semiconductor elements is This is effective when the film thickness is a flexible resin material of 200 μm or less.
[0014]
The wire bonding terminal of the present invention is not particularly limited, but copper, tungsten, molybdenum and the like are common. Moreover, it may be a case where copper, nickel or the like is plated on the metal terminal, and the surface treatment such as plating before electroless palladium plating is not particularly limited.
[0015]
【Example】
Example 1
A hole is made in Espanex (trade name, manufactured by Nippon Steel Chemical Co., Ltd.), a flexible copper-clad laminate using a polyimide film with a thickness of 100 μm, and through-hole plating is performed to form an etching resist. The following processing is performed on the exposed wire bonding terminals of the conductor pattern after etching away copper at various locations and forming the solder resist.
Figure 0003801334
[0016]
Example 2
A hole is made in Espanex (trade name, manufactured by Nippon Steel Chemical Co., Ltd.), which is a flexible copper-clad laminate using a polyimide film with a thickness of 100 μm, through-hole plating is performed, an etching resist is formed, and unnecessary copper is formed. After etching and forming a solder resist, the following processing is performed on the wire bonding terminal where the conductor pattern is exposed.
Figure 0003801334
[0017]
Comparative Example 1
A hole is made in Espanex (trade name, manufactured by Nippon Steel Chemical Co., Ltd.), which is a flexible copper-clad laminate using a polyimide film with a thickness of 100 μm, through-hole plating is performed, an etching resist is formed, and unnecessary copper is formed. After etching and forming a solder resist, the following process is performed on the wire bonding terminal where the conductor pattern is exposed.
Figure 0003801334
[0018]
The semiconductor element mounting substrates obtained in Examples 1 and 2 and Comparative Example 1 were subjected to wire bonding after heat treatment at 180 ° C. for 2 hours. As a result, the palladium film of Examples 1 and 2 was formed with an adhesion rate of 100%. Yes, the adhesion strength is 9 to 13 g, the conventional one of Comparative Example 1 has an adhesion rate of 90%, the non-adhesion is 10%, and without heat treatment, the adhesion rate is 100% in both Examples 1 and 2 and Comparative Example 1. The adhesion strength was 9 to 13 g. Thus, the method of the present invention is excellent in wire bonding characteristics after heat treatment.
[0019]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a semiconductor element mounting substrate having excellent wire bonding properties and a method for manufacturing the same.

Claims (6)

最外層が置換金めっき皮膜であるワイヤボンディング用端子を有し、ワイヤボンディング前にプラズマ処理を行われる半導体素子搭載用基板において、置換金めっき皮膜の下地に無電解パラジウムめっき皮膜を有することを特徴とする半導体素子搭載用基板。The outermost layer has a wire bonding terminal which is a displacement gold plating film, and a substrate for mounting a semiconductor element in which plasma treatment is performed before wire bonding has an electroless palladium plating film on the base of the displacement gold plating film A substrate for mounting semiconductor elements. 無電解パラジウムめっき皮膜の膜厚が、０．１μｍ〜１μｍの範囲であることを特徴とする請求項１に記載の半導体素子搭載用基板。2. The semiconductor element mounting substrate according to claim 1, wherein a film thickness of the electroless palladium plating film is in a range of 0.1 μm to 1 μm. 置換金めっき皮膜の膜厚が、０．００３μｍ〜０．１μｍの範囲であることを特徴とする請求項１または２に記載の半導体素子搭載用基板。3. The semiconductor element mounting substrate according to claim 1, wherein a thickness of the displacement gold plating film is in a range of 0.003 μm to 0.1 μm. 半導体素子搭載用基板の基材が、膜厚が２００μｍ以下のフレキシブルな樹脂材料であることを特徴とする請求項１〜３のうちいずれかに記載の半導体素子搭載用基板。4. The semiconductor element mounting substrate according to claim 1, wherein the base material of the semiconductor element mounting substrate is a flexible resin material having a film thickness of 200 [mu] m or less. 金属からなるワイヤボンディング用端子上に、無電解パラジウムめっき、置換金めっき皮膜を順次形成する工程と、ワイヤボンディング前にプラズマ処理を行う工程を有することを特徴とする半導体素子搭載用基板の製造方法。A method of manufacturing a substrate for mounting a semiconductor element, comprising: a step of sequentially forming an electroless palladium plating and a displacement gold plating film on a wire bonding terminal made of metal; and a step of performing a plasma treatment before wire bonding . 半導体素子搭載用基板の基材に、膜厚が２００μｍ以下のフレキシブルな樹脂材料を用いることを特徴とする請求項５に記載の半導体素子搭載用基板の製造方法。6. The method of manufacturing a semiconductor element mounting substrate according to claim 5, wherein a flexible resin material having a film thickness of 200 [mu] m or less is used as a base material of the semiconductor element mounting substrate.
JP34594797A 1997-12-16 1997-12-16 Semiconductor device mounting substrate and manufacturing method thereof Expired - Fee Related JP3801334B2 (en)

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