JP3881004B2 - Liquid crystal electro-optical device - Google Patents

Description

The present invention relates to a liquid crystal electro-optical device, and more particularly to reducing power consumption for driving a liquid crystal electro-optical device.

FIG. 10 shows an example of the configuration of a conventional liquid crystal electro-optical device.
In FIG. 10, the liquid crystal electro-optical device 1001 is roughly divided into a signal line driver unit 1015.
A gate driver unit 1016 and an m × n pixel matrix (horizontal m rows, vertical n
(M × n matrix of columns, the same shall apply hereinafter) 1005.

The signal line driver unit 1015 includes a source-side shift register 1002 formed of complementary thin film transistors and a sample / hold circuit 1003 that samples a video signal formed of the complementary thin film transistors.

The gate driver unit 1016 includes a gate side shift register 1006 formed of a complementary thin film transistor and a buffer circuit 1 formed of the complementary thin film transistor.
007.

The pixel matrix portion 1005 is configured by arranging pixels 1004 in a matrix on a plane. FIG. 2 shows a circuit configuration of each pixel. Each pixel is formed in an N-channel thin film transistor 200), a liquid crystal element 204, and an auxiliary capacitor 206. A liquid crystal element 204 and an auxiliary capacitor 206 are connected to the drain electrode 203 of the N-channel thin film transistor 200,
A counter electrode 205 is connected to the opposite side connected to the drain of the liquid crystal element, and the electrode on the side opposite to the drain side of the auxiliary capacitor is grounded 207.

Each pixel 1004 in the pixel matrix 1005 in FIG. 10 has a (source signal line (or signal line) 1009 connected to the source electrode 201 in FIG. 2 and a gate signal line (or scanning line) 1008 in the gate electrode in FIG. 202.

The arrangement configuration of each pixel in the pixel matrix 1005 is shown below. In the vertical direction, m source signal lines 1009 connected to the signal line driver 1015 are wired, and the source electrodes 201 of the individual thin film transistors 200 of n pixels are connected to each source signal line. . On the other hand, n scanning lines 1008 are wired in the horizontal direction, and the gate signal lines 100 are connected.
8 is connected to a gate electrode 202 of a thin film transistor 200 connected to m pixels.

In the signal line driver unit 1015, a source signal (display signal) start signal line 1010) and a source line (signal line) side shift clock 1011 are connected to the source line (signal line) side shift register 1002 as external terminals, and an image is displayed. A data signal line 1012 is connected to the sample and hold circuit as an external terminal.

Next, the operation of the conventional example will be described.
First, an operation for displaying pixels connected to one gate signal line (scanning line) per line will be described.

Consider the i-th line from the top in the vertical direction (hereinafter the i-th line). When the gate signal line (scanning line) 1008 of the i-th line becomes “H”, the gate electrodes 202 of all the pixels 1004 of the i-th line become “H”, and all the thin film transistors 200 of the i-th line become the source 201.
-The drain 203 is conducted.

With the signal line start signal 1010 and the source-side shift clock 1011, the sample signal 1017 samples the video signal from the left end of the i-th line by the sample and hold circuit and sequentially writes the display signal to the pixels. Writing ends.

Next, an operation for displaying one screen (one frame) will be described.
In the vertical direction 1 by the gate start signal 1013 and the gate side shift clock 1014
The gate signal of the top line becomes “H”, and the signal is shifted downward by the gate side shift clock 1014. As described above, the display principle of one line, the gate signal of each line "
One screen (one frame) is displayed by being executed when H ".

FIG. 3 shows the polarity state of the display signal of one screen.
When displaying one screen, in order to prevent the occurrence of flicker during display, the source signal line 10
The source signal (display signal) supplied from 09 is inverted in polarity between adjacent lines, that is, the i-th line and the (i + 1) -th line as shown in FIG. This is called inversion.) In other words, the polarity of the display signal is inverted between the odd (2i-1) th line and the even (2i) th line.

This is performed by supplying an image data signal input from the image data signal line 1012 so that the signals are inverted in polarity between adjacent lines. Moreover, in order to prevent deterioration of the liquid crystal for one line, the polarity is reversed for each frame. In FIG.
The input image data in the conventional apparatus is shown.

The problem to be solved by the present invention is to reduce power consumption during operation of the liquid crystal electro-optical device. Therefore, what is the problem in the conventional example will be described next.

As shown by the configuration and operation in the conventional example, in order to prevent flicker of the liquid crystal electro-optical device,
The image data signal is input with the polarity reversed for each line. However, inverting the image data signal for each adjacent line increases the power consumption when driving the liquid crystal electro-optical device.

Next, it will be briefly described with reference to FIGS. 10 and 2 that the inversion of the image data signal for each adjacent line increases the power consumption when driving the liquid crystal electro-optical device.

2, Con is the pixel capacitance when the N-type thin film transistor 200 is conductive, and Coff is the pixel capacitance when the N-type thin film transistor 200 is non-conductive. In FIG. 10, one vertical direction of the liquid crystal electro-optical device 1001. The capacity of the source signal line 1009 is Cl, the voltage for driving one liquid crystal element is V (the positive polarity side is V / 2, the negative polarity side is V / 2), the line inversion number is Fl, and an m × n matrix. When having a configuration, one vertical source signal line 1009 is provided.
To drive
Wl = (Cl + Con + Coff × (n−1)) × V × V × Fl (A)
Power Wl is required.

Therefore, to display one screen,
W1 = m × Wl (B)
Power W1 is required.

The problem here is driving by performing line inversion. Line inversion number Fl is
Since it is almost equal to the number of lines, that is, the gate signal lines (scanning lines), a general display for display has a line inversion number of about 400 to 500 times per screen.

If the line inversion is stopped, the power consumption associated with the polarity inversion of the display signal is consumed only when the polarity inversion for each frame is performed to prevent the deterioration of the liquid crystal, that is, for each frame inversion (for one screen). Is done. When the frame inversion number is Ff, the total power Wa consumed during the display is
Wa = (Cl + Con + Coff * (n-1)) * V * V * m * Fl ... (C)
It becomes.

In particular, the power consumption for each screen is the case where Fl = 1 in equation (C). Therefore, if only frame inversion is performed, the power consumption in the pixel matrix portion can be reduced to the number of line inversions compared to the case of line inversion, and the power consumption can be drastically reduced. It becomes.

Further, power consumption not only in the pixel matrix portion but also in the sample / hold circuit in the driver circuit portion, the analog buffer circuit, and the like can be significantly reduced by stopping the line inversion. However, if the line inversion is stopped and only the frame inversion (the polarity inversion of the display signal for each frame) is performed, flicker occurs and the image quality is extremely deteriorated.

As another method of reducing the power consumption, there is a method of reducing the power consumption of the source side shift register 1001, the gate side shift register 1006, and the gate side buffer 1007. However, considering the whole power consumption, there are few methods. In the above formula (A), only the wiring capacity is considered, but there is a method of narrowing the wiring in order to reduce the wiring capacity.

However, if the wiring width is narrowed, the wiring resistance increases, and there are limitations due to the limitations of design rules. Further, if the wiring is made thicker in order to reduce the wiring resistance, the wiring capacity is increased, the pixel interval is further increased, and the aperture ratio is lowered, so that the image quality is affected. Of course, as can be readily understood from the formula (A), the simplest and most effective way to reduce the power consumption is to reduce the drive voltage V, but it is practical when considering good image quality and display speed. It ’s not the right way

An object of the present invention is to reduce power consumption while maintaining high image quality in a liquid crystal electro-optical device.

In order to solve the above problems, the present invention
An active matrix type liquid crystal in which a plurality of pixels having switching elements are arranged in a matrix, and scanning lines for controlling ON / OFF of the switching elements and signal lines for outputting display signals are connected to the respective pixels. An electro-optic device,
A plurality of signal line driver circuits for outputting a single polarity display signal to the signal line within one frame display period;
The polarity of the display signal output by at least one of the plurality of signal line driver circuits is:
Unlike the polarity of the display signal output by other signal line driver circuits,
The polarity is reversed every frame,
The pixel connected to one of the scanning lines is connected to the signal line connected to any of the plurality of signal line driver circuits;
It is characterized by.

The present invention also provides:
A plurality of pixels having switching elements are arranged in a matrix, and an active matrix type in which scanning lines for controlling ON / OFF of the switching elements and signal lines for outputting display signals are connected to each pixel. A liquid crystal electro-optical device,
Two signal line driver circuits for outputting a single polarity display signal to the signal line within one frame display period,
The polarities of the display signals output from the two signal line driver circuits are different from each other, and the polarities are inverted every frame,
The pixel connected to the even-numbered scanning line is connected to the signal line connected to one of the signal line driver circuits,
The signal line connected to the other of the signal line driver circuits is connected to the pixels connected to the odd-numbered scanning lines;
It is characterized by.

With the above configuration, in the liquid crystal electro-optical device, generation of flicker can be prevented and power consumption can be reduced. That is, in the present invention, a plurality of signal line driver circuits are used,
In each signal line driver circuit, the polarity of the output display signal is not inverted within one frame period. Instead, different signal line driver circuits are connected in adjacent lines.

For example, using two signal line driver circuits, with odd-numbered lines and even-numbered lines,
Each one is connected to a signal line driver circuit. Since the two signal line driver circuits have opposite polarities, in the pixel matrix, the polarities of the signals of adjacent lines are always opposite to each other, and the lines are substantially inverted. Therefore, occurrence of flicker can be prevented.

Further, in each signal line driver circuit, the polarity of the display signal does not change within one frame. Therefore, power consumption associated with line inversion does not occur, and power consumption can be reduced to one-hundredth of the conventional power consumption. Further, by inverting the polarities of the display signals of the two signal line driver circuits for each frame, the deterioration of the liquid crystal can be prevented.

The line connection to the signal line driver circuit may be connected to a different signal line driver circuit for each adjacent line, or may be connected to a different signal line driver circuit for each of a plurality of lines. In addition, pixels connected to different signal line driver circuits may be included in the same line. The number of signal line driver circuits is arbitrary.

In addition, by providing a selector circuit that distributes image data and control signals from outside to the image data input signal lines and control signal input lines of the respective signal line driver circuits, the external input signals can be changed in any way. Therefore, it is possible to drive the liquid crystal electro-optical device while preventing flickering and reducing power consumption.

A selector that distributes image data corresponding to any one of the signal line driver circuits to image data input signal lines of each signal line driver circuit in synchronization with the vertical synchronization signal among image data input from the outside. A circuit may be provided.

Further, a selector that selects a display signal from any one of the signal line driver circuits among the display signals output from the plurality of signal line driver circuits in synchronization with a vertical synchronization signal, and outputs the selected display signal to the signal lines. By providing the circuit, the number of signal lines can be made the same as that of the conventional device, and the pixel interval can be increased and the accompanying deterioration in image quality can be prevented.

In the present invention, the selector circuit and the driver circuit may be composed of complementary, P-type, or N-type thin film transistors. The pixel switching element can be complementary, P-type or N-type.
Type thin film transistor, MIM (metal-insulator-metal), NIN, PIP, PIN, N
A thin film diode such as IP may be used.

According to the present invention, in the liquid crystal electro-optical device, the occurrence of flicker can be prevented and the power consumption can be significantly reduced.

Next, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a configuration of a liquid crystal electro-optical device according to the first embodiment.
First, the configuration will be described. The first embodiment is an embodiment having an m × n pixel matrix. For convenience of drawing, it is assumed that m and n are particularly even numbers. However, there is no adverse effect of the present invention due to a combination of even and odd numbers of m and n.

As in the conventional example, the liquid crystal display device 101 is roughly divided into signal line driver units 102 and 103 formed of complementary, N-type, or P-type thin film transistors, and complementary or N-type.
A gate driver unit 107 composed of a p-type or p-type thin film transistor and a pixel matrix unit 104 are configured.

The pixel matrix unit 104 is configured by arranging pixels 115 in a matrix on a plane. The circuit diagram of the pixel 115 is the same as that of the conventional example (shown in FIG. 2), and includes a thin film transistor and a liquid crystal element auxiliary capacitor.

The gate driver unit 107 is formed by a shift register and a buffer circuit.
Further, a gate start signal input terminal 108 and a gate clock signal input terminal are connected to the input side of the gate driver unit 107, and n gate signal lines 117 are connected to the output side in the horizontal direction. Each gate signal line 117 is connected to gate electrodes of m pixels 115 in one line. However, the wiring configuration of the source line signal lines 105 and 106 is significantly different from the conventional example.

In this embodiment, the signal line driver section is divided into two, and the upper signal line driver 102 is divided.
(Hereinafter referred to as O driver) and a lower signal line driver 103 (hereinafter referred to as E driver). A start signal input terminal 110, a shift clock signal input terminal 111, and an image data input terminal 112 for driving odd-numbered lines are connected to the input side of the O driver 102, and the output side of the O driver 102 is connected to the output side of the O driver 102. , M source wirings 105 (hereinafter referred to as O source wirings 105) are connected. One O source line 105 has an odd number from the top (1
3,...) Are connected to the source electrodes of the thin film transistors of the n / 2 pixels 115 connected to the gate signal line 117.

On the other hand, a start signal input terminal 131, a shift clock signal input terminal 132, and an image data input terminal 133 for driving even-numbered lines are connected to the input side of the E driver 103, respectively. Are connected to m source wirings 106 (hereinafter referred to as E source wirings 106). One E source line 106 includes the source of the thin film transistor of the n / 2 pixels 115 connected to the even-numbered (2, 4,...) Signal lines 117 from the top of the horizontal gate signal lines 117. The electrode is connected.

Next, the operation of the first embodiment will be described. Since the operation for displaying one line is the same as in the conventional example, the description is omitted. First, an operation for displaying an arbitrary screen will be described.

First, a display signal is written to the first line, that is, the O source line 105. At this time, the display signal written to the first line is supplied from the O driver 102, and the polarity of the display signal at that time is, for example, (+).

Next, a display signal is written to the second line, that is, the E source line 106. At this time, the display signal written to the second line is supplied from the E driver 103, and the polarity of the display signal at that time is (-).

Similarly, when a display signal is written to an odd-numbered line, the display signal is the O driver 10.
2 and the polarities of the display signals supplied from the O driver 102 are all the same (
In this screen, (+)) is displayed.

Similarly, when the display signal is written to the even-numbered lines, the display signal is supplied to the E driver 10.
3 and the polarities of the display signals supplied from the E driver 103 are all the same (
(-)) On this screen. By operating in this way, all the n lines are written and the display of one screen is completed.

Next, the operation for each frame will be described.
In a certain frame, a display signal for writing an odd-numbered line (O source line 105) is supplied from the O driver 102, and the polarities of the display signals supplied from the O driver 102 at that time are all the same (-). is there. On the other hand, even-numbered lines (E source wiring 10
6) The display signal for writing is supplied from the E driver 103, and the polarities of the display signals supplied from the E driver 103 at that time are all the same (+). In the next frame, the polarity is reverse to that of the previous frame.

That is, the display signal for writing the odd-numbered line is supplied from the O driver 102, and the polarity of the display signal supplied from the O driver 102 at that time is the opposite polarity (-) to that of the previous frame. It works to be. On the other hand, the display signal when writing even-numbered lines is supplied from the E driver, and the polarity of the display signal supplied from the E driver at that time is all opposite to the polarity (+) of the previous frame. Repeat this operation.

Next, power consumption is considered.
According to the driving method of the first embodiment, the voltages applied to the pixels in the horizontal direction in one vertical source signal line are frame-inverted for each of the odd-numbered lines and the even-numbered lines.

Therefore, as in the conventional example, the power consumption is the pixel capacitance when the thin film transistor is in the conductive state.
If the pixel capacitance in the non-conductive state is Coff, the capacitance of the source signal lines 105 and 106 is Cl, the voltage for driving one liquid crystal element is V, and the frame inversion number is Ff, the power consumption Wo of the O driver,
The power consumption We of the E driver can be expressed as follows:

Wo = (Cl + Coff * ((n / 2) -1) + Con) * V * V * Ff
We = (Cl + Coff * ((n / 2) -1) + Con) * V * V * Ff
Therefore, the total power consumption W is
W = (Wo + We) x m
It becomes.

In this embodiment, since line inversion is not performed, there is no power consumption associated with line inversion, and power consumption can be greatly saved as compared with the conventional liquid crystal electro-optical device. In the display within one frame, the polarity of adjacent lines is inverted, so that the occurrence of flicker can be prevented.

In the first embodiment, in FIG. 1, the image data input terminal is an image data terminal that is input to an odd-numbered horizontal line, an image input terminal that is input to an even-numbered horizontal line, a start input terminal, and a shift that shifts it. Two clocks were required for each.

Since it is better that the number of input terminals is as small as possible, the configuration and operation in which the number of input terminals is the same as in the conventional example will be described in the second embodiment. FIG. 6 shows the configuration of the liquid crystal electro-optical device of the second embodiment. First, the configuration of the second embodiment will be described with reference to FIGS. 6, 1, and 10. In FIG. 6, 601-617.
Is the same as 101-117 in FIG.

Further, the input terminals 131 to 133 connected to the E driver unit 603 (103) which is a component of the first embodiment are eliminated. However, image data, source side start pulse, and source side input from a control signal input terminal (line) such as a source side start signal input terminal 616 and a source side shift clock input terminal 611 and an image data input terminal (line) 616, respectively. The selectors 641, 642, 643 and selector signal lines 651, 65 are formed by thin film transistors that distribute the shift clock to the O driver 602 and the E driver 603.
2 and 653 are added.

Next, a configuration example of the selectors 641, 642, 643 formed by thin film transistors will be described with reference to FIGS. FIG. 7 shows the configuration of the selector circuits 641 and 642, and FIG.
The configuration of the selector circuit 643 is shown in FIG.

Reference numerals 701 and 702 denote transmission gates composed of P-type thin film transistors and N-type thin film transistors, and reference numeral 703 denotes an inverter circuit formed of the thin film transistors.

The operation of the selector circuits 641 and 642 is such that when the selection signal line 705 is at "L" level, the data signal input from the data signal line 704 is output to 706, and when the selection signal line 705 is at "H" level, the data signal line The data signal input from 704 is output to 707.

Next, the configuration of the selector 643 will be described with reference to FIG.
In FIG. 8, selector circuits 801, 802, and 803 each have the same configuration as the selector circuit described with reference to FIG. 7, and thus the selector circuit 643 is composed of three selector circuits.

The selection signal line 805 is connected to the selection signal line 705 in FIG.
Is connected to the data signal line 704 in FIG. 7, the data output line 806 is connected to 706 in FIG. 7, and the data output line 807 is connected to 707 in FIG. This selector circuit 643 has 3
It is configured to select bit data.

This is because normal color image data is composed of three primary colors (red, green, and blue). Therefore, in the case of 1-bit image data such as monochrome, the selector circuit 6
34 may have the same configuration as the selector circuits 641 and 642, and the selector circuit 641,
Naturally, 642 and 643 can be substituted for the selector circuit 643 shown in FIG.

Next, the operation of the selector of FIG. 8 will be described.
When the selection signal line 805 is at "L" level, 3 is input from the 3-bit data signal line 804.
When the bit data signal is output to 806 and the selection signal line 805 is at “H” level, the data signal input from the 3-bit data signal line 804 is output to 807.

Returning to FIG. 6, the selection signals 651, 652, 653 of the selectors 641, 642, 643.
Are all connected to the gate side shift clock 609. Therefore, when the gate side shift clock is “H”, the pixels on the odd-numbered horizontal lines are driven, and the gate side shift clock is “
By setting so that even-numbered horizontal line pixels are driven at L ″, vertical synchronization can be achieved. If the drive waveform shown in FIG. 11 is input, the O driver 602 and the E driver A drive waveform similar to that of the first embodiment shown in FIGS. 4 and 5 is input to 603.

Therefore, the number of input terminals is made the same as in the conventional example, and the first embodiment uses the same input signal as in the conventional device.
The same operation can be performed. Therefore, power consumption can be greatly reduced and flicker can be prevented.

In the first and second embodiments, two different signal line driver circuits 102, 103, 602,
Since 603 is provided, two signal lines for transmitting a source signal to one vertical line are necessary. In these configurations, there is a possibility that the pixel interval in the horizontal direction becomes wide and the image in the display state becomes coarse, leading to deterioration in image quality. Example 3 shows an example in which measures against the above-described deterioration are taken.

FIG. 9 shows the configuration of the liquid crystal electro-optical device of Example 3.
The liquid crystal display device 901 includes signal line driver units 902 and 903 and a gate driver unit 907.
And a pixel matrix portion 904. The pixel matrix unit 904 includes pixels 91
5 are arranged in a matrix on a plane. The pixel 915 includes a thin film transistor and a liquid crystal element auxiliary capacitor.

A gate start signal input terminal 908 and a gate clock signal input terminal 909 are connected to the input side of the gate driver unit 907, and n gate signal lines 117 are connected to the output side in the horizontal direction. Each gate signal line 917 is connected to gate electrodes of m pixels 915.

A start signal input terminal 910, a shift clock signal input terminal 911, and an image data input terminal 912 for driving odd-numbered lines are connected to the input side of the O driver 902, respectively, while the input side of the E driver 903 Are connected to a start signal input terminal 931, a shift clock signal input terminal 932, and an image data input terminal 933 for driving even-numbered lines, respectively.

In the present embodiment, there are two configuration points different from the first embodiment.
The first point is that the same vertical signal lines driven by the O driver 902 and the E driver 903 are two source signal lines 105 and 106, one in each, in the first embodiment. , It is a single source signal line 905.

The second point is that the source signal line 90 prevents the different signals from colliding with the source signal line 905.
A transmission gate (hereinafter referred to as TG) that makes it possible to select 5 is provided between the driver and the pixel matrix, and an input terminal 941 for inputting a signal for turning ON / OFF the TG is transmitted to the TG. Inverter circuits 942 and 943 each including a thin film transistor are provided.

The TGs 947 and 948 are composed of thin film transistors, a transmission gate 947 inserted between the O driver 902 and the pixel matrix 904, and an E driver 90.
There is a TG 948 inserted between 3 and the pixel matrix 904.

Next, the operation will be described. First, the pixel matrix 904, the O driver 902, and the E driver 9
The operation of TG 947 and 948 inserted between 03 and -03 will be described.
When the input terminal 941 is at the “H” level, the signal line 944 on the P-type transistor side of the TG 947 is set to the “L” level by the inverter circuit 942 and the signal line 94 on the N-type transistor side.
6, the TG 947 is turned on, and the source signal from the O driver 902 is transmitted to the source signal line 905 and is transmitted to the pixel matrix.

On the other hand, since the connection of the signal line of the TG 948 between the E driver 903 and the pixel matrix 904 is opposite to that of the TG 947, the TG 948 is turned off and the source signal from the E driver 903 is not transmitted to the pixel matrix 904.

When the input terminal 941 is at the “L” level, the operations of the TGs 947 and 948 are opposite to the above operations, so that the source signal of the E driver 903 is transmitted to the pixel matrix 904 and the source signal of the O driver 902 is transmitted to the pixel matrix. Not transmitted.

Therefore, a signal synchronized with the gate clock input terminal 909 (that is, a vertical synchronization signal) is
If the signal is input from the TG control signal line, even if there is only one signal line for each vertical line, the display signal output from each driver from the O driver and E driver can have a single polarity.

In this embodiment, the transmission of display signals from two drivers is shared by one signal line, so that the power consumption due to the capacity of the signal line and the like is considerably larger than in the first and second embodiments. In the circuit, the power consumption accompanying the line inversion can be reduced, and the power consumption can be greatly reduced as compared with the conventional device.

In [Embodiment 1] to [Embodiment 3], the O driver and the E driver are divided vertically, but there is no particular restriction on the position. That is, the O driver / E driver may be provided on the same side of the same display device.

1 is a configuration diagram of a liquid crystal electro-optical device according to Embodiment 1. FIG. The circuit block diagram of each pixel. Explanatory drawing of the state of the polarity of the display signal of 1 screen. Explanatory drawing of the image data input into O driver. Explanatory drawing of the image data input into E driver. FIG. 6 is a configuration diagram of a liquid crystal electro-optical device according to a second embodiment. The block diagram of a selector circuit. The block diagram of a selector circuit. FIG. 6 is a configuration diagram of a liquid crystal electro-optical device according to a third embodiment. 1 is a configuration diagram of a conventional liquid crystal electro-optical device. Explanatory drawing of the input image data in the conventional apparatus.

Explanation of symbols

101 ... Liquid crystal electro-optical device 102 ... O driver 103 ... E driver 104 ... Pixel matrix,
105: odd line source signal line,
106: even line source signal line,
107 ... Gate driver 108 ... Gate start signal input terminal,
109 ... Gate clock input terminal,
110: Odd line start signal input terminal,
111... Odd line shift clock input terminal,
112... Odd line image data input terminal,
116... Pixel
117: Gate signal line 131: Even line start signal input terminal,
132: Even line shift clock input terminal,
133: Even line image data input terminal,
200 ... N-type thin film transistor 201 ... source signal line 202 ... gate signal line 203 ... drain signal line 204 ... liquid crystal cell 205 ... grounding 206 ... auxiliary capacitor 207 ... counter Electrode 601 ... Liquid crystal electro-optical device 602 ... O driver 603 ... E driver 604 ... Pixel matrix 605 ... Odd line source signal line 606 ... Even line source signal line 607 ... Gate Driver 608 ... Gate start signal input terminal 609 ... Gate clock input terminal 610 ... Gate side line start signal input terminal 611 ... Gate side line shift clock input terminal 612 ... Gate side line image data input Terminal 616 ... Pixel 617 ... Gate signal lines 641, 642, 643 ... selector circuit 45 ... Odd line start signal line 646 ... Odd line shift clock line 647 ... Odd line image data line 648 ... Even line start line 649 ... Even line shift clock line 650 ... Even line Image data lines 651, 652, 653 ... selector signal lines 701, 702 ... transmission gate 703 ... inverter circuit 704 ... data input line 705 ... selection signal lines 706, 707 ... data output Lines 801, 802, 803 ... Selector circuit 804 ... Data input line 805 ... Selection signal line 806, 807 ... Data output line 901 ... Liquid crystal electro-optical device 902 ... O driver 903 ..E driver 904... Pixel matrix 905... Odd line source signal line 906. Several line source signal line 907... Gate driver 908... Gate start signal input terminal 909... Gate clock input terminal 910... Odd line start signal input terminal 911. ..Odd line image data input terminal 916... Pixel 917... Gate signal line 931... Even line start signal input terminal 932... Even line shift clock input terminal 933. 941... TG control terminals 942, 943... Inverter circuits 944, 945, 946... Signal lines 947, 948... TG circuit 1001. ... Sample and hold circuit 1004 ... Pixel 1005 ... Image Element matrix 1006 ... Gate side shift register 1007 ... Gate driver 1008 ... Gate signal line 1009 ... Source signal line 1010 ... Source side start signal line terminal 1011 ... Source side shift clock input terminal 1012 ... Image data input terminal 1013 ... Gate side start signal line terminal 1014 ... Gate side shift clock input terminal 1015 ... Signal line driver unit 1016 ... Gate driver unit 1017 ... Sample signal line

Claims (7)

A plurality of pixels arranged in a matrix, a first signal line driver circuit, a second signal line driver circuit, a first selector circuit, a second selector circuit, and a third selector circuit Have
Each of the first selector circuit, the second selector circuit, and the third selector circuit has a first transmission gate, a second transmission gate, a selection signal line, and a data signal line,
The first transmission gate and the second transmission gate are turned off when one is turned on according to a signal input to the selection signal line,
In the first selector circuit, a source side start signal input to the data signal line is output to the first signal line driver circuit via the first transmission gate that is turned on. Divided into a source side start signal and a second source side start signal output to the second signal line driver circuit via the second transmission gate turned on;
In the second selector circuit, the source side shift clock input to the data signal line is output to the first signal line driver circuit via the first transmission gate turned on. Divided into a source-side shift clock and a second source-side shift clock output to the second signal line driver circuit via the second transmission gate turned on;
In the third selector circuit, the image data input to the data signal line is the first image data output to the first signal line driver circuit via the first transmission gate turned on. And the second image data output to the second signal line driver circuit via the second transmission gate turned on,
The first signal line driver circuit outputs the first image data to pixels in an odd row of the plurality of pixels;
The liquid crystal electro-optical device, wherein the second signal line driver circuit outputs the second image data to an even row of pixels among the plurality of pixels. A plurality of pixels arranged in a matrix, a first signal line driver circuit, a second signal line driver circuit, a first selector circuit, a second selector circuit, and a third selector circuit Have
Each of the first selector circuit, the second selector circuit, and the third selector circuit has a first transmission gate, a second transmission gate, a selection signal line, and a data signal line,
The first transmission gate and the second transmission gate are turned off when one is turned on according to a signal input to the selection signal line,
In the first selector circuit, a source side start signal input to the data signal line is output to the first signal line driver circuit via the first transmission gate that is turned on. Divided into a source side start signal and a second source side start signal output to the second signal line driver circuit via the second transmission gate turned on;
In the second selector circuit, the source side shift clock input to the data signal line is output to the first signal line driver circuit via the first transmission gate turned on. Divided into a source-side shift clock and a second source-side shift clock output to the second signal line driver circuit via the second transmission gate turned on;
In the third selector circuit, the image data input to the data signal line is the first image data output to the first signal line driver circuit via the first transmission gate turned on. And the second image data output to the second signal line driver circuit via the second transmission gate turned on,
In the first selector circuit, the second selector circuit, and the third selector circuit, the same signal is input to the selection signal line,
The first signal line driver circuit outputs first image data to pixels in an odd row among the plurality of pixels,
The liquid crystal electro-optical device, wherein the second signal line driver circuit outputs second image data to even rows of pixels among the plurality of pixels. A plurality of pixels arranged in a matrix, a first signal line driver circuit, a second signal line driver circuit, a gate driver, a first selector circuit, a second selector circuit, a third selector circuit, And a selector circuit,
Each of the first selector circuit, the second selector circuit, and the third selector circuit has a first transmission gate, a second transmission gate, a selection signal line, and a data signal line,
The gate driver outputs a signal to a gate signal line of an odd-numbered row pixel among the plurality of pixels or a gate signal line of an even-numbered row pixel among the plurality of pixels according to a gate side shift clock,
Wherein the first transmission gate second transmission gate, one the other when on is turned off in response to the input to the selection signal line the gate side shift clock,
In the first selector circuit, a source side start signal input to the data signal line is output to the first signal line driver circuit via the first transmission gate that is turned on. Divided into a source side start signal and a second source side start signal output to the second signal line driver circuit via the second transmission gate turned on;
In the second selector circuit, the source side shift clock input to the data signal line is output to the first signal line driver circuit via the first transmission gate turned on. Divided into a source-side shift clock and a second source-side shift clock output to the second signal line driver circuit via the second transmission gate turned on;
In the third selector circuit, the image data input to the data signal line is the first image data output to the first signal line driver circuit via the first transmission gate turned on. And the second image data output to the second signal line driver circuit via the second transmission gate turned on,
The first signal line driver circuit outputs the first image data to pixels in an odd row of the plurality of pixels;
The liquid crystal electro-optical device, wherein the second signal line driver circuit outputs the second image data to an even row of pixels among the plurality of pixels. In any one of Claims 1 thru | or 3 ,
The liquid crystal electro-optical device, wherein each of the first image data and the second image data has a single polarity within one frame display period and has a different polarity. In any one of Claims 1 thru | or 4 ,
The plurality of pixels each include a switching element, and the switching element is a complementary, P-type, or N-type thin film transistor. In any one of Claims 1 thru | or 4 ,
The plurality of pixels each include a switching element, and the switching element is a thin film diode. In claim 6 ,
2. The liquid crystal electro-optical device according to claim 1, wherein the thin film diode is an MIM type, NIN type, PIP type, PIN type, or NIP type.

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