JP3866011B2 - Driver and liquid crystal display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a driver, and further to a driver including an amplifier that obtains a driving voltage based on a first gradation voltage and a second gradation voltage, and is applied to, for example, a source driver for driving a TFT color liquid crystal panel. It relates to effective technology.
[0002]
[Prior art]
The liquid crystal panel includes a plurality of source lines and gate lines arranged so as to intersect therewith, and a liquid crystal cell is disposed at the intersection between the source lines and the gate lines. A driving device for driving such a liquid crystal panel is provided with a source driver for driving a source line and a gate driver for driving a gate line. The source driver outputs drive information in units of one line. At this time, the gate source driver drives a plurality of source lines in a time division manner.
[0003]
An example of a document describing a liquid crystal display is “Electronic Communication Handbook (page 472)” issued by Ohm Co., Ltd. in 1983.
[0004]
[Problems to be solved by the invention]
In the source driver, display data is decoded, a gradation voltage selection corresponding to the decoding result is selected, and the selected gradation voltage is buffered and then output to the liquid crystal panel. The gradation voltage is formed by being divided by a gradation voltage generating circuit formed by combining a plurality of resistors. For example, in the case of 64 gradations, a 64 level voltage is output as it is from the resistance ladder circuit.
[0005]
Usually, the image quality is improved with 256 gradations rather than 64 gradations. However, in the case of 256 gradations, a 256-level voltage must be output from the resistance ladder circuit, and the structure of the gradation voltage generation circuit and its periphery becomes complicated. In order to avoid this, an intermediate level gray scale voltage may be formed in the amplifier circuit by the averaging of the voltages.
[0006]
That is, according to the output of the decoder, two kinds of voltages are selected from a plurality of gradation voltages from the gradation voltage generation circuit, and the selected two kinds of voltages are added and averaged in the amplifier circuit. A voltage at an intermediate level between the two types of voltages is formed on the amplifier circuit side. By doing so, it is not necessary to form the gradation voltage corresponding to the intermediate level in the gradation voltage generation circuit, and the gradation voltage generation circuit and its periphery can be simplified correspondingly. In order to perform such averaging, the amplifier circuit includes a plurality of input terminals corresponding to the number of gradation voltages input to the amplifier circuit, and active elements such as MOS transistors corresponding to the input terminals. Provided. The inventors of the present invention examined the amplifier circuit in that case, and when there are a plurality of input terminals for the above-mentioned averaging, a level difference occurs in the source line drive voltage due to variations in threshold values of the corresponding MOS transistors. It was found that the image quality was degraded.
[0007]
An object of the present invention is to provide a technique for preventing image quality deterioration when performing addition averaging of gradation voltages.
[0008]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0010]
That is, a gradation voltage generating circuit for generating a plurality of gradation voltages having different voltage levels, and a plurality of gradation voltages from the gradation voltage generating circuit based on the decoding result obtained by decoding input data A decoder for selecting a first gradation voltage and a second gradation voltage corresponding to the first gradation voltage, and a drive voltage based on the first gradation voltage and the second gradation voltage corresponding to the decoder. In the amplifier, a first transistor to which an output signal of the amplifier is fed back, a second transistor differentially coupled to the first transistor, and the second transistor A third transistor connected in parallel to the transistor, the first gradation voltage is transmitted to the first transistor, and the second gradation voltage is transmitted to the second transistor. Switching between the first state to be transmitted and the second state in which the first gradation voltage is transmitted to the second transistor and the second gradation voltage is transmitted to the first transistor at a predetermined period. The switch circuit is provided.
[0011]
According to the above means, the switch circuit switches between the first state and the second state at a predetermined cycle. Thereby, in the amplifier, errors due to the difference in threshold value between the second transistor and the third transistor connected in parallel to the second transistor are averaged. To prevent degradation of image quality.
[0012]
At this time, in order to easily obtain the operation control signal of the switch circuit, the first state and the second state are determined based on the AC signal for AC driving of the liquid crystal and the internal clock signal. A circuit for generating a control signal capable of controlling switching may be provided.
[0013]
In the amplifier, a first transistor for forming a differential pair, a second transistor differentially coupled to the first transistor, a third transistor connected in parallel to the second transistor, and the first transistor A fourth transistor connected in parallel to one transistor, the first gradation voltage is transmitted to the second transistor, the second gradation voltage is transmitted to the third transistor, and the output voltage of the amplifier is The first state transmitted to one transistor and the fourth transistor, the first gradation voltage is transmitted to the third transistor, the second gradation voltage is transmitted to the second transistor, and the amplifier The second state in which the output voltage is transmitted to the first transistor and the fourth transistor, and the first gray scale voltage is transmitted to the first transistor. The second gradation voltage is transmitted to the fourth transistor, the output voltage of the amplifier is transmitted to the second transistor and the third transistor, and the first gradation voltage is the fourth transistor. A fourth state in which the second grayscale voltage is transmitted to the first transistor and the output voltage of the amplifier is transmitted to the second transistor and the third transistor at a predetermined cycle. A switching circuit is provided.
[0014]
According to the above means, the switch circuit switches the first state, the second state, the third state, and the fourth state at a predetermined cycle. As a result, the threshold difference is averaged among the first transistor, the second transistor, the third transistor, and the fourth transistor. This achieves prevention of deterioration in image quality when the gradation voltage is averaged.
[0015]
At this time, in order to easily obtain the operation control signal of the switch circuit, the first state, the second state, and the above are based on the AC signal for AC driving of the liquid crystal and the internal clock signal. A circuit for generating a control signal capable of controlling switching between the third state and the fourth state may be provided.
[0016]
A liquid crystal display including a display panel including a plurality of gate lines and a plurality of source lines arranged to intersect the plurality of gate lines, and a source line driver for driving the plurality of source lines. When the device is configured, the driver configured as described above can be used as the source driver.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 4 shows a configuration example of a liquid crystal display device according to the present invention.
[0018]
The liquid crystal display device 36 is not particularly limited, but the color liquid crystal panel 12, a plurality of gate drivers 10-1 to 10-3 for driving the gate lines of the color liquid crystal panel 12, and the data of the color liquid crystal panel 12. A plurality of source drivers 11-1 to 11-n for driving lines, a controller 14 for controlling the operation of the entire liquid crystal display device 36, and a liquid crystal driving power source for supplying power for driving the color liquid crystal panel 12 Circuit 13.
[0019]
The color liquid crystal panel 12 is not particularly limited, but is of a TFT type, and has a size of 1024 × 768 dots, a plurality of gate lines, a plurality of data lines arranged so as to intersect with the gate lines, a gate line and data. It includes an n-channel MOS transistor and a liquid crystal element arranged corresponding to the intersection of the lines. For example, as shown in FIG. 5, the gate electrodes of a plurality of n-channel MOS transistors 221 are coupled to corresponding gate lines g1 to g4, and the drain electrodes of the transistors 221 are coupled to corresponding data lines d1 to d3. The liquid crystal element 222 is coupled between the source electrode of the transistor 221 and the ground GND. In order to enable color display, three adjacent data lines d1, d2, and d3 correspond to RGB (red, green, and blue), and one pixel is formed by three elements corresponding to RGB. Is formed. According to the configuration example shown in FIG. 5, the gate lines g1 to g4 are selectively driven to a high level by the gate driver 10-1, and the data lines d1 and d2 are driven by the source driver 11-1 at a voltage level corresponding to the concentration. , D3 are driven, the corresponding n-channel MOS transistor 221 is turned on, and the capacitance of the corresponding liquid crystal element 222 is charged up. Thereafter, the output signal of the gate driver 10-1 is set to a low level, the n-channel MOS transistor 221 is turned off, and the voltage of the liquid crystal element 222 is held.
[0020]
Next, the source drivers 11-1 to 11-n will be described in detail. The plurality of source drivers 11-1 to 11-n have the same configuration. Therefore, in the following description, only the source driver 11-1 will be described in detail.
[0021]
FIG. 6 shows a configuration example of the source driver.
[0022]
As shown in FIG. 6, the source driver 11-1 includes a clock control circuit 80, latch circuits 92, 93, 94, a decoder 84, an amplifier circuit 85, a data inversion circuit 86, and a gradation voltage generation circuit 87. Are formed on one semiconductor substrate such as a single crystal silicon substrate.
[0023]
The clock control circuit 80 receives horizontal expansion signals LCHPA1 and LCHPA20 to 2, a data output horizontal clock signal CL1, a data transfer clock CL2, and a data transfer clock CL4 from the controller 14. The enable signals EIO0 to 2R * (* indicates low active or signal inversion) and EIO0 to 2L * are source driver enable signals. When this enable signal is asserted to a low level, Data capture is performed. M is an alternating signal. In order to prevent damage to the liquid crystal, the AC drive of the liquid crystal is controlled by the AC signal M. This AC signal M is captured at the timing of the rising edge of the data output horizontal clock signal CL1, and according to the polarity of the AC signal M, the positive polarity side (V0 to V4) and the negative polarity side (V5 to V9) side. Output voltage is selectively generated. Although not particularly limited, when the AC signal M is a logical value “0”, a positive liquid crystal application voltage is output from the odd output terminals (Y1, Y3,..., Y383) and the even output terminals (Y2, Y4, Y3). ..., Y384) outputs a negative polarity liquid crystal applied voltage. Further, when the alternating signal M is a logical value “1”, a negative liquid crystal applied voltage is output from the odd output terminals (Y1, Y3,..., Y383), and the even output terminals (Y2, Y4,..., Y384). ) Outputs a liquid crystal applied voltage having a positive polarity. SHL is a signal for instructing the shift direction of the display data, and the shift direction of the display data written to the first latch circuit is controlled via the latch address selector 81.
[0024]
Data D57 to D50, D47 to D40, D37 to D30, D27 to D20, D17 to D10, D07 to D00 transmitted from the controller 14 are transmitted to the first latch circuit 92 via the data inversion circuit 86. The inversion circuit 86 inverts the logic of the data according to the data inversion signal POL transmitted from the controller 14.
[0025]
The first latch circuit 92 holds the data from the data inverting circuit 86 under the control of the latch address selector 81. Horizontal enlargement and centering display are performed by address control when the output data of the data inverting circuit 86 is written to the first latch circuit 92 under the control of the latch address selector 81. A second latch circuit 93 capable of holding the output data of the first latch circuit 92 is provided at the subsequent stage of the first latch circuit 92, and the output data of the latch circuit 93 is disposed at the subsequent stage of the second latch circuit 93. Is provided. A third latch circuit 94 is provided. Each of the first latch circuit 92, the second latch circuit 93, and the third latch circuit 94 includes eight planes of data latches corresponding to 384 data lines. Eight planes are provided because, for example, 8-bit digital data is required for each terminal in order to output a voltage of 256 gradations from each source line drive terminal.
[0026]
Further, a decoder 84 for decoding the latch circuit output data is provided at the subsequent stage of the latch circuit 94. The output signal of the decoder 84 is buffered by the amplifier circuit 85 in the subsequent stage for driving the source line, and then output externally.
[0027]
Various levels of voltage required for decoding by the decoder 84 are generated by resistance-dividing various levels of the input voltages V0 to V9 in the gradation voltage generation circuit 87. For example, as shown in FIG. 7, various levels of input voltages V0 to V9 are taken in, and representative 256 ladder gradations and negative 256 gradations are displayed by a combination of ladder resistors R1 to R8 that are representatively shown. Obtain multiple levels of voltage. In the amplifier circuit 85, an intermediate level is formed by averaging two types of gradation voltages, so that the number of voltage output terminals in the gradation voltage generation circuit 87 is 160. , Two of them are selected, and the corresponding gradation voltage is transmitted to the amplifier circuit 85. For example, the output voltage level of 256 gradations is set in steps of 20 mV in the range of 5 to 10V.
[0028]
The amplifier circuit 85 includes 384 amplifiers 85-1 to 85-384 corresponding to the number of output terminals of the decoder 84. The amplifiers 85-1 to 85-384 have the same configuration.
[0029]
8 to 10 show driving examples of the color liquid crystal panel 12. Note that “+” and “−” indicate that the logic of the dots is inverted.
[0030]
FIG. 8 shows a state of dot inversion driving.
[0031]
As described above, the source drivers 11-1 to 11-n are capable of AC driving of the liquid crystal by switching the logic of the AC signal M. For example, by switching the AC signal M for each data output horizontal clock signal CL1, it is possible to perform dot inversion driving in which gradation voltages having different polarities are applied to adjacent dots.
[0032]
FIG. 9 shows the state of n-line inversion driving.
[0033]
When the logic of the alternating signal M is switched every n times of the data output horizontal clock signal CL1, n line inversion driving is performed for every dot in the horizontal direction and every n lines in the vertical direction as shown in FIG.
[0034]
FIG. 10 shows the state of frame inversion driving.
[0035]
By switching the logic of the AC signal M for each frame, it is possible to perform frame inversion driving for each dot in the horizontal direction and for each frame in the vertical direction as shown in FIG.
[0036]
FIG. 11 shows the relationship between data input, AC signal M and output level at the time of frame inversion.
[0037]
Each gradation voltage is selected from the next data output horizontal clock signal CL1 by selecting each of the positive and negative gradation voltages according to the logic level of the alternating signal M at the rising edge of the data output horizontal clock signal CL1. Voltage is output. HV indicates a voltage of 256 gradations on the positive electrode side, and LV indicates a voltage of 256 gradations on the negative electrode side. When the AC signal M is a logical value “0”, a positive liquid crystal application voltage HV is output from the odd output terminal, and a negative liquid crystal application voltage LV is output from the even output terminal. When the AC signal M is a logical value “1”, a negative liquid crystal application voltage is output from the odd output terminal, and a positive liquid crystal application voltage is output from the even output terminal.
[0038]
Next, the amplifier circuit 85 will be described in detail. Since the 384 amplifiers 85-1 to 85-384 included in the amplifier circuit 85 have the same configuration, one of them will be described in detail.
[0039]
FIG. 1 representatively shows a configuration example of an amplifier 85-1, which is one of a plurality of amplifiers in the amplifier circuit 85.
[0040]
A p-channel MOS transistor Q11 and a p-channel MOS transistor Q12 are differentially coupled, and a p-channel MOS transistor Q13 is differentially coupled to the p-channel MOS transistor Q12. The source electrodes of the p-channel MOS transistors Q11 to Q13 are coupled to the high potential side power supply Vdd via the p-channel MOS transistor Q1. An input signal from the input terminal IN1 or IN2 is applied to the gate electrodes of the p-channel MOS transistors Q12 and Q13 via the switch circuit 41. The switch circuit 41 transmits the grayscale voltage input from the input terminal IN1 to the gate electrode of the p-channel MOS transistor Q12 based on the offset cancel signals LCHPA1 and LCHPA2, and the grayscale voltage input from the input terminal IN2 is transmitted. The first state transmitted to the gate electrode of the p-channel MOS transistor Q13 and the gradation voltage input from the input terminal IN1 are transmitted to the gate electrode of the p-channel MOS transistor Q13 and input from the input terminal IN2. The second state in which the regulated voltage is transmitted to the gate electrode of the p-channel MOS transistor Q12 is switched at a predetermined cycle. As a result, the two gradation voltages inputted from the decoder 84 via the input terminals IN1 and IN2 are alternately transmitted to the p-channel MOS transistors Q12 and Q13.
[0041]
The gate electrodes of the p-channel MOS transistors Q11 to Q13 are coupled to the ground GND through n-channel MOS transistors Q3 and Q4 forming a current mirror type load. A series connection node of p-channel MOS transistors Q12 and Q13 and p-channel MOS transistor Q4 is coupled to the gate electrode of n-channel MOS transistor Q5 at the subsequent stage. The p-channel MOS transistor Q5 is even connected in series to the p-channel MOS transistor Q2, and the output terminal OUT of the amplifier 85-1 is drawn from the series connection node. A phase compensation capacitor C1 is provided between the drain electrode and the gate electrode of the p-channel MOS transistor Q5.
[0042]
A predetermined bias voltage VB is supplied to the gate electrodes of the p-channel MOS transistors Q1 and Q2, and the p-channel MOS transistors Q1 and Q2 function as constant current sources.
[0043]
FIG. 2 shows a configuration example of the switch circuit 41.
[0044]
As shown in FIG. 2, the switch circuit 41 includes p-channel MOS transistors Q21, Q22, Q23, and Q24. The p-channel type MOS transistor Q21 is arranged so that the signal path between the input terminal IN2 and the p-channel type MOS transistor Q13 can be interrupted, and the operation is controlled by the offset cancel signal LCHPA1. The p-channel MOS transistor Q22 is arranged so that the signal path between the input terminal IN1 and the p-channel MOS transistor Q13 can be interrupted, and the operation is controlled by the offset cancel signal LCHPA2. The offset cancel signals LCHPA1 and LCHPA2 are complementary level signals. For this reason, one of the p-channel MOS transistors Q21 and Q22 is selectively turned on. The p-channel MOS transistor Q23 is disposed so that the signal path between the input terminal IN2 and the p-channel MOS transistor Q12 can be interrupted, and the operation is controlled by the offset cancel signal LCHPA2. The p-channel MOS transistor Q24 is arranged so that the signal path between the input terminal IN1 and the p-channel MOS transistor Q12 can be interrupted, and the operation is controlled by the offset cancel signal LCHPA1. The offset cancel signals LCHPA1 and LCHPA2 are complementary signals, and therefore either one of the p-channel MOS transistors Q23 and Q24 is selectively turned on.
[0045]
FIG. 12 shows an offset cancel signal generating circuit for generating offset cancel signals LCHPA1 and LCHPA2 for controlling the operation of the switch circuit 41.
[0046]
The offset cancel signal generation circuit 121 shown in FIG. 12 is not particularly limited, but a flip-flop circuit FF1 for synchronizing the AC signal M with the data output horizontal clock signal CL1, and an output signal of the flip-flop circuit FF1. And a flip-flop circuit FF2 that divides the frequency by 1/2. The flip-flop circuit FF2 is arranged in the clock control circuit 80 shown in FIG. The flip-flop circuits FF1 and FF2 include a data terminal D, a clock pulse terminal CP, a non-inverting output terminal Q, and an inverting output terminal QN. The output signal from the non-inverting output terminal D of the flip-flop circuit FF1 is transmitted to the clock pulse terminal CP of the subsequent flip-flop circuit FF2. In the flip-flop circuit FF2, feedback is performed from the inverted output terminal QN to the data terminal D. Offset cancel signals LCHPA1 and LCHPA2 are obtained from the non-inverted output terminal Q of the flip-flop circuit FF2, and transmitted to the switch circuit 41.
[0047]
FIG. 13 shows the operation timing of the main part in the offset cancel signal generation circuit 121. As shown in FIG. 13, the offset cancel signals LCHPA1 and LCHPA2 are set to complementary levels. The AC signal M is inverted at a constant cycle such as a frame unit in order to prevent the liquid crystal panel from being burned. By using this, the offset cancellation for performing an offset operation every 4 frames, for example, is performed. The signals LCHPA1 and LCHPA2 can be easily generated.
[0048]
FIG. 3 shows an example of an offset cancel operation by the switch circuit 41.
[0049]
In the first frame, the input terminal IN1 and the gate electrode of the p-channel MOS transistor Q12 are coupled, and the input terminal IN2 and the gate electrode of the p-channel MOS transistor Q13 are coupled.
[0050]
In the second frame, the dot inversion of the first frame is performed based on the AC signal M. At this time, since there is no logical change in the offset cancel control signals LCHPA1 and LCHPA2, the connection state by the switch circuit 41 is the same as that in the first frame.
[0051]
In the third frame, the logic of the AC signal M has already been inverted, and the logic change of the offset cancel control signals LCHPA1 and LCHPA2 is changed, so that the state of the switch circuit 41 changes and the input terminals IN1 and p The gate electrode of channel type MOS transistor Q13 is coupled, and input terminal IN2 and the gate electrode of p channel type MOS transistor Q12 are coupled.
[0052]
In the fourth frame, dot inversion in the third frame is performed based on the alternating signal M. At this time, since there is no logical change in the offset cancel control signals LCHPA1 and LCHPA2, the connection state by the switch circuit 41 is the same as that in the third frame.
[0053]
One cycle is completed from the first frame to the fourth frame, and in this one cycle, the switching of the connection state by the switch circuit 41 is performed only once. By switching the connection state by the switch circuit 41 in this way, two kinds of gradation voltages taken in through the input terminals IN1 and IN2 are alternately taken into the p-channel MOS transistors Q12 and Q13. Therefore, each time the connection state is switched by the switch circuit 41, the level relationship of the threshold value of the MOS transistor viewed from the input terminals IN1 and IN2 is reversed, and the offset due to the variation in threshold value is reduced. Canceled.
[0054]
FIG. 14 shows a computer system to which the liquid crystal display device according to the present invention is applied.
[0055]
This computer system includes a microcomputer 31, a DRAM (dynamic random access memory) 32, an SRAM 33 (static random access memory), a ROM (read only memory) 34, peripherals via a system bus BUS. The device control unit 35, the liquid crystal display device, and the like are coupled so as to be able to exchange signals with each other, and perform predetermined data processing according to a predetermined program. The microcomputer 31 is the logical core of the system, and mainly handles addressing, information reading and writing, data operations, instruction sequences, interrupt acceptance, and information exchange between the storage device and the input / output device. It has functions such as activation, and is composed of an arithmetic control unit, a bus control unit, a memory access control unit and the like. The DRAM 32, SRAM 33, and ROM 34 are positioned as internal storage devices. The DRAM 32 is a main memory and is used as a work area for calculation and control in the microcomputer 31. The SRAM 33 is a secondary cache memory, and a part of the storage contents of the DRAM 32, which is the main memory, is stored, so that information required by the microcomputer 31 can be quickly taken in. . The ROM 34 stores a read-only program. The peripheral device control unit 35 performs operation control of the external storage device 38 such as a hard disk and information input control from the keyboard 39 or the like. The liquid crystal display device 36 displays an image.
[0056]
According to the above example, the following effects can be obtained.
[0057]
(1) One cycle is completed from the first frame to the fourth frame in the liquid crystal panel, and the switching of the connection state by the switch circuit 41 is performed only once in this one cycle. By switching the connection state by the switch circuit 41 in this way, two kinds of gradation voltages taken in through the input terminals IN1 and IN2 are alternately taken into the p-channel MOS transistors Q12 and Q13. Therefore, each time the switching state is switched by the switch circuit 41, the level relationship of the threshold value of the MOS transistor viewed from the input terminals IN1 and IN2 is reversed, and the offset caused by the variation in threshold value is canceled. The
[0058]
(2) In the color liquid crystal panel 12 and the liquid crystal display device 36 including the source driver having the effect (1), the image quality is improved because the offset due to the threshold value variation of the MOS transistor in the amplifier is canceled. .
[0059]
FIG. 15 shows another configuration example of the amplifier 85-1.
[0060]
The amplifier 85-1 shown in FIG. 15 is greatly different from that shown in FIG. 1 in that a p-channel MOS transistor Q14 connected in parallel to the p-channel MOS transistor Q11 is provided, and a switch circuit. A switch circuit 42 is provided in place of 41. In the switch circuit 42, the first gradation voltage is transmitted to the p-channel MOS transistor Q12, the second gradation voltage is transmitted to the p-channel MOS transistor Q13, and the output voltage of the amplifier 85-1 is The first state transmitted to the p-channel MOS transistor Q11 and the p-channel MOS transistor Q14, the first gradation voltage is transmitted to the p-channel MOS transistor Q13, and the second gradation voltage is transmitted to the p-channel MOS transistor Q13. The second state in which the output voltage of the amplifier 85-1 is transmitted to the p-channel MOS transistor Q12 and the output voltage of the amplifier 85-1 is transmitted to the p-channel MOS transistor Q11 and the p-channel MOS transistor Q14, and the first gradation voltage is The signal is transmitted to the p-channel MOS transistor Q11, and the 2 A third state in which the regulated voltage is transmitted to the p-channel MOS transistor Q14 and the output voltage of the amplifier 85-1 is transmitted to the p-channel MOS transistors Q12 and Q13, and the first gradation voltage is the The second gradation voltage is transmitted to the p-channel MOS transistor Q11, and the output voltage of the amplifier is applied to the p-channel MOS transistor Q12 and the p-channel MOS transistor Q13. It is provided for switching the transmitted fourth state at a predetermined cycle.
[0061]
FIG. 16 shows a configuration example of the switch circuit 42.
[0062]
As shown in FIG. 16, the switch circuit 42 includes p-channel MOS transistors Q31 to Q42.
[0063]
The p-channel MOS transistor Q31 is arranged so that the signal path between the input terminal IN1 and the p-channel MOS transistor Q11 can be interrupted, and the operation is controlled by the offset cancel signal LCHPB1. The p-channel MOS transistor Q32 is arranged so that the signal path between the input terminal IN2 and the p-channel MOS transistor Q11 can be interrupted, and the operation is controlled by the offset cancel signal LCHPB2. The p-channel type MOS transistor Q33 is arranged so that the signal path between the output terminal OUT of the amplifier 85-1 and the p-channel type MOS transistor Q11 can be interrupted, and the operation is controlled by the offset cancel signal CHOPA. The p-channel MOS transistor Q34 is arranged so that the signal path between the input terminal IN1 and the p-channel MOS transistor Q14 can be interrupted, and the operation is controlled by the offset cancel signal LCHPB2. The p-channel MOS transistor Q35 is disposed so that the signal path between the input terminal IN2 and the p-channel MOS transistor Q14 can be interrupted, and the operation is controlled by the offset cancel signal LCHPB1. The p-channel MOS transistor Q36 is arranged so that the signal path between the output terminal OUT of the amplifier 85-1 and the p-channel MOS transistor Q14 can be interrupted, and the operation is controlled by an offset cancel signal CHOPA. The p-channel MOS transistor Q42 is disposed so that the signal path between the input terminal IN1 and the p-channel MOS transistor Q12 can be interrupted, and the operation is controlled by an offset cancel signal LCHPA1. The p-channel MOS transistor Q41 is disposed so that the signal path between the input terminal IN2 and the p-channel MOS transistor Q12 can be interrupted, and the operation is controlled by the offset cancel signal LCHPA2.
[0064]
The p-channel type MOS transistor Q40 is arranged so that the signal path between the output terminal OUT of the amplifier 85-1 and the p-channel type MOS transistor Q12 can be interrupted, and the operation is controlled by the offset cancel signal CHOPB. The p-channel MOS transistor Q39 is disposed so that the signal path between the input terminal IN1 and the p-channel MOS transistor Q13 can be interrupted, and the operation is controlled by the offset cancel signal LCHPA2. The p-channel MOS transistor Q38 is arranged so that the signal path between the input terminal IN2 and the p-channel MOS transistor Q13 can be interrupted, and the operation is controlled by an offset cancel signal LCHPA1. The p-channel type MOS transistor Q37 is arranged so that the signal path between the output terminal OUT of the amplifier 85-1 and the p-channel type MOS transistor Q13 can be interrupted, and the operation is controlled by the offset cancel signal CHOPB.
[0065]
FIG. 17 shows an offset cancellation signal generation circuit 122 that generates offset cancellation signals LCHPA1, LCHPA2, CHOBP, LCHPB1, LCHPB2, and CHOPA for controlling the operation of the switch circuit.
[0066]
The offset cancel signal generation circuit 122 shown in FIG. 17 is not particularly limited, but a flip-flop circuit FF3 for synchronizing the alternating signal M with the data output horizontal clock signal CL1, and an output signal of the flip-flop circuit FF3. A flip-flop circuit FF4 that divides the frequency by 1/2, a flip-flop circuit FF5 that further divides the output signal of the flip-flop circuit FF5, inverters G1 to G5, G10 to G14, and NAND gates G6 to G9 are provided. Comprising. The output signal from the non-inverting output terminal Q of the flip-flop circuit FF4 is inverted by the inverter G1, whereby the offset cancel signal CHOPB is obtained. Then, this signal is further inverted by the inverter G10, whereby an offset cancel signal CHOPA is obtained. The output signal from the non-inverting output terminal Q of the flip-flop circuit FF4 is inverted by the inverter G2, and the output signal from the inverting output terminal QN of the flip-flop circuit FF4 is inverted by the inverter G3. The output signal from the non-inverting output terminal Q of the flip-flop circuit FF5 is inverted by the inverter G4, and the output signal from the inverting output terminal QN of the flip-flop circuit FF5 is inverted by the inverter G5. The NAND logic of the output signals of the inverters G2 and G4 is obtained by a NAND gate G6, and the output signal is inverted by a subsequent inverter G11 to obtain an offset cancel signal LCHPB1. The NAND logic of the output signals of the inverters G3 and G5 is obtained by the NAND gate G7, and the output signal is inverted by the inverter G12 at the subsequent stage to obtain the offset cancel signal LCHPA1. The NAND logic of the output signals of the inverters G3 and G4 is obtained by the NAND gate G8, and the output signal is inverted by the inverter G13 at the subsequent stage to obtain the offset cancel signal LCHPA2. The NAND logic of the output signals of the inverters G2 and G5 is obtained by the NAND gate G9, and the output signal is inverted by the inverter G14 in the subsequent stage to obtain the offset cancel signal LCHPB2.
[0067]
FIG. 18 shows the operation waveforms of the main part of the offset cancel signal generation circuit 122. As shown in FIG. 18, offset cancel signals LCHPA1, LCHPA2, CHOPB, LCHPB1, LCHPB2, and CHOPA are easily generated based on the AC signal M and the data output horizontal clock signal CL1. As described above, since the AC signal M is inverted at a constant cycle such as a frame unit, the offset cancel signal can be easily generated at a timing such as performing an offset cancel operation every 8 frames. can do.
[0068]
FIG. 19 shows an example of an offset cancel operation by the switch circuit 41.
[0069]
In the first frame, the input terminal IN1 and the gate electrode of the p-channel MOS transistor Q12 are coupled, the input terminal IN2 and the gate electrode of the p-channel MOS transistor Q13 are coupled, and the output terminal p-channel of the amplifier 85-1. The gate electrodes of type MOS transistors Q11 and Q14 are coupled.
[0070]
In the second frame, the dot inversion of the first frame is performed based on the AC signal M. At this time, since there is no logical change in the offset cancel signals LCHPA1, LCHPA2, CHOPB, LCHPB1, LCHPB2, and CHOPA, the connection state by the switch circuit 42 is the same as that in the first frame.
[0071]
In the third frame, the logic of the alternating signal M has already been inverted, and the offset cancel signal LCHPA2 is set to low level, whereby the input terminal IN1 is connected to the gate electrode of the p-channel MOS transistor Q13, Input terminal IN2 is coupled to the gate electrode of p-channel MOS transistor Q12.
[0072]
In the fourth frame, dot inversion in the third frame is performed based on the alternating signal M. At this time, since there is no logical change in the offset cancel signals LCHPA1, LCHPA2, CHOPB, LCHPB1, LCHPB2, and CHOPA, the connection state by the switch circuit 42 is the same as that in the third frame.
[0073]
In the fifth frame, when the offset cancel signal LCHPB1 is changed to the low level, the signal input terminal IN1 is coupled to the gate electrode of the p-channel MOS transistor Q11, and the input terminal IN2 is the gate of the p-channel MOS transistor Q14. Coupled to the electrode. At this time, the offset cancel signal CHOPB is set to the low level, so that the output terminal OUT of the amplifier 85-1 is coupled to the gate electrodes of the p-channel MOS transistors Q12 and Q13.
[0074]
In the sixth frame, the dot inversion in the fifth frame is performed based on the AC signal M. At this time, since there is no logical change in the offset cancel signals LCHPA1, LCHPA2, CHOPB, LCHPB1, LCHPB2, and CHOPA, the connection state by the switch circuit 42 is the same as that in the fifth frame.
[0075]
In the seventh frame, when the offset cancel signal LCHPB2 is changed to a low level, the input terminal IN1 is coupled to the gate electrode of the p-channel MOS transistor Q14, and the input signal IN2 is coupled to the gate electrode of the p-channel MOS transistor Q12. Combined with
[0076]
In the eighth frame, dot inversion in the seventh frame is performed based on the alternating signal M. At this time, since there is no logical change in the offset cancel signals LCHPA1, LCHPA2, CHOPB, LCHPB1, LCHPB2, and CHOPA, the connection state by the switch circuit 42 is the same as that in the seventh frame.
[0077]
Thus, in the configuration shown in FIG. 16, the first gradation voltage is transmitted to the p-channel MOS transistor Q12, the second gradation voltage is transmitted to the p-channel MOS transistor Q13, and the amplifier 85 -1 output voltage is transmitted to the p-channel MOS transistor Q11 and the p-channel MOS transistor Q14, and the first gradation voltage is transmitted to the p-channel MOS transistor Q13. A second state in which two gradation voltages are transmitted to the p-channel MOS transistor Q12, and an output voltage of the amplifier 85-1 is transmitted to the p-channel MOS transistor Q11 and the p-channel MOS transistor Q14; The first gradation voltage is the p-channel MOS transistor Q11. A third state in which the two gradation voltages are transmitted to the p-channel MOS transistor Q14, and an output voltage of the amplifier 85-1 is transmitted to the p-channel MOS transistors Q12 and Q13; One gradation voltage is transmitted to the p-channel MOS transistor Q14, the second gradation voltage is transmitted to the p-channel MOS transistor Q11, and the output voltage of the amplifier is the p-channel MOS transistor Q12 and the p-channel MOS transistor Q12. Since the fourth state transmitted to the channel type MOS transistor Q13 is switched at a predetermined cycle, offset cancellation caused by variations in threshold values of the p channel type MOS transistors Q11 to Q14 can be cancelled.
[0078]
Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.
[0079]
In the above description, the case where the invention made mainly by the present inventor is applied to the TFT type color liquid crystal panel, which is the field of use behind it, has been described. However, the present invention is not limited thereto, and various display panels are used. Can be widely applied to.
[0080]
The present invention can be applied on condition that an amplifier circuit for outputting a liquid crystal applied voltage is provided based on at least the first gradation voltage and the second gradation voltage corresponding to the first gradation voltage.
[0081]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0082]
That is, the switch circuit switches between the first state and the second state at a predetermined cycle, thereby causing a difference in threshold between the second transistor and the third transistor connected in parallel thereto. Therefore, it is possible to prevent image quality deterioration when performing averaging of gradation voltages.
[0083]
In addition, the first state, the second state, the third state, and the fourth state are switched at a predetermined cycle by the switch circuit, so that the first transistor, the second transistor, the third transistor, and the second state The difference in threshold value between the four transistors is averaged, so that it is possible to prevent the deterioration of the image quality when the averaging of gradation voltages is performed.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a configuration example of an amplifier in a liquid crystal driver according to the present invention.
FIG. 2 is a circuit diagram illustrating a configuration example of a switch circuit included in the amplifier.
FIG. 3 is an explanatory diagram of an example of an offset cancel operation by the switch circuit.
FIG. 4 is a block diagram illustrating a configuration example of a liquid crystal display device including the liquid crystal driver.
FIG. 5 is a circuit diagram of a configuration example of a color liquid crystal panel included in the liquid crystal display device.
FIG. 6 is a block diagram illustrating a configuration example of a source driver which is the liquid crystal driver.
FIG. 7 is an explanatory diagram of an output voltage of a gradation voltage generation circuit included in the source driver.
FIG. 8 is an explanatory diagram of a driving example of the color liquid crystal panel.
FIG. 9 is an explanatory diagram of a driving example of the color liquid crystal panel.
FIG. 10 is an explanatory diagram of a driving example of the color liquid crystal panel.
FIG. 11 is a diagram for explaining the relationship between data input, an alternating signal, and an output level at the time of frame inversion of the color liquid crystal panel.
FIG. 12 is a block diagram illustrating a configuration example of an offset cancel signal generation circuit included in the source driver.
FIG. 13 is an operation timing chart of the main part of the offset cancel signal generation circuit.
FIG. 14 is a block diagram illustrating a configuration example of a computer system as an application example of the liquid crystal display device.
FIG. 15 is a circuit diagram of another configuration example of the amplifier.
FIG. 16 is a circuit diagram showing another configuration example of the switch circuit.
FIG. 17 is a circuit diagram illustrating another configuration example of the offset cancel signal generation circuit.
18 is an operation timing chart of the main part of the offset cancel signal generation circuit shown in FIG.
FIG. 19 is an explanatory diagram of an example of an offset cancel operation by the switch circuit.
[Explanation of symbols]
12 LCD panel
11-1 to 11-n Source driver
10-1 to 10-3 Gate driver
36 Liquid crystal display device
41, 42 switch circuit
80 Clock control circuit
81 Latch address selector
84 Decoder
85 Amplifier circuit
85-1 to 85-384 amplifier
86 Data inversion circuit
87 Gradation voltage generation circuit
92 First latch circuit
93 Second latch circuit
94 Third latch circuit
121, 122 Offset cancel signal generation circuit
Q11, Q12, Q13, Q14 p-channel MOS transistors

Claims (5)

A gradation voltage generation circuit for generating a plurality of gradation voltages having different voltage levels;
A decoder for decoding input data and selecting a first gradation voltage and a corresponding second gradation voltage from a plurality of gradation voltages from the gradation voltage generating circuit based on the decoding result When,
A driver including an amplifier for obtaining a driving voltage based on the first gradation voltage and the second gradation voltage corresponding to the first gradation voltage;
The amplifier includes a first transistor for forming a differential pair;
A second transistor differentially coupled to the first transistor;
A third transistor connected in parallel to the second transistor;
The first state in which the first gradation voltage is transmitted to the second transistor, the second gradation voltage is transmitted to the third transistor, and the first gradation voltage is transmitted to the third transistor. And a switch circuit for switching a second state in which the second gradation voltage is transmitted to the second transistor at a predetermined cycle. 2. A circuit for generating a control signal capable of controlling switching between the first state and the second state based on an AC signal for AC driving of liquid crystal and an internal clock signal. Driver. A gradation voltage generation circuit for generating a plurality of gradation voltages having different voltage levels;
A decoder for decoding input data and selecting a first gradation voltage and a corresponding second gradation voltage from a plurality of gradation voltages from the gradation voltage generating circuit based on the decoding result When,
A driver including an amplifier for obtaining a driving voltage based on the first gradation voltage and the second gradation voltage corresponding to the first gradation voltage;
The amplifier includes a first transistor for forming a differential pair;
A second transistor differentially coupled to the first transistor;
A third transistor connected in parallel to the second transistor;
A fourth transistor connected in parallel to the first transistor;
The first gradation voltage is transmitted to the second transistor, the second gradation voltage is transmitted to the third transistor, and the output voltage of the amplifier is transmitted to the first transistor and the fourth transistor. 1 state, the first gradation voltage is transmitted to the third transistor, the second gradation voltage is transmitted to the second transistor, and the output voltage of the amplifier is the first transistor and the fourth transistor. And the second grayscale voltage is transmitted to the first transistor, the second grayscale voltage is transmitted to the fourth transistor, and the output voltage of the amplifier is the second transistor and The third state transmitted to the third transistor, the first gradation voltage is transmitted to the fourth transistor, and the second gradation voltage is transmitted to the first transistor. By the driver, characterized in that it comprises a switch circuit for switching a fourth state in which the output voltage of the amplifier is transmitted to the second transistor and the third transistor at a predetermined period. Control capable of controlling switching between the first state, the second state, the third state, and the fourth state based on an AC signal for AC driving of the liquid crystal and an internal clock signal 4. The driver of claim 3, comprising a circuit for generating a signal. In a liquid crystal display device including a display panel including a plurality of gate lines and a plurality of source lines arranged to intersect the plurality of gate lines, and a source driver for driving the plurality of source lines,
5. A liquid crystal display device comprising the driver according to claim 1 as the source driver.

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