JP3725230B2 - LSI function design support device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus for supporting functional design of an LSI (Large Scale Integrated Circuit), and more specifically, hardware description data in a hardware description language of a register transfer level from data describing an LSI operation in a state transition diagram format. The present invention relates to an LSI function design support apparatus having a function of generating a function.
[0002]
[Prior art]
In recent years, a top-down design method using a hardware description language (hereinafter referred to as “HDL”) has been adopted in LSI development. In other words, hardware description data in which the LSI to be designed is described in HDL at the register transfer level is created at the functional design stage, and gate level circuit data is generated from this hardware description data by a logic synthesis tool. ing.
[0003]
In such a top-down design method, in order to facilitate the creation of hardware description data by HDL at the register transfer level, the designer operates the LSI to be designed from the graphic terminal in a format based on the state transition diagram. An LSI function design support apparatus for inputting data (design information) to be shown has been proposed. In this apparatus, hardware description data by register transfer level HDL is automatically generated from the input data in the state transition diagram format. For example, in Japanese Patent Application Laid-Open No. 3-41567, state transition diagrams and function diagrams are registered in a database interactively as CAD (Computer Aided Design) data, converted from this database into a corresponding hardware description language, and output as a file. A state transition diagram design system is disclosed. According to this, the user interface in the digital circuit design system is improved, and it is possible to improve the design efficiency.
[0004]
When hardware description data is generated by the LSI function design support apparatus, the quality and performance of a circuit after logic synthesis differs depending on the description style. For this reason, a hardware description that enables high-quality logic synthesis according to the purpose is desired.
[0005]
For example, when importance is attached to the reduction of the circuit scale after logic synthesis, a hardware description that can use a logic synthesis tool based on a logic compression algorithm with a high compression rate is desired. In addition, when it is expected that it takes time to debug and test a circuit after manufacturing, a hardware description that facilitates debugging and testing is desired. By the way, the flip-flop for storing the state code indicating each state represented by the above-described state transition diagram is usually composed of a plurality of and is synchronized with the same clock. Therefore, in order to realize a stable circuit that does not cause clock skew, a hardware description is desired in which a plurality of flip-flops that store status codes are realized as one circuit block. Also, with the recent spread of portable devices, it is important to reduce the power consumption of LSIs. For LSIs used in portable devices, priority is given to reducing power consumption over operating speed, and hardware that supports this A hardware description is desired.
[0006]
[Problems to be solved by the invention]
However, in the conventional LSI function design support apparatus, the above points are not taken into consideration in the generation of hardware description data. That is, the state transition diagram data (design information) input by the designer is a finite state machine (hereinafter referred to as “FSM”) and the register operation description in a predetermined state (data path description). Can be used for hardware description data generated from this data by a conventional LSI design support device based on a FSM-dedicated logical compression algorithm with a high compression ratio. There wasn't.
[0007]
Also, the conventional LSI function design support device facilitates debugging of the circuit after logic synthesis, timing analysis, and power consumption when generating the hardware description data at the register transfer level from the input data in the state transition diagram format. There was nothing to consider about the reduction. Further, there has been no LSI function design support device that generates hardware description data for a plurality of flip-flops synchronized with the same clock so that they are realized as one circuit block after logic synthesis.
[0008]
Therefore, the present invention makes it possible to perform high-quality logic synthesis according to various purposes such as reduction in circuit scale (chip area), ease of debugging, reduction of power consumption, stabilization of circuit operation, and the like. An object of the present invention is to provide an LSI function design support device capable of generating simple hardware description data from input data in a state transition diagram format.
[0013]
[Means for Solving the Problems]
According to the present invention 1 In the LSI functional design support device,
Input data generation means for generating state transition diagram data describing the operation of the LSI to be designed based on a state transition diagram capable of hierarchical description of state transitions based on an input operation by an operator;
State determination means for determining whether each state of the LSI represented by the state transition diagram data is a macro state which is a state having a lower state;
Flag description generating means for generating description data of a flag signal having a value of “1” when the LSI is in the macro state and a value of “0” when not in the macro state;
A gate that generates description data of a gate that supplies a transition clock of a lower state in the macro state when the flag signal is “1” and stops supply of the transition clock when the flag signal is “0” A description generation means;
Hardware in which the LSI for which the supply and stop of the transition clock is controlled by the flag signal is described in a register description level hardware description language using the description data generated by the flag description generation means and the gate description generation means Hardware description generation means for generating description data;
It is characterized by having.
[0014]
According to the present invention 2 In the LSI functional design support apparatus, 1 LSI function design support device
Instead of the gate description generating means, a clock for register operation assigned to a lower state of the macro state is supplied when the flag signal is "1", and when the flag signal is "0" Gate description generating means for generating description data of a gate for stopping the supply of the clock;
The hardware description generation means uses the description data generated by the flag description generation means and the gate description generation means to transfer the LSI, whose supply and stop of the clock are controlled by the flag signal, to a register transfer level hardware. Hardware description data described in a hardware description language is generated.
[0020]
【The invention's effect】
According to the present invention 1 According to the LSI functional design support apparatus, the LSI obtained based on the generated hardware description data supplies a transition clock of a lower state of the macro state by a flag signal indicating whether the state is the macro state or not. And the stop is controlled. As a result, the supply of the transition clock to the status register that stores the status code in the lower level of the macro state is stopped during the period in which the lower level status transition does not occur (during the period in which the status is other than the macro status). LSI power consumption is reduced.
[0021]
According to the present invention 2 According to the LSI functional design support apparatus, the LSI obtained based on the generated hardware description data is assigned to a lower level state of the macro state by a flag signal indicating whether the state is the macro state or not. The clock supply and stop for register operation are controlled. As a result, for the register operation assigned to the lower state of the macro state, the clock supply is stopped during a period in which the lower state transition does not occur (during a period other than the macro state). Therefore, the power consumption of the LSI is reduced.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
<Embodiment 1>
Hereinafter, an LSI functional design support apparatus according to an embodiment of the present invention (hereinafter referred to as “Embodiment 1”) will be described. This LSI function design support apparatus is realized by a general-purpose computer and a computer program executed thereby.
[0024]
FIG. 1 is a schematic block diagram showing the configuration of a computer that is hardware of the LSI functional design support apparatus of this embodiment. The hardware of this LSI functional design support apparatus includes a main body 10 including a CPU 16 and a memory 18, a hard disk device 12 that stores expanded transition diagram data and library data described later, an input device 14 such as a keyboard and a mouse, And a display device 20 such as a CRT display. In such a configuration, a predetermined program is stored in the memory 18 of the main body 10, and various functions for supporting the functional design of the LSI are realized by the CPU 16 operating based on the program.
[0025]
FIG. 2 is a flowchart showing processing in the LSI function design support apparatus. In the design by the LSI function design support device, first, in step S10, the operator who is the designer operates the input device 14 such as a keyboard and a mouse while looking at the display device 20, so that the digital which is the LSI to be designed. Input information indicating the operation of the circuit. In this LSI functional design support device, information indicating the operation of the LSI to be designed can be input in the form of a state transition diagram. At this time, register operations such as arithmetic processing in an arbitrary state shown in the state transition diagram Can be described. Specifically, an assignment statement or an arithmetic expression indicating the operation of the data path portion in the state shown in the state transition diagram is described in HDL. Hereinafter, a state transition diagram expanded by adding a register function description function or the like is referred to as an “extended state transition diagram” (in the extended state transition diagram described later, a function of hierarchical description of state transition is also added. ). As an extended state transition diagram for LSI design information input, for example, an “open chart” can be used (Takamitsu Yamada, Takashi Yasui, Yoshiharu Oka, “Designing a sorting circuit using a function entry tool” ”, CQ Publisher, Magazine“ Interface ”, March 1995, pp. 160-166).
[0026]
FIG. 4 is a diagram illustrating an example of an extended state transition diagram, which is design information input by the LSI functional design support apparatus, together with input / output definitions of the LSI to be designed. In FIG. 4, “C = A + B” is written beside the circle indicating the state S1, and this indicates an operation executed in the state S1, that is, a register operation. When the operator inputs the design information shown by the extended state transition diagram, design data having a data structure as shown in FIG. 5 is generated in the memory 18 and stored in the hard disk device 12 as extended state transition diagram data. Is done.
[0027]
When the design information is thus input and the extended state transition diagram data is generated, a predetermined check is performed on the extended state transition diagram data in step S12. That is, a check on a state transition diagram such as whether a state transition destination exists (state transition diagram check), a grammar check of a hardware description describing a register operation (HDL grammar check), and the possibility of logic synthesis Perform a check (composite check).
[0028]
If an error is found as a result of the above various checks, the process returns to step S10 (step S14), and steps S10 to S14 are repeatedly executed until there is no error. If there is no error, the process proceeds to step S16, and the operator designates the HDL generation method by a predetermined operation. In other words, when generating hardware description data, prioritize whether to prioritize logic synthesis efficiency (LSI chip area reduction), prioritize reduction of power consumption, or prioritize debugging. specify.
[0029]
When the HDL generation method is specified, in step S18, hardware description data is generated from the extended state transition diagram data (hereinafter, the process of generating the hardware description data is referred to as “HDL generation process”), and the LSI function design is performed. The process of the support device is terminated. The hardware description data obtained in this way is a description of the LSI to be designed at the register transfer level, and this hardware description data corresponds to the LSI manufacturing technology using an existing logic synthesis tool. Logic circuit data is generated using macros in the technology library.
[0030]
FIG. 3 is a flowchart showing a subroutine for executing the HDL generation process in step S18 of FIG. The LSI functional design support device generates register transfer level hardware description data from the above extended state transition diagram data by the processing shown in this flowchart. Hereinafter, the HDL generation process will be described with reference to FIG. In this embodiment, Verilog-HDL is used as a hardware description language (HDL).
[0031]
In the HDL generation process, first, in step S20, the extended state transition diagram data stored in the hard disk device 12 is read into the memory 18. In step S22, an input signal to the FSM indicated by the read extended state transition diagram data is input to the input port, and an output signal from the FSM and a signal indicating the current state (hereinafter referred to as "state signal") are obtained. One hierarchical block such as an output port is set, and hardware description data in which this is described as a hierarchical block that operates as an FSM (hereinafter referred to as “finite state machine block”) is generated. For example, for the extended state transition diagram data shown in FIG. 4, data as shown in FIG. 8 is generated as hardware description data of a finite state machine block. Thereafter, in step S24, the input bus of the data path portion (the portion corresponding to the description of “C = A + B” in the example shown in FIG. 4) indicated by the extended state transition diagram data, and the output signal of the FSM hierarchical block A hierarchical block that has a status signal as an input port and an output bus of the data path portion at the output port is set, and this operates as the data path portion (hereinafter referred to as “data path block”) The hardware description data described as) is generated. For example, for the extended state transition diagram data shown in FIG. 4, data as shown in FIG. 9 is generated as hardware description data of the data path block. After outputting the hardware description data of both the finite state machine block and the data path block in this way, in step S28, the description data of the finite state machine block FSM shown in FIG. 8 and the data shown in FIG. The hardware description data composed of the description data of the data path block REGACT is used as the hardware description data of the highest hierarchical block TOP composed of these hierarchical blocks, that is, the hardware description corresponding to the block diagram shown in FIG. Output as data. As a result, the HDL generation process is terminated, and the process returns from this subroutine.
[0032]
FIG. 6 shows the hardware description data generated from the extended state transition diagram data shown in FIG. 4 by the conventional method for comparison with the hardware description data generated in the present embodiment as described above. The input / output relationship of the external port of the LSI to be designed at this time is as shown in FIG.
[0033]
In this embodiment, the hardware description data generated from the extended state transition diagram data shown in FIG. 4 is as shown in FIGS. 8 and 9 as described above, and corresponds to a portion corresponding to the FSM and a data path. The hardware description data is such that the portion is configured as a separate hierarchical block. Therefore, it becomes possible to apply a logic synthesis tool based on a logic compression algorithm dedicated to FSM to the portion corresponding to the FSM in the generated hardware description, thereby obtaining a high compression ratio. In addition, since circuit debugging and timing analysis after logic synthesis can be carried out separately from the FSM and the data path portion, debugging and timing analysis are facilitated, and design work efficiency is improved.
[0034]
<Embodiment 2>
According to the hardware description data generated in the above embodiment, the LSI to be designed has a configuration in which the finite state machine block and the data path block are separated, but the data path block is further combined with only the combinational circuit. If the configuration is separated into a hierarchical block consisting of and a hierarchical block consisting of a register group, logic synthesis and debugging can be performed for each of these hierarchical blocks. This makes it easier to debug the circuit after synthesis and analyze the timing. For this purpose, the generation of the hardware description data of the data path block in step S24 of FIG. 3 may be changed as follows (hereinafter referred to as “embodiment 2”). ").
[0035]
That is, as shown in the flowchart of FIG. 11, first, in step S102, the data path portion indicated by the extended state transition diagram data read in step S20 is extracted from the data load operation caused by the clock signal. Hardware description data in which this is described as one hierarchical block (hereinafter referred to as “combination circuit block”) is generated. For example, for the extended state transition diagram data shown in FIG. 4, data as shown in FIG. 12 is generated as hardware description data of the combinational circuit block. Next, in step S104, the data path portion is extracted that is converted into a flip-flop constituting an internal register (register group) by logic synthesis, and this is extracted as one hierarchical block (hereinafter referred to as "register block"). Hardware description data described as) is generated. For example, for the extended state transition diagram data shown in FIG. 4, data as shown in FIG. 13 is generated as hardware description data of the register block. According to the hardware description data composed of the description data of the combinational circuit block COMB of FIG. 12 and the description data of the register block REG of FIG. 13 obtained as described above, as shown in FIG. 14, the data path block REGACT The combinational circuit block COMB and the register block REG are configured as separate hierarchical blocks.
[0036]
<Embodiment 3>
Next, an embodiment of the present invention (hereinafter referred to as “Embodiment 3”) corresponding to the testability design will be described. In the present embodiment, the HDL generation process is as shown in the flowchart of FIG. This flowchart is obtained by adding step S26 for inserting a test circuit to the flowchart of FIG. 3 in the first embodiment. Other configurations are the same as those of the first embodiment.
[0037]
In this embodiment, when generating the register transfer level hardware description data from the extended state transition diagram data, the processing in steps S20 to S24 in FIG. 15 is performed as in the first embodiment, and then the test is performed in step S26. Performs processing for circuit insertion. That is, together with hardware description data for the test mode signal and test clock signal supplied from the outside, when the test mode signal is “0”, normal clocks corresponding to the finite state machine block and the data path block are respectively provided. And generate hardware description data for the multiplexer that supplies a test clock to the finite state machine block and the datapath block when the test mode signal is "1". Thereby, hardware description data of a register transfer level corresponding to the circuit having the configuration shown in FIG. 16 is obtained. FIG. 16 is a block diagram showing the configuration of the highest hierarchical block TOP. According to this configuration, the test mode signal TEST_MODE is set to “0” during normal operation, and the finite state machine block FSM has The clock signal CLK is supplied to the data path block REGACT, and the clock signal CK2 is supplied to the data path block REGACT. At the time of the test, the test mode signal TEST_MODE is set to “1”, and the test clock signal is supplied to the finite state machine block FSM and the data path block REGACT. TEST_CLOCK is supplied.
[0038]
As described above, according to the present embodiment, the test circuit is inserted in the hardware description data generation at the register transfer level, so that design for testability is realized without inserting the test circuit after logic synthesis. Thereby, the work efficiency of LSI design is improved.
[0039]
<Embodiment 4>
Next, an LSI functional design support apparatus according to a fourth embodiment (hereinafter referred to as “embodiment 4”) of the present invention will be described.
The LSI functional design support apparatus of this embodiment has the same hardware configuration as those of the first to third embodiments (see FIG. 1), and describes the operation of the LSI to be designed as in the first to third embodiments. The extended state transition diagram data to be input is input (see steps S10 to S14 in FIG. 2). However, in the present embodiment, the HDL generation process is different from those in the first to third embodiments. In this embodiment, a macro library that collects macros that can be used for hardware description at the register transfer level is stored in the hard disk device 12. In this macro library, macros corresponding to flip-flop macros having a flip-flop function for a plurality of bits registered in the technology library corresponding to the LSI manufacturing technology to be designed are registered. .
[0040]
Hereinafter, the HDL generation processing of the present embodiment will be described with reference to the flowchart shown in FIG.
First, in step S30, extended state transition diagram data, which is design information stored in the hard disk device 12, is read into the memory 18 in the same manner as in the first to third embodiments. In the following description, it is assumed that state transition diagram data as shown in FIG. 18 has been read in this step. In FIG. 18, for example, the state name “S0” indicates a state labeled S0, and “S1” is described as the next state next to the state name “S0” means that the state transitions to state S1 next to state S0. Is shown. In addition, whether or not “Z” is described as an output indicates that the output signal of the signal name Z is “1” in a state where “Z” is described, and the output of the signal name Z is in a state where “Z” is not described. Indicates that the signal is “0”. In the example shown in FIG. 18, since the description of the register operation is not included, the data read into the memory 18 is normal state transition diagram data.
[0041]
In the next step S32, the state represented by the read state transition diagram data is examined, and a state code is assigned to each state (state code analysis process). In the case of the state transition diagram data shown in FIG. 18, there are nine states S0 to S8. Therefore, if a status code is assigned with a minimum bit width, a status register with a 4-bit width is required. FIG. 19 shows the result of the state code analysis for the state transition diagram data of FIG. 18, and in this example, 4-bit state codes “0000” to “1000” are assigned to the states S0 to S8, respectively. When the status code is assigned in this way, the state transition diagram showing the operation of the LSI to be designed is as shown in FIG. 22, and this is displayed on the display device 20.
[0042]
After assigning the status code, in step S34, the macro library stored in the hard disk device 12 is referred to obtain a flip-flop macro necessary for realizing the status register for storing the status code. Now, as shown in FIG. 20, a 4-bit flip-flop macro named “R42” and an 8-bit flip-flop macro named “R82” are registered in the macro library. It shall be. In this case, if the status code is assigned as shown in FIG. 19, the flip-flop macro R42 is selected, and the data shown in FIG. 21 corresponding to this is used for the hardware description of the LSI to be designed. It is stored in the hard disk device 12 as flip-flop data.
[0043]
In step S36, hardware description data at the register transfer level is generated by referring to the flip-flop data obtained in step 34 from the state transition diagram data read in step S30.
[0044]
FIG. 23 shows the hardware description data generated from the state transition diagram data of FIG. 18 by the conventional LSI functional design support apparatus for comparison with the hardware description data generated in the present embodiment as described above. . In FIG. 23, an HDL description 201 indicates allocation of a 4-bit status code, and an HDL description 202 indicates a status register. When a logic circuit is synthesized from the hardware description data shown in FIG. 23 by a logic synthesis tool, a circuit as shown in FIG. 25 is obtained.
[0045]
On the other hand, the hardware description data generated from the state transition diagram data of FIG. 18 in this embodiment is as shown in FIG. In FIG. 24, the HDL description 211 indicates the status code assignment, the HDL description 212 indicates the status register, and the HDL description 213 indicates the use of the 4-bit flip-flop macro R42. When a logic circuit is synthesized from the hardware description data shown in FIG. 24 by a logic synthesis tool, a circuit as shown in FIG. 26 is obtained. In the logic circuit shown in FIG. 25 obtained by the conventional LSI function design support apparatus, four 1-bit flip-flops DFFC0R are generated as registers for storing the status codes, whereas the logic circuit shown in FIG. In this case, one 4-bit flip-flop macro R42 is generated as a register for storing the status code.
[0046]
As described above, according to the present embodiment, hardware description data using a multi-bit flip-flop macro as a status register for storing a status code is obtained. This flip-flop macro corresponds to a macro registered in a technology library corresponding to the manufacturing technology of the LSI to be designed. Therefore, when logic synthesis is performed on the hardware description data, a plurality of bits of flip-flops are generated as a single circuit block as a status register. As a result, it is possible to realize an LSI that operates stably without causing clock skew or the like. Further, since the status register is realized as one macro, it is advantageous in terms of chip area.
[0047]
<Embodiment 5>
Next, an LSI function design support apparatus according to a fifth embodiment (hereinafter referred to as “embodiment 5”) of the present invention will be described.
The LSI function design support apparatus of the present embodiment also has the same hardware configuration as that of the first to fourth embodiments (see FIG. 1), and describes the operation of the LSI to be designed in the same manner as the first to fourth embodiments. The extended state transition diagram data to be input is input (see steps S10 to S14 in FIG. 2). However, the extended state transition diagram used in the present embodiment can describe not only register operations in an arbitrary state but also state transitions in a hierarchical manner. For example, the aforementioned open chart has such a description function.
[0048]
The HDL generation process of the present embodiment is different from those of the first to fourth embodiments. Hereinafter, the HDL generation processing of this embodiment will be described with reference to the flowchart shown in FIG.
First, in step S 40, extended state transition diagram data, which is design information expressed by an extended state transition diagram that can be hierarchically described, is read from the hard disk device 12 into the memory 18. FIG. 28 is a diagram illustrating an example of extended state transition diagram data read in step S40. Of the states represented by the extended state transition diagram data, the state HS0 has a state transition as shown in the extended state transition diagram 304 as its lower layer, and the states HS1 and HS2 also have a lower layer. The HDL description 303 for the state S0 in the lower layer of the state HS0 indicates a register operation, and the HDL description 302 defines a clock supplied for this register operation.
[0049]
After the extended state transition diagram data is read in step S40, hardware description data is generated while sequentially checking the states represented thereby.
That is, first, in step S42, it is determined whether or not there is an uninvestigated state. At this time, when an unexamined state exists in the same hierarchy, an unexamined state in the same hierarchy is selected, and when an unadjusted state does not exist in the same hierarchy, an unexamined state in an upper hierarchy is selected. .
[0050]
In the next step S46, it is determined whether or not the state obtained in step 44 has a lower level state transition (has a lower state). If there is no lower level state transition, the process goes to step S48. It is determined whether or not there is an arrow that goes out of the state obtained in step S44. As a result, if there is no arrow, the process returns to step S42, and if there is an arrow, the process proceeds to step S50.
[0051]
In step S50, a state transition condition is obtained. In the next step S52, if a register operation is described for the state to be investigated (the state obtained in step S44), hardware description data indicating the register operation is described. Is generated. Thereafter, in step S54, a state transition destination is obtained. In step S56, hardware description data for the FSM is generated based on the transition condition, the transition destination (next state), and the current state thus obtained. Thereafter, the process returns to step S42. Thereafter, unless there is an unexamined state and the state obtained in step S44 has a lower-level state transition (see step S46), step S42 → S44 → S46 → S48 → S50 → S52 → S54 → S56 → S42. The above loop (however, when there is no arrow exiting from the state to be investigated, the process returns from step S48 to S42) is repeatedly executed. If it is determined in step S46 that there is a lower level state transition during this execution (hereinafter, a state having a lower level state transition is referred to as a “macro state”), the process proceeds to step S58.
[0052]
In step S58, hardware description data for a clock that operates only in the lower hierarchy is generated. Specifically, first, when the state code in the state transition diagram of the upper layer of the lower layer is a value indicating that this state (macro state having the state transition of the lower layer) is “1”, Otherwise, hardware description data of a flag signal that becomes “0” is generated, and then a logical product signal of this flag signal and an original clock to be supplied for lower-level state transition is generated. Then, hardware description data indicating supply as a clock to a status register storing a lower-level status code, that is, hardware description data indicating clock gating by an AND gate using the flag signal is generated.
[0053]
After the execution of step S58, the process proceeds to the lower level state transition. Unless an unexamined state exists and the state obtained in step S44 has a lower level state transition (see step S46), S42 → S44 → A loop of S46->S48->S50->S52->S54->S56-> S42 (however, if there is no arrow exiting from the state to be investigated, the process returns from step S48 to S42) is repeatedly executed. As a result, the same processing as described above is performed for the state transition diagram of the lower hierarchy. During this execution, if it is determined in step S46 that there is a further lower level state transition, the above loop is repeatedly executed for the lower level. Thereafter, in the same manner, the same processing as described above is performed until the lowest state transition diagram is reached. If there is no unexamined state as a result of such processing, the process returns from this subroutine (step S42), and the HDL generation processing is terminated.
[0054]
In the HDL generation processing in the present embodiment, each state in the extended state transition diagram having a hierarchical structure is sequentially examined as described above, and register transfer level hardware description data for the LSI to be designed is generated. FIG. 29 is a diagram showing a part of hardware description data obtained from the extended state transition diagram data shown in FIG. 28 by such HDL generation processing. The HDL description 402 in this figure is a part generated in step S58, and includes flags CLK3M and CLK3MM indicating that the macro state HS0 operates in a lower hierarchy state transition, and a lower hierarchy of the macro state HS0. This indicates that the clock CLK3 is generated by performing gating of the clock by taking a logical product with the original clock CLK to be supplied for state transition. This clock CLK3 is actually supplied as a lower-level state transition clock. In addition, the HDL description 403 in FIG. 29 is also generated in step S58, which indicates creation of the flags CLK3M and CLK3MM.
[0055]
According to the present embodiment, by the processing as described above in step 58, for each macro state, the state transition is performed for the lower layer of the macro state, except when the LSI to be designed is in the macro state. Hardware description data describing a configuration in which no clock is supplied is generated. Therefore, in an LSI manufactured based on this hardware description data, for each macro state, during the period during which no state transition of the lower layer of the macro state occurs, that is, during the period when the state is other than the macro state, Supply of the state transition clock to the hierarchy is stopped, thereby reducing power consumption.
[0056]
In the above embodiment, the power consumption is reduced by gating the clock of the lower layer state transition, but the power consumption can also be reduced by gating the clock supplied to the lower layer register operation. Can be reduced. That is, first, when the state code in the state transition diagram of the upper layer of the lower layer is a value indicating this state (macro state having the state transition of the lower layer), it becomes “1”. The hardware description data of the flag signal that sometimes becomes “0” is generated, and the logical product signal of this flag signal and the original clock to be supplied for the lower layer register operation is Hardware description data indicating that the clock is supplied as a clock for the register operation may be generated. In an LSI manufactured based on such hardware description data, a clock to be supplied for register operation is gated using the above flag, so that each macro state is in a state other than the macro state. In the middle, the supply of the clock to the register operation assigned to the lower layer state is stopped. Thereby, the power consumption of LSI is reduced.
[0057]
<Modification>
Each of the embodiments described above is characterized in that the finite state machine block and the data path block are separated from each other in order to improve the efficiency of logic synthesis and the ease of debugging, and the occurrence of clock skew. The feature that the state register is realized as one circuit block consisting of flip-flops for multiple bits for prevention, etc., and the feature that the gate for the lower-level state transition is gated to reduce power consumption, etc. However, it is also possible to realize an LSI function design support device having a plurality of these features and an LSI function design support device having all of these features.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing a hardware configuration of an LSI function design support apparatus according to an embodiment of the present invention.
FIG. 2 is a flowchart showing processing in the LSI function design support apparatus.
FIG. 3 is a flowchart showing HDL generation processing by the LSI functional design support apparatus according to the first embodiment;
FIG. 4 is a diagram showing an example of extended state transition diagram data input to the LSI functional design support device according to the first embodiment.
FIG. 5 is a view showing a data structure of the extended state transition diagram data.
FIG. 6 is a diagram showing hardware description data generated from the extended state transition diagram data by a conventional LSI function design support device.
7 is a diagram showing an input / output relationship of an external port of an LSI to be designed corresponding to the hardware description data of FIG. 6;
FIG. 8 is a diagram showing a finite state machine block portion of the hardware description data generated from the extended state transition diagram data in the first embodiment.
FIG. 9 is a diagram showing a data path block portion of the hardware description data generated from the extended state transition diagram data in the first embodiment.
FIG. 10 is a block diagram showing a configuration of an LSI corresponding to hardware description data generated in the first embodiment.
FIG. 11 is a flowchart showing generation of a hardware description of a data path block in HDL generation processing by the LSI functional design support apparatus according to the second embodiment;
FIG. 12 is a diagram showing a combinational circuit block portion of hardware description data generated from the extended state transition diagram data in the second embodiment.
FIG. 13 is a diagram showing a register block portion of hardware description data generated from the extended state transition diagram data in the second embodiment.
FIG. 14 is a block diagram showing a data path block portion of the LSI configuration corresponding to the hardware description data generated in the second embodiment.
FIG. 15 is a flowchart showing HDL generation processing by the LSI functional design support apparatus according to the third embodiment;
FIG. 16 is a block diagram showing a configuration of an LSI corresponding to hardware description data generated in the third embodiment.
FIG. 17 is a flowchart showing HDL generation processing by the LSI functional design support apparatus according to the fourth embodiment;
FIG. 18 is a diagram showing an example of state transition diagram data input to an LSI functional design support device according to a fourth embodiment.
FIG. 19 is a diagram illustrating a result of state code analysis of the state transition diagram data according to the fourth embodiment.
FIG. 20 is a diagram showing flip-flop macros registered in a macro library according to the fourth embodiment.
FIG. 21 is a diagram showing flip-flop data used when hardware description data is generated in the fourth embodiment.
FIG. 22 is a diagram showing a state transition diagram after state code allocation corresponding to state transition diagram data input to the LSI functional design support device of the fourth embodiment;
FIG. 23 is a diagram showing hardware description data generated from the state transition diagram data by a conventional LSI function design support apparatus.
FIG. 24 is a diagram showing hardware description data generated from the state transition diagram data in the fourth embodiment.
25 is a diagram showing a logic circuit obtained by logic synthesis from the hardware description data of FIG. 23 generated by a conventional LSI function design support device.
FIG. 26 is a diagram showing a logic circuit obtained by logic synthesis from the hardware description data of FIG. 24 generated in the fourth embodiment.
FIG. 27 is a flowchart showing HDL generation processing by the LSI functional design support apparatus according to the fifth embodiment;
FIG. 28 is a diagram showing an example of extended state transition diagram data input to the LSI functional design support device according to the fifth embodiment.
FIG. 29 is a diagram showing a part of hardware description data generated from the extended state transition diagram data of FIG. 28 in the fifth embodiment.
[Explanation of symbols]
10 ... Hardware body of LSI functional design support device
12: Hard disk device
16 ... CPU
18 ... Memory
211 ... Hardware description indicating allocation of status codes (Embodiment 4)
212 ... Hardware description indicating status register (Embodiment 4)
213 ... Hardware description showing use of 4-bit flip-flop macro (Embodiment 4)
402: Hardware description indicating gating of state transition clock (Embodiment 5)
403 ... Hardware description indicating creation of flag used for gating (Embodiment 5)
FSM ... Finite state machine block
REGACT ... Datapath block
COMB… Combination circuit block
REG ... Register block
R42 ... 4-bit flip-flop macro

Claims (2)

Input data generation means for generating state transition diagram data describing the operation of the LSI to be designed based on a state transition diagram capable of hierarchical description of state transitions based on an input operation by an operator;
State determination means for determining whether each state of the LSI represented by the state transition diagram data is a macro state which is a state having a lower state;
Flag description generating means for generating description data of a flag signal having a value of “1” when the LSI is in the macro state and a value of “0” when not in the macro state;
A gate that generates description data of a gate that supplies a transition clock of a lower state in the macro state when the flag signal is “1” and stops supply of the transition clock when the flag signal is “0” A description generation means;
Hardware in which the LSI for which the supply and stop of the transition clock is controlled by the flag signal is described in a register description level hardware description language using the description data generated by the flag description generation means and the gate description generation means Hardware description generation means for generating description data;
An LSI function design support apparatus comprising: Input data generation means for generating state transition diagram data describing the operation of the LSI to be designed from a state transition diagram capable of describing a hierarchical description of state transitions and register operations in an arbitrary state based on an input operation by an operator When,
State determination means for determining whether each state of the LSI represented by the state transition diagram data is a macro state which is a state having a lower state;
Flag description generating means for generating description data of a flag signal having a value of “1” when the LSI is in the macro state and a value of “0” when not in the macro state;
A clock for register operation assigned to a lower state of the macro state is supplied when the flag signal is “1”, and the supply of the clock is stopped when the flag signal is “0”. Gate description generation means for generating description data;
Hardware description in which the LSI whose supply and stop of the clock are controlled by the flag signal is described in a register description level hardware description language using the description data generated by the flag description generation means and the gate description generation means Hardware description generation means for generating data;
An LSI function design support apparatus comprising:

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