JP3721673B2 - Semiconductor device provided with capacitive element - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device provided with a capacitor element, and more particularly to a semiconductor memory device having a capacitor element having a configuration that can be easily formed in a semiconductor device and having a high soft error resistance.
[0002]
[Prior art]
In semiconductor memory devices such as SRAM, there is a soft error phenomenon in which stored data is temporarily lost when radiation such as α rays enters the memory cell, and reliability of memory retention becomes a problem. There is. This problem is becoming more and more serious because the capacitance of the storage node in the memory cell is reduced with the miniaturization of the device. Also, the problem of soft error is that the noise current at the time of α-ray incidence is sufficiently larger than the driving current of the MOSFET, so that it is not limited to a high resistance load type or TFT (Thin Film Transistor) load type cell, but also in a 6 transistor SRAM cell. It is a problem as well.
As countermeasures against this, (1) a chip coat, for example, a buffer coat such as a polyimide film, is deposited thickly on the passivation film to limit the incidence of α rays, and (2) the impurity profile of the substrate region is devised, It is conceivable to suppress the collection of excess carriers generated in the substrate to the storage node, and (3) to increase the capacitance at the storage node by devising the structure of the memory cell.
[0003]
[Problems to be solved by the invention]
However, the countermeasure (1) has a detrimental effect that the wafer is warped, causing problems in later processing steps, or causing problems during assembly such as difficulty in bonding. In the countermeasure (2), However, a sufficient effect cannot always be obtained, and there is a concern about the influence on the characteristics of the semiconductor device, for example, the MOSFET characteristics. In the measure (3), for example, a method of forming a capacitive element by adding a polysilicon layer is used, but this is sufficient for reducing the memory cell area accompanying the miniaturization of the memory cell. It is becoming difficult to add a large capacitance.
In the case of a TFT load type cell, an example of combining with a resistance element has been studied, but it is not always easy to realize it due to an influence on write characteristics and the like. In addition, application to 6 transistors is concerned about an even greater effect than in a TFT load type cell. There is also an example in which a fin-structure capacitive element is formed on the upper portion of the MOSFET, but since the step between the cell region and other regions is enlarged, when forming the upper structure, for example, when forming a wiring layer, processing is performed. There are problems such as difficulty.
[0004]
Therefore, an object of the present invention is to provide a semiconductor memory device including a capacitive element that can add a large capacitance to a semiconductor device so that soft error is unlikely to occur. A six-transistor SRAM cell having the following structure is provided.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, a capacitor element included in a semiconductor device according to the present invention includes a first conductivity type first diffusion layer provided in an upper layer of a first conductivity type substrate region, and an element isolation. As an area, an opening is formed over the thick first insulating film provided in the substrate region in the vicinity of the first diffusion layer, and the bottom is located deeper than the lower surface of the first insulating film. A groove-shaped or cylindrical recess formed in the substrate region;
A second thin insulating film provided along the recess wall;
A second conductive type semiconductor layer formed inside the second insulating film;
A third thin insulating film provided along the inside of the semiconductor layer;
A conductor layer provided in a rod-like or columnar shape between the third insulating films,
A first capacitor composed of a substrate region and a semiconductor layer via a second insulating film, and a second capacitor composed of a semiconductor layer and a conductor layer via a third insulating film Yes.
[0006]
Since this capacitor element is provided close to the element isolation region, it is not necessary to enlarge the semiconductor device, and is suitable for miniaturization of the semiconductor device. Whether to form a groove or a cylinder depends on the structure of the semiconductor device.
The materials of the semiconductor layer and the conductor layer are not limited, and can be formed of, for example, polysilicon.
The second insulating film is formed along the sidewall of the recess wall except for the bottom of the recess, and the semiconductor layer is formed as a sidewall semiconductor layer inside the second insulating film along the sidewall of the recess wall. The lower edge is in contact with the substrate region at the bottom of the recess, the top of the sidewall semiconductor layer is in contact with the first insulating film and the first diffusion layer, and the third insulating film is on the bottom of the recess and inside the sidewall semiconductor layer. It can also be formed. Since the upper portion of the sidewall semiconductor layer is connected to the first diffusion layer, that is, the drain region or the source region, the semiconductor memory device and the capacitor element are electrically connected with a simple configuration.
[0007]
A semiconductor device according to the present invention is a semiconductor device comprising the above-described capacitive element and configured as an SRAM cell,
The first diffusion layer of the capacitor and the second diffusion layer provided separately from the capacitor correspond to the diffusion layers of the two storage nodes of the SRAM cell, and the conductor layer of the capacitor is the first. 2 diffusion layers. Thereby, the capacitive element can be connected to the diffusion layer of the semiconductor device with a simple configuration.
In the case where the semiconductor device is configured as a six-transistor type SRAM cell, the first and second conductivity types of the capacitive element are n-type and p-type, respectively, in the pMOSFET region of the SRAM cell. The diffusion layer is p-type, and the nMOSFET region of the SRAM cell has two types of capacitive elements in which the first and second conductivity types are p-type and n-type, respectively, and the second diffusion layer is n-type.
[0008]
According to the present invention, in order to add a sufficiently large capacitance to the storage node, the capacitive element is formed inside the semiconductor substrate, and in the SRAM cell, the two electrodes are connected to the two storage nodes. Further, a capacitive element is formed in each of the pMOSFET and nMOSFET regions in the 6-transistor cell.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
Configuration of Capacitance Element Formed in Semiconductor Device of Present Invention FIG. 1 is a cross-sectional view of a substrate showing a basic configuration when a capacitance element is formed in an nMOSFET, and shows a partial region of the nMOSFET having the capacitance element.
As shown in FIG. 1, the nMOSFET 10 in which the capacitive element is formed includes a p-well region 14 formed in the n-type semiconductor substrate 12 and a thick first film formed in the upper layer of the p-well region 14. An element isolation region 16 made of a field oxide film, and a first n-type diffusion layer 18 and a second n-type diffusion layer 20 formed as active regions in the upper layer of the p-well region 14 on both sides of the element isolation region 16, respectively And a channel region 22 adjacent to the first diffusion layer 18.
A gate electrode 30 having a laminated structure of a polysilicon layer 26 and a tungsten silicide layer 28 is formed in the channel region 22 with a gate oxide film 24 interposed therebetween. On the other hand, the second diffusion layer 20 is connected to the first wiring layer 34 through a metal contact 32 penetrating the interlayer insulating film 31.
[0010]
The capacitive element 36 has an opening extending over the first diffusion layer 18 and the element isolation region 16, has a bottom portion deeper than the lower surface of the element isolation region 16, and is formed in the p well region 14. It is provided in the cylindrical tube hole 38.
The capacitive element 36 includes a second thin oxide film 40 formed in a cylindrical shape along the hole wall except the bottom of the cylindrical hole 38, and a sidewall semiconductor layer 42 made of an n-type semiconductor formed in a cylindrical shape inside the second thin oxide film 40. And a third thin insulating film 44 formed on the bottom of the cylindrical hole 38 and on the inner side of the sidewall semiconductor layer 42, and a cylindrical conductor layer 46 provided between the third oxide films 44. And have.
The sidewall semiconductor layer 42 contacts the p-well region 14 without the second oxide film 40 interposed at the bottom of the cylindrical hole 38, and a part of the sidewall semiconductor layer 42 also has the second oxide film 40 interposed above the cylindrical hole 38. The first diffusion layer 18 or the element isolation region 20 is in contact without any contact. Thereby, the sidewall semiconductor layer 42 is electrically connected to the first diffusion layer 18 and is electrically separated from the p-well region by the pn junction. Unlike the present embodiment, the second oxide film 40 may be interposed at the bottom and top of the cylindrical hole 38.
The conductor layer 46 is formed of a polysilicon layer, and includes a tungsten silicide layer 47 on the upper portion like the gate electrode 30. The conductor layer 46 is electrically connected to the metal contact 32 on the element isolation region 16, and the shared contact 32. Is configured. A conductor layer (not shown) having the same configuration as that of the conductor layer 46 is electrically connected to the gate electrode 30 and functions as a wiring layer of the gate electrode 30.
[0011]
With the above-described configuration, the capacitive element 36 includes the first grounding capacitor 48 including the p-well region 14 and the sidewall semiconductor layer 42 with the second oxide film 40 interposed therebetween, and the third oxide film 44. A second capacitor 50 including a sidewall semiconductor layer 42 and a conductor layer 46 with a gap interposed therebetween.
[0012]
Although the above-described example has been described by taking an nMOSFET as an example, the semiconductor device according to the present invention can also be applied to a pMOSFET in which a p-type diffusion layer is formed on an n-type Si substrate. In this case, the above-described conductivity type n and p are replaced with each other.
[0013]
Method for Forming Capacitive Element Formed in Semiconductor Device of the Present Invention A method for forming the semiconductor device shown in FIG. 1 will be described with reference to FIGS. FIGS. 2A, 2B, and 2C are cross-sectional views of the substrate for each step of forming the nMOSFET shown in FIG. FIGS. 3D and 3E are cross-sectional views of the substrate for each nMOSFET formation process following FIG. 2C.
First, as shown in FIG. 2A, a field oxide film 16 is formed as a first oxide film on an n-type Si substrate 12, and a thin Si nitride film 52 of about 10 nm is deposited thereon. Next, a photoresist film is formed and further patterned to form a resist mask 54 for etching the cylindrical hole 38.
Next, as shown in FIG. 2B, a depth of about 1 μm is formed so as to penetrate the end portion of the field oxide film 16 by anisotropic etching using a condition with a small selection ratio between Si and Si oxide film. A cylindrical hole 38 is formed in the n-type Si substrate 12, and then a p-well region 14 is formed by impurity ion implantation. Subsequently, an oxide film 40 having a thickness of about 10 nm is formed on the Si nitride film 52, n-type polysilicon having a thickness of about 50 nm is further deposited, and then on the region other than the cylindrical hole 38 and the cylindrical hole 38. The polysilicon layer on the bottom is etched back to form a sidewall semiconductor layer 42 made of n-type polysilicon through the oxide film 40 along the hole wall of the cylindrical hole 38. The oxide film 40 functions as a second oxide film.
Next, as shown in FIG. 2C, the exposed oxide film 40 on the Si nitride film 52, the exposed oxide film 40 in the cylindrical hole 38, and the top and bottom portions of the sidewall semiconductor layer 42 and the hole wall The intermediate oxide film 40 is removed by etching with hydrofluoric acid. Next, n-type polysilicon 56 is deposited in the space between the top and bottom of the sidewall semiconductor layer 42 removed by etching the oxide film 40 and the hole wall, and then etched back to fill it.
[0014]
As shown in FIG. 3D, after the Si nitride film 52 is removed by etching with hot phosphoric acid, an oxide film is formed on the entire surface of the substrate to form a gate oxide film 24 and a third oxide film 44. Next, a polysilicon layer 58 made of n-type polysilicon and a tungsten silicide layer 60 are sequentially deposited thereon.
As shown in FIG. 3E, the n-type polysilicon layer 58 and the tungsten silicide layer 60 are patterned so that the conductor layer 46, the tungsten silicide layer 47 thereon, and the polysilicon constituting the gate electrode 30 are formed. A silicon layer 26 and a tungsten silicide layer 28 are formed. Next, impurities are ion-implanted to form an nMOSFET including the first n-type diffusion layer 18 and the second n-type diffusion layer 20.
Further, as shown in FIG. 1, after the interlayer insulating film 31 is deposited, a shared contact 32 is formed by a tungsten plug, and a metal wiring 34 is further formed.
[0015]
Example 1
The present embodiment is an example in which the semiconductor device according to the present invention is applied to a six-transistor cell type SRAM cell, and the first and second diffusion layers 18 and 20 described in FIG. to, respectively corresponding to the diffusion layer of the storage node _{D 1} and _{D 2.} FIG. 4 shows an equivalent circuit of a 6-transistor cell type SRAM cell using the capacitive element according to the present invention.
This SRAM cell is a cell having two n-type MOSFETs as a switch between a flip-flop circuit by two inverters and an input / output line, and includes a C ₁ and a _first capacitor corresponding to the first capacitor 48 in FIG. A first capacitive element 62 having C ₂ corresponding to a second capacitance 50, a second capacitive element 64 having C ₃ corresponding to the first capacitance 48 and C ₄ corresponding to the second capacitance 50, It has.
The example of FIG. 1 assumes a region using an nMOSFET, but the second capacitor element 64 provided in the region of the pMOSFET of the six-transistor cell has a conductivity type of FIG. It is a conductive type capacitive element replaced with.
[0016]
With the above configuration, since a cross-coupled capacitance is formed between the storage nodes of the SRAM cell, a large capacitance can be obtained effectively in a small region, and a large storage node capacitance is also provided in the pMOSFET region. Even in the obtained and miniaturized memory cell, a large capacitance can be added with a small area, and an SRAM cell having good soft error resistance can be realized.
[0017]
The layout pattern under the first Al wiring layer (corresponding to the wiring layer 34 in FIG. 1) and the layout pattern of the first Al wiring layer of the SRAM cell having the equivalent circuit shown in FIG. The arrangement of the element 62 and the second capacitor element 64 is as shown in FIGS. 5 and 6.
FIG. 7 is a cross-sectional view of the substrate taken along lines I-II and II-III in FIGS. 5 and 6. In FIG. 7, the right side from the vertical line XX ′ and the left side from the vertical line XX ′ show a cross section taken along the line I-II and a cross section taken along the line II-III, respectively. Therefore, the first and capacitive elements 62 and 64 are not shown. FIG. 7A is a detailed view showing the layer structure of the gate electrode.
Note that FIGS. 1 to 3 illustrate the case of an n-MOSFET, but FIG. 7 illustrates the use of a p-MOSFET whose conductivity type is reversed.
Thus, the capacitive element according to the present invention can be easily applied to a memory cell having a known configuration. Further, in order to form the capacitive element inside the substrate, there is no increase in the level difference between the memory cell region and the surrounding region.
[0018]
【The invention's effect】
According to the configuration of the present invention, a groove-shaped or cylindrical recess is provided at a position straddling the diffusion layer and the element isolation region, and a capacitor element having two capacitors connected in series is formed in the recess. Yes. By providing the capacitive element according to the present invention in a semiconductor memory device, a cross-coupled capacitance and a grounded capacitance between the storage nodes are formed without increasing the area of the memory cell, and a sufficiently large electrostatic capacity is formed in the storage node. Since the capacitance can be added, the soft error resistance of the semiconductor device, particularly the SRAM memory cell, can be improved while meeting the demand for miniaturization of the semiconductor device.
In addition, since the capacitor element is formed in the substrate region and the step between the memory cell region and the peripheral region is not increased, a semiconductor memory device that can be easily processed in a later processing step and has good characteristics is realized. be able to. Furthermore, when forming the capacitive element, the number of photolithography processes is increased by one process (adding one reticle), so that the formation cost does not increase, and matching with the layout pattern of an existing cell is required. Good nature. Needless to say, the capacitive element according to the present invention is applicable not only to SRAM cells but also to DRAM cells and other semiconductor devices.
[Brief description of the drawings]
1 is a substrate cross-sectional view showing the structure of a capacitor element that will be formed in the semiconductor device of the present invention.
FIGS. 2A, 2B, and 2C are cross-sectional views of a substrate for each step of forming the nMOSFET shown in FIG.
3 (d) and 3 (e) are cross-sectional views of the substrate for each nMOSFET formation process following FIG. 2 (c), respectively.
FIG. 4 is a diagram showing an equivalent circuit of a 6-transistor SRAM cell according to the present invention.
FIG. 5 is a cross-sectional view of an SRAM cell.
6 is a cross-sectional view of the SRAM cell at a position above FIG.
FIG. 7 is a cross-sectional view of an SRAM cell substrate.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Semiconductor device according to the present invention, 12 ... n-type semiconductor substrate, 14 ... p-well region, 16 ... element isolation region comprising first field oxide film, 18 ... first n-type diffusion layer , 20 ... second n-type diffusion layer, 22 ... channel region, 24 ... gate oxide film 24, 26 ... polysilicon layer, 28 ... tungsten silicide layer, 30 ... gate electrode, 31 ... Interlayer insulating film 32... Metal contact, shared contact 34... First wiring layer 36... Capacitive element 38... Cylindrical hole 40 .. second oxide film 42. , 44... Third oxide film, 46... Conductor layer, 48... First capacitor, 50.

Claims (2)

A first diffusion layer of the second conductivity type provided in the upper layer of the substrate region of the first conductivity type, and a thick first film provided in the substrate region in the vicinity of the first diffusion layer as the element isolation region A groove-shaped or cylindrical recess formed in the substrate region so as to have a bottom at a position deeper than the lower surface of the first insulating film,
A second thin insulating film formed along the recess wall excluding the bottom of the recess;
Second conductive film formed as a sidewall semiconductor layer on the inner side of the second insulating film so that the lower edge thereof is in contact with the substrate region of the recess and the upper portion is in contact with the first insulating film and the first diffusion layer. A mold semiconductor layer;
A third thin insulating film provided along the bottom of the recess and the inside of the semiconductor layer;
A conductor layer provided in a rod-like or columnar shape between the third insulating films;
A first capacitor comprising a substrate region and a semiconductor layer via a second insulating film;
A capacitor element having a second capacitor composed of a semiconductor layer and a conductor layer via a third insulating film;
A semiconductor device configured as an SRAM cell, wherein the first diffusion layer is a source region or a drain region,
The first diffusion layer of the capacitor and the second diffusion layer provided separately from the capacitor correspond to the diffusion layers of the two storage nodes of the SRAM cell, and the conductor layer of the capacitor is the first. A semiconductor device connected to two diffusion layers. The semiconductor device is configured as a 6-transistor SRAM cell,
In the nMOSFET region of the SRAM cell, the first and second conductivity types of the capacitive element are n-type and p-type, respectively, and the second diffusion layer is p-type,
2. The nMOSFET region of an SRAM cell has two types of capacitive elements in which the first and second conductivity types are p-type and n-type, respectively, and the second diffusion layer is n-type. A semiconductor device according to 1.

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