JP3706696B2 - Digital information receiving apparatus and digital information receiving method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital information receiving apparatus and a digital information receiving method for receiving a digital information signal or the like while switching a plurality of receiving facilities according to a line state.
[0002]
[Prior art]
As a countermeasure against fluctuations in the received electric field level due to local rain attenuation in satellite communication transmission and fading on ground micro-links, multiple receiving facilities are prepared, and these received waves are switched or the outputs of multiple receiving facilities are switched. It is known that a diversity technique that suppresses the influence due to level fluctuations by combining them is effective. Also, MPEG2 (Moving Picture Expert Group 2) is becoming mainstream recently as a method for compressing and transmitting moving images.
[0003]
In the digital data transmission system, a conventional example in the case of applying MPEG2 as an image compression transmission method and switching between two waves as a diversity method will be described with reference to FIG.
[0004]
The received wave input to the first receiving antenna 11 of the first receiving facility 1 is demodulated by the first demodulating circuit 12 and the demodulated data is sent to the first error correcting circuit 13. If there is an error in the demodulated data, the error correction circuit 13 performs error correction.
[0005]
The demodulated data error-corrected by the error correction circuit 13 becomes a transport stream (TS) in MPEG2, and is sent to the data changeover switch 4. Further, an error flag amount indicating the line state of the transmission path is sent to the switch control circuit 3.
[0006]
Similarly to the first receiving equipment 1, the second receiving equipment 2 is composed of the second receiving antenna 21, the second demodulating circuit 22, the second error correcting circuit 23, etc., and operates in the same manner. TS data is sent to the data changeover switch 4 and an error flag amount is sent to the switch control circuit 3.
[0007]
The switch control circuit 3 receives the error flag amount sent from the first error correction circuit 13 and the second error correction circuit 23, and selects the data with the smaller correction amount, that is, the data with the better line state. Thus, the data changeover switch 4 is controlled. The TS data selected by the changeover switch 4 is sent to the MPEG decoder 35 to be decoded and output from the terminal 6 as video data (V-out).
[0008]
[Problems to be solved by the invention]
The conventional method of switching between two received waves shown in FIG. 4 is simple without providing means for synchronizing the output data string of the first receiving equipment 1 and the output data string of the second receiving equipment 2. The data string was switched.
[0009]
When the data string is simply switched in this way, an instantaneous interruption occurs because the synchronization is reestablished within the MPEG decoder 35. Therefore, the instantaneous interruption time by limiting the switching timing such as switching at the break of the transmission frame. Shortening measures are taken.
[0010]
Thereby, the continuity of the data string can be maintained, but in order to ensure the continuity of the data after decoding the signals having different transmission times without instantaneous interruption, the first receiving equipment 1 and the second receiving equipment It is necessary to adjust the processing time of the equipment 2 equally including the transmission path. This adjustment is difficult, and once it is adjusted, it is difficult to change the processing time. Therefore, there is a problem that it is impossible to cope with the case where the state of the transmission path constantly changes like mobile reception.
[0011]
In addition, when it is difficult to adjust the processing time because the two receiving facilities are physically separated, there is a problem that adjustment must be performed by an external device having a large-capacity memory such as a frame synchronizer after decoding. there were.
[0012]
An object of the present invention is to provide a digital information receiving apparatus and method in which there is no instantaneous interruption at the time of switching of receiving equipment in view of the above-mentioned problems.
[0013]
[Means for Solving the Problems]
The digital information receiving apparatus of the present invention comprises first and second receiving facilities, and transport stream data encoded by the MPEG2 system received by the first and second receiving facilities, respectively, according to the line state. Digital information receiving apparatus that receives the first program time reference information (PCR) that is a clock reference of a program from transport stream data encoded by the MPEG2 method received by the first receiving facility. ) And second program time reference information (PCR), which is the clock reference of the program, is detected from the transport stream data encoded by the MPEG2 system received by the second receiving facility. And receiving at the first receiving facility using the first program time reference information as a writing address reference. A first delay memory for writing the transport stream data, a second delay memory for writing the transport stream data received by the second receiving facility using the second program time reference information as a write address reference, A decoder for selectively decoding transport stream data stored in the first delay memory and the second delay memory, and reading the transport stream data from the first and second delay memories; A common read address is used.
[0014]
Also, the digital information receiving method of the present invention comprises first and second receiving facilities, and transport stream data encoded by the MPEG2 system received by the first and second receiving facilities, respectively. The first program time reference information that is a clock reference of a program from transport stream data encoded by the MPEG2 method received by the first receiving equipment. A step of detecting (PCR) and a step of detecting second program time reference information (PCR), which is a clock reference of the program, from transport stream data encoded by the MPEG2 method received by the second receiving facility And the transformer received by the first receiving facility using the first program time reference information as a write address reference. Port stream data in the first delay memory, and the second program time reference information as the write address reference, the transport stream data received by the second receiving facility is stored in the second delay memory. And a step of reading out the transport stream data written in the first and second delay memories using a common read address and selectively outputting the data to a decoder.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail based on illustrated embodiments.
FIG. 1 is a block diagram showing a configuration of a digital image line switching apparatus according to an embodiment of the present invention.
In FIG. 1, reference numeral 1 denotes a first receiving equipment, and 2 denotes a second receiving equipment, which comprises a receiving antenna 11 (21), a demodulating circuit 12 (22), and an error correcting circuit 13 (23) as in the conventional example. The operation is the same as that described in the conventional example.
[0024]
The transport stream data (TS) received by the first receiving facility 1 and the second receiving facility 2 are temporarily written in the first delay memory 15 and the second delay memory 25, respectively. At this time, the first PCR detection means 14 and the second PCR detection means 24 detect the program time reference information (PCR) from the respective TS data, and the first delay memory 15 and the second delay memory 25 This is used as a reference address signal for a circuit for generating write addresses WARD1 and WARD2.
[0025]
Generation of write / read addresses in the first delay memory 15 and the second delay memory 25 is generated from the first address generation circuit 16 and the second address generation circuit 26, respectively.
[0026]
As described in the conventional example, the switch control circuit 3 controls the data selector switch 4 so as to select data having a better line state. The TS data with the better line state selected by the data switch 4 is sent to the MPEG2 decoder 5.
[0027]
The MPEG2 decoder 5 detects the PCR data from the input TS data and reproduces the system clock. Then, the transmission data is decoded based on the reproduced system clock, and the PCR data is sent to the first address generation circuit 16 to read out the reference address of the first delay memory 15 and the second delay memory 25. Use as
[0028]
Next, with respect to the operations of the first address generation circuit 16 and the second address generation circuit 26, the operation is stable from the system start-up using the block diagram of the first address generation circuit of FIG. 2 and the flowchart of FIG. I will explain until.
[0029]
The PCR data detected by the first PCR detection means 14 is input to the first address generation circuit 16, the number of bits covering the delay time required in the system is selected, and the first write address generation counter 61 is loaded.
[0030]
Here, the required number of bits is the number of bits that can represent the time required by the system, in other words, the time that is twice the maximum data arrival time difference from two assumed receiving facilities by PCR.
[0031]
For example, if the maximum data arrival time difference is t, the PCR update time in MPEG2 is 1/90000 [s], so the required number of bits b is
b = roundup (log ₂ (2t × 90000)) (roundup (*): rounded up to the nearest decimal point)
Thus, the lower-order b bits of the PCR are the required number of bits (b ≦ 33 in MPEG2).
[0032]
The output of the first write address generation counter 61 becomes the write address WARD1 of the first delay memory 15.
[0033]
Next, generation of the read address of the first delay memory 15 will be described with reference to the flowchart of FIG.
First, in step S1, the PCR detection information from the MPEG decoder 5 is confirmed.
[0034]
At the time of system startup, the MPEG decoder 5 cannot stably detect the PCR, so the process proceeds from step S1 to step S2, and the data changeover switch 4 selects the data from the first receiving facility 1 to be input. The address selection switch 64 selects the first read address RADR1.
[0035]
The first write address WARD1 is also sent to the adder 62, where approximately ½ of the maximum number of occurrences of the first write address generation counter 61 is added so that the memory can be used effectively. However, necessary bits are loaded into the address generation counter 63.
[0036]
The first read address RADR1, which is the output of the first read address generation counter 63, passes through the read address selection switch 64 and serves as the initial read address of the first delay memory 15 for the first delay memory 15. Sent to. The read output of the first delay memory 15 is sent to the MPEG decoder 5 via the data changeover switch 4.
[0037]
In the MPEG decoder 5, PCR detection is performed from the input TS data, and data d having a necessary number of bits is sent to the address conversion circuit 65 of the first address generation circuit 16.
[0038]
The address conversion circuit 65 calculates a difference s (s <0) from the first read address RADR1, adds the calculated difference s from the first read address RADR1 to the data d of the necessary number of bits, The second read address RADR2 is output to the address selection switch 64.
[0039]
Here, the selection switch control circuit 67 compares the values of the first read address RADR1 and the second read address RADR2 (step S3). If the comparison result in step S3 is equal, the process in step S4 is performed. In this case, the selection switch control circuit 67 operates and outputs the second read address RADR2 as the read address RADR of the first delay memory 15.
[0040]
Next, in step S5, the PCR detection information from the MPEG decoder 5 is monitored. If PCR detection information is detected, the process proceeds to step S6, and the address selection switch 64 is fixed to the second read address RADR2. To do.
[0041]
On the other hand, if PCR cannot be detected as a result of monitoring the PCR detection information in step S5, the process returns to step S1 to repeat the above-described operation. That is, in the digital image transmission line switching apparatus according to the present embodiment, after the reading address RADR is selected once, it is fixed to the second reading address RADR2 side until the PCR cannot be detected by the MPEG decoder 5. It is set as follows.
[0042]
On the other hand, the second address generation circuit 26 that generates the write address of the second delay memory 25 operates in the same manner as the first write address counter 62 of the first address generation circuit 16, and the second write address WADR2 Is output.
[0043]
Since the read address of the second delay memory 25 is the same read address RADR as that of the first delay memory 15, the two data input to the data changeover switch 4 are equal. That is, even if the data changeover switch 4 is switched, the synchronization of the MPEG decoder 5 is not disturbed.
[0044]
As described above, the encoding method has been described using MPEG2, but the present invention is not limited by the encoding method as long as the transmission data includes the transmission side time information in the received data stream. Needless to say, any configuration may be used as long as it can achieve the functions described in the claims or the functions of the embodiments.
[0045]
[Other Embodiments of the Present Invention]
The present invention may be applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.) or an apparatus composed of a single device.
[0046]
Further, program code for software for realizing the functions of the above-described embodiment for a computer in an apparatus connected to the various devices so as to operate the various devices so as to realize the functions of the above-described embodiments. Implemented by operating the various devices in accordance with a program stored in a computer (CPU or MPU) of the apparatus.
[0047]
In this case, the program code of the software itself realizes the functions of the above-described embodiments, and the program code itself and means for supplying the program code to the computer, for example, the program code is stored. The storage medium constitutes the present invention. As a storage medium for storing the program code, for example, a floppy disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.
[0048]
Further, by executing the program code supplied by the computer, not only the functions of the above-described embodiments are realized, but also the OS (operating system) or other application software in which the program code is running on the computer, etc. It goes without saying that the program code is also included in the embodiment of the present invention even when the functions of the above-described embodiment are realized in cooperation with each other.
[0049]
Further, after the supplied program code is stored in the memory provided in the function expansion board of the computer or the function expansion unit connected to the computer, the CPU provided in the function expansion board or function expansion unit based on the instruction of the program code Needless to say, the present invention includes a case where the functions of the above-described embodiment are realized by performing part or all of the actual processing.
[0050]
【The invention's effect】
As described above, according to the present invention, in the system including the first and second receiving facilities and receiving the transport stream data respectively received by the receiving facility according to the line state, the receiving facility It is possible to decode the transport stream data so that the decoder output is not momentarily interrupted at the time of switching.
[0051]
In addition, according to another feature of the present invention, it is possible to easily move the receiving equipment. Therefore, when applied to a mobile communication system, the system can be easily changed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a digital image transmission line switching apparatus according to the present invention.
FIG. 2 is a block diagram showing a first address generation circuit which is a component of the embodiment of the present invention.
FIG. 3 is a flowchart for explaining an operation of a first address generation circuit which is a component of the embodiment of the present invention.
FIG. 4 is a block diagram illustrating a conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 1st receiving equipment 2 2nd receiving equipment 3 Switch control circuit 4 Data changeover switch 5 MPEG2 decoder

Claims (4)

Digital information reception comprising first and second receiving facilities for receiving transport stream data encoded by the MPEG2 system, which is received by the first and second receiving facilities, respectively, according to the line state A device,
First detection means for detecting first program time reference information (PCR) which is a clock reference of a program from transport stream data encoded by the MPEG2 method received by the first receiving facility;
Second detection means for detecting second program time reference information (PCR) which is a clock reference of a program from transport stream data encoded by the MPEG2 system received by the second receiving facility;
A first delay memory for writing the transport stream data received by the first receiving facility using the first program time reference information as a writing address reference;
A second delay memory for writing the transport stream data received by the second receiving facility using the second program time reference information as a write address reference;
A decoder that selectively decodes transport stream data stored in the first delay memory and the second delay memory;
A digital information receiving apparatus characterized by having a common read address for reading transport stream data from the first and second delay memories.   2. The digital information receiving apparatus according to claim 1, wherein the read address is generated based on program time reference information detected from transport stream data currently processed by the decoder. Digital information reception comprising first and second receiving facilities for receiving transport stream data encoded by the MPEG2 system, which is received by the first and second receiving facilities, respectively, according to the line state A method,
Detecting first program time reference information (PCR) which is a clock reference of a program from transport stream data encoded by the MPEG2 system received by the first receiving facility;
Detecting second program time reference information (PCR) which is a clock reference of a program from transport stream data encoded by the MPEG2 method received by the second receiving facility;
Writing the transport stream data received at the first receiving facility into the first delay memory using the first program time reference information as a write address reference;
Writing the transport stream data received at the second receiving facility into the second delay memory using the second program time reference information as a write address reference;
A digital information receiving method comprising: reading the transport stream data written in the first and second delay memories using a common read address and selectively outputting the read data to a decoder.   4. The digital information receiving method according to claim 3, wherein the common read address is generated based on program time reference information detected from transport stream data currently processed by the decoder.

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