JP3705733B2 - Manufacturing method of semiconductor device - Google Patents

Description

となる。
【０１２０】
ところで、∂ｆ_ｃ(ｒ_ｉｊ)／∂ｒ_ｉｊは
∂ｆ_ｃ(ｒ_ｉｊ)／∂ｒ_ｉｊ＝(−π／４Ｄ)ｃｏｓ{(π／２)(ｒ−Ｒ)／Ｄ}
（Ｒ−Ｄ＜ｒ＜Ｒ＋Ｄ）
∂ｆ_ｃ(ｒ_ｉｊ)／∂ｒ_ｉｊ＝０ （その他の場合） …（１７）
また、

以上はｘ方向について演算したものなので、これらの他にｙ方向や、ｚ方向のものも用意する必要がある。その場合それぞれの最終変形式に於けるｘを単にｙやｚに変化させれば良い。
【０１２１】
さらに、本発明者は計算を進めた。定積計算とは、原子の運動があっても系の全体体積を一定に保つものである。上記今まで述べてきた手法は、定積計算であり、体積変化には格段の注意を払っていない。しかし、例えば再結晶化固相成長はおおむね体積変化を伴う。この場合、一般的には、運動エネルギからなる内部エネルギと、さらにポテンシャルエネルギと、エントロピ及び体積等を考慮したラグランジアンに戻り、ラグランジアンに対する運動方程式を立てる必要がある。ラグランジアンは次の様に記述できる。
【０１２２】
即ち、
Ｌ(ｒ_ｉ、∂_ｔ、Ｖ、∂Ｖ／∂ｔ)＝(１／２)Σｍ(∂ｒ_ｉ／∂ｔ)^２＋{(１／２)Ｍ(∂Ｖ／∂ｔ)^２}−Ｐ_ＥＶ
である。
【０１２３】
ここでＰＥは外部圧力であり、定圧計算の場合は、内部圧力がこれに等しくなる様に体積Ｖが変動する。またＭは仮想質量である。これを基にラグランジアンに対する運動方程式を立てる。
【０１２４】
即ち
(∂Ｌ(ｑｊ，ｑ´ｊ)／∂ｑｊ)−ｄ(∂Ｌ／∂ｑ´ｊ)／ｄｔ)＝０
である。
【０１２５】
この式を基に計算を進めれば良い。本発明者はこの部分についても厳密な作業を進めた。
【０１２６】
本システムは上述したように個々のＳｉ原子の運動を厳密に調べるものである。従って基本的な出力は個々粒子の各時間における、位置、速度、力等であるが、もっとマクロ的な諸量を算出することもできる。即ち、その一例として、熱伝導率をも求めることが出来る。本発明者はこの熱伝導率を算出する事によってその精度及び基本動作を検討した。また、このシステムでは単結晶を有限の温度として扱える様に工夫した。従来の演算方式では単結晶を絶対零度とするものがあったがこれでは熱流束が無限大となり、正確な伝導率の計算は出来なかった。今回、本発明者は「熱浴」を結晶の両端に付加し得るようにし、エネルギのやりとりを管理した。計算の結果、図１３８に示す様に、１８０Ｗａｔｔ／ｍｅｔｅｒ／Ｋｅｌｖｉｎの値を得ている。これは一般の文献によれば１４８〜１５０Ｗａｔｔ／ｍｅｔｅｒ／Ｋｅｌｖｉｎであるので、２０％程度の誤差範囲内でほぼ満足な値である。
【０１２７】
まず、このシミュレータを用いて、酸化膜上の非晶質薄膜の各粒子の時々刻々の運動を克明に検討した。例えば、６００℃において結晶成長が進んでいる最中の成長端の各粒子の運動を図１３９に示す。非晶質薄膜中の原子密度が成長端の付近で低くなっていることがわかる。
【０１２８】
上記シミュレータを用いて解析した結果を以下に記す。
【０１２９】
まずこのシミュレータを用いて、酸化膜上の非晶質薄膜の各粒子の時々刻々の運動を克明に検討した。その結果を表１に示す。
【０１３０】

特に計算では、Ｓｉ原子の搖れの分布からまず、算術平均寸法を求め、この値からのズレの２乗和の平方根を∂ｘで表現してみた。この∂ｘの値の深さ方向の平均が、上述してきた平均原子間距離に相当するものである。また、表１は非晶質薄膜の再結晶化直前の表面層からほぼ１オングストローム程度の深さまでの粒子を対象にして算出したものである。表１からわかる様に、例えば６００℃においては、∂ｘは０．３１３５オングストロームであり、他方、非晶質薄膜上に酸化膜を被着させた状態での再結晶化直前の∂ｘの値を求めたのが、下段の値である。即ち、６００℃では０．１７９２オングストロームである。ここでも、表面層からほぼ１オングストローム程度の深さまでの粒子を対象にして算出したものである。
【０１３１】
上記２つの値から比較するとわかる様に、明らかに酸化膜が表面に被着していると、原子の揺らぎ寸法は小さくなっていることがよく分かる。この∂ｘの変動の影響範囲を求めたところ、６００℃程度であれば、ほぼ２００オングストローム程度まで残存することが分かった。
【０１３２】
さらに計算を進め、５２５℃で表１に示す様に、表面酸化膜が被着していない時は、∂ｘ＝０．３０１１オングストロームであり、表面酸化膜が被着している時は、∂ｘ＝０．１７００オングストロームである。さらに４００℃では、表１に示す様に、表面酸化膜が被着していない時は、∂ｘ＝０．２７８２オングストロームであり、表面酸化膜が被着している時は、∂ｘ＝０．１５４２オングストロームである。
【０１３３】
このシミュレーション結果の指摘するところに従って作成した解析してみると次の様に解釈できる。即ち、半導体薄膜が、上記の様に、薄くなると、平均原子間距離が増大し、原子が非常に動き易い状態になるのである。従って、この様な状態では、「種」部から非常に高速に再結晶化するだけでなく、非常に良質な結晶が得られるわけである。図６（ａ）および（ｂ）に本発明による、膜厚と平均原子間隔の算出値と実行値を示す。図６の横軸は膜厚の深さ方向を示し、縦軸は平均原子間隔距離を示している。膜厚が薄くなるほど、平均原子間距離が大きくなるのがわかる。
【０１３４】
また、「種」部が無い状態の場合には、非晶質膜は、順次凝固して行き粒状になることが確認できた。このとき、本発明者らの計算によれば、非晶質膜が一端、凝固を始め、粒状になり出すと、内部エネルギのはけ口が無くなるので、その分だけ、温度が若干上昇し、再結晶化が一層促進されることが見いだされた。
【０１３５】
試作したシミュレータの予想では、再結晶化前では、膜厚が薄くなるほど、非晶質膜表面及び膜中は結合状態が「緩んで」おり、下地界面のみが、その構造情報を与えている。
【０１３６】
また、本発明者等は、なぜこのように、粒状になるかについても、上記シミュレータを用いて解折した。その結果、内部エネルギを小さくしようとする力によるものであることが確認できた。
【０１３７】
以上のことから、本発明者の検討結果では、得られる単結晶膜の膜質と成膜ガス中の酸素分圧との関連は全くなく、別の現象であることを突き止めた。本発明者等の提案する方法によれば、非常に良好な単結晶が得られており、双晶等は全く認められていない。
【０１３８】
また、「種」部がない状態の場合には本発明者らの計算によれば、表面側から結晶化が始まり、下方に向かって結晶化が進行し、結晶成長端の先に、低原子密度領域が発生することが見出だされた。また同時にシミュレータを用い、低原子密度領域で引っ張り歪みが発生していることも見出だした。
【０１３９】
さらにまた、非晶質薄膜を６００℃程度の温度に加熱すると再結晶化が開始される。このとき成長端付近の非晶質中には原子密度が低い領域が形成される。もともと非晶質膜が一般的成膜条件のＣＶＤ法などにおいて成膜されると単結晶よりも密度が低く、平均原子間隔が大きくなる。再結晶化の際には、もとの状態よりも密度を高める必要があるため、非晶質膜側の原子が結晶側に多めに引き寄せられるためである。結晶化が進むほど、結晶化端での低密度化は顕著になる。しかしあらかじめ、単結晶とほぼ等しい平均原子間隔の非晶質を用意すると、低密度領域は出現しないことになる。従って結晶化距離が遠くまで伸長することになる。
【０１４０】
これを証明するために、次に示すような実験を行った。まず図１４０に示すように（１００）シリコン基板上に絶縁膜を形成しこの一部を開口しシリコン基板を種とした試料を用い、従来の堆積条件で５２５℃、ＳｉＨ_４分圧１Ｔｏｒｒで膜厚２００ｎｍのアモルファスシリコン膜を堆積し、６００℃の熱処理をおこない［１００］方向の成長について測定した。
【０１４１】
これを光学顕微鏡で測定した結果を図１４１（ａ）に示す。この図は試料を真上から撮影した典型的な光学顕微鏡写真であるが、白い領域がすでに結晶化が進み単結晶になった領域である。１μｍまで再現性よく「種」から均一に伸びるが、さらに長く熱処理を行うと成長端が波状になってくることがわかった。図１４１（ｂ）は６００℃５分間の熱処理後写真撮影を行う手順を数回繰り返し、横方向に固相成長していく時の成長端の移動から求めた典型的な成長距離の時間依存性を示す。図中の直線は原点を通らないが、成長のはじめにまず「種」から真上に伸び、次に横にのびはじめるため、上に伸びている時間だけ横に伸び始めるのが遅れていると考えられる。図中にひいた各々の直線の傾きから成長速度を求めると、ａおよびｂで多少ばらつきがみられるが、１．５〜２．０μｍまでは成長速度１００ｎｍ／分で進み、その後その１／４まで成長速度が遅くなる。一旦成長が遅れ始めた場所では成長速度は回復せず成長端は波状になる。そして最後は「種」以外のところから発生した結晶とぶつかって成長が止まる。
【０１４２】
次に、この成長途中の成長端（アモルファスシリコンと結晶との界面）を断面の透過電子顕微鏡観察（ＴＥＭ）で詳細に解析した。典型的な例として０．５μｍまで成長させたものと２μｍまで成長させたもの成長端の断面写真を図１４２、１４３、１４４、１４５に示す。この結果これらはそれぞれ（１１０）シリコン面優先成長モードと（１１１）シリコン面優先成長モードであることを見出だした。
【０１４３】
これを図１４６に模式図で示す。すなわち［１００］方向に横方向成長するに従い優先成長面が変化していくことを見出だした。
【０１４４】
さらに本発明者らは、この膜内の応力を顕微ラマン法を用いて測定した。この結果図１４７に示すように、「種」ではほとんど応力がみられず「種」から１μｍ程度離れたところで３×１０^９ｄｙｎ／ｃｍ^２にまで達していることがわかった。
【０１４５】
これらの事実から、（１１０）シリコン面から（１１１）シリコン面への優先成長面の変化について以下のように考察した。
【０１４６】
まず、シリコンの剪断降伏応力についてはこの結晶化を進めている温度では、２〜３×１０^９ｄｙｎ／ｃｍ^２と思われる。この値は「種」から０．５μｍ以上横に成長した位置で発生するとみられる。この応力によって（１１１）シリコン面のずれが起こり（１１１）シリコン面の優先成長に変化していくと考えた。とくにこの考えでは成長が進むと、（１１１）双晶が引き続き起こるので、１μｍ以降では応力は一定値になり、しかも結晶性は回復しないはずである。事実、断面ＴＥＭで観察すると図２６で示したように双晶が見えている。また若干寸法位置に誤差はあるが、成長速度の変化する点が（１１１）面優先成長モードの発生位置に相当している。
【０１４７】
このように膜中の応力が結晶成長に極めて不利であることを発見し、この応力を低減すべく、応力発生の原因を種々考察した。この結果、応力は「種」部にはみられず成長に伴い増加している。そこで膜が結晶化するときの体積変化がその原因の１つであることに気付きこれに着目した。
【０１４８】
膜が成長するに従い体積が変化するということは、同じ元素で構成されていても単結晶状態と非晶質状態で原子間の結合距離が変わる事によると考えられる。そこで非晶質状態でも単結晶の状態と同じ平均原子間隔にしておけば応力が生じないはずであると考えた。
【０１４９】
このような予測から、単結晶の平均原子間隔にほぼ一致するような原子間隔の非晶質薄膜を形成して横方向固相成長を行ったところ、予測通り（１１０）面優先成長が１０μｍ以上も続き、双晶など結晶欠陥がなく結晶性の良好な単結晶薄膜を得ることができた。
【０１５０】
このように、非晶質膜が、所謂「種」になる単結晶露出部分に接触していると、その「種」結晶から、一気に高速で再結晶化し、不随意に再結晶化する部分が発生する迄に、再結晶化寸法領域を拡大できるわけである。
【０１５１】
また、他方、非晶質膜が、所謂上記「種」になる単結晶露出部分に接着していない場合は、一定の膜厚以下の薄い膜を用意した場合、非晶質部分は、個々に、結晶成長しながら凝集し、粒状の欠陥の無い単結晶になる。
【０１５２】
本発明は、原子間距離に着目した全く新しい方法を提供している。この方法による効果は、今までにない現象を応用しているので、学問的にはまだ完全に解明されるに至っていないが、現段階では、上記の様に説明できる。
【０１５３】
【発明の実施の形態】
本発明では、非晶質半導体薄膜を基板あるいは絶縁膜上に堆積するにあたり、特に、その膜を構成する主元素からなる非晶質膜の平均原子間隔分布が、単結晶の平均原子間隔分布にほぼ一致するように形成し、これに再結晶化エネルギーを付与し固相成長を行い単結晶半導体薄膜を形成する。
【０１５４】
以下、実施例を用いて図面を参照しつつ詳細に説明する。
【０１５５】
まず、第１の参考例ではＳｉ単結晶薄膜を得るにあたり、非晶質Ｓｉ膜の平均原子間隔を、予め、Ｓｉ単結晶の平均原子間隔の１．０２倍以上からなる膜を用い、非晶質膜の表面に酸化膜の成長付着を抑止し固相成長直前まで原子間隔を緩めるため、非酸化性雰囲気であるＮ_２雰囲気にして、熱処理した。
【０１５６】
図２は、本発明の第１の参考例の薄膜形成装置の概略を示す図である。この装置は、チャンバー１０１と、膜堆積用の原料ガス導入口１０２と、排気口１０３と、薄膜を形成すべき試料を載置する試料台１０４とを具備している。本参考例では、例えば原料ガスとして水素Ｈ_２やＳｉＨ_４あるいはジシラン等を導入するようになっており、また必要に応じてドーピングガスも導入可能である。図では簡略化のため、導入口は１つになっているが、これも必要に応じて試料台近傍まで別々に導入するようにしても良い。試料台１０４は加熱機構を具備しており、温度は適宜上昇あるいは降下できるようになっている。さらにここでは結晶性を判定するための評価装置（特殊ＲＥＥＨＤ装置）を具備しており、試料表面にビームを照射するビーム照射手段１０５と、試料表面からの反射電子を受ける受光管１０６とによって、「平均原子間隔」を高精度にモニタすることができるようになっている。このビーム照射手段および受光管は、試料表面に非常に小さい角度で入射及び反射させることができ、また適宜角度を変更できる。さらに上方には、結晶性評価装置の一つである、特殊ラマン分光器１０７が設けられている。この装置を用いて薄膜形成を行う方法について説明する。図３（ａ）および（ｂ）は、本発明の第１の参考例の膜堆積のシーケンスの概略を示す図である。図３中横軸は時刻であり、縦軸は温度である。図４（ａ）乃至（ｃ）は薄膜形成工程を示す図である。ここで縦軸の温度は図２の試料台１０４に付着させた熱電対で測定した。勿論上記熱電対は十分較正をしたものを用いている。
【０１５７】
まず、図４（ａ）に示すように、ｐ型の単結晶（１００）シリコン基板２０１表面に予め酸化シリコン膜２０２を堆積させ、フォトリソグラフィにより開口部２０３を作成した。そして薄膜の堆積に先立ち、図３（ａ）および（ｂ）の点Ｔ１以前の時点で基板等の清浄化を行うため、所定の温度及びガス組成で処理をした。
【０１５８】
引き続き、図４（ｂ）に示すように膜厚３１５オングストロームの非晶質シリコン膜２０４を堆積する。図３では点Ｔ１から点Ｔ２の間が所謂成膜工程に相当し、例えばこの参考例１では５２５℃であった。
【０１５９】
そしてこの後窒素Ｎ_２雰囲気中で再結晶化のための熱処理を行う。これは図３中時点Ｔ３からＴ４に相当し温度は例えば６００℃であった。しかる後に温度を降下させ、時点Ｔ５以降で取りだす。このようにして図４（ｃ）に示すように単結晶シリコン膜２０５が得られる。ここで、点１から点Ｔ２の成膜を、温度及びガス組成を変化させて行った結果、成膜速度Ｒが下式を満たす条件下でおこなった場合に、平均原子間距離が１．０２以上の膜が得られた。
【０１６０】
ｌｏｇＲ（Å／ｍｉｎ）≧−１０６１４／τ（Ｋ）＋１４．８５７
この条件が示す領域を図５に記す。この条件以外の領域では、平均原子間隔が１．０２を上回る膜は成膜できなかった。
【０１６１】
本参考例では、平均原子間隔を、シリコン単結晶の１．０２倍以上を保持するため、非晶質シリコン膜２０４の表面に酸化膜が付着しないように、図２に示すチャンバ１０１内で、真空排気した状態で保持した。そして、そのまま図３のＴ３からＴ４に示す時点に相当する６００℃で再結晶化させた。
【０１６２】
図３（ｂ）には、例えばここで用いた膜質の変遷の概略を示す。膜質は例えば図２に示した、特殊ＲＨＥＥＤ装置１０５、１０６及び特殊ラマン分光器１０７を用いて評価した。測定した結果を図３（ｂ）に示す。横軸は時間の経過を示し、縦軸は平均原子間隔を示す。Ｔ２すなわち成膜終了の時点では、酸化シリコン膜２０２上の非晶質シリコン膜２０４の平均原子間隔は、シリコン単結晶に比較して１．０２倍であった。また時点Ｔ５は、再結晶化した後に相当し、平均原子間隔は、シリコン単結晶に比較して１．００となっている。
【０１６３】
この後、図２のチャンバ内でその膜質がどのようになっているかを評価した。評価結果を図６に示す。図６（ａ）は測定原理を示す図である。図６（ｂ）から明らかなように、平均原子間距離は表面から８０ｎｍ程度までは１．０２以上であり、さらに深くなると極めて小さくなることがわかる。また横方向固相成長速度の測定結果を図７に示す。横軸は再結晶化時間をしめす。これは換言すれば、図３の時点Ｔ３からＴ４に相当するものである。縦軸は横方向再結晶化距離である。この横方向距離の寸法は、長ければ長いほどＳＯＩ素子としての利用に適するわけである。そしてまた、この再結晶化領域に結晶欠陥が極力少ない方が、ＳＯＩ素子への応用展開に有利になるわけである。図７の図中の曲線ａは、上記示してきた参考例に相当するものである。図７中の曲線ｂ、ｃ、ｄは、比較の為に作成した、従来方法に依るもので、いずれも膜厚２００ｎｍの非晶質膜を堆積し、格段の注意は払わず、途中で大気に曝した。その後、別の炉に入れ、Ｎ_２雰囲気でアニールし、６００℃１時間の熱処理を行ったものである。この時の平均原子間隔は１．００１であった。このようにして再結晶化された従来例の場合、再結晶化速度が遅く双晶も多く含んでいた。
【０１６４】
図からあきらかなように、本発明参考例の方法によれば、従来例の結果に比べて、約１．７倍の勾配で成長している。この勾配、即ち成長速度が早ければ早いほど、結晶性が良く、遠くまでのびるわけである。
【０１６５】
既に作用の項で述べたように、非晶質から単結晶に再結晶化して行く過程では、不随意に結晶核が発生する部分があると、結晶性が不良になるばかりでなく、再結晶化寸法が伸びない等の不都合が生じる。従って、結晶性の改善及び結晶距離の伸長を目指すには、出来るだけ高速で再結晶化させることである。本発明の参考例の結果は、上記データでもわかる様に、「高速性」と、「結晶性」の両面に大きな成果を見出している。従来方法では、不純物を高濃度に添加したり、圧力を加えたりする手段を用いているが、本発明者等は、原子間距離に着目した全く新しい方法を提供している。
【０１６６】
このように非晶質シリコン膜表面を清浄にし、膜厚等を予め薄くすることにより、原子が一応結合しているが、原子間の結合が緩んだ自由な状態を作り出しており、これが結果的には、平均原子間距離の寸法増大につながる。そして平均原子間距離の増大を保ったまま、熱処理を行うと非晶質シリコン膜表面の原子は動き易くなる。そして、「種」になる単結晶露出部分から、一気に高速で再結晶化し、不随意に再結晶化する部分が発生する迄に再結晶化寸法領域を拡大することができた。
【０１６７】
なお、本参考例では、再結晶化工程に於いて、その雰囲気をＮ_２としたが、これを水素雰囲気やアルゴン雰囲気としても良い。また、本参考例では固相成長温度を堆積温度よりも高温としたが逆に固相成長温度を低温として長時間熱処理してもよく、また光で固相成長を促進させてもよい。また熱処理以外にＥＢなどを用いても良い。
【０１６８】
次に本発明の第２の参考例について説明する。
【０１６９】
集積回路の微細化にともない半導体素子の大きさは限界に近づき、単に２次元的に縮小するだけでなく３次元的な配慮、すなわちチャネル領域の縮小を単にソースとドレインの間隔を狭めるというだけでなく、深さ方向にも縮小することが必要になってきた。例えばＭＯＳでは、チャネルの間隔が〜０．１μｍ程度に狭くなってくると、実際に電流の流れるチャネルの表面近傍だけを低濃度層にする必要も生じてきており、今後のデバイスサイズの縮小にはこのような極薄い単結晶層の形成技術が不可欠となってくる。さらに、バイポーラートランジスタにおいてもベース領域を薄くすることで高速動作が可能となるなど本発明の応用範囲広い。
【０１７０】
図８は本発明の第２の参考例としてバイポーラトランジスタのベース領域に用いることができる薄い単結晶シリコン層の製造方法を示したものである。
【０１７１】
まず図８（ａ）に示すように、シリコン基板の表面を０．１％ＨＦ水溶液で洗浄して、表面の自然酸化膜２を除去し、基板の表面を清浄にする。この基板を図２の装置に移す。
【０１７２】
つぎに、水素ガスを１００００ＳＣＣＭ、１Ｔｏｒｒ流しながら５２５℃に温度を上げる。そして、５２５℃に保持したままシランガス５００ＳＣＣＭ、３Ｔｏｒｒを２分間流し、シランガスの熱分解反応により基板上に非晶質膜を堆積した。このときの非晶質膜の平均原子間隔は単結晶の１．０２倍となった。但しこの平均原子間隔は別途基板上に設けた酸化シリコン膜の上に堆積した非晶質膜を用いてモニターした。非晶質膜３の膜厚を８０ｎｍ以下にすると平均原子間隔は単結晶の１．０２倍から徐々に増大した。
【０１７３】
またシランガスと同時にジボランを流すとｐ型の半導体層ができ、ホスフィンを同時に流すとｎ型の半導体膜ができる。ここではシランガスのみを流した場合を示す。
【０１７４】
このようにして、シランガスを流し非晶質シリコン膜３を成膜した後、再び高純度の水素ガスを流して非晶質シリコン膜の表面が酸化されないようにしながら６００℃に昇温し、１０時間保持した。なお、水素ガスの代わりにアルゴンガス、ヘリウムガス、窒素ガスなどの高純度ガスを用いても同様であり、さらに、１０^−４Ｔｏｒｒ以下の高真空に維持しても良い。このように、６００℃の非酸化性雰囲気で熱処理している間に図８（ｃ）に示すように固相成長により下地シリコン基板から結晶化が起こり、非晶質シリコン３は単結晶シリコン層４になる。この時、非晶質シリコンの平均原子間隔は単結晶の１．０２倍と緩んだ状態にあり、図１に示したように非晶質表面からシリコン原子が自由に動いて、固相成長するに従って余ったシリコン原子が表面に抜けたり、足りないシリコン原子が表面から補われるため、結晶欠陥の無い高品質の単結晶を成長させることができたものと思われる。
【０１７５】
ここでシリコン原子の移動できる範囲、表面から補給の届く範囲、あるいは表面の活性なシリコン原子の結合ポテンシャルの及ぶ範囲を測定するため、膜厚を変化させて非晶質膜の平均原子間隔を変化させ、他の条件はまったく同様にして欠陥密度を測定した。すなわち非晶質シリコン膜の成長と固相成長は同一のチャンバー内で行うようにし表面に酸化膜の無い状態で固相成長させた場合の単結晶膜と、種々の膜厚の非晶質シリコン膜を成膜し従来通り一旦別の反応炉に移して表面に自然酸化膜を形成した後固相成長した場合との単結晶膜の欠陥密度の差を測定した。その結果を図９に示す。この図からあきらかなように、非晶質シリコン膜の膜厚を８０ｎｍ以下にするのが望ましく、８０ｎｍ以上にするとこれらの効果が及ばなくなり結晶欠陥がみられるようになる。
【０１７６】
次に、膜厚を変えて非晶質膜の平均原子間隔を変化させ、酸化膜のない自由表面を維持した場合（曲線ａ）と、非晶質膜成膜後一旦大気中に取り出したり、固相成長中の雰囲気を酸化雰囲気にしたりすることで非晶質膜表面に酸化膜が存在する場合（曲線ｂ）と、エレクトロンモビリティと非晶質膜の膜厚との関係を測定した結果を図１０に示す。この場合酸化膜が存在しない形成方法である本発明膜厚が８０ｎｍ以下の場合、すなわち非晶質膜の平均原子間隔が単結晶の１．０２倍以上の場合には、エレクトロンモビリティは大きく、これを越えると小さくなるのに対し、表面に酸化膜が存在する従来の形成方法の場合はエレクトロンモビリティが小さい。この図から酸化膜の存在しないこと、平均原子間隔を単結晶の１．０２倍以上に保つことがエレクトロンモビリティに極めて重要な役割をはたすことがわかる。比較のため図１３４に非晶質膜の表面が酸化されており、平均原子間隔が単結晶の１．０２倍より小さい場合の固相成長の様子を説明したものを示したがこの場合、非晶質膜は原子がランダムに配置されており、結晶成長が進むと規則性のある結晶格子位置にそれぞれの原子が収まっていく。この時、ランダムな配置をしている原子の数と規則性のある格子位置に入っている原子の数は一致していない。これは局所的にはさらにひどく、図１３５に示したように結晶成長に伴い格子の間に余ったり、格子位置にあるべき原子が足りなくなったりしてしまう。にもかかわらず、それぞれの原子は非晶質といえども互いに結晶をもっておりモビリティは小さく全く自由に動けるわけではない。そこで、これらは格子歪や結晶欠陥、双晶などとして単結晶膜に残ってしまう。このため従来の方法の場合では、非晶質成膜後、固相成長で結晶化をすると単結晶中に多数の結晶欠陥存在する。これらは双晶や積層欠陥と呼ばれるものであり、点欠陥や転位ネット、らせん転位なども多く含む。
【０１７７】
次に本発明の第３の参考例について説明する。なお前記参考例では水素雰囲気中で非晶質シリコン膜を成長したが、この例ではターボ分子ポンプを使って１×１０^−４Ｔｏｒｒの高真空に排気しながら、熱処理して単結晶化する。すなわちシランガスの熱分解を用い、圧力３Ｔｏｒｒ、流量２００ｓｃｃｍ、５２５℃において堆積速度１０ｎｍ／分で非晶質シリコンを堆積し、５分間シランガスを流し、シランガスを止めた後、ターボ分子ポンプを使って１×１０^−４Ｔｏｒｒの真空に排気しながら、６００℃、１０時間熱処理して単結晶化し５０ｎｍの単結晶薄膜を成膜した。従来はロータリーポンプを用いて１０^−２Ｔｏｒｒ程度に排気しており、微量の酸素が自然酸化膜を形成していたが、ターボ分子ポンプの導入により極めて高真空を得ることができる。
【０１７８】
この場合、透過電子顕微鏡（ＴＥＭ）では、結晶欠陥が観察されず、膜厚を変化させたが、膜厚が８０ｎｍ以下で、平均原子間隔が単結晶の１．０２倍以上の膜ではいずれもＴＥＭで結晶欠陥が観察されなかった。
【０１７９】
次に本発明の第４の参考例について説明する。
【０１８０】
この例では、キャリア濃度１×１０^１７ｃｍ^−３になるように、非晶質膜成膜時にシランガスと同時にホスフィンを流して形成した膜の単結晶化後の移動度を、Ｈａｌｌ測定で求めた結果，図１０に示したのと同様になった。従来のように表面に酸化膜があると薄い非晶質を用いても移動度の高い結晶性の良い単結晶は得られなかったのに対し、本発明の方法を用いると、膜厚が８０ｎｍ以下すなわち平均原子間隔が単結晶の１．０２倍以上である非晶質膜を用いて固相成長させると結晶性が急激に良くなり、単結晶シリコンで得られる移動度の限界まで移動度は向上させることができた。
【０１８１】
次に本発明の第５の参考例について説明する。
【０１８２】
この例では熱処理中の真空度による依存性を測定するため、前記参考例と同様にして非晶質シリコンを５０ｎｍ成膜した後、真空度を変えて６００℃、１０時間熱処理した膜のＨａｌｌ移動度を測定した。この成膜直後の膜の平均原子間隔は単結晶の１．０２５倍であった。この結果、真空度が１×１０^−３Ｔｏｒｒより悪くなると図１１に示すように結晶化後の膜中の移動度は急激に低下した。これらの膜の表面を熱処理中にＲＨＥＥＤ（Ｒｅｆｌｅｃｔｉｏｎ Ｈｉｇｈ Ｅｎｅｒｇｙ Ｅｌｅｃｔｒｏｎ Ｄｉｆｒａｃｔｉｏｎ）により観察すると１×１０^−３Ｔｏｒｒより悪い真空では、結晶化が終わってもシリコンの結晶を示す回折像が得られず、表面が酸化物が覆われていることも判明した。固相成長前後の平均原子間隔の時間変化を調べた結果成膜直後に単結晶の１．０３倍であったものの炉内に放置されている間に徐々に平均原子間隔が縮み、固相成長直前には１．００５まで縮んでいることが判明した。これは本発明の平均原子間隔の縮みの効果を裏付ける証拠の一つとして挙げられる。
【０１８３】
さらに本発明の第６の参考例として、固相成長中の非晶質シリコン表面の酸化を防ぐために雰囲気を還元雰囲気とする方法について説明する。配管のつなぎ目などからの空気の漏れあるいは炉内の壁の吸着分子の再蒸発などによって、炉の中には酸素、水分などが漂っており、これを水素ガスで希釈あるいは押し流すことによって還元雰囲気とした。ここで、水素ガスの圧力を高く、流量を大きくすると表面の酸化が抑止され、堆積された非晶質膜の平均原子間隔が固相成長直前まで維持されるため、単結晶中の欠陥がなくなり、移動度が向上してくる。ここで下地基板として砒素濃度２×１０^１９ｃｍ^−３のｎ型シリコン基板を用い、この上層に膜厚２０ｎｍのイントリンシックの非晶質シリコン膜を形成し、上記水素を用いた還元雰囲気中で、５８０℃、１時間の熱処理を行い単結晶シリコン膜を形成した。堆積した２０ｎｍの非晶質シリコン膜の平均原子間隔は単結晶の１．０３倍であった。但しこの値は別途堆積した酸化シリコン上の非晶質膜を用いてモニターした。
【０１８４】
このとき水素流量を変化させ、水素流量とエレクトロンモビリティとの関係を測定した結果を図１２に示す。この図からもあきらかなように、水素流量が増大するとエレクトロンモビリティが増大することがわかる。
【０１８５】
なお還元性の水素雰囲気以外にアルゴンガス、ヘリウムガス、窒素ガスなどの不活性ガスを流しても同様の効果が得られた。
【０１８６】
単結晶化を終了した後の不純物分布をＳＩＭＳで分析した結果の一例を図１３に示す。下地基板は砒素濃度２×１０^１９ｃｍ^−３のｎ型半導体であるが、その上に本発明の方法によって形成した２０ｎｍの単結晶薄膜はＳＩＭＳの検出限界以下の導電性不純物を含まないイントリンシックのままであった。
【０１８７】
以上シリコンを含むガスの熱分解による化学気相堆積法（ＣＶＤ法）を例に示したが、非晶質シリコン成膜に蒸着法、スパッタ法などを用いても同様の効果を得ることができた。また、シリコン以外にもゲルマニウムでも同様の効果を得ることができることはいうまでもない。
【０１８８】
本発明の第７の参考例としてこの装置を用いてＭＯＳ型トランジスタを形成する方法について説明する。
【０１８９】
まず、図１４（ａ）に示すようにシリコン基板表面１１に、一層目の半導体装置を形成した後、ＣＶＤ法によりシリコン基板全面にシリコン酸化膜１２を約１μｍ堆積する。ここで一層目の半導体装置はゲート電極６とソースドレイン領域７とからなるＭＯＳＦＥＴであり、８は素子分離絶縁膜である。
【０１９０】
次に図１４（ｂ）に示すように、レジストを塗布し露光現像した後、反応性イオンエッチングにより所望領域のシリコン酸化膜１２をエッチングし、積層部分単結晶化の際に種結晶となるシリコン基板表面を露出させ、残るレジストを剥ぐ。そしてシリコン基板を酸等で洗浄し、露出しているシリコン表面を清浄に保ちながら非晶質シリコンの反応炉内に搬入する。
【０１９１】
形成に際してはまず、ウェハを反応炉に搬入した後、反応炉内を真空引きする。後で固相成長をさせる時に種結晶となる露出シリコン面には、自然酸化膜が成長しないよう細心の注意をする。そして基板温度を４５０〜５５０℃に上げる。
【０１９２】
ここで非晶質シリコンの堆積をシランガスを用いて行う場合、良質の非晶質シリコンを得るために基板温度は５００〜５５０℃の間に保ち、ジシランガスを用いる場合には４５０〜５５０℃の間に保つ。シランあるいはジシランガスを反応炉内に導入し、これらシラン系ガスの熱分解反応により、基板全面に非晶質シリコン１３を堆積する（図１４（ｃ））。この時，シラン系ガスにジボランあるいはホスフィンを混入し、ボロンあるいはリンを含む非晶質シリコン膜を堆積しても良い。この非晶質シリコン層の膜厚は２０ｎｍ以下とする。このようにして２０ｎｍ以下の所望の膜厚が得られた段階で、シラン系ガスの反応炉内への導入を止め炉内温度を低下させる。堆積速度はガス流量等で制御し前記の堆積速度式を満たす条件で成膜する。
【０１９３】
続いて、継続して装置内を真空引きし、１０^−７Ｔｏｒｒ以下の高真空にして、炉内温度を６００℃程度まで昇温し薄い非晶質シリコン膜を結晶化し、単結晶シリコン層１４を形成する（図１４（ｄ））。この工程で、基板シリコンと接している面を固相成長のシードとして非晶質シリコンが横方向に単結晶化する。高真空中では、非晶質膜の平均原子間隔は堆積時の値に維持されるため、非晶質膜の結合は緩い状態に保たれており、非晶質及び単結晶シリコンの表面のシリコン原子は結合が不完全であるため非常に動き易く、表面をマイグレートして移動する。さらにまた２０ｎｍ以下の薄膜にすることにより、表面マイグレートの影響が膜中全体に及び、膜中の原子全体が非常に動き易い状態に保たれる。そのため結晶化速度が大きく、単結晶化を妨げる無作為の結晶核生成が起こる前に、シードから遠くまで単結晶化される。例えば６００℃で結晶化させた場合、２０μｍの長さまで単結晶化した。結晶成長させる温度はさらに低い温度でも良い。しかしその場合より長い時間が必要となる。例えば５８０℃では２０時間以上必要であった。また、非晶質シリコン中に濃度１０^２０ｃｍ^−３程度のボロンあるいはリンを導入すると、結晶化速度が増加し、単結晶化領域は１００μｍとなった。さらに、下地の絶縁膜表面にあらかじめ高濃度のリン、ボロンなどシリコンに対して電気的活性な元素を入れておくとさらに広い領域の単結晶化を進めることができた。また絶縁膜そのものをリン、ボロンなどを含むガラスで形成しても同様の効果を得ることができた。これらの工夫により表面の原子のマイグレーションに加え、下の方の界面の原子の移動も起き易くすることで結晶成長の速度が速くなり、より広く単結晶化が進んだと考えられる。
【０１９４】
また、非晶質シリコンを単結晶化する前に反応炉から一旦搬出して、イオン注入によりボロンやリンを導入するようにしても良い。この場合には、炉内に再度搬入した後、固相成長の前に自然酸化膜の剥離を再び行い、平均原子間隔を再度緩める必要がある。
【０１９５】
またこの変形例として、単結晶化前に、非晶質層を所望の形状に整形しても良い。この場合には、レジストを塗布し、露光現像した後、ＲＩＥでシリコンをエッチングし、残るレジストを剥離する。また固相成長速度は成長の方向で大きく異なり、＜１００＞方向が最も早いことが確認されている。そのため、非晶質層の形状は図１５に示すように＜１００＞方向に長辺がある形状にした。炉内にウェハを搬入し、非晶質シリコン上の自然酸化膜を前述の還元反応により剥離する。その後、高真空状態で固相成長を行う。
【０１９６】
以上の工程で薄くかつ高品質の単結晶シリコン薄膜１４が形成されるが特に必要がなければ、２０ｎｍ以下の膜厚の単結晶薄膜をそのまま用いて素子を形成しても良い。この場合、むしろ移動度などは大きくなり、ＮＭＯＳで１０００ｃｍ^−２／Ｖ・ｓｅｃを越えるものも得られた。ただし素子を形成する際、通常の素子と異なりソース・ドレインのコンタクト形成等に工夫を要する。まず、単結晶シリコン薄膜１４の上に絶縁膜１８を形成し、この絶縁膜１８のソース・ドレインの一方に相当する領域にコンタクトを開ける。これにはＲＩＥ、ＣＤＥ、フッ素系の水溶液などのいずれを用いても、オーバーエッチングにより単結晶膜を突き抜けるということが起きる。そこで、コンタクト抵抗を下げるために配線としては、通常用いられる多結晶シリコンではなく、タングステンシリサイドなどのシリサイドを用いた。例えばタングステンシリサイドの形成には、六フッ化タングステンと水素ガスの混合ガスなどを用いた。また、本発明を用いてコンタクト領域の単結晶薄膜の露出部分のクリーニングをしてから連続して高濃度にドープした２０ｎｍ以下の薄膜非晶質シリコンを堆積し結晶化して配線として用いても良い。いずれにしても良好なコンタクト特性が得られ前記したように高移動度の素子（トランジスタなど）を形成することができた（図１４（ｅ））。
【０１９７】
さらに本発明の第８の参考例として２回の非晶質シリコンの堆積と熱処理による結晶化を用いてより厚い単結晶層を形成する例について説明する。
【０１９８】
１回目の非晶質シリコン堆積と結晶化は図１４（ａ）乃至図１４（ｄ）に示した前記第６の参考例とまったく同様に行い図１６（ａ）乃至図１６（ｄ）に示すように単結晶シリコン膜１４を得る。
【０１９９】
この後、２回目の非晶質シリコン堆積と結晶化を行う。すなわち第１の単結晶シリコン膜形成のための熱処理後、反応炉を開けることなくそのまま反応炉温度を４５０℃〜５５０℃にして、シラン系ガスを反応炉内に導入し、膜厚２００ｎｍの非晶質シリコン膜１３ｓを堆積して（図１６（ｅ））、ガスの導入を止める。この時点ではシリコン基板１１を炉外に搬出し、別のアニール炉を用いて結晶化しても良い。そして炉内温度を６００℃程度に昇温し、図１６（ｆ）に示すように、先に結晶化した膜１４をシードとして非晶質膜を垂直方向に単結晶化する。２００ｎｍの非晶質膜１３ｓを堆積した場合、垂直方向に容易に単結晶化し単結晶シリコン膜１４が得られた。
【０２００】
この後シリコン基板を真空炉外に搬出し、ＣＶＤ法でシリコン酸化膜を堆積し、レジストを堆積して露光現像し、このレジストをマスクにして下層のシリコン酸化膜の所望領域を反応性イオンエッチングによりエッチングする。そして残りのレジストを剥離し、次にシリコン酸化膜をマスクとして単結晶化したシリコンの所望領域を反応性イオンエッチングによりエッチングする。再び、ＣＶＤ法でシリコン酸化膜２０を堆積した後、バイアススパッタ法でシリコン酸化膜を平坦化する。その後、単結晶シリコン層が露出されるまでシリコン酸化膜を湿式エッチングする（図１６（ｇ））。このようにしてシリコン酸化膜２０によって素子分離のなされた２層目の単結晶シリコン層が得られ、単結晶シリコン層１４としての合計膜厚２２０ｎｍとなる。
【０２０１】
以下は２層目のＭＯＳ型トランジスタの製造を記す。まず２層目のシリコン基板にしきい値制御のためのチャネルドーピングをし、ゲート絶縁膜となるＣＶＤシリコン酸化膜を２０ｎｍ堆積し、ゲート電極となるＣＶＤポリシリコン膜を２００ｎｍ堆積する。レジストを塗布し、露光現像し、ＲＩＥでポリシリコンをエッチングしてゲート電極を形成しさらに、ソース・ドレインとなる領域に導電性不純物をイオン注入する。ドーズ量は２層目シリコン膜の膜厚を考慮して決定する。例えば、膜厚が５０ｎｍの場合、１×１０^１５ｃｍ^−２とすると、Ａｓイオンで１×１０^２０ｃｍ^−３の高濃度が得られた。そして活性化アニールを行い、導電性不純物を活性化する。さらにＣＶＤシリコン酸化膜を堆積し、ソース・ドレイン電極形成のための開口部を設け、電極及び配線層を形成する。
【０２０２】
また、本発明においては、非晶質膜形成は、スパッタ法あるいはＵＨＶ法を用いても良い。例えば、一部シリコン基板を露出させた絶縁膜を有するシリコン基板を１０^−１０Ｔｏｒｒ以下の高真空に保持し、高純度シリコンをターゲットとして電子ビームで蒸発させ、このシリコン基板表面に蒸着させる。この時まず、蒸着により絶縁膜上に平均原子間隔１．０３倍、膜厚２０ｎｍの非晶質シリコン膜を形成した後、このシリコン基板を高真空に保持したまま６００℃で５時間以上加熱すると絶縁膜上に単結晶シリコン薄膜を形成することができた。
【０２０３】
次に本発明の第１の実施例について説明する。
【０２０４】
この例では図１７に示すように、粒状の単結晶シリコン２０５を形成することを特徴とする。ここでもやはり、参考例１と同様にシリコン単結晶薄膜を得るにあたり、非晶質シリコン膜の平均原子間隔を、予め、シリコン単結晶の平均原子間隔の１．０３倍以上からなる膜を用い、非晶質膜の表面に酸化膜の成長付着を抑止するため非酸化性雰囲気のＮ_２にして、熱処理した。
【０２０５】
膜作成の装置は、図２に示したものと同一のものを用いた。また薄膜形成のためのシーケンスは図３（ａ）と同一とした。しかし、試料構造は若干異なる形を選んだ。即ち、先の参考例１では図４に示すように酸化シリコン膜２０２に開口部２０３を設けたが、この実施例１では、図１８（ａ）乃至（ｃ）に示すように開口部を設けなかった。
【０２０６】
まず、図１８（ａ）に示すように、酸化シリコン膜２０２を形成した後、図１８（ｂ）に示すように非晶質シリコン膜２０４を堆積する。この膜厚は参考例１では３１５オングストロームであったが、ここでは２００オングストロームとした。しかし、本実施例１の文頭にも報告した様に、膜堆積直後の測定結果では、平均原子間距離は、単結晶シリコン基板のそれに対して、１．０３倍の値を得た。
【０２０７】
この後、図１８（ｃ）に示すように６００℃５時間の熱処理を行い単結晶シリコン２０５を形成する。ここで、再結晶化条件に関しては、参考例１と同一とした。即ち、表面自然酸化膜の被着を抑えるために、例えば同一炉を用いた。ここでは前述したように、非晶質シリコン膜が、再結晶化するにあたり、所謂「種」になる単結晶シリコン露出部分に接触していない様にした。その結果、図１９にＴＥＭ写真を示す様に、非晶質部分は、結晶成長しながら凝集し、欠陥の全く無い極めて良質な単結晶粒を得た。図２０にＴＥＭ写真を示す様に、その単結晶詳細観察の結果、下地の酸化シリコンに対して、垂直方向に〈００１〉シリコン軸が成長している。
【０２０８】
本発明者等は、更に、膜厚や温度、下地などを選ぶことでこの粒を、任意の大きさに揃えうることも突き止めた。ちなみに、図２１（ａ）乃至（ｃ）は、初期非晶質シリコン膜厚を２００オングストローム、１００オングストーム、５０オングストロームとした場合の結果を示す。それぞれの場合の初期非晶質の平均原子間距離は、単結晶シリコン膜のそれに対して、１．０３倍、１．０３２倍、１．０３４であった。これらは、いずれも、極めて良好な単結晶となっている。
【０２０９】
次に本発明の第２の実施例について説明する。
【０２１０】
ここではＧｅ単結晶薄膜を得るにあたり、非晶質Ｇｅ膜の平均原子間隔を、予め、Ｇｅ単結晶の平均原子間隔の１．０２倍以上からなる膜を用い、非晶質膜の表面に酸化膜の成長付着を抑止するため非酸化性雰囲気のＮ_２にして、熱処理した。膜作成の装置は、参考例１と同様図２に示したものを用いた。
【０２１１】
また膜堆積のためのシーケンスもここでは図３（ａ）と同一であった。試料構造は図２２（ａ）に示すように図１８（ａ）に示した実施例１のものと同様にした。即ち、この例でも、開口部を設けなかった。
【０２１２】
そして、膜中のゲルマニウムの平均原子間隔が、Ｇｅ単結晶の平均原子間隔の１．０２倍となるような堆積条件を用いて非晶質ゲルマニウム２０６を堆積した（図２２（ｂ）） 。このとき非晶質ゲルマニウムの膜厚は例えば１１５オングストロームであった。
【０２１３】
このあと、再結晶化に関しては、参考例１と同様にして再結晶化を行い、粒状の単結晶ゲルマニウム膜２０７を形成した（図２２（ｃ））。即ち、表面自然酸化膜の被着を抑えるために、参考例１と同様の炉を用いた。
【０２１４】
この例では、非晶質ゲルマニウム膜が、再結晶化するにあたり、所謂「種」になる単結晶露出部分に接触していないため、その結果は先の図１８に示した例と同様に、非晶質部分は、結晶成長しながら凝集し、欠陥の全く無い極めて良質な単結晶を得た。しかも一軸性の配向を得た。
【０２１５】
本発明者等は、更に、膜厚や温度、下地などを選ぶことでこの粒を、任意の大きさに揃えうることも突き止めた。
【０２１６】
すなわち、非晶質膜の平均原子間隔を単結晶の１．０２以上となるようにし、この非晶質膜の表面を自由な状態に保ち、原子が膜内で自由に動けるようにし、ケミカルポテンシャル（ギプス自由エネルギー）の変化に注目し、結晶化と同時にシリコン原子を動かし、原子を凝集させるものである。
【０２１７】
この例について実施例３としてさらに説明する。
【０２１８】
まず、図２３（ａ）に示すようにシリコン基板４１表面を９５０℃水蒸気雰囲気中で酸化し、膜厚０．１μｍの酸化シリコン膜４２を形成する。そしてＣＶＤ法により膜厚０．０２μｍの非晶質シリコン膜４３を堆積する。ここで非晶質シリコン膜はシランガス１Ｔｏｒｒ、５２５℃で２分間の成膜を行った。
【０２１９】
そして、この後シランガスを止め連続して６００℃３０分の熱処理を行い、図２３（ｂ）に示すように単結晶の粒状体４４を形成する。この時ガス清浄器を通したアルゴンガスを流し続け、非晶質シリコンの表面が酸化されるのを抑制した。この熱処理により、非晶質シリコンは結晶化すると同時に凝集し、１つ１つが単結晶の粒状体層を形成する。このときの電子顕微鏡（ＳＥＭ）写真を図２４および図２５に、断面の透過電子顕微鏡（ＴＥＭ）写真を図２６に示す。この１つ１つの粒は写真からも分かるように大きさ、間隔共に揃っている。しかもその大きさは再現性よく同じ大きさに制御されて形成される。
【０２２０】
次にこの場合に、非晶質シリコン膜の膜厚と６００℃で１時間熱処理した後の粒の大きさとの関係を測定した。この結果を図２７に示す。この図からもともとの非晶質シリコンの膜厚が厚くすると粒の大きさを大きくすることができることがわかる。
【０２２１】
また下地と非晶質シリコンとのなじみの程度により凝集したときの粒の形状を制御することも可能である。
【０２２２】
すなわちシリコン酸化膜を下地にすると１つ１つの粒は小さくなる。これに対してリン硅酸ガラス（ＰＳＧ）の場合、粒は大きく偏平になる。
【０２２３】
次に、下地をＰＳＧ膜、窒化シリコン膜、酸化シリコン膜の場合に非晶質シリコン膜の膜厚と６００℃１時間の熱処理語の粒の直径との関係を測定しその結果を図２８に示す。この結果から下地を種々選択することによっても粒の直径を制御することができることがわかる。この他、ＢＳＧ、ＢＰＳＧ、ＡｓＳＧ膜などを用いても同様に粒の大きさを大きくすることができる。
【０２２４】
さらにまた、熱処理の温度、雰囲気の酸化度によっても同様な制御を行うことができる。
【０２２５】
次に本発明の第４の実施例について説明する。
【０２２６】
まず、図２９（ａ）に示すようにシリコン基板５１表面にシランガスと酸素の混合ガスを用いてＣＶＤ法により基板温度４５０℃で、膜厚０．１μｍの酸化シリコン膜５２を形成し、さらにシランガスを用いたＣＶＤ法により膜厚０．０３μｍの非晶質シリコン膜５３を堆積する。
【０２２７】
そして、この後シランガスを止め連続して水素ガスを流しながら１時間保持すると、非晶質シリコンは結晶化し、凝集して図２９（ｂ）に示すように単結晶の粒状体５４を形成する。
【０２２８】
これを７５０℃、２０時間にわたり塩酸ガスと水蒸気の混合ガスで酸化すると表面が約０．０５μｍ周期の凹凸を有する酸化シリコン膜５５を形成する（図２９（ｃ））。
【０２２９】
この後この上層にシランガスを用いたＣＶＤ法により基板温度６３０℃で多結晶シリコン膜５６を形成する（図２９（ｄ））。
【０２３０】
これにより、表面を０．０５μｍの凹凸にして表面積を大きくした電極を形成することができる。この多結晶シリコン膜を電極として用いる場合には導電性不純物を後からイオン注入で形成しても良いが、ジボランなどのガスを同時に流して形成することもできる。このようにして全工程を８００℃以下で実施することができるため、他の領域にＭＯＳ素子等が形成されている場合にも適用することができる。
【０２３１】
さらに図２９（ｃ）の工程でシランガスによる成膜を基板温度５５０℃で行い非晶質シリコン膜を堆積し、再び図２９（ａ）に示した工程から繰り返すことにより凹凸の大きな表面を形成することができる。
【０２３２】
さらにシランガスに代えてジシランガスを用いたり、蒸着法やＭＢＥ法など他の方法で非晶質シリコン膜を形成するようにしても表面が酸化されず自由な状態を保つようにして結晶化を進めるようにすれば同様の効果を得ることができる。次に本発明の第５の実施例として、ＭＯＳキャパシタに本発明を用いる方法について説明する。
【０２３３】
まず図３０（ａ）に示すように、シリコン基板６１表面に膜厚０．０５μｍの酸化シリコン膜６２を形成し、レジストパターン６３をマスクとしてイオン６４を用いた異方性イオンエッチングにより酸化シリコン膜をエッチングする。
【０２３４】
この後図３０（ｂ）に示すようにＣＶＤ法により酸化シリコン膜６５を０．２５μｍ堆積する。
【０２３５】
そしてさらに図３０（ｃ）に示すようにレジストパターン６６を形成してイオン６７によって異方性エッチングを行う。
【０２３６】
そしてエッチングがシリコン基板６１まで進んだところでエッチングを終了する。このようにして図３０（ｄ）に示すように断面コの字状の酸化シリコン膜を形成する。ここで多少はオーバーエッチングになっても酸化シリコン膜の底が残るようにすればよい。
【０２３７】
このようにして下地の形状加工ができたところで、まず、図３０（ｅ）に示すように表面全体に、シランガスを用いたＣＶＤ法により膜厚０．０２μｍの非晶質シリコン膜６８を堆積する。
【０２３８】
そして、この後シランガスを止め連続して水素ガスを流しながら５５０℃１時間の熱処理を行うと、断面コの字状の酸化シリコン膜６５表面の非晶質シリコンは結晶化し、凝集して図３０（ｆ）に示すように単結晶の粒状体６９を形成する。ここでシリコン基板６１表面では非晶質シリコンは凝集せず単結晶シリコン基板と同様の結晶方位に固相成長し平坦な膜となる。
【０２３９】
これを７５０℃、２０時間にわたり塩酸ガスと水蒸気の混合ガスで酸化すると表面が約０．０５μｍ周期の凹凸を有する酸化シリコン膜７０を形成する（図３０（ｇ））。
【０２４０】
この後この上層にシランガスを用いたＣＶＤ法により基板温度６３０℃でキャパシタ電極としての多結晶シリコン膜７１、キャパシタ絶縁膜としての酸化シリコン膜７２、キャパシタ電極としての多結晶シリコン膜７３を形成しキャパシタを得る（図３０（ｈ））。
【０２４１】
これにより、表面を０．０５μｍの凹凸にして表面積を大きくし実効的な容量の大きいキャパシタを形成することができる。
【０２４２】
次に本発明の第９の参考例について説明する。
【０２４３】
この方法では、Ｓｉ単結晶薄膜を得るにあたり、図３１に示すようにシリコン基板１表面に開口部をもつ酸化シリコン膜２を形成しこの上層に非晶質Ｓｉ膜３を平均原子間隔が、Ｓｉ単結晶の平均原子間隔とほぼ一致するように堆積し、これをＮ_２雰囲気で、熱処理しシリコン単結晶を得るようにしている。
【０２４４】
図３２は、本発明の第９の参考例の薄膜形成装置の概略を示す図である。この装置は、チャンバー３１１にのぞき窓Ｗが形成され、この窓を介してレーザ光源３１５および分光器３１６が設置され、ラマン散乱分光法により非晶質膜の密度を、連続的に観察できるようにしたことを特徴とするものである。すなわちチャンバー３１１内に膜堆積用の原料ガス導入口３１２と、排気口３１３と、薄膜を形成すべき試料を載置する試料台３１４とを具備している。本実施例では、例えば原料ガスとして水素Ｈ_２やＳｉＨ_４あるいはジシラン等をマスフローコントローラ３１７を介して導入するようになっており、また必要に応じてドーピングガスも導入可能である。図では簡略化のため、導入口は１つになっているが、これも必要に応じて試料台近傍まで別々に導入するようにしても良い。さらにターボ分子ポンプ３１８によってチャンバー内の圧力も調整可能であり、さらにヒータ３１９によって基板温度を調整できるようになっている。
【０２４５】
この装置を用いて薄膜形成を行う方法について説明する。
【０２４６】
まず、ｐ型の単結晶（１００）シリコン基板表面に予め酸化シリコン膜を堆積させ、フォトリソグラフィにより開口部を作成した。そして薄膜の堆積に先立ち基板等の清浄化を行うため、所定の温度及びガス組成で処理をした。
【０２４７】
引き続き、分光器によって平均原子間隔を測定しながらＳｉＨ_４分圧１Ｔｏｒｒ、堆積速度７ｎｍ／分の条件で膜厚３１５オングストロームの非晶質シリコン膜を堆積する。ここで基板温度は５２５℃とした。分光器の出力から４８０ｃｍ^−１にピークを持つスペクトルを得ることができ、このようにして形成した非晶質シリコン膜の平均原子間隔は４８０ｃｍ^−１にピークを持つスペクトルを得ることができ、すなわち密度は単結晶シリコンのそれとほぼ同一であることがわかる。ここでスペクトル位置がシリコン原子の平均原子間隔および密度を反映していることも実験的に確かめた。すなわち、例えばスペクトルが低周波数側に１．０１倍シフトしている試料について、ＲＢＳ（ラザフォードバックスキャッタリング）法で密度測定を行うと、単結晶の密度に比べこの密度は１／１．０１小さくなっていることがわかり、平均原子間隔が１．０１倍に広がっていることが確認された。ここで非晶質膜の平均原子間隔は単結晶のそれの０．９８以上で１．０２までであるとよいが、望ましくは１．０１以下さらに望ましくは０．９９５上で１．００５まで、すなわち１に近いほどよい。
【０２４８】
ここで、非晶質シリコンの成膜を、温度及びガス組成を変化させて行った結果、成膜速度Ｒが下式を満たす条件下でおこなった場合に、平均原子間距離が０．９８〜１．０２までの膜が得られた。
【０２４９】
ｌｏｇＲ（Ａ／ｍｉｎ）＜−１０６１４／Ｔ（Ｋ）＋１４．８５７この条件が示す領域を図３３に記す。この条件以外の領域では、平均原子間隔が１．０２を下回る膜は成膜できなかった。
【０２５０】
このようにして非晶質膜の形成されたシリコン基板を、チャンバーから取り出し、図３４に示すように窒素Ｎ_２雰囲気中で再結晶化のための熱処理を行う。この温度は例えば６００℃であった。この装置は導入口と排気口につながり、排気口は真空ポンプに接続され、真空引きを行うこともできるようになっている。次に、光学顕微鏡３２１で「種」から横方向への成長距離の時間依存性を測定した。このとき、炉の昇温速度は５０℃／分、降温速度は９９℃／分であった。熱処理を数分毎に分け、光学顕微鏡で写真撮影を行い、成長距離の時間依存性および成長速度の変化などを求めた。図３５にその結果を示す。この結果成長速度は一定であり成長距離は時間と共に直線的に伸びていることがわかる。
【０２５１】
このときの非晶質シリコンと単結晶シリコンとの界面いわゆる成長端の形状の観察および膜内の結晶欠陥の観察を透過電子顕微鏡を用いて行った。この結果、前述したように優先成長面の変化による双晶など結晶欠陥の発生と成長速度の減少を突き止めた。
【０２５２】
次に、この優先成長面変化の抑止を確認するために、成長初期用として、６００℃５分の熱処理のもの、長時間用として２時間のものを用意し、これらの試料の断面を、加速電圧４００ＫＶ、分解能１オングストロームの透過電子顕微鏡（ＴＥＭ）で観察した。図３６および図３７にこの写真を示す。図３６は５分後のＴＥＭ像、図３７（ａ）は２時間後の電子線回折像、図３７（ｂ）は２時間後のＴＥＭ像である。特に熱処理２時間を行った後の試料では、「種」から１２μｍまで結晶化が進んでおり、成長端も良好に（１００）面を維持しており、電子線回折像でシリコン基板と同じ結晶方位の双晶などの欠陥を含まない良質の単結晶であることが確認された。
【０２５３】
同様の評価を平均原子間距離が単結晶の０．９８〜１．０２の非晶質膜についても行ったが、いずれも高品質の単結晶を得ることができた。
【０２５４】
さらに、この非晶質膜が単結晶化した後の残留応力を実際に顕微ラマン法によって測定し効果を確認した。ここで分光器は本発明者らが鋭意開発したもので、図３８に示すように、Ａｒレーザ４１６からのレーザ光を顕微鏡を介して試料表面の直径１μｍの領域に集光し、１８０度散乱された光を分光器４１７に導入して分光測定を行った。受光部としてはマルチチャンネルＣＣＤを用い、スペクトルを一度に受光してメモリに積算するように構成され、高感度を得ることができるようにしたものである。測定条件としては、レーザ波長５１４．５ｎｍ、試料照射エネルギー３ｍＷ、照射スポット直径１μｍとした。
【０２５５】
応力（σ）は〜５２０ｃｍ^−１のスペクトルピークを用い次式により算出した。
【０２５６】
σ＝２．４９×１０^９・(ω_Ｏ−ω_ｒ)(ｄｙｎ／ｃｍ^２）ここでσは応力、ω_Ｏ（ｃｍ^−１）は試料のスペクトルピークの波数，ω_ｒ（ｃｍ^−１）は（１００）シリコン（ａ）基板の室温におけるスペクトルピークの波数を示す。この係数を算出するのに用いた弾性歪み定数などは単結晶シリコンの値を用いた。図３９にこの分光器で測定したラマンスペクトルを示す。このスペクトルのシフトから前記式を用いて応力を求めた。ピークが低応力側にシフトしていれば応力が引っ張りであることもわかる。ここではシフト量のみ用いた。レーザビームは直径１μｍφまで絞られており、その範囲での平均応力を得ることができた。図４０はこれによって得られた応力分布を示す図である。「種」から離れていても残留応力はほとんど見られず、本発明者のねらいどおりであることが確認できた。従って従来の膜で生じていた引っ張り応力は膜が縮むために生じていたことも再確認された。
【０２５７】
以上の結果から、単結晶に近い密度の非晶質膜を用いることにより、結晶化に伴う応力が生じず、従って（１１０）シリコン面から（１１１）シリコン面への優先成長面の変化を抑制することができ、成長速度を落とすこと無く遠くまで伸ばすことができ、結晶性もよいものとなっている。
【０２５８】
ここで非晶質膜の堆積に先立ち、「種」部の表面をできるだけ清浄にしておくこと、とりわけ自然酸化膜の除去が重要であるが、「種」部の表面の自然酸化膜の除去は、反応性ガスによる還元反応を用いた。例えば、８５０℃、ＳｉＨ_４分圧７×１０^−４Ｔｏｒｒで３０分処理することにより自然酸化膜は完全に除去することができた。また自然酸化膜除去後連続して非晶質膜を堆積することが重要である。 なお、本実施例では、再結晶化工程に於いて、その雰囲気をＮ_２としたが、これを水素雰囲気やアルゴン雰囲気としても良い。また、本実施例では固相成長温度を堆積温度よりも高温としたが逆に固相成長温度を低温として長時間熱処理してもよく、また光で固相成長を促進させてもよい。また熱処理以外にＥＢなどを用いても良い。
【０２５９】
次に本発明の第１０の参考例について説明する。
【０２６０】
この例では非晶質シリコン膜８３の密度を単結晶の密度に一致させるために、成膜後の非晶質シリコン膜の密度を顕微ラマン法により測定し、この値に応じて算出された量のシリコンイオンをイオン注入するようにしたことを特徴とするものものである。
【０２６１】
まず、図４１（ａ）に示すように膜厚０．２μｍの非晶質シリコン膜を堆積し、密度を顕微ラマン法により測定した。その結果０．９７であることがわかり、この値から最適イオン注入量を算出し、３．７５×１０^２０ａｔｏｍ／ｃｍ^３を注入した。このとき加速電圧８０ｋｅＶ、ドーズ量８．３×１０^１４ａｔｏｍ／ｃｍ２としたとき、密度を１．００にすることができた。
【０２６２】
そして図４１（ｃ）に示すように，６００℃２時間の熱処理を行い、単結晶シリコン膜３を形成した。
【０２６３】
この様にして得られた単結晶シリコン膜には結晶欠陥は見られず図４２に示すように残留応力は小さくまた、図４３に示すように良好な単結晶シリコン膜となっている。
【０２６４】
前記第９および第１０の参考例では、「種」を用いた例について説明したが、次に本発明の第６の実施例として「種」を用いることなく熱処理をおこなった場合の実施例について説明する。
【０２６５】
まず図４４に示すように、（１００）シリコン基板１表面に酸化シリコン膜２を形成した後、基板温度を５１５℃に保ちながらＳｉＨ_４分圧２Ｔｏｒｒで、膜厚２０ｎｍの非晶質シリコン膜３を堆積する。この非晶質シリコン膜の平均原子間隔は単結晶の１．０３倍であった。
【０２６６】
この後この非晶質シリコン膜に加速電圧２０ｋｅＶで５×１０^１５ａｔｏｍ／ｃｍ^２のシリコンイオンをイオン注入した。この結果非晶質シリコン膜の平均原子間隔は単結晶の平均原子間隔とほぼ同程度となった。
【０２６７】
次に、このシリコン基板の表面を純水で１００倍に希釈したＨＦ水溶液に１分間浸漬し、表面の自然酸化膜を除去し、基板の表面を清浄にする。この後５分以内にこの基板を図３２に示した熱処理装置に移す。
【０２６８】
つぎに、この熱処理装置内を１×１０^−７Ｔｏｒｒ以下の高真空にした後、基板温度を５５０℃まで昇温し、２時間保持した。
【０２６９】
そして、基板温度を室温近くまで降温せしめたのち、真空を破り、シリコン基板を搬出した。
【０２７０】
このようにして得られた結果を走査形電子顕微鏡（ＳＥＭ）で観察した結果を図４５（ａ）および（ｂ）に写真および模式図に示す。この図からあきらかなように絶縁膜上に大きさが揃いかつ均一な粒状の単結晶シリコン４が形成されている。１つ１つのシリコン粒の構造を透過形電子顕微鏡（ＴＥＭ）を用いて測定した結果を図４６に示す。この結果シリコン粒には格子像が鮮明にみられ、それぞれの粒が単結晶化していることがわかった。そしてこの結果単結晶中に結晶欠陥の全く無い完全な単結晶が得られている。またこれら結晶粒の配向性を電子線回折で調べた結果を図４７に示す。どの粒も垂直方向に＜１００＞軸がある結晶方位を示すことがわかった。この配向性は全く新しい現象であるため、原因は未だ明らかでないが、どの粒もすべて良好な配向性を示している。
【０２７１】
これに対し、シリコンイオンの注入を行うことなく同様の熱処理を行った場合のＴＥＭ写真を図４８に示す。この場合も絶縁膜上に大きさが揃いかつ均一な粒状の単結晶シリコンが形成されているが、粒の格子像をよくみると、双晶等の結晶欠陥が認められる。また、それぞれの粒の配向性を電子線回折を用いて調べたところ、特に配向性は認められなかった。このような粒化単結晶の固相成長機構および欠陥発生機構はいまだ明らかではないが発明者らはＴＥＭ像の観察から以下のような機構を推察した。すなわち、結晶粒の「結晶核」は、結晶粒がほぼ球形の形状をしていること、および粒の中心の高さが非晶質膜の膜厚と一致することから、非晶質膜の表面で発生していると推察した。この核から単結晶化が進行する。結晶化の成長端の形状は絶縁膜側に鋭角の面で構成されている。成長端が下方（絶縁膜側に）ある程度進むと、非晶質膜と単結晶化膜の密度の違いから成長端に大きな応力が発生する。この応力を緩和させるために、成長端の面のずれが起こり、結晶欠陥が発生する。これは前述したシミュレーション結果と一致する。また、注入量を種々変化させた場合、５×１０^１５ａｔｏｍ／ｃｍ^２を大きく外れるものについても同様であった。また、注入量を種々変化させ、非晶質膜の平均原子間隔を変化させたものを用いた場合の単結晶の結晶性との相関関係についてについて測定した結果を図４９に示す。この結果、平均原子間隔が単結晶の０．９８倍以上１．０２倍までの場合結晶性が良好であることがわかった。
【０２７２】
次に本発明の第７の実施例について説明する。この例では絶縁膜に凹凸を形成しこの上に非晶質シリコン膜を形成し、これを熱処理することにより結晶化するようにしている。
【０２７３】
まず図５０（ａ）に示すように（１００）シリコン基板１を用意しこの表面に膜厚３００ｎｍの酸化シリコン膜２を堆積する。
【０２７４】
この後図５０（ｂ）に示すようにこの酸化シリコン膜２の表面にレジストパターンを塗布し露光現像を行い形成したレジストパターンをマスクにして酸化シリコン膜を１００ｎｍ程度エッチングし微細な凹凸を形成する。そしてレジストパターンを剥離し、基板温度を５１５℃に保ちながらＳｉＨ_４分圧０．５Ｔｏｒｒで、膜厚２０ｎｍの非晶質シリコン膜３を堆積する。この非晶質シリコン膜の平均原子間隔は単結晶の１．０１倍であった。
【０２７５】
つぎに、この熱処理装置内を１×１０^−７Ｔｏｒｒ以下の高真空にした後、基板温度を６００℃まで昇温し、１時間保持した。
【０２７６】
そして、基板温度を室温近くまで降温せしめたのち、真空を破り、シリコン基板を搬出した。
【０２７７】
このようにして図５０（ｃ）に示すように結晶方位の完全に揃ったシリコン単結晶粒が形成されることがわかった。なお成膜に用いた装置にターボポンプを付けるなどの工夫をすれば成膜後連続して６００℃に温度を上げるだけで同様の結果を得ることができた。
【０２７８】
この現象は次のように説明することができる。すなわち図５０（ｄ）に拡大図を示すように下地に凹凸がある場合凹部に堆積した非晶質シリコン膜は側面と底面に絶縁膜を有するため水平方向と垂直方向との２方向に＜１００＞軸がくるように配向する。２軸で結晶方位が抑えられるため、いずれの結晶粒も配向性を示すことになる。
【０２７９】
これに対し、平坦な絶縁膜上の非晶質シリコン膜を単結晶化して粒を形成する場合垂直方向に＜１００＞軸があるように単結晶化する。しかしながら１軸のみが配向しているため、水平面内の結晶方位は図５１に示すように回転して定まらずそれぞれの粒で異なっている。
【０２８０】
さらに、絶縁膜に微細な間隔で線状の凹凸を形成し、その上に非晶質シリコン膜を５０ｎｍ堆積した例を図５２に示す。ここでは非晶質シリコン膜の密度をラマン散乱法で測定しつつ単結晶の密度にほぼ等しくなるように成膜条件を制御して成膜し、熱処理を行った。この結果、非晶質シリコン膜が厚く形成されているため、単結晶膜は粒に分離せず欠陥の全く無い単結晶膜を得ることができた。
【０２８１】
さらにこの単結晶膜の上層に第２の非晶質シリコン膜を２００ｎｍ程度堆積し、熱処理を行うと、シリコン基板上に直接堆積して熱処理を行うことにより得られる単結晶化膜と同程度の結晶性を有する単結晶化膜を得ることができた。
【０２８２】
次に本発明の第８の実施例について説明する。ここでは下地材質に微細な変化をつけて配向性を制御したことを特徴とする。すなわち、シリコン基板表面に形成された窒化シリコン膜２ａに微細な線状の酸化シリコン膜２ｂを形成したものを用い、これに非晶質シリコン膜を形成し、熱処理を行うことにより単結晶シリコン膜を形成する。
【０２８３】
まず、図５３（ａ）に示すように（１００）シリコン基板表面に窒化シリコン膜２ａを形成しレジストパターンをマスクとして５０ｎｍ程度の線状の凹部を形成し、ここに酸化シリコン膜２ｂを堆積してエッチバックを行い、凹部に酸化シリコン膜２ｂを埋め込むようにする。そしてこの上層に膜厚１０ｎｍの非晶質シリコン膜を堆積する。この非晶質シリコン膜の平均原子間隔は単結晶と同程度とした。ここでは同程度とするのが望ましいが０．９８以上１．０２さらに望ましくは０．９９５以上１．００５までであればほぼ同様の効果を得ることができる。
【０２８４】
そしてこのシリコン基板を、酸化膜が生じないように留意しつつ真空装置に搬入し、５３０℃２時間の熱処理を行い、図５３（ｂ）に示すように配向性の良好なシリコン単結晶結晶粒が生成される。
【０２８５】
この原因は非晶質シリコン表面で結晶核が発生する際に、材質による界面でのポテンシャルの違いが何等かの影響で結晶核の面内回転を抑えるためと推察される。
【０２８６】
この場合も単結晶膜の上層に第２の非晶質シリコン膜を堆積し、熱処理を行うと、シリコン基板上に直接堆積して熱処理を行うことによりえらえる単結晶化膜と同程度の結晶性を有する単結晶化膜を得ることができ、絶縁膜の「種」なしで完全な単結晶膜を形成することができた。
【０２８７】
なお、窒化シリコン膜など熱膨張率がシリコンより大きいもので非晶質膜を覆い、熱応力により若干非晶質膜を収縮させるようにすると平均原子間隔１．０２以上の膜でも結晶性の改善を得ることができた。
【０２８８】
さらに本発明は、シリコンに限定されることなくゲルマニウムなどの半導体、金属、シリサイドなど非晶質膜と結晶の密度が異なる場合にこれを揃えることで結晶性の大幅な改善をはかることができる。
【０２８９】
次に本発明の第９の実施例について説明する。
【０２９０】
この例ではキャパシタ容量の実効的増大をはかるために、表面にシリコン粒を形成し、電極表面に凹凸を形成する方法について説明する。
【０２９１】
まず、図５４に示すようにｎ型（１００）シリコン基板８１表面に、素子分離絶縁膜８２を形成して素子領域を形成した後、燐イオンを注入しコンタクトとしてのｎ^＋拡散層８３を形成し、ＣＶＤ法により５００ｎｍの酸化シリコン膜８４を形成しリソグラフィとドライエッチングにより開口を形成する。そしてＬＰＣＶＤ法により膜厚１００ｎｍの多結晶シリコン膜８５を形成し、ＰＯＣｌ_３を雰囲気中で９５０℃の熱処理を行うことにより燐を拡散し、さらに燐拡散中に多結晶シリコン膜表面に形成された自然酸化膜をフッ化アンモニウムを用いて除去し、リソグラフィおよびエッチングにより１００×２００μｍの燐添加多結晶シリコン膜からなる下部電極８５を形成する。このとき電極表面には膜厚１ｎｍ程度の薄い自然酸化膜８６が形成されている。
【０２９２】
そしてこの上層に図５５に示すように、ＳｉＨ_４ガスを用い、ＣＶＤ法により基板温度５２５℃圧力１Ｔｏｒｒで、膜厚１０ｎｍ程度の非晶質シリコン膜８７を堆積する。
【０２９３】
こののちＳｉＨ_４ガスを排気し、非酸化性のＡｒガスを導入して昇温し、６００℃１時間の熱処理を行った。これにより図５６に示すように非晶質シリコン膜８７が単結晶シリコン粒８８に変化し、表面に良好な凹凸が形成される。
【０２９４】
そしてさらに８００℃３０分の熱処理を行う。これにより自然酸化膜８６が消失し、多結晶シリコン膜と単結晶シリコン粒８８とが電気的に接続される。
【０２９５】
そして粒間の自然酸化膜を１％のＨＦ溶液で除去した後、膜厚５．５ｎｍの窒化シリコン膜８９をＳｉＨ_２Ｃｌ_２とＮＨ_３とを用いたＬＰＣＶＤ法により堆積し（図５７）、さらに８００℃の酸素雰囲気中で酸化して酸化シリコン膜９０を形成しいわゆるＮＯ膜を形成する（図５８）。
【０２９６】
そしてシランガスを用いたＣＶＤ法により基板温度６３０℃で燐添加の多結晶シリコン膜を堆積し（図５９）、これをパターニングして上部電極９１（図６０）を形成することによりキャパシタが完成する。
【０２９７】
これにより、表面を０．０５μｍの凹凸にして単位面積を大きくした電極を形成することができる。このようにして全工程を８００℃以下で実施することができるため、他の領域にＭＯＳ素子等が形成されている場合にも適用することができる。
【０２９８】
またここでシリコン粒の分布密度は１平方μｍあたり２００個程度であり、幾何学的表面積を計算すると、シリコン粒が無い場合に比較しておよそ５０％程度増大することがあきらかとなった。
【０２９９】
なお図５６の工程で非晶質シリコンが粒状の単結晶となった基板を大気中に取り出し、ＳＥＭで表面を観察したところ、図６１に示すように非晶質シリコン膜８７が単結晶シリコン粒８８に変化しており、断面ＴＥＭでさらに詳しく観察した結果図６２に示すように粒径６０ｎｍ程度の完全に分離したシリコンの単結晶シリコン粒８８が間隔２０ｎｍ程度で形成されていることが確認された。粒径よりも粒間距離が小さいため、単結晶粒による表面積増大効果が顕著に得られることが分かった
【０３００】
この堆積および加熱方法によれば条件のマージンが広く再現性よくシリコン粒を形成することができる。また、非晶質シリコンの堆積膜厚、下地材質、熱処理温度を変えることで、粒径、粒間隔、粒分布密度を制御することが可能である。なお、この例では、熱処理に先立ち、非晶質シリコンは単結晶の平均原子間隔と同じになるようにする。あるいは単結晶の平均原子間隔の１．０２倍以上となるようにしてもよい。
【０３０１】
次に例として、下地を酸化シリコン、熱処理温度を６００℃とし非晶質シリコンの膜厚を５、１０、２０ｎｍと変化させた場合に形成される粒のＳＥＭ写真を図６３に示す。また図６４にＳＥＭ写真から求めた膜厚に対する粒径と粒分布密度との関係を示す。この結果から膜厚を制御することで粒径、分布密度を選択することができ、堆積膜厚が１０ｎｍのオーダーと非常に薄くすみ、電極形状に依存することなく粒を形成することができるため、スタック構造、トレンチ構造などの立体的電極構造との組み合わせが容易である。
【０３０２】
なお、この方法では自然酸化膜８６の上に単結晶粒を形成し、これを図６５（ａ）および（ｂ）に拡大説明図を示すように熱処理により自然酸化膜８６を破壊し島状にし、さらに下地の多結晶シリコン膜８５から燐を単結晶粒中に拡散せしめ、十分な電気的接続を得ることができることを発見しこれを利用している。
【０３０３】
この様にして得られたキャパシタの容量を測定し、シリコン粒の形成されていない従来例のキャパシタの容量とキャパシタ数とを示すヒストグラムを図６６に示す。この結果から従来のキャパシタに比べ本発明のキャパシタによれば容量が１．５６倍に再現性よく増大していることがわかる。
【０３０４】
また、この例では自然酸化膜の破壊を熱処理によって行うようにしたが、これに代えてイオン注入を用いても自然酸化膜の破壊とシリコン粒への不純物の導入による導電性の付与を行うことができる。
【０３０５】
さらにまた、下地としては自然酸化膜の他窒化シリコン膜、ＰＳＧ、ＢＰＳＧなどを用い、同様にして表面に粒を形成し、熱処理あるいはイオン注入などによって粒と電極の導通を得ることができる。粒の材質に関しても、シリコンのみならず、ゲルマニウムなどの半導体、アルミニウム、金、等の金属の非晶質薄膜を非酸化性雰囲気中で熱処理した場合にも同様にして導電性微細粒を形成することが可能である。
【０３０６】
次に本発明の第１０の実施例について説明する。
【０３０７】
前記第９の実施例では自然酸化膜上に非晶質シリコン膜を形成し熱処理によりシリコン粒を形成したが、絶縁膜に限らず、カーボンなどの導電性膜上でもシリコン粒は形成可能であることを利用している。この例ではトレンチを含む表面に非晶質カーボン膜を形成しこの上層に非晶質シリコン膜を形成し熱処理によりシリコン粒を形成することによりトレンチ型キャパシタの下部電極に凹凸を形成する方法について説明する。この場合、シリコン粒形成後、絶縁膜を除去する必要がないという大きな利点がある。
【０３０８】
まず、図６７に示すようにｎ型（１００）シリコン基板表面に酸化シリコン膜４０３を堆積しリソグラフィとＲＩＥにより開口したのち、これをマスクとしてＲＩＥによりトレンチＴを形成する。
【０３０９】
そして図６８に示すようにアセチレンを原料ガスとしてＣＶＤ法により非晶質カーボン膜４０５を形成し、排気後同一チャンバー内で続いて図６９に示すように、ＳｉＨ_４ガスとＰＨ_４ガスの混合ガスを導入し、ＣＶＤ法により基板温度５２５℃圧力１Ｔｏｒｒで、膜厚１０ｎｍ程度の燐添加の非晶質シリコン膜４０７を堆積する。
【０３１０】
こののちＳｉＨ_４ガスおよびＰＨ_４ガスの混合ガスを排気し、非酸化性のＡｒガスを導入して昇温し、６００℃１時間の熱処理を行った。これにより図７０に示すように燐添加非晶質シリコン膜４０７が単結晶シリコン粒４０８に変化し、トレンチ内壁を含む表面全体に良好な凹凸が形成される。この粒径や粒間隔は前記第９の実施例とは異なるが、ここでも良好なシリコン粒が形成されている。そして、図７１に示すように膜厚１０ｎｍの酸化シリコン膜４０９を形成しキャパシタ絶縁膜とする。
【０３１１】
そしてシランガスを用いたＣＶＤ法により基板温度６３０℃で燐添加の多結晶シリコン膜を堆積し、これをパターニングして上部電極４１１（図７２）を形成することによりキャパシタが完成する。
【０３１２】
これにより、表面を０．０５μｍの凹凸にして単位面積を大きくした電極を形成することができ、実効的なキャパシタ容量を大幅に増大することができる。ここでは第９の実施例の効果に加え、シリコン粒を直接電極に接して形成できるため、絶縁膜の除去工程が不要になり工程が簡略化される。
【０３１３】
なお、前記実施例では下部電極をカーボンで構成したが、多結晶シリコン膜などで形成した後表面をカーボン膜で被覆し、シリコン粒を形成するようにしてもよい。またシリコン粒の下地となる膜はカーボン膜に限定されること無くＷ、Ｔａ、Ｎｉ、Ｔｉなどの金属、ＮｉＳｉ、ＴｉＳｉなどの金属硅素化合物、あるいはＴｉＮなどを電極もしくは電極被覆剤として用いるようにしても、カーボン上同様表面に導電性微細粒を形成することができる。
【０３１４】
次に本発明の第１１の実施例について説明する。
【０３１５】
これまでに示した例では、非晶質膜の形成後連続して非酸化性雰囲気中で熱処理を行うようにしたが、この例では非晶質膜の表面に酸化膜が形成されてしまった場合、フッ酸などを用いて自然酸化膜を除去し熱処理を行うようにすればシリコン粒が形成される。以下この例について説明する。
【０３１６】
まず、図７３（ａ）に示すように１０００℃１５分の熱酸化によりｎ型（１００）シリコン基板５０１表面に膜厚５００ｎｍの酸化シリコン膜５０２を形成し、この上層に、ＳｉＨ_４ガスを用い、ＣＶＤ法により基板温度５２５℃圧力１Ｔｏｒｒで、膜厚１０ｎｍ程度の非晶質シリコン膜５０３を堆積し、大気中に取り出す。このとき表面に自然酸化膜５０２ｓが形成されている。この状態で前記第９および第１０の実施例と同様に６００℃１時間の熱処理を行っても多結晶シリコン薄膜となり微細シリコン粒は形成されない。
【０３１７】
ここではついで５％のＨＦ溶液で自然酸化膜５０２ｓを除去し図７３（ｂ）に示すように非晶質シリコン膜５０３表面を露出せしめた後、表面が再び酸化されないように維持しつつ２５℃以下に維持して基板を真空容器に搬入する。
【０３１８】
そして、容器内を１×１０^−８Ｔｏｒｒまで排気したのち昇温し、６００℃１時間の熱処理を行う。これにより図７３（ｃ）に示すように単結晶シリコン粒５０４が形成される。この後この基板を大気中に取り出し、ＳＥＭで観察したところ図７４に示すようにシリコン粒が確認された。
【０３１９】
このように非晶質シリコン膜表面に一旦酸化膜が形成されても、酸化膜を除去してから再酸化を防ぎ高真空中あるいは非酸化性雰囲気中で熱処理を行うようにすれば、連続的に熱処理を行うことができない場合にも、シリコン粒を得ることができる。これは実際のキャパシタ形成工程で極めて有効な方法である。
【０３２０】
なお、前記実施例ではキャパシタへの適用について説明したが、キャパシタに限定されること無く、表面積の増大が必要な場合など、低温下で容易に凹凸を形成可能であるためデバイス形成に極めて有効な方法である。
【０３２１】
次に、本発明の第１１の参考例について説明する。
【０３２２】
この例では、図７５にその製造工程図を示すように、シリコン基板６０１表面を覆う酸化シリコン膜６０２に形成された窓Ｗを種として固相成長せしめられた単結晶シリコン薄膜６０３内にソース・ドレイン領域Ｓ、Ｄを形成するとともに、これらの間にゲート絶縁膜６０４を介してゲート電極６０５を形成したものである。
【０３２３】
本参考例の特徴は、従来に比べ結晶性の格段に優れた単結晶薄膜をＭＯＳ素子のチャネル領域に用いることであり、これによって従来得られなかった、高速動作素子を作成することができる。高速動作が可能となる要因は、結晶性が大幅に改善されたことであるが、さらに、チャネル領域が数十ｎｍの極薄膜である事も大きく効いている。このような超薄膜を従来の方法で得ようとする場合、厚い非晶質シリコン層を形成して固相成長を行い再結晶化したのち、所望の厚さまでエッチバックするのが通常の方法であり、エッチングによって高精度の膜厚を得るのは極めて困難であったが、この方法では非晶質シリコン膜の形成に際し膜厚を制御すれば良いため、制御性よく容易に高精度の制御が可能である。また、ここではその詳細な原理にふれないが垂直電界の緩和によると考えられている。さらに、この素子構造では、基板とチャネル領域とが極めて良好な界面状態で電気的に接触しているため、ドレイン近傍で発生するインパクトイオン化による電流を基板へ流すことで素子動作の安定化を達成することができる。
【０３２４】
製造に際してはまず、シリコン基板上にシランガスと酸素を材料としてＣＶＤ法を用いて５００ｎｍの酸化シリコン膜６０２を形成する。次にレジストをマスクに用い、酸化シリコン膜の一部をエッチングして窓Ｗを形成し、シリコン基板６０１を露出させる。なおエッチングには、反応性イオンエッチングあるいはフッ酸などによるウェットエッチングなどいずれの方法を用いても良いが、ここでは、反応性イオンエッチングを用いた。
【０３２５】
続いて、「種」部のシリコン基板表面の酸化膜除去のため、高真空のＣＶＤ炉内にシランガスを導入し６００℃、１×１０^−６Ｔｏｒｒ、２時間処理した後、連続して炉内の条件を５２５℃、１Ｔｏｒｒに変更、非晶質シリコン膜を２０ｎｍ堆積した。さらに、シランガスの導入を停止した後、連続して、６００℃、３０分の熱処理を行った。ここまでの工程で「種」部に２０ｎｍの単結晶シリコンの埋め込みがなされる。このようにし連続して、５２５℃の非晶質シリコン膜の成膜、６００℃での結晶化を繰り返し、図７５（ａ）に示すように「種」部の埋め込みを完了した。「種」部以外のシリコン膜はエッチングにより除去した。
【０３２６】
この時、５２５℃で成膜した非晶質シリコン膜は、ラマン分光法で測定すると、原子間隔の平均距離がシリコン単結晶の原子間隔のほぼ１．０２倍であり、高真空炉内で連続して結晶化を進めているときも結晶化する直前までこの値を維持していた。このようにシリコン原子の結合がゆるんだ状態で結晶化を進めると極めて結晶性の良好な単結晶が得られ、透過電子顕微鏡で調べても欠陥はみられなかった。
【０３２７】
このように本発明の方法を用いれば、従来の選択エピタキシャル法「種」部のシリコン結晶の埋め込みには、ジクロルシランガスを材料として８５０℃、１Ｔｏｒｒの成膜条件で、選択エピタキシャル成長を用いても良いが、我々は、ここでも本発明を用いてシリコン単結晶の埋め込みを行った。この方法では、選択エピタキシャル成長のような高温工程を必要とせず、すでに他の領域に素子を形成しておいても何等問題を生じない。
【０３２８】
次にこの「種」部を用いて素子の能動層形成を行った。まず、高真空のＣＶＤ炉内に図７５（ａ）の構造の試料を設置し、シランガスを導入しながら６００℃、１×１０^−６Ｔｏｒｒ、２時間処理した。つぎに、連続して炉内の条件を５２５℃、１Ｔｏｒｒに変更、非晶質シリコン膜を５０ｎｍ堆積した。さらに、シランガスの導入を停止した後、連続して、６００℃、３０分熱処理を行った。
【０３２９】
ここでも、５２５℃で成膜した非晶質シリコン膜は、原子間隔の平均距離がシリコン単結晶の原子間隔のほぼ１．０２倍であり、高真空炉内で連続して結晶化を進めているときもこの値を維持した。結晶化後の膜を透過電子顕微鏡で調べても欠陥はみられなかった。
【０３３０】
このようにして単結晶シリコン薄膜６０３を形成した後、ケミカルドライエッチング（ＣＤＥ）を用いて素子分離を行った。そしてこの素子領域に図７５（ｂ）に示すようにソースおよびドレインとなる領域をイオン注入により形成し、さらに、ゲート酸化膜６０４の形成およびゲート電極６０５の形成を行った。
【０３３１】
素子分離に用いたＣＤＥおよびイオン注入はほぼ室温の工程であり、ゲート酸化膜など酸化膜はシランガスと酸素を用いたＣＶＤ法によって４５０℃で形成した。ゲートはジシランおよびジボランなどを材料としたＣＶＤ法により３５０℃で形成した。
【０３３２】
このようにして形成されたＭＯＳトランジスタの素子特性を図７６に曲線ａで示す。ここで曲線ｂは比較のために、基板とは接していない２００ｎｍのシリコン膜を用いた従来例の典型的なＭＯＳトランジスタの素子特性を示した図である。両者を比較してみるとあきらかにドレイン電圧の増加に対するドレイン電流の増加の程度が、本発明の構造の方で大きくなっていることがわかる。この増加の程度は素子の移動度に相当している。この素子の移動度を実測したところ例えばＮＭＯＳでは７００ｃｍ^２Ｖ／ｓｅｃであった。これは、従来のバルク素子を上回る性能である。また、図中従来例のＭＯＳトランジスタの方では「キンク」と呼ばれる素子特性の不規則な変化がみられているが、これはインパクトイオン化により生じた空孔がシリコン薄膜中に止まるために起きる現象と考えられる。素子をＬＳＩ回路として利用する際、このような特性の不規則な変化は設計上極めて不都合であるが、本発明の方法により作成した構造の素子ではこのような特性の不規則性はまったくみられなかった。
【０３３３】
従来、結晶性の優れた単結晶薄膜を得るためにシリコンを一旦溶融する方法や、８５０℃程度の温度でエピタキシャル成長させる方法などが提案されているが、いずれも高温が必要であった。また低温で結晶成長を行う固相成長法も存在はあったが結晶性が悪く素子には使えないという問題があった。このような状況の中で本発明によれば、上記した方法を用いた固相成長法により、シリコン薄膜の結晶性を大幅に改善した。
【０３３４】
以上の工程はすべて６００℃以下の工程であり、例えば素子を積層化するなどすでに他の領域に素子を形成してある場合でも、すでに形成した素子に熱拡散など熱的影響を与えずに次々と新しく素子を追加形成していくことができる。しかも、それぞれの素子特性はシリコン基板に形成したもの以上に優れている。図７７に、本発明の方法を用いて絶縁膜上にＭＯＳ素子を形成する前後でシリコン基板上にすでに形成しておいたＭＯＳ素子の特性を測定した結果を表で示す。ここではＭＯＳ素子の特性の代表的な例としてしきい値と移動度を示した。まずシリコン基板にｎチャネル，ｐチャネルのＭＯＳ素子を１０００個作成し、その特性を測定した。次に本発明の工程をすべて行うことにより、絶縁膜上にＭＯＳ素子を作成してから、すでにシリコン基板上に作成しておいたＭＯＳ素子の特性を再び測定した。表に示すようにｎチャネル、ｐチャネルともに閾値、移動度の変化はみられなかった。この表からも、本発明は、素子の集積化、微細化に極めて有効な方法であることがわかる。
【０３３５】
次に本発明の第１２の参考例として、ＳＯＩ素子の形成に本発明を用いた例を以下に示す。
【０３３６】
本参考例の特徴を一言でいえば、図７８に示すように「種」結晶を用いた固相成長法により絶縁膜上に単結晶シリコン薄膜を形成する際、「種」部から数十μｍの遠方まで単結晶を成長させ、ＳＯＩ素子を任意の位置に作製可能にした点にある。従来技術では、「種」からたかだか２〜３μｍまでしか単結晶化できず、これは単体のＳＯＩ素子の大きさとほぼ同じ広さしかなく、素子のレイアウト上の自由度がほとんどなかった。
【０３３７】
さらに従来技術でのもう一つの欠点は、集積化に不利である点である。例えば１μｍのパターンを形成できる技術でＳＯＩ素子を作製しようとすると、まず酸化膜に穴をあける「種」の形成に１μｍ^２の領域が必要になる。ソース、ドレインおよびゲートにそれぞれ１μｍ^２の領域が必要であるから３μｍしか単結晶が延びないと１つの「種」に１つのＳＯＩ素子しか作製できない。この時「種」の占める面積は、素子の占める面積の１／３にも達し集積化には極めて不利である。極論すればシリコン基板の１／４が「種」として使われて無駄になってしまう。さらに、０．５μｍでパターンを形成できる技術を用いても、１／７の面積が「種」として使われて無駄になってしまう。また、従来技術では、「種」から単結晶成長している領域でも双晶などの欠陥が多数見られた。
【０３３８】
本参考例は、非晶質の密度が単結晶シリコンと異なると、非晶質が結晶化する際に膜中に応力が生じ、これが結晶成長を阻害していることを発見し、非晶質の密度を単結晶シリコンに近づけることで、従来不可能であった数十μｍの薄膜単結晶成長を可能にした。しかも、応力が低減されたため、結晶欠陥の発生も抑制され、上記数十μｍの単結晶領域全体にわたって双晶などの欠陥も見られなくなった。
【０３３９】
本参考例では、まず（１００）シリコン基板に酸化シリコン膜６０２を５００ｎｍ形成した。酸化シリコン膜６０２は熱酸化法で形成しても良いが、ここではシランガス０．２Ｔｏｒｒ、酸素ガス０．８Ｔｏｒｒ、堆積温度４５０℃の条件でＣＶＤ法を用いて形成した。次にレジストをマスクに、反応性イオンエッチングを用いてこの酸化シリコン膜６０２に開口部を設けた。このように酸化シリコン膜６０２に開口部を設け一部シリコン基板６０１を露出させた試料を、５％フッ酸溶液で５分間処理してからバックグランド１×１０^−６Ｔｏｒｒ以下の高真空まで排気可能なＣＶＤ炉に導入した。この炉を４８０℃まで昇温した後、ジシランガスを２００ＳＣＣＭ、０．０４Ｔｏｒｒ導入し非晶質膜を０．２μｍ厚に堆積した。この非晶質膜の密度をＲＢＳ測定（ラザフォード後方散乱測定）により求めたところ、ほぼ単結晶シリコンと等しい値であった。ここで、例えばジシランガスの圧力を０．１Ｔｏｒｒまで上げて非晶質の堆積を行うと、その密度は単結晶の０．９９倍であった。この場合、シリコンイオンを加速電圧８０ｋｅＶ、３×１０^１４ａｔｏｍ／ｃｍ^２イオン注入すると、ほぼシリコン単結晶の密度と等しくすることができた。我々は、非晶質シリコン膜を堆積するときに、堆積速度を適正化するとともに、特に基板の温度を下げることにより、容易に単結晶に近い密度の非晶質膜を成膜できることも見いだした。
【０３４０】
このように非晶質膜を堆積した後、５８０℃、２０時間の熱処理を行うと、図７８（ａ）に示すような構造の単結晶薄膜を形成することができた。この単結晶薄膜の結晶性を高分解能透過電子顕微鏡を用いた断面ＴＥＭ観察で調べたところ、双晶等の結晶欠陥の無い良好な結晶性の単結晶が数十μｍの領域にわたって形成できていることが確認できた。
【０３４１】
つぎに、この単結晶薄膜を用いてＭＯＳ素子の作製を行った。まず、単結晶薄膜を、ハロゲン系ガスを用いたＣＤＥ法により島状に素子分離した。つぎにゲート酸化膜４０ｎｍおよびゲート電極４００ｎｍをＣＶＤ法で堆積した。これを反応性イオンエッチングでゲート形状にパターニングした。さらに、ソースおよびドレインとする領域に、ＰＭＯＳの場合には硼素を、ＮＭＯＳの場合にはリンをイオン注入し９５０℃、３０分の活性化熱処理を行った。
【０３４２】
このようなＭＯＳ素子を図７８（ｂ）に示すように「種」から＜０１０＞方向に５μｍ間隔で１２個配置した。この「種」から距離の異なる位置に作製した素子の特性を測定したところ、ＰＭＯＳでは１５０ｃｍ^２Ｖ／ｓｅｃ、ＮＭＯＳでは６００ｃｍ^２Ｖ／ｓｅｃというほぼシリコン基板上に作製した素子と同程度の移動度が得られた。従来技術では、このような高移動度の素子は形成できず、また、「種」から２〜３μｍ離れた位置の素子では、正常なＭＯＳ動作が得られないものもあった。
【０３４３】
図７９は、この方法を用いて形成したシリコン薄膜（曲線ａ）と従来のシリコン薄膜（曲線ｂ）の結晶欠陥の数をエッチピットで評価した結果を示す図である。エッチピットはフッ硝酸系混合溶液でシリコン膜表面を処理した後電子顕微鏡で観察すると、ピット状の窪みとして観察される。このピットは結晶欠陥がフッ硝酸系混合溶液で選択的に速くエッチングされることにより現れるものであり、欠陥の数と一致する。従来膜では欠陥の数が非常に多く、特に「種」を離れるとわずか数μｍで１０^１０個／ｃｍ^２にも達する。本発明の方法によれば、「種」から３５μｍ離れた位置においても、１００個／ｃｍ^２以下に押さえることができた。
【０３４４】
さらに図７９に示した構造のｎチャネルおよびｐチャネルのＭＯＳ素子を「種」からの距離を代えて１０００００個作成し、その特性を測定した。図８０にこの特性の代表的値として、しきい値および移動度とその標準偏差を示した。この図に示すように、ｐチャネルｎチャネルともに、移動度はシリコン基板に作成したＭＯＳと同程度の値であり、しかも「種」から離れてもほとんど低下しない。また、しきい値のばらつきもほとんど増加せず、本発明を用いることにより「種」から離れた位置でも、従来よりも格段の素子特性の向上をはかることができた。
次に本発明の第１２の実施例について説明する。
【０３４５】
この例では、図８１（ａ）乃至（ｋ）に工程図を示すように、基板表面に形成されたｐ型シリコン領域と、その上層に本発明の方法で形成したｎ型の粒状単結晶シリコンとでｐｎ接合を形成し、特性のばらつきの小さいダイオードを得るようにしたものである。
【０３４６】
まず、図８１（ａ）に示すように、シリコン基板７０１としてＮ−ｔｙｐｅのＳｉ（１００）を用意する。このシリコン基板７０１の不純物濃度は特に限定しないが、本発明者らは１０^１５／ｃｍ^３程度を選んだ。このシリコン基板７０１に、１１００℃で選択熱酸化を施し膜厚３５０ｎｍ程度の素子分離領域７０２を形成する。
【０３４７】
次に図８１（ｂ）に示すように、ドライ酸化雰囲気で膜厚３５ｎｍの薄い酸化シリコン膜７０３を形成した。
【０３４８】
しかる後に、図８１（ｃ）に示すように、イオン注入法により、例えばボロン不純物を、注入し埋め込みｐ^＋電極領域７０４を形成した。この時、別の方法として、例えば、埋め込みエピタキシャル法を用いても良い。ただし、エピタキシャル法の場合は、若干手順を変える必要がある。この領域７０４は後続工程で形成されるダイオードの電極の一部の引き出し拡散層になる。
【０３４９】
次に、この酸化シリコン膜７０３に、フォトリソグラフィを用いて、図８１（ｄ）に示すように開口部７０５を形成する。しかる後に、再びフォトリソグラフィ法を用いて、マスクを形成しイオン注入を行い、図８１（ｅ）に示すようにこの開口部７０５の一方の部分に、引き出し用の高濃度ｐ^＋不純物層７０６を形成した。他方開口部のうちもう一方の部分には、図８１（ｆ）に示すようにダイオードのもう一方の電極部分になるｐ⁻領域７０７を形成した。
【０３５０】
次に、図８１（ｇ）に示す様に、本発明の構成要素の根幹の一部である極薄酸化膜７０８を形成する。この極薄酸化膜としては、例えば自然酸化膜を用いるようにしても良い。
【０３５１】
次に図８１（ｈ）に示すように、やはり本発明の根幹の一部である非晶質シリコン膜７０９を堆積させた。ここでは、堆積温度は、例えば５２５℃で、堆積ガスは例えばＳｉＨ_４であった。もっとも重要な用件である非晶質膜厚は、例えば、１９．８ｎｍであった。この時、本発明者等は、ドーピングガスとして、ＰＨ_３を用い、堆積膜には高濃度ｎ^＋不純物を含ませた。この非晶質シリコン膜７０９をパターニングし、ここでは図８１（ｉ）に示すように、ダイオード部分になるところを残して置く。しかる後に、この膜７０９の上に酸化膜等が被着していることが考えられるので、これを十分取り除き、再結晶化炉に挿入した。例えばその温度は６００℃であった。
【０３５２】
図８１（ｊ）に示す様に、６００℃で熱処理すると、非晶質シリコン膜７０９の部分は再結晶化して、単結晶シリコン７１０となる。これは本発明の特徴である。しかも、その方位は基板と同一であり、このとき別にアニールを行ってもよいが、再結晶化のための熱処理により図８１（ｋ）に示すように、酸化膜の一部が収縮して破れ、上下の結晶性が連続になる。これが本発明になる単結晶ダイオードの骨子になるわけである。そして電極７１１、７１２をそれぞれ形成しダイオードが完成する。
【０３５３】
上記述べてきた、単結晶粒成長時になぜ下地の極薄膜酸化膜が一部剥離し、上下に結晶的に結合したか、さらに、このような低温で、上下の結晶がなぜ方位まで揃って、良好な結晶が得られたのかを、本発明者らは鋭意追求したので、ここで簡単に説明する。
【０３５４】
本発明者は、既に紹介した様に新しい分子動力学シミュレーションシステムを開発した。これを用いて上記プロセス現象の真髄に迫った。分子動力学シミュレータ中の各原子間のポテンシャル表現部分と界面作成部分を改良し、Ｓｉ／ＳｉＯ_２界面を含むＳｉ原子とＯ原子の運動計算ができる様にした。計算作業の一部を記す。Ｓｉ／ＳｉＯ_２界面作成の初期条件としては、以下の通りである。即ち２つの約束事を設け、（ｉ）初期条件としてはｄａｎｇｌｉｎｇ ｂｏｎｄを一切残さないこと，（ｉｉ）初期結合長ｄ及び初期結合角θはそれぞれｄＳｉ−Ｓｉ＝２．３５オングストローム、ｄＳｉ−Ｏ＝１．６０オングストローム、θＳｉ＝１０９．４７°、θＯ＝１４４．０°とすることである。しかる後、ＳｉとＯ原子それぞれにマックスウエリアンに従った速度を乱数的に割り当てる。その後、界面を含む系全体で、エネルギを最小にする様に全粒子を運動方程式に則り移動させた。従って、充分計算が進んだ時点で、構造的緩和が起こり、結合長や結合角の分布等が求まる手はずである。多量の出力（各原子についての、時々刻々の位置と力と速度と、界面近傍の応力等のデータ）を分析した。
【０３５５】
その結果を明らかになったことを以下に記す。まず非晶質シリコン膜７０９の再結晶化は、膜の上面近傍から成長、下層の薄膜酸化膜７０８に向かって進む。この時、基板７０１の結晶方位との整合性は全く無い。シリコン単結晶の成長が伸びるにしたがい、成長端近傍に引っ張り応力が蓄積することがわかった。他方、下層の薄酸化膜７０８にも、初期から基板７０１と極薄酸化膜７０８の原子間構造に起因する圧縮応力が蓄積している。従って、酸化膜７０８には大きな圧縮応力が蓄積し、蓄積量が一定値に達すると部分的に酸化膜７０８が破れることが解った。さらにこの瞬間に再結晶化粒７１０は、シリコン基板７０１との結晶方位の違いによるエネルギ量を下げる方向に力が働くことも解った。その後、再結晶化粒７１０は下地基板７０１と完全に近い同一軸になることも解った。
【０３５６】
この後、本発明による単結晶微細ダイオードの特性を評価してみた。その結果を図８２に示す。図中のｑは電気素量で、Ｖは電圧を示し、ｋはボルツマン定数である。またＴは絶対温度を示している。まず図から解る様に、良好な整流特性がみられている。更に、逆方向であるが、ｑ｜Ｖ｜／ｋＴの値で見てみると、耐圧は測定範囲では殆ど検出できず、理想に近い挙動を示している。この様に、理想に近い、整流特性及び耐圧が得られた理由は良く解らないが、考えられる項目としては以下の２点がある。一つには、結晶性が良い事，もう一つは、不純物の再分布がなく、完全急峻型が得られた事にある。
【０３５７】
比較の為に、本発明者等は、従来の技術を用いてｐｎジャンクションを作成してみた。以下に作成手順と特性結果を簡単に報告する。
【０３５８】
従来例としては、例えば、図８１で代用すれば、図８１（ｇ）までは同じでも良い。その後、図８１（ｈ）では非晶質シリコン膜を堆積させたが、ここでは、多結晶Ｓｉを堆積させたものを用いる。この温度はたとえば、６２５℃であった。此の温度は、ここで明記しておきたいが、非常に高いわけである。このような温度処理は、もし下地に素子が有れば非常に不利になる。
【０３５９】
そのあと、従来良く行われている様に、基板と多結晶Ｓｉの界面を目指して、ミクシング用のイオン注入を行った。その後、例えば９７０℃で熱処理を行い、その後、電極等を形成して、接合特性を測定した。その結果を図８３に示す。明らかに耐圧が低下していることがわかる。此の様に、耐圧が低下している原因を調べると、一つには、接合領域が、完全に単結晶になっておらず、多分ミクシング時の欠陥だと推定されるものが多数残っている。さらにＳＩＭＳによって不純物分布を観察したが、急峻さが低下している。これらにより、特性が劣化したものと考えられる。
【０３６０】
次に、本発明の第１３の実施例について説明する。
【０３６１】
この例では図８４に示すように、固相成長により形成した粒状の単結晶シリコンを用いて、結晶粒径の揃った、しかもグレイン内部の結晶性が極めて良い多結晶シリコンを形成し、ここに移動度のバラツキ等の無い、素子特性の安定した薄膜トランジスタを形成した実施例を示す。
【０３６２】
まず、シリコン基板９０１上に絶縁膜を堆積した後、単結晶シリコンを得るに当たり、非晶質シリコンの平均原子間隔を予めシリコン単結晶と一致するようにした膜を用い、さらに非晶質膜の表面に酸化膜の成長付着を抑止するため、還元性雰囲気のＨ_２雰囲気にして、熱処理した。膜作成の装置は図３２に示したものと同一のものを用いた。
【０３６３】
まず図８４（ａ）に示したように、シリコン基板９０１の上にシリコン酸化膜９０２を５００ｎｍ堆積した後、非晶質シリコン膜９０３を堆積する。この膜厚は７５ｎｍとした。すると、本実施例の文頭に報告したように、堆積直後の測定結果では、平均原子間隔は、単結晶基板の１．００５倍の値を得た。この後、堆積装置と同一装置を用いて、表面自然酸化膜の付着を抑えながら、５８０度５時間の熱処理を行い、単結晶シリコンを形成した。その結果、図８４（ｂ）に示したように、非晶質シリコン膜は単結晶化して粒状のシリコン単結晶粒が形成された。
【０３６４】
ＴＥＭ写真を用いた詳細な観察により、この単結晶粒は、垂直方向に＜１００＞軸が配向しており、しかも、大きさと粒間隔がほぼ揃っていることが観察された。例えば、基板の真上から粒を捉えたＳＥＭ写真により、粒径分布を調べると、図８５（ａ）に示したように、最大出現頻度の粒径１５００オングストロームを中心に、±２０％以内に９０％以上の粒が含まれた。特に、最大出現頻度よりも１割以上大きい粒は、ほとんど見られなかった。この現象は、おそらく、ほとんどの結晶核の生成が、熱処理開始から比較的速い時間に同時に起こっているためと考えられる。また、隣接する粒の中心から中心までを測定して粒間隔を調べると、図８５（ｂ）に示したように、最大出現頻度の粒間隔１９００オングストロームを中心に、±１０％以内に９０％以上の粒が含まれた。この様に、単結晶粒は大きさも間隔も揃い、しかも粒と粒は各々分離していた。
【０３６５】
この粒の上に、図８４（ｃ）に示すように第２の非晶質シリコン９０３を２０００オングストローム堆積した。この非晶質シリコンの平均原子間隔は１．００５であった。
【０３６６】
この後、５８０℃で３０分熱処理し、図８４（ｄ）に示すように、粒状単結晶シリコン９０４を結晶の種として、第２の非晶質シリコンが固相成長し、多結晶シリコン９０５が形成される。ＴＥＭ写真から多結晶シリコンのグレインを調べた所、幅１９００オングストローム程度の柱状になっており、各々の柱状グレインが、垂直方向に＜１００＞配向していた。また、多結晶シリコンのグレイン内も、図８６（ａ）に示すように、通常の任意核形成による固相成長膜に比較して、結晶性が良好であった。この原因は明確では無いが、おそらく、結晶種として用いた単結晶粒の結晶性が極めて良好なためではないかと予想している。
【０３６７】
比較のため、通常の非晶質膜固相成長により形成した多結晶膜の大粒径グレインの結晶性を図８６（ｂ）にＴＥＭ写真で示す。グレイン内部には双晶等の欠陥が多数見られる。しかもこれらの欠陥は１２００℃以上の高温で熱処理しない限り、容易には消滅しない。
【０３６８】
このようにしてグレインの大きさが揃った多結晶シリコン膜を形成した後、多結晶シリコン膜表面をエッチングして平坦化するとともにパターニングを行い、図８４（ｅ）に示したように表面が平坦な多結晶シリコン膜９０５をＲＩＥ等で島状に成形した。次に、Ｂ＋チャネルイオン注入をドーズ量１×１０^１３ａｔｏｍｓ／ｃｍ^−２、４０ｋｅＶの条件で行った図８４（ｆ）。この後、多結晶シリコン膜９０５表面を熱酸化して、ゲート絶縁膜９０６を形成した。通常の多結晶膜表面は、様々な面方位のグレインで構成されているため、熱酸化でゲート絶縁膜を形成すると、各々の面方位で異なった酸化速度を有するため、酸化膜厚は１割程度ばらつく。このように酸化膜厚のばらつきを残したまま、トランジスタを形成した場合、しきい値電圧が大きくばらつく原因となる。ところが、本方法で形成した場合、多結晶の表面は殆ど（１００）面であるため、ＴＥＭ写真による測定の結果、３％程度のばらつきで抑えられていた。
【０３６９】
次に図８４（ｇ）に示したように、ゲート電極９０７を形成した後、ゲート側壁に絶縁膜を堆積し、ソース・ドレインの導電層形成の為に、Ａｓ^＋イオン注入を２ｘ１０^１９ａｔｏｍｓ／ｃｍ^−３、４０ｋｅＶで行う。そして層間絶縁膜９０８を堆積し、電極形成用の開口部を設けた後に、ソース／ドレイン電極９０９、９１０を形成した。
【０３７０】
このようにして、形成した薄膜トランジスタの電気特性を測定したところ、グレインの大きさが１９００オングストロームと大きく、しかも１５００オングストローム以下のグレインが無いために、多結晶膜表面のどの場所にトランジスタのチャネル領域が来ても、素子特性が安定していた。例えば、室温で移動度のばらつきを調べると、図８７に示すように、従来の固相成長膜を用いる場合よりも、格段に移動度のばらつきが減少した。
【０３７１】
従来の膜を用いた場合のＶｇ−エレクトロン移動度特性は、図８８に示すように、粒界がチャネル領域にたまたま存在しなかった場合と、存在した場合で、大きく異なってくる。この場合のエレクトロンの移動度の温度依存性を測定した結果を図８９に示す。従来膜は、チャネル領域に粒界が存在する場合に、移動度は温度の低下に伴い大きく減少し、粒界が存在する場合と比較して、移動度の差は一層顕著になる。これに対して、本実施例の膜は、図８８中に示したように、粒界がチャネル領域に均等に存在するため、素子特性が安定している。また、温度依存性も、図８９に示した領域に落ちついていた。
【０３７２】
なお、前記実施例では、熱処理に際しての非晶質シリコンの平均原子間隔をシリコン単結晶と同程度となるようにし、歪みのない単結晶シリコン膜を得たが、１．０２以上となるようにしてもよい。
【０３７３】
また、前記実施例では、全面に堆積した第一の非晶質シリコン膜を熱処理し、単結晶粒を形成したが、第一の非晶質シリコン膜を堆積後にＲＩＥ等によって、成形しても良い。次に本発明の第１４の実施例としてこの例を示す。
【０３７４】
まず、上述の非晶質シリコン膜を堆積した後、一旦堆積装置から出して図９０（ａ）に示すように０．２μｍ幅の線状に整形した後、表面の自然酸化膜を剥離して清浄表面とし、再び堆積装置内に搬入した。このとき、平均原子間隔を測定すると、１．０２であった。この状態で水素雰囲気で５５０℃２時間晒し、装置より搬出した。ＳＥＭ写真で単結晶粒の並びを調べると、図９０（ｂ）に示すように、単結晶粒がほぼ一列に並んでいた。ここに第２の非晶質シリコン膜９０３を堆積して、図９０（ｃ）に示すように整形する。第一の非晶質シリコン膜９０３より形成した単結晶シリコン粒９０４を結晶核として第２の非晶質シリコン膜９０３を固相成長すると、第２の非晶質シリコン膜は図９０（ｄ）に示したように、粒界が垂直方向に走る、いわゆるバンブー構造の多結晶膜になった。ここに、図９０（ｅ）に示した様に粒界に平行にチャネルが形成されるようにしたトランジスタを形成した。多結晶膜のグレインサイズはおよそ２０００オングストロームであった。この構造では移動度のばらつきは更に改善され、図９１に示すように極めて狭い範囲内に制御することができた。
【０３７５】
次に本発明の第１５の実施例を示す。
【０３７６】
この例も第１４の実施例と同様に、単結晶シリコンを得るに当たり、非晶質シリコンの平均原子間隔を予めシリコン単結晶の１．０２倍以上からなる膜を用い、熱処理を行って固相成長により形成した、結晶性の極めて良好な粒状の単結晶シリコンを用い、結晶粒径の揃った多結晶シリコンを形成して、移動度が高くしかもバラツキが小さい薄膜トランジスタを形成した例である。ここではゲート電極９０７の上層に多結晶シリコン９０５からなる素子領域を形成したことを特徴とする。
【０３７７】
図９２（ａ）に示したように、シリコン基板９０１上に絶縁膜９０２を堆積した後、多結晶シリコン膜からなるゲート電極９０７を形成した。次に、ＣＶＤ法により、ゲート絶縁膜９０６を堆積した。
【０３７８】
次いで図９２（ｂ）に示すように、ゲート絶縁膜９０６の上に、非晶質シリコン膜９０３を平均原子間隔が単結晶シリコンの１．０２倍以上となるように堆積した。堆積膜厚は４０ｎｍとし、平均原子間隔を測定したところ、単結晶の１．０２倍であった。この基板を図２に示した装置内に設置し、非酸化性雰囲気の５５０℃２時間熱処理したところ、図９２（ｃ）に示したように粒状の単結晶シリコンが得られた。ＴＥＭ写真を用いた詳細な観察により、この単結晶粒も、垂直方向に＜１００＞軸が配向しており、しかも、大きさと粒間隔がほぼ揃っていることが観察された。図９３に示すように、粒径分布を調べると、最大出現頻度の粒径９００オングストロームを中心に、±２０％以内に９０％以上の粒が含まれている。図９４に示したように、粒間隔を調べると、最大出現頻度の粒間隔１２００オングストロームを中心に、±２０％以内に９０％以上の粒が含まれている。
【０３７９】
次に同一装置内で図９２（ｄ）に示すように第２の非晶質シリコン膜９０３を１２００オングストローム堆積した。この非晶質膜の平均原子間隔は、単結晶の１．００９倍であった。堆積装置内で６００℃１５分熱処理したところ、図９２（ｅ）に示すように、第２の非晶質シリコン膜９０３は単結晶シリコン粒を結晶種として、固相成長により単結晶化し、多結晶シリコンが形成された。この多結晶シリコンもＴＥＭ写真を用いて測定したところ、前記実施例１４と同様にグレインの大きさが揃い、垂直方向に＜１００＞軸が優先的に配向した多結晶薄膜であった。 グレインの大きさが揃った多結晶シリコン膜を形成した後、図９２（ｆ）に示したように多結晶シリコン膜をＲＩＥ等で島状に成形した。次に、ドーズ量１×１０^１３ａｔｏｍｓ／ｃｍ^２、４０ｋｅＶでＰイオンをチャネルイオン注入した。そして活性化の為の熱処理を９００℃３０分行った。
【０３８０】
次に、ソース・ドレインの導電層形成の為に、Ｂ^＋イオン注入を３×１０^１５ａｔｏｍｓ／ｃｍ^２、２０ｋｅＶで行う。層間絶縁膜９０８を堆積し、電極形成用の開口部を設けた後に、ソース／ドレイン電極９０９、９１０を形成した。
【０３８１】
このようにして請求項１の方法を用いて形成した単結晶シリコンを用いた薄膜トランジスタは、下地側のチャネル領域も１２００オングストローム程度の均一な粒径のグレインで構成されている。通常のＣＶＤ法で、導電性不純物濃度の低い多結晶シリコンを堆積すると、粒径は僅か３００オングストローム程度にしかならない。このためキャリアの移動度は粒界での散乱により非常に小さくなる。また通常の非晶質膜の固相成長で形成した多結晶シリコンでも、下地との界面には玉砂利状の微小なグレインが多数存在し、移動度の減少の原因となっていた。ところが、この方法により形成した多結晶膜に於いては、チャネル領域である下地界面に微小グレインが全く無く、しかも結晶性が格段に向上しているため、移動度のバラツキが改善され、平均的な移動度も格段に向上している。また、移動度に影響する膜中酸素濃度をＳＩＭＳ分析により測定したところ、図９５に示すように、第一の非晶質膜の膜質が影響する下地界面近傍には酸素濃度が極めて低かった。これにより、酸素原子による散乱も低減され、高移動度の素子が作成出来た。
【０３８２】
次に本発明の第１３の参考例を示す。
【０３８３】
この例では図９６乃至図１０４に示すように、固相成長により形成した極めて結晶性の良好な単結晶シリコンを用いて形成した、ソースドレイン持ち上げ型ＭＯＳすなわちエレベーテッドソースドレインＭＯＳ素子について説明する。この方法で形成したＭＯＳ素子ではゲート酸化膜直下のチャネル領域に不純物がほとんど入っていない層を形成することができるため、キャリアの走行が不純物によって妨げられることなく、高移動度のトランジスタを得ることができるという特徴を有する。また、ゲート酸化膜直下で不純物濃度が高ければ高いほど反転層形成時の垂直方向の電界が強くなるため、キャリアがより強く酸化シリコン／シリコン界面に張り付いて走行するため、界面のわずかな凹凸もキャリアの散乱の原因となっていたが、本発明のＭＯＳ素子によればこのような問題もない。
【０３８４】
まず図９６に示すように、シリコン基板８０１表面に選択酸化によりフィールド酸化膜８０２を形成する。そして必要に応じて閾値電圧調整のためのイオン注入を行う。
【０３８５】
そして図９７に示すように、素子領域表面の清浄化を行った後、膜厚２０ｎｍのノンドープの非晶質シリコン膜８０３を堆積する。堆積直後の測定結果では、平均原子間隔は、単結晶シリコンの１．０３倍であった。
【０３８６】
この後、図９８に示すように、堆積装置と同一装置内で、表面自然酸化膜の付着を抑えながら、５５０度１時間の熱処理を行い、単結晶シリコン８０４を形成した。このときシリコン基板上では単結晶８０４となるが、フィールド酸化膜８０２上では多結晶シリコン膜８０４Ｓとなっている。
【０３８７】
そして図９９に示すように素子領域のパターニングを行い、図１００に示すようにゲート酸化膜８０５を形成する。
【０３８８】
さらに図１０１に示すようにこの上層に多結晶シリコン膜８０６を堆積し図１０２に示すようにこれらをパターニングしてゲート電極８０６を形成する。
【０３８９】
そして図１０３に示すようにこのゲート電極８０６をマスクとしてイオン注入を行いソース・ドレインＳ，Ｄを形成し、さらに層間絶縁膜８０７を形成した後コンタクトホールを介してソース電極８０８、ドレイン電極８０９、ゲート電極８１０を形成し、図１０４に示すようにＭＯＳ素子が完成する。
【０３９０】
このようにして形成されたＭＯＳ素子のゲート電圧と移動度との関係を測定した結果を図１０５に曲線ａに示すように極めて高移動度の特性を得ることができた。比較のために従来例の測定結果を曲線ｂに示す。従来の方法では高温でのエピタキシャル成長によって単結晶シリコンを形成するため基板からのオートドーピングによって、ゲート酸化膜直下のチャネル領域に不純物がドーピングされるのを避けることができないが、この方法によれば、低温下で結晶性の良好な単結晶シリコン膜を形成することがきるため基板からのオートドーピングもなく、ゲート酸化膜直下のチャネル領域に不純物がほとんどはいっていない層をつくることができる。このように、キャリアの走行の散乱体となる不純物のない単結晶層を形成することができるため、高移動度を得ることができる。またゲート酸化膜直下で不純物濃度が高ければ高いほど、反転層形成時の垂直方向の電界が高くなる。垂直電界が高いと、キャリアはより強く酸化シリコン／シリコン界面にはりついて走行することになり、界面のわずかな凹凸もキャリアの散乱体となり、移動度低下の原因となるが、本発明の方法で形成される素子構造ではゲート酸化膜下での不純物濃度を低くすることができるため移動度の低下を防ぐことができる。 またこの方法を用いて形成したリングオシレータの遅延時間とＶｄｄとの関係を測定した結果を図１０６に示す。この結果からも高速動作可能であることがわかる。これは本発明の素子では、上記効果に加えソースドレイン領域はフィールド酸化膜上に形成されるため、印加電圧に応じて基板側に空乏層が広がるのを防ぐことができ、充放電の度に遅延が生じるという問題もないためである。
【０３９１】
このように本発明の方法を用いて形成したリングオシレータでは、移動度の向上とソース・ドレインのキャパシタンス低下の両方の効果により大幅な高速化をはかることができる。
【０３９２】
次に本発明の第１４の参考例を示す。
【０３９３】
この例でも固相成長により形成した極めて結晶性の良好な単結晶シリコンを用いて形成した、ソースドレイン持ち上げ型ＭＯＳすなわちエレベーテッドソースドレインＭＯＳ素子について説明する。この方法では、図１０７乃至図１１５に示すように、トレンチ分離された素子領域内に、ゲート電極を形成しこの上層にソース・ドレイン領域のみを本発明の固相成長で形成し、チャネルは基板表面に形成するようにしている。この素子では低温下でソースドレインを形成することができるため不純物分布を急峻にすることができパンチスルーが抑制されるという特徴を有する。
【０３９４】
この方法でも前記第１３の参考例と同様、ゲート酸化膜直下のチャネル領域に不純物がほとんど入っていない層を形成することができるため、キャリアの走行が不純物によって妨げられることなく、高移動度のトランジスタを得ることができるという特徴を有する。また、ゲート酸化膜直下で不純物濃度が高ければ高いほど反転層形成時の垂直方向の電界が強くなるため、キャリアがより強く酸化シリコン／シリコン界面に張り付いて走行するため、界面のわずかな凹凸もキャリアの散乱の原因となっていたが、本発明のＭＯＳ素子によればこのような問題もない。
【０３９５】
まず図１０７に示すようなシリコン基板８１１表面にＳＯＩ法によりトレンチ８１２を形成し図１０８に示すように、絶縁膜８１３を埋め込み素子分離を行う、そして必要に応じて閾値電圧調整のためのイオン注入を行う。
【０３９６】
そして図１０９に示すように、ゲート酸化膜８１４を形成し、さらに図１１０に示すようにこの上層に多結晶シリコン膜を堆積し図１１１に示すようにこれらをパターニングしてゲート電極８１５を形成する。
【０３９７】
そして図１１２に示すようにこのゲート電極８１５の上層にＣＶＤ法により酸化シリコン膜８１６を形成しＲＩＥ法によりゲート電極８１５の側壁のみに残留せしめ、リンイオンを注入して基板表面にｎ⁻層（図示せず）を形成する。そしてさらに基板表面の清浄化を行った後、膜厚２０ｎｍのノンドープの非晶質シリコン膜８１７を堆積する。堆積直後の測定結果では、平均原子間隔は、単結晶シリコンの１．０３倍であった。
【０３９８】
この後、図１１３に示すように、堆積装置と同一装置内で、表面自然酸化膜の付着を抑えながら、５５０度１時間の熱処理を行い、単結晶シリコン８１７Ｓを形成した。このときシリコン基板上では単結晶８１７Ｓとなるが、絶縁膜上では多結晶シリコン膜となっており、単結晶シリコンと多結晶シリコンの間で選択性をもつエッチング条件で選択エッチングを行い多結晶シリコンをエッチング除去して単結晶シリコン８１７Ｓのみを残留せしめる。
【０３９９】
そして図１１４に示すようにパッシベーション膜としての酸化シリコン膜８１８を形成し、これにコンタクトホールを介してソース・ドレイン電極８２１、ゲート電極８２２を形成し、図１１５に示すようにエレベーテッドＭＯＳトランジスタが完成する。
【０４００】
このようにして形成されたＭＯＳトランジスタのゲート電圧とドレイン電流との関係を測定した結果を図１１６に曲線ａに示す。比較のために従来例の測定結果を曲線ｂに示す。ここで示したトランジスタではチャネル長が０．２３μｍであった。このように非常に微細な素子であるにもかかわらず、サブスレッシホールド領域も良好な特性を得ることができることが分かる。このように微細素子であるにもかかわらず、パンチスルーが十分に良くできている理由については明らかではないが、ソースドレインの不純物分布が急峻になっているからであると考えられる。これは工程が特に低温下で行われていることにある。
【０４０１】
また図１１７に曲線ａで閾値電圧とチャネル長との関係を示した。この結果から本発明によればチャネル長が０．２２μｍ程度になっても閾値電圧が低下していないことがわかる。これも不純物の再分布がないためであると考えられる。比較のために従来法で形成したトランジスタの特性を曲線ｂに示した。このトランジスタではチャネル長が０．５μｍ程度ですでにショートチャネル効果が出現している。
【０４０２】
次に本発明の第１５の参考例を示す。
【０４０３】
この例では本発明の固相成長方法を用いてバイポーラトランジスタとＭＯＳトランジスタとを集積化した例について説明する。
【０４０４】
ＭＯＳトランジスタとバイポーラトランジスタとを比較すると、ＭＯＳトランジスタは大規模集積化が可能であるという長所がある反面、動作が遅いという欠点がある。これに対しバイポーラトランジスタは出力に大電流が得られ高速動作が可能であるという長所があるが、素子面積が大きく集積化が不利であるという欠点がある。この２種類のトランジスタを同時に用いて両者の長所を生かした大規模集積回路が知られている。
【０４０５】
このような集積回路は、図１３３に一例を示すようにシリコン基板上にＭＯＳトランジスタとバイポーラトランジスタとを横に配列し、バイポーラトランジスタのベースとＭＯＳトランジスタのドレインとを電気的に接続し、ドレイン電流をバイポーラで増幅して大電流を得るようにすることができるという利点を有している。しかしながら、ドレインとベースが離れているため、配線を引き回さなければならず、大面積を必要とする上、互いの素子領域に影響を与えることなく形成しなければならないため、非常に複雑で長い工程を必要とするという問題があった。
【０４０６】
この例ではこのような問題を解決すべく、ＭＯＳトランジスタのドレインに直接ベースが接続するように、上層に本発明の固相成長法で形成した単結晶シリコン内にバイポーラトランジスタを形成したものである。
【０４０７】
図１１８乃至図１３１にその製造工程図、図１３２に等価回路図を示す。
【０４０８】
まず図１１８に示すように、シリコン基板９１１表面に選択酸化によりフィールド酸化膜９１２を形成する。そして必要に応じて閾値電圧調整のためのイオン注入を行う。
【０４０９】
そして図１１９に示すように、熱酸化を行いゲート絶縁膜９１３となる膜厚１０ｎｍの酸化シリコン膜を形成し、さらに図１２０に示すようにゲート電極９１４となるリンドープの多結晶シリコン膜を形成し、図１２１に示すようにこれらをパターニングする。
【０４１０】
この後図１２２に示すようにＣＶＤ法により酸化シリコン膜を形成した後ＲＩＥ法を用いてゲート電極９１４の側壁に酸化シリコン膜９１５を形成し、これをマスクとしてＡｓイオンを５×１０^１５ａｔｏｍｓ／ｃｍ^２イオン注入し、９００℃３０分の窒素雰囲気中での熱処理を行い、図１２３に示すようにソース・ドレイン領域９１６を形成する。
【０４１１】
そして図１２４に示すようにＣＶＤ法により全面に膜厚３００ｎｍの酸化シリコン膜を堆積し、図１２５に示すようにドレイン領域９１６にコンタクトホール９１８を形成する。
【０４１２】
そして図１２６に示すように全面に平均原子間隔が単結晶シリコンのそれとほぼ等しくなるように非晶質シリコン膜９１９を膜厚５０ｎｍ程度堆積する。このときシランガスと同時にホスフィンガスＰＨ_３を流し、あらかじめリンが微量含まれた非晶質シリコン膜とした。
【０４１３】
この後、図１２７に示すように、堆積装置と同一装置内で、表面自然酸化膜の付着を抑えながら、６００℃３時間の熱処理を行い、ｎ⁻単結晶シリコン９２０を形成した。単結晶化距離を測定するためにあらかじめ用意したモニタ装置を調べると、結晶化距離は１５μｍであった。またリン濃度を測定すると８×１０^１７ａｔｏｍｓ／ｃｍ^３であった。
【０４１４】
そして図１２８に示すように素子領域のパターニングを行い、図１２９に示すようにこの単結晶シリコン９２０の一部にボロンイオンを注入しｐ⁻領域９２１を形成した。
【０４１５】
次いで図１３０に示すようにエミッタ・コレクタ領域にボロンをイオン注入してｐ^＋領域９２２を形成し、不純物活性化のために８５０℃５分間のアニールをＲＴＡで行い図１３１に示すようにソース電極９２３、ゲート電極９２４、エミッタ電極９２５、コレクタ電極９２６を形成し、集積回路が完成する。
【０４１６】
このように積層構造でありながら、６００℃という低温下で結晶性の良好な単結晶シリコンを得ることができ、かつ下層との界面特性が極めて良好であり、ドレインとベースの接続部における接触抵抗が極めて低い上、ＭＯＳトランジスタの拡散層に拡散長の伸びを生じるようなこともない。
【０４１７】
この集積回路によれば、積層構造であるため素子面積を大幅に低減することができるのみならず、バイポーラトランジスタがＭＯＳトランジスタの上方に形成されるため図１３３に示した従来の構造に比べ、バイポーラ領域で発生する熱がＭＯＳトランジスタに伝達されにくく、ＭＯＳトランジスタの動作特性に影響を及ぼすことがない。またバイポーラトランジスタ自身も上層に位置するため放熱性がよく温度上昇を抑制することができる。
【０４１８】
【発明の効果】
本発明では、キャパシタの下部電極を粒状の導電層で構成しているため、表面の凹凸によってキャパシタ面積の増大をはかることができる。
【０４１９】
また、熱処理を施して絶縁膜を収縮させ、粒状の第２導電層を第１の導電層に導通させることにより、極めて容易に容量の大きいキャパシタを形成することができる。
【図面の簡単な説明】
【図１】本発明の半導体薄膜の形成原理を示す説明図
【図２】本発明の第１の参考例で用いられる薄膜形成装置を示す図
【図３】本発明の第１の参考例の膜堆積のシーケンスの概略を示す図
【図４】本発明の第１の参考例の薄膜形成工程を示す図
【図５】本発明の第１の参考例における平均原子間距離が１．０２以上の非晶質シリコン膜を得るための成膜速度と基板温度との関係を示す図
【図６】本発明の第１の参考例における表面からの深さと平均原子間距離との関係を測定した結果を示す図
【図７】本発明の第１の参考例の方法及び従来例の方法における横方向固相成長速度の測定結果を示す比較図
【図８】本発明の第２の参考例の薄膜形成方法を示す工程図
【図９】本発明の第２の参考例および従来例における非晶質シリコン膜の膜厚と単結晶シリコン薄膜の欠陥密度との関係を示す図
【図１０】本発明の第２の参考例および従来例における非晶質シリコン膜の膜厚とエレクトロンモビリティとの関係を示す図
【図１１】本発明の第２の参考例におけるアニール時の真空度とエレクトロンモビリティとの関係を示す図
【図１２】本発明の第２の参考例におけるアニール時の水素流量とエレクトロンモビリティとの関係を示す図
【図１３】本発明の第６の参考例における表面からの深さとヒ素濃度との関係を示す図
【図１４】本発明の第７の参考例の半導体薄膜の製造工程図
【図１５】同半導体薄膜を用いた半導体装置の製造工程の変形例を示す図
【図１６】本発明の第８の参考例の半導体薄膜の製造工程図
【図１７】本発明の第１の実施例で形成された半導体薄膜を示す図
【図１８】本発明の第１の実施例の半導体薄膜の製造工程図
【図１９】本発明の第１の実施例の半導体薄膜の製造工程で得られた単結晶薄膜を示す写真
【図２０】本発明の第１の実施例の半導体薄膜の製造工程で得られた単結晶薄膜を示す写真
【図２１】本発明の第１の実施例の半導体薄膜の製造工程で得られた単結晶薄膜を示す写真
【図２２】本発明の第２の実施例の半導体薄膜の製造工程図
【図２３】本発明の第３の実施例の半導体薄膜の製造工程図
【図２４】本発明の第３の実施例の半導体薄膜の製造工程で得られた単結晶薄膜を示す写真
【図２５】本発明の第３の実施例の半導体薄膜の製造工程で得られた単結晶薄膜を示す写真
【図２６】本発明の第３の実施例の半導体薄膜の製造工程で得られた単結晶薄膜を示す写真
【図２７】非晶質膜の膜厚と得られる単結晶粒の直径の関係を示す図
【図２８】下地絶縁膜が異なるときの非晶質膜の膜厚と得られる単結晶粒の直径の関係を示す図
【図２９】本発明の第４の実施例の半導体薄膜の形成工程を示す図
【図３０】本発明の第５の実施例のキャパシタの製造工程を示す図
【図３１】本発明の第９の参考例の半導体薄膜の形成原理を示す説明図
【図３２】本発明の第９の参考例で用いられる薄膜形成装置を示す図
【図３３】本発明の第９の参考例における平均原子間距離が単結晶の０．９８〜１．０２までの非晶質シリコン膜を得るための成膜速度と基板温度との関係を示す図
【図３４】本発明の第９の参考例で用いられる熱処理装置を示す図
【図３５】本発明における成長距離の時間依存性を示す図
【図３６】本発明の第９の参考例における断面ＴＥＭ写真を示す図（熱処理５分）
【図３７】本発明の第９の参考例における電子線回折像断面ＴＥＭ写真を示す図（熱処理２時間）
【図３８】本発明の第９の参考例で用いられるラマン測定装置を示す図
【図３９】同装置で測定されたラマンピークを示す図
【図４０】本発明の第９の参考例における応力分布を示す図
【図４１】本発明の第１０の参考例のシリコン薄膜形成工程を示す図
【図４２】本発明の第１０の参考例における応力分布を示す図
【図４３】本発明の第１０の参考例で形成されたシリコン薄膜のＳＥＭ像を示す図
【図４４】本発明の第６の実施例で用いられる試料構造を示す図
【図４５】本発明の第６の実施例で形成されたシリコン粒のＳＥＭ像を示す図
【図４６】同シリコン粒のＴＥＭ像を示す図
【図４７】同シリコン粒の電子線回折像を示す図
【図４８】従来の方法で形成されたシリコン粒のＴＥＭ像を示す比較図
【図４９】非晶質膜の平均原子間隔と単結晶粒の結晶性との相関関係を示す図
【図５０】本発明の第７の実施例の半導体薄膜の製造工程図
【図５１】従来のシリコン粒の形成を示す比較図
【図５２】本発明の半導体薄膜の製造工程で得られた単結晶薄膜を示す図
【図５３】本発明の第８の実施例の半導体薄膜の製造工程図
【図５４】本発明の第９の実施例のキャパシタの製造工程図
【図５５】本発明の第９の実施例のキャパシタの製造工程図
【図５６】本発明の第９の実施例のキャパシタの製造工程図
【図５７】本発明の第９の実施例のキャパシタの製造工程図
【図５８】本発明の第９の実施例のキャパシタの製造工程図
【図５９】本発明の第９の実施例のキャパシタの製造工程図
【図６０】本発明の第９の実施例のキャパシタの製造工程図
【図６１】本発明の第９の実施例で得られたシリコン薄膜のＳＥＭ像を示す図
【図６２】本発明の第９の実施例で得られたシリコン薄膜のＴＥＭ像を示す図
【図６３】非晶質膜の膜厚と熱処理後の表面状態の差を示す比較図
【図６４】堆積膜厚と粒分布密度を示す図
【図６５】本発明の第９の実施例における自然酸化膜の除去工程を示す説明図
【図６６】本発明の第９の実施例で得られたキャパシタの容量と従来のキャパシタの容量との比較図
【図６７】本発明の第１０の実施例のキャパシタの製造工程図
【図６８】本発明の第１０の実施例のキャパシタの製造工程図
【図６９】本発明の第１０の実施例のキャパシタの製造工程図
【図７０】本発明の第１０の実施例のキャパシタの製造工程図
【図７１】本発明の第１０の実施例のキャパシタの製造工程図
【図７２】本発明の第１０の実施例のキャパシタの製造工程図
【図７３】本発明の第１１の実施例の半導体薄膜形成工程図
【図７４】同工程で得られた半導体薄膜のＳＥＭ像を示す図
【図７５】本発明の第１１の参考例の半導体装置の製造工程を示す図
【図７６】同工程で得られたＭＯＳトランジスタの素子特性を示す図
【図７７】下地基板に形成されているＭＯＳトランジスタの同工程の前後での特性変化を示す図
【図７８】本発明の第１２の参考例の半導体装置の製造工程図
【図７９】同工程で形成されたトランジスタの種からの距離とエッチピットとの関係を示す図
【図８０】同工程で形成されたトランジスタの種からの距離と素子特性との関係を示す図
【図８１】本発明の第１２の実施例の半導体装置の製造工程を示す図
【図８２】同工程で形成された半導体装置の素子特性を示す図
【図８３】同工程で形成された半導体装置の接合特性を示す図
【図８４】本発明の第１３の実施例の半導体装置の製造工程を示す図
【図８５】同工程で得られた半導体薄膜の粒径分布を示す図
【図８６】同工程および従来の工程で得られた半導体薄膜の平面ＴＥＭ写真を示す図
【図８７】同工程で形成されたトランジスタのエレクトロンモビリティを測定した結果を示す図
【図８８】同工程で形成されたトランジスタのＶｇ−Ｉｄ特性を示す図
【図８９】同工程で形成されたトランジスタと従来のトランジスタのエレクトロンモビリティの温度依存性を測定した結果を示す図
【図９０】本発明の第１４の実施例の半導体装置の製造工程を示す図
【図９１】同工程で形成されたトランジスタのエレクトロンモビリティを測定した結果を示す図
【図９２】本発明の第１５の実施例の半導体装置の製造工程を示す図
【図９３】同工程で得られた半導体薄膜の粒径分布を示す図
【図９４】同工程で得られた半導体薄膜の粒間隔分布を示す図
【図９５】同工程で得られた半導体装置の膜中酸素濃度分布を示す図
【図９６】本発明の第１３の参考例の半導体装置の製造工程図
【図９７】本発明の第１３の参考例の半導体装置の製造工程図
【図９８】本発明の第１３の参考例の半導体装置の製造工程図
【図９９】本発明の第１３の参考例の半導体装置の製造工程図
【図１００】本発明の第１３の参考例の半導体装置の製造工程図
【図１０１】本発明の第１３の参考例の半導体装置の製造工程図
【図１０２】本発明の第１３の参考例の半導体装置の製造工程図
【図１０３】本発明の第１３の参考例の半導体装置の製造工程図
【図１０４】本発明の第１３の参考例の半導体装置の製造工程図
【図１０５】同工程で得られたトランジスタのゲート電圧と移動度との関係を示す図
【図１０６】同工程で得られたリングオシレータの遅延時間とＶｄｄとの関係を示す図
【図１０７】本発明の第１４の参考例の半導体装置の製造工程図
【図１０８】本発明の第１４の参考例の半導体装置の製造工程図
【図１０９】本発明の第１４の参考例の半導体装置の製造工程図
【図１１０】本発明の第１４の参考例の半導体装置の製造工程図
【図１１１】本発明の第１４の参考例の半導体装置の製造工程図
【図１１２】本発明の第１４の参考例の半導体装置の製造工程図
【図１１３】本発明の第１４の参考例の半導体装置の製造工程図
【図１１４】本発明の第１４の参考例の半導体装置の製造工程図
【図１１５】本発明の第１４の参考例の半導体装置の製造工程図
【図１１６】同装置で得られたトランジスタのゲート電圧とドレイン電流との関係を示す図
【図１１７】同装置で得られたトランジスタのチャネル寸法と閾値電圧との関係を示す図
【図１１８】本発明の第１５の参考例の半導体装置の製造工程図
【図１１９】本発明の第１５の参考例の半導体装置の製造工程図
【図１２０】本発明の第１５の参考例の半導体装置の製造工程図
【図１２１】本発明の第１５の参考例の半導体装置の製造工程図
【図１２２】本発明の第１５の参考例の半導体装置の製造工程図
【図１２３】本発明の第１５の参考例の半導体装置の製造工程図
【図１２４】本発明の第１５の参考例の半導体装置の製造工程図
【図１２５】本発明の第１５の参考例の半導体装置の製造工程図
【図１２６】本発明の第１５の参考例の半導体装置の製造工程図
【図１２７】本発明の第１５の参考例の半導体装置の製造工程図
【図１２８】本発明の第１５の参考例の半導体装置の製造工程図
【図１２９】本発明の第１５の参考例の半導体装置の製造工程図
【図１３０】本発明の第１５の参考例の半導体装置の製造工程図
【図１３１】本発明の第１５の参考の半導体装置の製造工程図
【図１３２】同半導体装置の等価回路図
【図１３３】従来例の半導体装置を示す図
【図１３４】従来例の半導体薄膜の形成工程を示す図
【図１３５】従来例の半導体薄膜の形成の経過を示す説明図
【図１３６】本発明の検証に用いたシミュレータの基本モデルを示す図
【図１３７】本発明の検証に用いたシミュレータの変数を示す図
【図１３８】本発明の検証に用いたシミュレータの基本出力を示す図
【図１３９】従来の方法で形成された単結晶薄膜試料の電子線回折像
【図１４０】従来の方法を説明するための試料構造を示す図
【図１４１】従来の方法で得られた単結晶薄膜の光学顕微鏡写真および成長距離
の時間依存性質を示す図
【図１４２】同工程で得られた半導体薄膜のＴＥＭ像を示す図
【図１４３】同工程で得られた半導体薄膜のＴＥＭ像を示す図
【図１４４】同工程で得られた半導体薄膜のＴＥＭ像を示す図
【図１４５】同工程で得られた半導体薄膜のＴＥＭ像を示す図
【図１４６】従来例の半導体薄膜の成長を示す模式図
【図１４７】従来例の半導体薄膜の応力分布を示す図
【符号の説明】
１…シリコン基板
２…シリコン酸化膜
３…非晶質シリコン層
４…単結晶シリコン層
６…ゲート電極
７…ソース・ドレイン領域
８…素子分離絶縁膜
１１…シリコン基板表面
１２…シリコン酸化膜
１３…非晶質シリコン
１４…単結晶シリコン
４１…シリコン基板
４２…シリコン酸化膜
４３…非晶質シリコン
４４…単結晶シリコン粒
５１…シリコン基板
５２…シリコン酸化膜
５３…非晶質シリコン
５４…単結晶シリコン
６１…シリコン基板
６２…酸化シリコン膜
６３…レジストパターン
６４…イオン
６５…酸化シリコン膜
６６…レジストパターン
６７…イオン
６９…単結晶粒状体
７０…酸化シリコン膜
７１…多結晶シリコン膜
７２…酸化シリコン膜
７３…多結晶シリコン膜
１０１…チャンバー
１０２…原料ガス導入口
１０３…排気口
１０４…試料台
１０５…ビーム照射手段
１０６…受光管
２０２…酸化シリコン膜
２０３…開口部
２０４…非晶質シリコン膜
２０５…単結晶シリコン膜
２０６…非晶質ゲルマニウム
２０７…単結晶ゲルマニウム
３１１…チャンバー
３１２…原料ガス導入口
３１３…排気口
３１４…試料台
３１５…レーザ光源
３１６…分光器
３１７…マスフローコントローラ
４１６…Ａｒレーザ
４１７…分光器[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to formation of a single crystal and a polycrystal by solid phase growth.
[0002]
[Prior art]
Currently, in order to increase the degree of integration of LSIs, not only miniaturization of semiconductor elements but also layering of circuit elements has been actively attempted. For example, it is proposed to construct composite elements, multilayer capacitors, etc. consisting of a light receiving part, a signal transfer part, a high-speed arithmetic processing part such as BiMOS in order from the upper layer, rather than simply creating arithmetic and memory circuits by stacking. ing. In this way, the stacking of elements has gained many possibilities, such as the development of a new multi-functional element having a multilayer structure and the application to shortening the manufacturing process, and research and development are now being conducted both inside and outside the country.
[0003]
As a basic structure for producing such a laminated element, there is an SOI (Si Insulator) substrate structure. As process technologies for specifically realizing this lamination, there have been (1) a wafer bonding method, (2) a SIMOX (separation by implanted oxygen) method, and (3) a solid phase growth method. In the solid phase growth method (3), for example, as shown in FIG. 134A, an amorphous semiconductor film 3 (for example, amorphous Si) is previously formed at a low temperature of about 300 to 600 ° C. (for example, amorphous Si). It is deposited on a silicon oxide film 2 (insulating film insulator) formed on the silicon substrate 1 to form an SOI, which is also heat-treated at a low temperature of about 500 to 600 ° C., for example, to be single-crystallized in a solid state. Single crystal silicon 4 is formed as shown in FIG. 134 (b). Reference numeral 2 denotes a silicon oxide film formed by natural oxidation. As can be seen from the temperature range of the SOI process, the temperature is very low, and the redistribution of impurities introduced into the substrate or the like until the SOI process is almost impossible. As described above, the solid phase growth SOI technology has an advantage that it can be easily adapted to an actual process and can be easily laminated.
[0004]
However, the solid phase growth method has many disadvantages as described above, but is still difficult to use because of several drawbacks.
[0005]
That is, in the prior art, the solid phase growth distance is about 1 to 2 μm, and the dimensions are insufficient to mount the device. 10 for the crystalline film²⁰/ Cm³In this case, it is not appropriate to form a device in this region. Furthermore, in the prior art, the crystallinity of the solid phase growth region is not always good. When created, the mobility is 200-400cm with enhancement type n-MOS.²/ V · sec, which is 1/2 to 1/3 that of an ordinary single crystal substrate. In addition, at present, the solid-phase growth distance depends on factors caused by thermal phenomena. It depends. That is, during the solid phase growth from the seed part, in the non-crystalline region, each atom constituting the amorphous film repeats desorption and concentration at a specific frequency at the process temperature. However, with a certain probability, when the aggregate exceeds a certain size, growth begins to progress quickly using it as a seed. If this happens, the crystals that have grown from the original seeds will either collide with this or the crystallinity will deteriorate. Also, because of this thermal factor, there is a distribution that can be seen as a stochastic solid phase growth distance itself, and when creating millions or more of recrystallized regions, variations are likely to occur. There are concerns about reliability.
[0006]
In addition, in the prior art, it is considered that better crystals can be obtained by increasing the thickness of the film, and in the case of forming a single crystallized film by lateral solid phase growth using seeds, a thicker film is also experimentally used. It has also been reported that a wide area can be monocrystallized. Furthermore, when trying to move the atoms so as to change the shape of the material only by heat treatment, it was necessary to raise the temperature to almost the melting point, and there were many problems to be overcome. Furthermore, the phenomenon of solid-phase growth itself is hardly understood, and it is not possible to establish a new process or develop a new application. At best, it can be used as a load transistor using polycrystalline silicon, or a fuse ROM using polycrystalline silicon. It was the use degree as.
[0007]
[Problems to be solved by the invention]
Thus, in solid phase growth
1. Improving the crystallinity of the solid phase growth region
2. Perform reliable and reproducible solid phase growth (improved reliability)
Is an essential issue.
[0008]
If the above two problems are solved, a single crystal having good crystallinity can be provided at a low temperature by using a solid phase growth method.
[0009]
An object of the present invention is to provide a fine and large-capacity capacitor by using, for example, the above-described solid phase growth method to form an electrode having a small occupation area and a large surface area.
[0010]
An object of the present invention is to provide a semiconductor device and a semiconductor integrated circuit device having good crystallinity and high reliability by using, for example, the solid phase growth method.
[0011]
Another object of the present invention is to provide a diode having good characteristics, for example.
[0012]
Furthermore, an object of the present invention is to provide a thin film transistor and a transistor integrated circuit which have little variation in characteristics and high reliability.
[0013]
[Means for Solving the Problems]
  In the present invention, a first conductive layer having an insulating film is formed on the surface, an amorphous thin film is deposited on the first conductive layer, and the amorphous thin film is subjected to a solid phase growth by heat treatment to form a granular single crystal. Forming the first electrode composed of the first conductive layer and the granular single crystal by shrinking the insulating film by heat treatment and electrically connecting the first conductive layer and the granular single crystal. The capacitor insulating film and the second electrode are formed on the upper layer.
[0015]
Here, in the amorphous thin film, the average atomic spacing of the main constituent elements of the thin film is set to be 1.02 times or more of the average atomic spacing in the single crystal of the element.
[0016]
Further, an amorphous thin film may be deposited so as to substantially coincide with the average atomic spacing in the single crystal of the element.
[0017]
Desirably, during the heat treatment, the surface of the amorphous thin film is heated while being kept in a clean state in a non-oxidizing atmosphere, and is crystallized by solid phase growth to form a single crystal thin film.
[0018]
Preferably, this heat treatment is performed at a degree of vacuum of 10^-4Particularly preferably below Torr, preferably 10^-6The operation is performed under a high vacuum of Torr or less.
[0019]
Desirably, the heat treatment is performed in an inert gas atmosphere such as high-purity argon, nitrogen or helium, or in a reducing gas atmosphere such as hydrogen.
[0020]
Desirably, the heat treatment temperature is set to 450 ° C. to 600 ° C.
[0021]
More preferably, the amorphous thin film deposition step and the heat treatment step are continuously performed in the same chamber without breaking the vacuum.
[0030]
[Action]
When depositing an amorphous semiconductor thin film on a substrate or an insulating film using a solid phase growth method, the present inventors previously calculated the average interatomic spacing distribution of the amorphous film made of the main elements constituting the film. The inventors have found for the first time a method for controlling the shape and film quality during recrystallization as desired by changing the method (hereinafter referred to as “method related to the present invention”). In the method related to the present invention, first, in particular, the average atomic spacing distribution of the amorphous film made of the main element constituting the film is 1.02 times or more of the average atomic spacing distribution of the single crystal. A single crystal semiconductor thin film is formed by applying a recrystallization energy and performing solid phase growth in a state where the film is formed under various film forming conditions and the average atomic spacing distribution is maintained at 1.02 times or more of the single crystal. The second is to recrystallize the amorphous film made of the main element constituting the film in a state where the average atomic spacing is substantially equal to a single crystal.
[0031]
First, in a first method related to the present invention, an amorphous semiconductor thin film is formed at a deposition rate that is 1.02 times or more the average atomic spacing of single crystals at the deposition temperature, and heat treatment is performed. The method of forming such a state is characterized by maintaining a state in which the atomic interval is relaxed until immediately before recrystallization by applying recrystallization energy, etc., and recrystallizing at once at the time of heat treatment. There are several ways. In order to obtain an amorphous film having an average interatomic distance which is 1.02 times or more of the interatomic distance in this single crystal, the deposition rate and film thickness at the temperature of the heat treatment are largely governed. In this case, as a result of performing various experiments by changing the temperature and the gas composition, a film having an average interatomic distance of 1.02 or more is obtained when the film formation rate R is performed under the condition satisfying the following formula. I found out that
[0032]
logR (Å / min) ≧ −10614 / T (K) +14.857
In addition, in order to obtain an amorphous film having an average interatomic distance that is 1.02 times or more the interatomic distance in a single crystal, the impurity concentration at the heat treatment temperature, the base material for the heat treatment, and the film quality of the amorphous film Etc.
[0033]
That is, (1) depositing at a deposition rate in a specific range at each heat treatment temperature, (2) preparing a film thickness in a specific range at each heat treatment temperature, (3) at each heat treatment temperature Examples include preparing a specific range of film thickness and specific range of dopant impurity concentration, and (4) preparing a specific range of film thickness characterized by the base material at each heat treatment temperature. Further, (5) In order to maintain the above-described state in which the atomic spacing is relaxed on the amorphous surface, a combination of means for making the surface of the amorphous film a clean surface is combined (6) on the amorphous surface In addition, in order to maintain or further amplify the state in which the atomic spacing is relaxed, there is a means for depositing another film on the amorphous film surface and performing a heat treatment.
[0034]
Note that after the amorphous thin film is formed, the temperature may be once lowered and heat treatment may be performed again. However, when recrystallization energy such as heat treatment is applied, the amorphous thin film has an interatomic distance in the single crystal. It is necessary to prepare conditions such as a clean surface so as to have an average interatomic distance of 1.02 times or more. Further, the recrystallization energy may be energy other than thermal energy, such as electron beam irradiation or ultraviolet light irradiation, in addition to thermal energy.
[0035]
In the first method related to the present invention, basically, an example in which the present invention is applied to a semiconductor mainly composed of a covalent bond or a semiconductor amorphous is shown. If it adds, it is possible to apply.
[0036]
For example, in a third method related to the present invention, an amorphous thin film having a film thickness of 80 nm or less (more preferably 20 nm or less) is deposited on the surface of a substrate on which an insulating film having an opening is formed. An amorphous thin film having an average interatomic distance that is 1.02 times or more of the interatomic distance in GaN is obtained, and crystallization energy is applied while maintaining the amorphous thin film surface in a clean state in a non-oxidizing atmosphere. Thus, a single crystal is formed by solid phase growth to form a single crystal thin film. Preferably, this heat treatment is performed at a degree of vacuum of 10^-4Torr or less, more preferably 10^-6The operation is performed under a high vacuum of Torr or less. Desirably, this heat treatment is performed in an inert gas atmosphere such as high-purity argon, nitrogen, or helium. Desirably, the heat treatment temperature is set to 450 ° C. to 600 ° C. More preferably, the amorphous thin film deposition step and the heat treatment step are continuously performed in the same chamber without breaking the vacuum.
[0037]
In a fourth method related to the present invention, the distance from the surface to the interface with the insulating film reaches the interface on the substrate on which the insulating film having an opening is formed. An amorphous thin film having a thin film thickness is deposited to obtain an amorphous thin film having an average interatomic distance that is 1.02 times or more the interatomic distance in a single crystal. While maintaining the surface in a free surface state that allows free atoms on the surface to reach the interface freely, crystallization energy is imparted in a non-oxidizing atmosphere, single-crystallized by solid phase growth, Try to form. However, the average atomic spacing at this time is SiO provided separately on the silicon substrate.₂Monitoring was performed with an amorphous silicon film deposited thereon.
[0038]
In a fifth method related to the present invention, an opening is formed in an insulating film covering the substrate surface to expose the substrate surface, and a first amorphous thin film having a thickness of 20 nm or less is formed on the substrate surface. An amorphous thin film having an average interatomic distance that is 1.02 times or more the interatomic distance in a single crystal is deposited, and the surface of the first amorphous thin film is in a free surface state in a non-oxidizing atmosphere. The first crystallized thin film is formed by using the substrate as a crystal seed by solid phase growth to form a first single crystal thin film, and then a second film having a thickness of 80 nm or less is formed on the single crystal thin film. Amorphous thin film is deposited, crystallization energy is applied while maintaining the surface of the second amorphous thin film in a free surface state in a non-oxidizing atmosphere, and the substrate is used as a single crystal by solid phase growth. And a single crystal thin film is formed. Desirably, the step of imparting crystallization energy to the first amorphous semiconductor thin film comprises 10 steps.^-4Torr or less, more preferably 10^-6This is a step of heating under a high vacuum of Torr or less. More preferably, an element that is electrically active with respect to the first amorphous semiconductor is included. Further, prior to the deposition of the first amorphous thin film, the surface of the insulating film is made to contain an element that is electrically active with respect to the first amorphous thin film. More preferably, the same process is performed for the second amorphous thin film.
[0039]
Further, in a sixth method related to the present invention, an amorphous thin film is deposited on the surface of the insulating film so as to satisfy the deposition rate condition shown in the above formula, and an interatomic distance of 1.02 in the single crystal is satisfied. An amorphous thin film having an average interatomic distance of twice or more is obtained, crystallization energy is imparted, and atoms are aggregated simultaneously with crystallization to form a granular single crystal. Desirably, this surface is kept in a free state so that atoms can move freely in the film, paying attention to changes in chemical potential (gypsum free energy), silicon atoms are moved simultaneously with crystallization, atoms are aggregated, and granular A single crystal is formed.
[0040]
In a seventh method related to the present invention, a source / drain region is formed in a single crystal semiconductor thin film formed on the insulating film by solid phase growth from an opening of the insulating film covering the surface of the substrate to form a MOS type. A semiconductor device is formed. In addition, a plurality of elements are formed in a single crystal semiconductor thin film formed so as to extend to a position far from the opening by solid phase growth from the opening of the insulating film covering the substrate surface. That is, a single crystal semiconductor thin film formed on the insulating film by solid-phase growth from an opening of the insulating film covering the substrate surface, and a plurality of elements that are formed in the single crystal semiconductor thin film and each constitute a semiconductor element In the semiconductor integrated circuit including the regions, the number of the openings may be smaller than the number of the element regions.
[0041]
Furthermore, in the eighth method related to the present invention, when an amorphous semiconductor thin film is deposited on a substrate or an insulating film, the average atomic spacing distribution of the amorphous film composed of the main element constituting the film is particularly large. The single crystal semiconductor thin film is formed so as to substantially coincide with the average atomic spacing distribution of the single crystal, and crystallizing energy is applied to this to perform solid phase growth.
[0042]
That is, according to the present invention, the amorphous semiconductor thin film is kept at the same density before and after the crystallization, so that it is possible to achieve an unprecedented low stress at the time of crystallization and a large crystallization size. To improve the film quality and improve the film quality.
[0043]
It is desirable to use an amorphous film that is approximately the same as the interatomic distance in this single crystal, that is, 0.98 to 1.02 times the interatomic distance in the single crystal, and more preferably 0.995 to 1 times. 0.005 times is desirable, and in order to obtain an amorphous film having such an average interatomic distance, deposition conditions such as deposition rate and film thickness are largely governed. For example, in the case of silicon As a result of various experiments conducted by changing the temperature and gas composition, a film having an average interatomic distance of less than 1.02 can be obtained when the film formation rate R is performed under the condition satisfying the following formula. I understand.
[0044]
logR (A / min) <-10614 / T (K) +14.857
In addition, in order to obtain an amorphous film having an average interatomic distance substantially equal to the interatomic distance in the single crystal, the impurity concentration at the temperature of the heat treatment, the base material of the heat treatment, the film quality of the amorphous film, and the like can be mentioned.
[0045]
That is, (1) depositing at a deposition rate within a specific range at each heat treatment temperature, (2) preparing a film thickness within a specific range at each heat treatment temperature, (3) specific ranges at each heat treatment temperature And a specific range of dopant impurity concentrations, and (4) a specific range of film thickness characterized by the base material at each heat treatment temperature. In addition to thermal energy, the crystallization energy may be energy other than thermal energy, such as electron beam irradiation or ultraviolet light irradiation, or these may be used simultaneously.
[0046]
In addition, the method related to the present invention basically shows an example applied to a semiconductor mainly composed of a covalent bond or a semiconductor amorphous, but can be applied to a metal or the like with some modifications. Is possible.
[0047]
For example, in the ninth method related to the present invention, an amorphous thin film on a substrate is measured to measure the average atomic spacing of the main constituent elements of the thin film, and substantially matches the average atomic spacing in the single crystal of the element. In this way, the deposition conditions are controlled to deposit an amorphous thin film, and by applying crystallization energy to the amorphous thin film, solid phase growth is performed to form a single crystal. For example, a Raman scattering method is used for the measurement of the average atomic spacing.
[0048]
In the tenth method related to the present invention, an amorphous silicon thin film is deposited on a substrate, and then, for example, silicon ions are implanted into the amorphous silicon thin film to substantially match the average atomic spacing in the single crystal. Then, by applying crystallization energy to the amorphous silicon thin film, solid phase growth is performed to form a silicon single crystal.
[0049]
Furthermore, in an eleventh method related to the present invention, the average atomic spacing is selectively changed for each region, and the ion implantation amount is selectively controlled for each region based on the value.
[0050]
In a twelfth method related to the present invention, an amorphous thin film is formed on an uneven surface (insulating film, semiconductor film, conductive film, etc.), and the average atomic spacing of the main constituent elements of the thin film is a single crystal of the element. An amorphous thin film is deposited so as to substantially coincide with the average atomic spacing in, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to form a single crystal. The unevenness is desirably a step having a line and space of 20 to 40 nm.
[0051]
In a thirteenth method related to the present invention, in a semiconductor device in which a MOS semiconductor element and a bipolar semiconductor element are mixed on the same substrate, the bipolar element is formed in an opening of an insulating film covering the MOS semiconductor element. A part of the single crystal semiconductor thin film formed by solid-phase growth from the drain region of the MOS type semiconductor element to be exposed is used as a base region, and the base region is a drain region of the MOS type semiconductor element through the opening. To be electrically connected.
[0052]
By the way, in the process of recrystallization from amorphous to single crystal, if there is a part where crystal nuclei are generated or grown involuntarily, not only the crystallinity is deteriorated but also the recrystallization dimension does not increase. Such inconveniences occur. In order to improve the crystallinity and extend the crystallization distance (range in which a single crystal is formed), it is necessary to recrystallize at as high a speed as possible.
[0053]
As a result of intensive studies and various experiments, the present inventors have found a completely new method focusing on the interatomic distance. This method is intended to control the movement of individual atoms in an amorphous semiconductor during solid phase growth, and since it applies an unprecedented phenomenon, its action is still completely elucidated from an academic perspective. Although it has not been done, it will be described based on the results of intensive research by the inventor.
[0054]
When an amorphous film is deposited at a high speed, if the surface is cleaned and the film thickness is reduced, atoms are bonded temporarily, but a state in which the bonds between atoms are loosened can be created. As a result, this leads to an increase in the size of the average interatomic distance. Then, when energy is applied such as heat treatment while maintaining the increase in the average interatomic distance, the atoms on the surface can move easily. If the amorphous film is in contact with the so-called “seed” single crystal exposed portion, the “seed” crystal is regenerated at a high speed at a stroke until an involuntarily recrystallized portion is generated. It has been found that the recrystallization dimension region can be expanded by crystallizing.
[0055]
On the other hand, if the amorphous film is not in contact with the so-called “seed” exposed portion of the single crystal, a thin film having a certain thickness or less is prepared. It was also found that it can be agglomerated and made into a granular single crystal without defects. At this time, each of the grains becomes a single crystal, but the present inventors have also found that the grains can be arranged in an arbitrary size by selecting the film thickness, temperature, base, and the like.
[0056]
In addition, many controls are possible due to the easy movement of atoms, such as lowering the crystallization heat treatment temperature, shortening the heat treatment time, reducing defects, and controlling crystal orientation.
[0057]
Also, in the conventional solid phase growth method using a thick film, as shown in FIG. 135, crystal growth proceeds at a low temperature, so that free atoms cannot move as in epitaxial growth, and some atoms are latticed. When this mismatch occurs, this mismatch remains as a crystal defect. Therefore, the displacement of the atomic position accompanying silicon growth remains as a strain, and this causes many defects such as twins, or the presence of oxides or other substances also gives rise to strain in the surrounding area. And found out that it was easy to get defects.
[0058]
In the method related to the present invention, in order to proceed with crystallization without causing crystal defects, the atoms in the amorphous film 3 can be moved freely even at a low temperature in order to alleviate the mismatch, strain, and the like. As shown in FIG. 1, the surface of the amorphous film is solid-phase-grown while being kept clean so that the atoms on the surface are left free, and excess atoms that cause strain and the like The point is to escape from the surface or to make up for the deficient atoms from the surface. Therefore, it is important not only to make the surface a free surface, but also to form an amorphous semiconductor film with a film thickness of 80 nm or less, preferably several tens of nm or less, at which this surface state is transmitted to the crystal growth interface. As a result, strain and the like when performing solid phase growth at 600 ° C. or lower are released from the surface, and a single crystal layer having no defect can be formed.
[0059]
For example, according to a third method related to the present invention, a thin amorphous film having a thickness of 80 nm or less is deposited on a semiconductor substrate, and the surface of the amorphous thin film is maintained in a free surface state in a non-oxidizing atmosphere. However, if a single crystal silicon thin film is formed by heating and solidifying by solid phase growth, a good single crystal thin film having no defects can be formed. Further, the lower limit of the film thickness is not particularly limited in consideration of the film formation limit, but it is desirable that it is theoretically several times the lattice radius or more if an ultra-thin film can be formed theoretically.
[0060]
In this way, by performing heat treatment while allowing free movement of atoms, generation of defects due to distortion of atomic positions is suppressed, and a single crystal thin film with good film quality is formed. At this temperature of 600 ° C. or lower, the diffusion of impurities is extremely slow and the impurities in the single crystal cannot move, so that the base substrate is in the amorphous state or the single crystal is advanced from the amorphous film to the base substrate. Impurities do not move.
[0061]
In the conventional method, since the amorphous semiconductor film is exposed to the atmosphere before solid phase growth, a natural oxide film is formed on the surface, and the atoms on the surface are fixed by bonding with oxygen. Further, even if the substrate is not exposed to the atmosphere, the surface atoms are usually oxidized and fixed in a heat treatment atmosphere for solid phase growth, and solid phase growth is usually performed in a state where the atoms are pressed down.
[0062]
Conventionally, there has not been much discussion about the heat treatment atmosphere during the solid phase growth, and the normal degree of vacuum is 10^-3Heat treatment may be performed in a vacuum up to about Torr or in an inert gas atmosphere.^-3A trace amount of oxygen was contained in a vacuum up to about Torr or in a normal inert gas atmosphere, and a thin natural oxide film was formed.
[0063]
Therefore, the inventors have made the heat treatment atmosphere high vacuum, or in particular, to use an inert atmosphere controlled to a high purity, and by performing the heat treatment by shutting off oxygen from the atmosphere to a nearly close state. We have succeeded in maintaining a free surface and forming a defect-free single crystal film. Further, when the formation of the amorphous thin film and the solid phase growth are performed in different chambers, it is necessary to remove the natural oxide film in a reducing atmosphere prior to the solid phase growth.
[0064]
Note that an impurity having a concentration different from that of the base substrate can be added in advance to the amorphous semiconductor film, whereby a single crystal layer having a different impurity concentration can be formed in a very shallow region of the substrate surface. It is also possible to form a single crystal layer of a different material by changing the material of the amorphous film.
[0065]
Here, the following method is used to control the concentration of the conductive impurities in the amorphous film. In the case of using thermal decomposition of gas, at the time of film formation, a gas containing a conductive impurity is flowed simultaneously with a gas containing a semiconductor material, and the conductive impurity is taken into the film. If an impurity exists in the base substrate, an intrinsic layer is formed on the p-type or n-type substrate by limiting the thickness to several tens of nm near the surface by forming an amorphous film that does not contain the impurity. Therefore, the semiconductor device has high utility value for miniaturization. As another method, the UHV method, which is a method of evaporating a target of a semiconductor material and depositing it on a substrate surface maintained in a high vacuum, is also effective. As a method of evaporating, there are a method of heating with a heater, a method of heating by applying an energy beam such as an electron beam, a sputtering method of accelerating ions such as argon ions and knocking out target atoms. Regardless of which method is used, an amorphous film having a different impurity concentration from that of the base substrate can be formed by simultaneously depositing conductive impurities other than the semiconductor material as a target. Alternatively, it goes without saying that a semiconductor material containing conductive impurities may be targeted.
[0066]
Preferably in this method, this heat treatment is performed at a degree of vacuum of 10^-4If it is carried out under a high vacuum of Torr or less, the oxygen concentration becomes extremely small, the formation of the surface oxide film can be suppressed, and a single crystal with good film quality can be formed.
[0067]
Desirably, if this heat treatment is performed in an inert gas atmosphere such as high-purity argon, nitrogen, or helium, the oxygen concentration becomes extremely small, and the formation of a surface oxide film can be suppressed, and the film quality is good. A single crystal thin film can be formed. Further, in this method, desirably, the heat treatment temperature is set to 450 ° C. to 600 ° C., so that almost no impurity can be diffused and the interface characteristics can be improved.
[0068]
Furthermore, in this method, it is desirable to form a single crystal thin film very easily if the amorphous thin film deposition step and the heat treatment step are performed continuously without breaking the vacuum in the same chamber. Become.
[0069]
In a fourth method related to the present invention, the distance from the surface to the interface with the semiconductor substrate on the semiconductor substrate is such that the thickness is so thin that free atoms on the surface can reach the interface. A crystalline thin film is deposited, and the amorphous thin film surface is heated in a non-oxidizing atmosphere while maintaining a free surface state to the extent that free atoms on the surface can freely reach the interface. Since a single crystal is formed to form a single crystal, atoms on the surface can move freely, and a good single crystal thin film free from distortion can be formed.
[0070]
In a fifth method related to the present invention, an opening of an insulating film formed on the surface of the semiconductor substrate is formed to expose the substrate surface, and a first amorphous film having a thickness of 20 nm or less is formed on the substrate surface. A thin film is deposited, heated while maintaining the surface of the amorphous thin film in a free surface state in a non-oxidizing atmosphere, and the substrate is converted into a single crystal by solid phase growth to form a first single crystal thin film. As a result, atoms can freely move to obtain a film with good crystallinity, and then a second amorphous thin film having a thickness of 80 nm or less is deposited on the single crystal semiconductor thin film. The amorphous thin film surface is heated while being maintained in a free surface state in a non-oxidizing atmosphere, and the substrate is single-crystallized as a crystal seed by solid phase growth to form a second single-crystal thin film. Again, atoms move freely to obtain a film with good crystallinity Bets can be, a semiconductor layer of the blanket shape can be favorably formed at a low temperature.
[0071]
Desirably in this method, the step of heating the first amorphous semiconductor thin film comprises 10 steps.^-6If it is performed under a high vacuum of less than Torr, the surface atoms are more easily migrated and single crystallization is promoted, and a wide range of single crystallization is performed from the surface of the opening serving as a seed far away. Is possible.
[0072]
Further, by adding an electrically active element to the first amorphous semiconductor, the single crystallization rate is increased.
[0073]
Furthermore, prior to the deposition of the first amorphous semiconductor thin film, the single crystallization speed can be increased by incorporating an electrically active element with respect to the first amorphous semiconductor in the insulating film surface. .
[0074]
In a sixth method related to the present invention, an amorphous thin film is deposited on the surface of the insulating film, and an amorphous thin film having an average interatomic distance that is 1.02 times or more the interatomic distance in a single crystal is obtained. At the same time as this crystallization, atoms are aggregated to form a granular single crystal, so that single crystals with extremely good crystallinity and uniform grain size can be easily formed without depending on the accuracy of lithography. The
[0075]
In a seventh method related to the present invention, a single crystal thin film having good crystallinity is electrically connected to the substrate through the opening, and a current caused by impact ionization generated in the vicinity of the drain is caused to flow to the substrate. Thus, a MOS transistor with stable element operation can be obtained. In addition, since the channel region can be an ultra-thin film with good crystallinity, high-speed operation is possible. Further, since a layer containing almost no impurities (i layer) can be formed in the channel region, a high-mobility transistor in which carrier travel is not hindered by impurities can be obtained. Furthermore, since a single crystal thin film with good crystallinity can be extended far from one opening (seed), solid phase growth from the opening of the insulating film covering the substrate surface leads to a position far from the opening. If a single crystal semiconductor thin film is extended to form a plurality of elements, a thin film with good crystallinity can be formed without being restricted by other element regions. Here, when the single crystal thin film is formed, the first, second, eighth, ninth, etc. methods related to the present invention are used.
[0076]
Furthermore, as a result of the study, the inventors have found that the growth edge does not extend far in the conventional method and that a stochastic distribution is seen in the growth distance. It was discovered that this was caused by the fact that the (interface) did not move at a constant speed and was wavy.
[0077]
As for the cause of poor crystallinity, it was found that twins and the like rapidly increased when the film was extended by about 1 μm or more. In particular, in the current process, the region having relatively good crystallinity is about 1 μm, and it has been found that the size is insufficient to produce an active device.
[0078]
Therefore, the present inventors have intensively studied and conducted various experiments, and as a result, found a completely new method focusing on the interatomic distance. That is, this cause was investigated using a high-resolution transmission electron microscope and microscopic Raman spectroscopy, and a method capable of reliably obtaining a single crystal having good crystallinity was found. In addition, the present inventors have found a method for providing completely oriented single crystal grains as a new application.
[0079]
Specifically, the growth distance time dependence of lateral solid phase growth was investigated using a small electric furnace, the growth edge was evaluated in detail using a transmission electron microscope, and the inside of the film was examined using a microscopic Raman method. The stress distribution was measured. As a result, the present inventors have grasped that there is a very important relationship between the growth distance and the preferential growth surface, crystal defects, and residual stress. We found a measure to improve the crystallinity, and also formed fully oriented single crystal grains and confirmed it experimentally.
[0080]
In particular, in order to reduce stress during crystallization, in order to make the interatomic distance approximately equal to that of a single crystal, the atomic density at each heat treatment temperature largely dominates.
Impurity concentration at each heat treatment temperature
Surface condition at each heat treatment temperature
Material and structure of the underlying film at each heat treatment temperature
Etc.
[0081]
That is, in the process of crystallization from amorphous to single crystal, if the average interatomic distance between the amorphous and single crystal is different, stress is generated along with the crystallization, and such stress is further generated on the surface of the crystallization interface. In order to prevent such inconveniences, such as changing the orientation, inducing crystal defects, and also causing inconveniences such as not extending the single crystallization dimension, the average atomic spacing of the amorphous film is set to By making the average atomic spacing approximately the same (0.98 times or more, preferably 1.01 or less, preferably 1.01 or less), the stress during crystallization is suppressed and the crystallinity is improved and the single crystallization distance is reduced. Enables extension. It was also found that self-single crystals can be grown from the surface, thereby obtaining complete single crystal grains.
[0082]
The effect of this method is based on an unprecedented phenomenon and has not yet been fully elucidated academically.
[0083]
According to the eighth method related to the present invention, a single crystal having good crystallinity without crystal defects such as twins can be extended far.
[0084]
In a ninth method related to the present invention, an amorphous thin film is measured on a substrate using a Raman scattering method or the like while measuring the average atomic spacing of the main constituent elements of the thin film. Since the amorphous thin film is deposited by controlling the deposition conditions so that it is almost the same as the average atomic spacing, the density change during crystallization is small, so the generation of stress is suppressed and a good single crystal is obtained. Can do.
[0085]
In the tenth method related to the present invention, the implantation value is determined by a method such as measuring the average atomic spacing of silicon in the deposited amorphous silicon thin film, and based on this value, By implanting silicon ions so as to be close to the average atomic spacing to substantially match the average atomic spacing in the single crystal, the amorphous silicon thin film is subjected to heat treatment or the like, so that the density change is small during crystallization as in the second case. Therefore, generation of stress can be suppressed and a good single crystal can be obtained.
[0086]
By the way, since recrystallization occurs from a place close to the seed, the distance between atoms increases in the distance. Therefore, paying attention to this point, in the eleventh method related to the present invention, prior to recrystallization, ions are selectively implanted into a predetermined region. That is, the average atomic spacing of silicon in the deposited amorphous silicon thin film is measured for each region, and based on this value, the amount of silicon ions calculated for each region is ion-implanted so that a predetermined average atomic spacing is obtained. By applying heat treatment to the amorphous silicon thin film so that the average atomic spacing in the single crystal is almost the same, the density change during crystallization is small, so that the generation of stress can be suppressed and a good single crystal can be obtained. it can.
[0087]
Furthermore, in a twelfth method related to the present invention, an amorphous thin film is formed on a substrate having an uneven surface (insulating film, semiconductor film, conductive film), and the average atomic spacing of the main constituent elements of the thin film is Since the amorphous thin film is deposited so as to substantially coincide with the average atomic spacing in the single crystal, and the single crystal is formed by solid phase growth by applying crystallization energy to the amorphous thin film. Generation of strain is suppressed, and a single crystal with good crystallinity and good orientation is formed. Here, the unevenness is desirably about 20 to 40 nm.
[0088]
In a thirteenth method related to the present invention, a bipolar element is formed on a single crystal semiconductor thin film formed by solid phase growth from a drain region of a MOS semiconductor element exposed in an opening of an insulating film covering the MOS semiconductor element. Since a part of the base region is formed so as to be electrically connected to the drain region of the MOS type semiconductor element through the opening, the crystallinity of the connection portion is extremely good. In addition, the contact resistance is small, and even though it has a laminated structure, it can be formed at a low temperature, and the underlying element is not deteriorated. Further, since the current value can be amplified by the bipolar element, the current value of the lower MOS type semiconductor element can be amplified and the output can be increased to enable high-speed operation.
[0089]
The first to fourteenth aspects of the present invention can be obtained by using the method related to the present invention as described above.
[0090]
In the first to fifth aspects of the present invention, since the lower electrode of the capacitor is formed of a granular conductive layer, the capacitor area can be increased by the unevenness of the surface.
[0091]
In the sixth aspect of the present invention, it is necessary to conduct the granular second conductive layer to the first conductive layer, but it has been found that the heat treatment causes the insulating film to contract and conduct. The present invention has been made based on this result, and a capacitor having a large capacity can be formed very easily. This granular second conductive layer can also be easily obtained by using the first, second, eighth, ninth, etc. methods of the invention related to the present invention.
[0092]
In the seventh aspect of the present invention, granular semiconductors or insulators are separately formed on a substrate or a thin film formed on the substrate so that the intergranular distance is smaller than the grain size, and this is used as an element region. Thus, a semiconductor device with favorable characteristics and high reliability can be obtained.
[0093]
In the eighth aspect of the present invention, granular semiconductors or insulators are separately formed on a substrate or a thin film formed on the substrate so that the intergranular distance is smaller than the grain size, and this is used as an element region. Thus, a semiconductor device with favorable characteristics and high reliability can be obtained. In forming the grains, the first, second, eighth, ninth, etc. methods are used.
[0094]
In the ninth aspect of the present invention, the single crystal silicon is configured such that the vertical axis with respect to the underlying substrate or thin film surface is oriented in the <100> direction. There will be no reliability.
[0095]
In the tenth semiconductor device of the present invention, the granular single crystal silicon has a particle size distribution in which 90% or more of grains are contained within ± 20% of the particle diameter centering around the most frequently occurring particle diameter. Therefore, even when a fine element is formed, the characteristics do not vary and the reliability is high.
[0096]
In the eleventh aspect of the present invention, a very good pn junction is formed by the first conductive type semiconductor region formed on the substrate surface and the second conductive type granular single crystal silicon formed thereon. Therefore, it is possible to obtain a diode with extremely good characteristics and small variations.
[0097]
In the twelfth aspect of the present invention, as a result of various experiments, it is easy to form a granular second conductive layer on a conductive layer having an insulating film on the surface. Although it is necessary to conduct the two conductive layers to the first semiconductor region (conductive layer), it has been found that the insulating film contracts and conducts by performing heat treatment. In view of this point, an amorphous silicon thin film is deposited on a substrate including a semiconductor region of the first conductivity type via an insulating film having a predetermined thickness, and the second conductivity type is obtained. Next, the amorphous silicon thin film is subjected to a heat treatment to form solid phase growth to form a second conductive type granular single crystal silicon, and the first conductive type semiconductor region and the Since the insulating film between the granular single crystal silicon is contracted and disappeared by heat treatment, and is contacted to form a pn junction to form a diode, the diode is fine and has very good characteristics and small variation Can be obtained. This granular single crystal silicon can also be easily obtained by using the first, second, eighth, ninth, etc. methods of the invention related to the present invention.
[0098]
In a thirteenth aspect of the present invention, a source / drain is formed in a polycrystalline silicon film formed on an insulating film covering the substrate surface and having a substantially uniform grain size and a grain boundary along a vertical axis with respect to the surface of the underlying substrate. Since the thin film transistor is formed by forming the region, the number of grain boundaries in the channel can be made uniform, and stable operation characteristics can be obtained with small variations in characteristics.
[0099]
In the fourteenth aspect of the present invention, an amorphous thin film is deposited on an insulating film covering the substrate, and the amorphous thin film is subjected to heat treatment to perform solid phase growth so that the grain boundary is perpendicular to the underlying substrate surface. Since the polycrystalline silicon film formed along the axis is formed, and the thin film transistor is formed in the polycrystalline silicon film, it is possible to easily obtain stable operation characteristics with little variation in characteristics. If an amorphous film is deposited on the surface of the insulating film having unevenness, atoms can move more freely and the crystal orientation can be easily aligned.
[0100]
The main point proposed by the present inventors is as described above, but the reason why the semiconductor thin film prepared according to the pointed out provides a high-quality film far exceeding the conventional film quality as described above is still unexplained. At present, sufficient analysis has not progressed.
[0101]
However, the present inventors have intensively studied and in accordance with computational physics, have reached an area where a new and strict computer simulator that has never existed before can be guessed. In the following, the present inventors will explain a newly created simulator and explain the folding by the simulator.
[0102]
The most important thing in this simulator system is the calculation of the force acting between Si atoms, and further the calculation of the potential of the atoms. The present inventor has thoroughly investigated in advance what potential is most suitable for the Si semiconductor. As a result, it was considered that the Tersoff potential should basically be used for the problem targeted by the present inventors, that is, the recrystallization phenomenon and the system containing amorphous. The inventors have made a unique improvement to Tersoff's potential, and added a strict deformation derivation that has never been done mathematically. If the magnitude of the potential is known, the force applied to the particle, the speed, etc. can be easily obtained therefrom.
[0103]
According to the inventor, according to the independently improved Tersoff, the total potential for the i-th Si is
Σ (1/2) (V_ij+ V_ji(1)
It can be described by. Since the potential of the improved Tersoff by the present inventor considers the force between three or more particles, V in the above equation (1)_ij≠ V_jiIt is. If the position number of the Si particle of interest is i and the other particle numbers around it are j, V_ijIs
V_ij= F_c(r_ij) {a_ijf_R(r_ij) + B_ijf_A(r_ij)}… (2)
It is. Here, r is the distance between the particles. F_c(r_ij) Is called the cut-off function and f_R(r_ij) Indicates repulsive force and f_A(r_ij) Indicates attractive force. a_ijIs the cut-off coefficient considering the coordination number, b_ijIs also a cut-off coefficient considering the coordination number. In the improved Tersoff by the present inventor, by giving a special parameter to the coordination number, the effect of the force of three or more bodies is incorporated in the shade. f_RAnd f_AIs a modified version of the Morse potential,
f_R(r) = Aexp (−λ₁r), f_A(r) = − Bexp (−λ₂r)
It is.
[0104]
Of these, λ₁And λ₂Is a constant whose magnitude is the reciprocal of the value of the distance between atoms.
[0105]
Substituting these
V_ij= F_c(r_ij) {a_ijAexp (−λ₁r) -b_ijBexp (−λ₂r)}
It becomes.
[0106]
By the way, the cutoff function f_c(r_ij)
f_c(r) = 1 (r ≦ RD)
f_c(r) = 1 / 2−1 / 2sin {(π / 2) (r−R) / D} (R−D <r <+ D)
f_c(r) = 0 (r ≧ R + D) (3)
Where R is dimensioned to include only the first adjacent zone of the structure of normal interest. Its value is approximately 2-3 angstroms.
[0107]
Next, the effective coordination number b_ijHowever, the cutoff function is also used here. The definition is according to the improved Tersoff by the inventor,
b_ij= (1 + βⁿζ_ij ⁿ)^{-1 / 2n}    ... (4)
here
ζ_ij= Σf_C(r_ik) g (θ_ijk) exp {λ₃ ³(r_ij-R_ik)³} (5)
It is. The symbol Σ is turned by k ≠ i, j. As you can see here, ζ_ijThe meaning of is an environmental factor due to the entry of the third atom k, and therefore the size is different from that of the i atom and the k atom. That is, ζ_ij≠ ζ_jiIt is.
[0108]
Therefore, b_ij≠ b_jiFurthermore, as described in the above equation (1), V_ij≠ V_jiIt is.
[0109]
G (θ) is a bond angle factor,
g (θ) = 1 + (c²/ D²-C²/ (D²+ Cosθ²(6)
It is. Here, θ is assumed as shown in FIG. In obtaining θ, it is expressed using actual orthogonal coordinates.
[0110]
That is
r_ij= [{(X_j-X_i)²+ (Y_j-Y_i)²+ (Z_j-Z_i)²}]^1/2    ... (7)
And r_ikIs required in the same procedure.
[0111]
Then the inner product is P_ijkThen,
P_ijk= (X_j-X_i) (x_k-X_i) + (Y_j-Y_i) (y_k-Y_i) + (Z_j-Z_i) (z_k-Z_i(8)
It is.
[0112]
With these
cosθ_ijk= P_ijk/ (R_ijr_ik(9)
It becomes.
[0113]
Here, the constants in the above equations are shown. That is,
R = 3.0Å, D = 0.2Å, A = 3264.7 eV, B = 95.373 eV, C = 4.8811,
λ₁= 3.2394Å, λ₂= 1.3258Å, λ₃= Λ₂(10)
β = 0.33675, n = 22.956, d = 2.0417
It is.
[0114]
After making the above preparations, the present inventor has proceeded with rigorous and unprecedented calculation for the calculation of the force acting between Si atoms and the calculation of the speed of movement. Differentiating the potential formula (2) with respect to the coordinates of the position yields a force. That is
-(1/2) (∂V_ij/ ∂x_i(11)
-(1/2) (∂V_ij/ ∂x_j(12)
Are the x components of force vectors acting on the particles i and j, respectively. In actuality, however, the present inventor carefully packed the contribution of each variable and created a strict high-order partial differential expression.
[0115]
In calculating the angular component and the radial component, the order was arranged as shown in FIG.
[0116]
The values of the equations described in the equations (11) and (12) were obtained by using the partial differential equation formula and the responsive relationship diagram of FIG. That is,
-(1/2) (∂V_ij/ ∂x_i) = (1/2) [(∂V_ij/ ∂r_ij) (∂r_ij/ ∂x_i) + (∂V_ij/ ∂ζ_ij) {(∂ζ_ij/ ∂r_ij) (∂r_ij/ ∂x_i) + Σ (∂ζ_ij/ ∂r_ik) (∂r_ik/ ∂x_i) + Σ (∂ζ_ij/ ∂cos_ijk) (∂cosθ_ijk/ ∂x_i)}]… (13)
Similarly, the modification of the partial differential equation with respect to j is as follows. In particular, the blank part was left blank so that the correspondence with the above could be understood.
[0117]
-(1/2) (∂V_ij/ ∂x_j) = (1/2) [(∂V_ij/ ∂r_ij) (∂r_ij/ ∂x_j) + (∂V_ij/ ∂ζ_ij) {(∂ζ_ij/ ∂r_ij) (∂r_ij/ ∂x_j) + Σ (∂ζ_ij/ ∂cos_ijk) (∂cosθ_ijk/ ∂x_j)}]… (14)
Similarly, the modification of the partial differential equation with respect to k is as follows. The blank portion was left blank so that the correspondence with the above equation (13) was understood.
[0118]
-(1/2) (∂V_ij/ ∂x_k) = (1/2) [(∂V_ij/ ∂ζ_ij) {(∂ζ_ij/ ∂r_ik) (∂r_ik/ ∂x_k) + (∂ζ_ij/ ∂cosθ_ijk) (∂cosθ_ijk/ ∂x_k)}]… (15)
And disassemble.
[0119]
And V_ijAs for the partial differential equation using Equation (2),

It becomes.
[0120]
By the way, ∂f_c(r_ij) / ∂r_ijIs
∂f_c(r_ij) / ∂r_ij= (− Π / 4D) cos {(π / 2) (r−R) / D}
(R−D <r <R + D)
∂f_c(r_ij) / ∂r_ij= 0 (other cases) (17)
Also,

Since the above is the calculation for the x direction, it is necessary to prepare the y direction and the z direction in addition to these. In that case, what is necessary is just to change x in each final deformation type to y or z.
[0121]
Furthermore, the present inventor advanced the calculation. Constant product calculation is to keep the entire volume of the system constant even when there is atomic motion. The method described so far is a constant product calculation and does not pay much attention to volume change. However, for example, recrystallization solid phase growth is generally accompanied by a volume change. In this case, in general, it is necessary to return to the Lagrangian considering the internal energy composed of kinetic energy, further potential energy, entropy, volume, and the like, and to establish the equation of motion for the Lagrangian. Lagrangian can be described as:
[0122]
That is,
L (r_i, ∂_t, V, ∂V / ∂t) = (1/2) Σm (∂r_i/ ∂t)²+ {(1/2) M (∂V / ∂t)²} -P_EV
It is.
[0123]
Here, PE is an external pressure, and in the case of constant pressure calculation, the volume V varies so that the internal pressure becomes equal to this. M is a virtual mass. Based on this, the equation of motion for Lagrangian is established.
[0124]
That is
(∂L (qj, q′j) / ∂qj) −d (∂L / ∂q′j) / dt) = 0
It is.
[0125]
Calculations can be advanced based on this formula. The present inventor has proceeded with strict work on this part as well.
[0126]
As described above, this system strictly examines the motion of individual Si atoms. Therefore, the basic output is the position, velocity, force, etc. of each particle at each time, but more macroscopic quantities can be calculated. That is, as an example, the thermal conductivity can be obtained. The inventor studied the accuracy and basic operation by calculating the thermal conductivity. In addition, this system was devised so that a single crystal can be handled as a finite temperature. In the conventional calculation method, there was one in which the single crystal was set to absolute zero, but this caused the heat flux to be infinite, and accurate calculation of conductivity could not be performed. This time, the present inventor has made it possible to add a “heat bath” to both ends of the crystal and manage the exchange of energy. As a result of the calculation, a value of 180 Watt / meter / Kelvin is obtained as shown in FIG. Since this is 148 to 150 Watt / meter / Kelvin according to general literature, it is a satisfactory value within an error range of about 20%.
[0127]
First, using this simulator, we examined the movement of each particle of the amorphous thin film on the oxide film. For example, FIG. 139 shows the motion of each grain at the growth edge during crystal growth at 600 ° C. It can be seen that the atomic density in the amorphous thin film is low near the growth edge.
[0128]
The results of analysis using the simulator are described below.
[0129]
First, using this simulator, we examined the motion of each particle of the amorphous thin film on the oxide film. The results are shown in Table 1.
[0130]

In particular, in the calculation, first, an arithmetic average dimension was obtained from the distribution of Si atom deflection, and the square root of the square sum of the deviation from this value was expressed by ∂x. The average in the depth direction of the value of ∂x corresponds to the average interatomic distance described above. Table 1 is calculated for particles from the surface layer immediately before recrystallization of the amorphous thin film to a depth of about 1 angstrom. As can be seen from Table 1, for example, at 600 ° C., ∂x is 0.3135 angstrom, and on the other hand, the value of ∂x immediately before recrystallization in a state where an oxide film is deposited on an amorphous thin film. Is the lower value. That is, it is 0.1792 angstrom at 600 ° C. Again, this is calculated for particles from the surface layer to a depth of approximately 1 angstrom.
[0131]
As can be seen from the comparison of the above two values, it can be clearly seen that when the oxide film is clearly deposited on the surface, the fluctuation dimension of the atoms is reduced. When the influence range of the variation of ∂x was obtained, it was found that if it was about 600 ° C., it remained up to about 200 angstroms.
[0132]
As shown in Table 1 at 525 ° C., when the surface oxide film is not deposited, ∂x = 0.3011 angstrom, and when the surface oxide film is deposited, x = 0.1700 angstroms. Further, at 400 ° C., as shown in Table 1, when the surface oxide film is not deposited, ∂x = 0.2782 angstroms, and when the surface oxide film is deposited, ∂x = 0. 1542 angstroms.
[0133]
The analysis created according to the pointed out by the simulation results can be interpreted as follows. That is, when the semiconductor thin film becomes thin as described above, the average interatomic distance increases, and the atoms become very easy to move. Therefore, in such a state, not only recrystallization from the “seed” part is performed at a very high speed but also a very high quality crystal is obtained. FIGS. 6A and 6B show calculated values and effective values of the film thickness and average atomic spacing according to the present invention. The horizontal axis in FIG. 6 indicates the depth direction of the film thickness, and the vertical axis indicates the average atomic distance. It can be seen that the average interatomic distance increases as the film thickness decreases.
[0134]
Further, it was confirmed that in the case where there was no “seed” portion, the amorphous film was sequentially solidified to become granular. At this time, according to the calculation by the present inventors, when the amorphous film starts to solidify once and begins to become granular, the internal energy outlet disappears, and accordingly, the temperature rises slightly and recrystallization occurs. It has been found that the process is further promoted.
[0135]
As predicted by the prototype simulator, as the film thickness decreases before recrystallization, the bonding state of the amorphous film surface and in the film becomes “relaxed”, and only the underlying interface gives the structural information.
[0136]
Moreover, the present inventors also solved why it became granular like this using the simulator. As a result, it was confirmed that it was due to the force to reduce the internal energy.
[0137]
From the above, the results of the study by the present inventor have found that there is no relation between the film quality of the obtained single crystal film and the partial pressure of oxygen in the film forming gas, which is another phenomenon. According to the method proposed by the present inventors, a very good single crystal is obtained, and twins and the like are not recognized at all.
[0138]
Further, in the case where there is no “seed” portion, according to the calculation by the present inventors, crystallization starts from the surface side, crystallization proceeds downward, and there is a low atom at the tip of the crystal growth end. It has been found that a density region occurs. At the same time, using a simulator, we found that tensile strain occurred in the low atomic density region.
[0139]
Furthermore, when the amorphous thin film is heated to a temperature of about 600 ° C., recrystallization starts. At this time, a region having a low atomic density is formed in the amorphous region near the growth edge. When an amorphous film is originally formed by a CVD method or the like under general film formation conditions, the density is lower than that of a single crystal and the average atomic spacing is increased. This is because, when recrystallization is performed, it is necessary to increase the density as compared with the original state, so that atoms on the amorphous film side are attracted more to the crystal side. The lower the density at the crystallization edge, the more the crystallization progresses. However, if an amorphous material having an average atomic interval substantially equal to that of a single crystal is prepared in advance, the low density region does not appear. Therefore, the crystallization distance is extended far.
[0140]
In order to prove this, the following experiment was conducted. First, as shown in FIG. 140, an insulating film is formed on a (100) silicon substrate, a part of the insulating film is opened, and a sample using the silicon substrate as a seed is used.₄An amorphous silicon film having a thickness of 200 nm was deposited at a partial pressure of 1 Torr, and a heat treatment at 600 ° C. was performed to measure the growth in the [100] direction.
[0141]
The result of measuring this with an optical microscope is shown in FIG. 141 (a). This figure is a typical optical micrograph of the sample taken from directly above. The white region is a region where crystallization has already progressed to become a single crystal. It has been found that the seed extends uniformly from the “seed” up to 1 μm with good reproducibility, but it has been found that the growth edge becomes wavy after further heat treatment. FIG. 141 (b) shows the time dependence of a typical growth distance obtained from the movement of the growth edge during the solid-phase growth in the horizontal direction by repeating the procedure of taking a photograph after heat treatment at 600 ° C. for 5 minutes several times. Indicates. The straight line in the figure does not pass through the origin, but at the beginning of growth it grows directly from the “seed” and then begins to spread sideways, so it seems that it is delayed to begin to grow sideways only for the time it is growing up. It is done. When the growth rate is obtained from the slope of each straight line drawn in the figure, there is some variation in a and b, but the growth rate is 1.5 nm to 2.0 μm, and the growth rate is 100 nm / min. The growth rate is slowed down. Once the growth has started to lag, the growth rate does not recover and the growth edge becomes wavy. Finally, growth stops when it hits a crystal generated from a place other than the “seed”.
[0142]
Next, the growth edge (interface between amorphous silicon and crystal) during the growth was analyzed in detail by transmission electron microscope observation (TEM) of the cross section. FIGS. 142, 143, 144, and 145 show cross-sectional photographs of growth edges that have been grown to 0.5 μm and those that have been grown to 2 μm as typical examples. As a result, it has been found that these are the (110) silicon face preferred growth mode and the (111) silicon face preferred growth mode, respectively.
[0143]
This is shown schematically in FIG. In other words, it has been found that the preferential growth surface changes as it grows laterally in the [100] direction.
[0144]
Furthermore, the inventors measured the stress in the film using a micro Raman method. As a result, as shown in FIG. 147, almost no stress is observed in the “seed”, and 3 × 10 3 away from the “seed” by about 1 μm.⁹dyn / cm²I found out that
[0145]
From these facts, the change of the preferential growth surface from the (110) silicon surface to the (111) silicon surface was considered as follows.
[0146]
First, the shear yield stress of silicon is 2 to 3 × 10 at the temperature at which this crystallization is proceeding.⁹dyn / cm²I think that the. This value appears to occur at a position that grows laterally by 0.5 μm or more from the “seed”. It was thought that this stress caused a shift of the (111) silicon surface and changed to a preferential growth of the (111) silicon surface. In particular, with this idea, as the growth progresses, (111) twinning continues to occur, so that the stress becomes a constant value after 1 μm and the crystallinity should not recover. In fact, when observed with a cross-sectional TEM, twins are visible as shown in FIG. Although there is some error in the dimensional position, the point at which the growth rate changes corresponds to the generation position of the (111) plane priority growth mode.
[0147]
In this way, the stress in the film was found to be extremely disadvantageous for crystal growth, and various causes of stress generation were studied in order to reduce this stress. As a result, the stress does not appear in the “seed” part and increases with growth. Therefore, I noticed that the volume change when the film crystallizes was one of the causes, and paid attention to this.
[0148]
The fact that the volume changes as the film grows is considered to be due to the fact that the bond distance between atoms changes between a single crystal state and an amorphous state even if they are composed of the same element. Therefore, it was considered that stress should not occur even in the amorphous state if the same average atomic spacing as in the single crystal state was used.
[0149]
From this prediction, when an amorphous thin film having an atomic spacing substantially matching the average atomic spacing of a single crystal was formed and lateral solid phase growth was performed, the (110) plane preferred growth was 10 μm or more as predicted. Then, a single crystal thin film having no crystal defects such as twins and good crystallinity could be obtained.
[0150]
Thus, when the amorphous film is in contact with the so-called “seed” single crystal exposed part, the “seed” crystal is recrystallized at a high speed at a stretch, and the part that is involuntarily recrystallized. By the time it occurs, the recrystallization dimension area can be expanded.
[0151]
On the other hand, when the amorphous film is not bonded to the so-called “seed” single crystal exposed portion, when a thin film having a certain thickness or less is prepared, the amorphous portion is individually , Agglomerates during crystal growth and becomes a single crystal without granular defects.
[0152]
The present invention provides a completely new method focusing on interatomic distances. The effects of this method are not yet fully elucidated academically because they apply an unprecedented phenomenon, but can be explained as described above at this stage.
[0153]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, when an amorphous semiconductor thin film is deposited on a substrate or an insulating film, the average atomic spacing distribution of the amorphous film composed of the main elements constituting the film is particularly changed to the average atomic spacing distribution of the single crystal. A single crystal semiconductor thin film is formed by applying a recrystallization energy thereto and performing solid phase growth.
[0154]
Hereinafter, embodiments will be described in detail with reference to the drawings.
[0155]
First, in obtaining the Si single crystal thin film in the first reference example, an amorphous Si film having an average atomic interval of 1.02 times or more of the average atomic interval of the Si single crystal is used in advance. N, which is a non-oxidizing atmosphere, is used to suppress the growth and adhesion of the oxide film to the surface of the porous film and relax the atomic spacing until just before the solid phase growth.₂The atmosphere was heat treated.
[0156]
FIG. 2 is a diagram showing an outline of a thin film forming apparatus according to a first reference example of the present invention. This apparatus includes a chamber 101, a source gas introduction port 102 for film deposition, an exhaust port 103, and a sample stage 104 on which a sample on which a thin film is to be formed is placed. In this reference example, for example, hydrogen H as the source gas₂And SiH₄Or disilane etc. are introduce | transduced and doping gas can also be introduce | transduced as needed. In the figure, for the sake of simplification, there is only one introduction port, but this may also be introduced separately to the vicinity of the sample stage as necessary. The sample stage 104 has a heating mechanism so that the temperature can be raised or lowered as appropriate. Further, here, an evaluation device (special REEHD device) for determining crystallinity is provided, and includes a beam irradiation means 105 for irradiating the sample surface with a beam and a light receiving tube 106 for receiving reflected electrons from the sample surface. The “average atomic spacing” can be monitored with high accuracy. The beam irradiation means and the light receiving tube can be incident on and reflected from the sample surface at a very small angle, and the angle can be appropriately changed. Further above, a special Raman spectroscope 107, which is one of crystallinity evaluation apparatuses, is provided. A method for forming a thin film using this apparatus will be described. FIGS. 3A and 3B are diagrams showing an outline of a film deposition sequence according to the first reference example of the present invention. In FIG. 3, the horizontal axis represents time, and the vertical axis represents temperature. 4A to 4C are views showing a thin film forming process. Here, the temperature on the vertical axis was measured with a thermocouple attached to the sample stage 104 in FIG. Of course, the thermocouple is a well-calibrated one.
[0157]
First, as shown in FIG. 4A, a silicon oxide film 202 was previously deposited on the surface of a p-type single crystal (100) silicon substrate 201, and an opening 203 was formed by photolithography. Prior to the deposition of the thin film, the substrate and the like were cleaned at a predetermined temperature and gas composition before the point T1 in FIGS. 3 (a) and 3 (b).
[0158]
Subsequently, as shown in FIG. 4B, an amorphous silicon film 204 having a film thickness of 315 angstroms is deposited. In FIG. 3, the area between the points T1 and T2 corresponds to a so-called film forming process.
[0159]
After this, nitrogen N₂Heat treatment for recrystallization is performed in an atmosphere. This corresponds to time points T3 to T4 in FIG. 3, and the temperature was, for example, 600.degree. After that, the temperature is lowered and taken out after time T5. In this way, a single crystal silicon film 205 is obtained as shown in FIG. Here, as a result of performing film formation from point 1 to point T2 while changing the temperature and gas composition, when the film formation rate R is performed under the condition satisfying the following formula, the average interatomic distance is 1.02. The above film was obtained.
[0160]
logR (Å / min) ≧ −10614 / τ (K) +14.857
The region indicated by this condition is shown in FIG. In regions other than these conditions, a film having an average atomic spacing exceeding 1.02 could not be formed.
[0161]
In this reference example, the average atomic spacing is maintained to be 1.02 times or more that of the silicon single crystal, so that an oxide film does not adhere to the surface of the amorphous silicon film 204 in the chamber 101 shown in FIG. It was kept in an evacuated state. And it recrystallized as it is at 600 degreeC corresponded to the time shown to T4 of FIG.
[0162]
FIG. 3B shows, for example, an outline of the transition of the film quality used here. The film quality was evaluated using, for example, special RHEED apparatuses 105 and 106 and a special Raman spectrometer 107 shown in FIG. The measurement results are shown in FIG. The horizontal axis shows the passage of time, and the vertical axis shows the average atomic spacing. At T2, that is, at the end of film formation, the average atomic spacing of the amorphous silicon film 204 on the silicon oxide film 202 was 1.02 times that of the silicon single crystal. Time T5 corresponds to after recrystallization, and the average atomic spacing is 1.00 compared to the silicon single crystal.
[0163]
Thereafter, the film quality in the chamber of FIG. 2 was evaluated. The evaluation results are shown in FIG. FIG. 6A shows the measurement principle. As is clear from FIG. 6B, it can be seen that the average interatomic distance is 1.02 or more from the surface to about 80 nm, and becomes extremely small as the depth further increases. Moreover, the measurement result of a horizontal direction solid-phase growth rate is shown in FIG. The horizontal axis shows the recrystallization time. In other words, this corresponds to the time T3 to T4 in FIG. The vertical axis represents the lateral recrystallization distance. The longer the distance in the lateral direction, the more suitable for use as an SOI device. In addition, it is advantageous that the recrystallization region has as few crystal defects as possible for application to SOI devices. A curve a in FIG. 7 corresponds to the reference example shown above. Curves b, c, and d in FIG. 7 are based on a conventional method prepared for comparison, and each deposits an amorphous film having a thickness of 200 nm, and no particular attention is paid to the atmosphere on the way. Exposed to. Then put in another furnace, N₂Annealed in an atmosphere and heat-treated at 600 ° C. for 1 hour. The average atomic spacing at this time was 1.001. In the case of the conventional example recrystallized in this way, the recrystallization rate was low and many twins were included.
[0164]
As is clear from the figure, according to the method of the reference example of the present invention, the growth is performed at a gradient of about 1.7 times as compared with the result of the conventional example. The higher this gradient, that is, the faster the growth rate, the better the crystallinity and the longer the distance.
[0165]
As already described in the section of action, in the process of recrystallization from amorphous to single crystal, if there is a part where crystal nuclei are involuntarily generated, not only the crystallinity is deteriorated but also recrystallization. Inconveniences such as non-elongated dimensions occur. Therefore, in order to improve the crystallinity and extend the crystal distance, recrystallization should be performed as fast as possible. As can be seen from the above data, the results of the reference example of the present invention have found significant results in both “high speed” and “crystallinity”. In the conventional method, means for adding impurities at a high concentration or applying pressure is used, but the present inventors have provided a completely new method focusing on the interatomic distance.
[0166]
By cleaning the surface of the amorphous silicon film and thinning the film thickness etc. in this way, the atoms are temporarily bonded, but a free state in which the bonds between atoms are loosened is created. Leads to an increase in the average interatomic distance. When heat treatment is performed while maintaining the increase in the average interatomic distance, atoms on the surface of the amorphous silicon film can easily move. Then, the recrystallized size region could be expanded from the exposed portion of the single crystal that became the “seed” until a portion that recrystallized at a high speed and an involuntary recrystallization occurred.
[0167]
In this reference example, the atmosphere in the recrystallization step is N.₂However, this may be a hydrogen atmosphere or an argon atmosphere. In this reference example, the solid-phase growth temperature is set higher than the deposition temperature. Conversely, the solid-phase growth temperature may be low and heat treatment may be performed for a long time, or the solid-phase growth may be promoted by light. In addition to heat treatment, EB or the like may be used.
[0168]
Next, a second reference example of the present invention will be described.
[0169]
With the miniaturization of integrated circuits, the size of semiconductor elements is approaching the limit, and not only two-dimensionally reducing but also three-dimensional considerations, that is, reducing the channel region simply by reducing the distance between the source and drain. It has become necessary to reduce in the depth direction. For example, in the case of MOS, when the channel spacing becomes narrower to about 0.1 μm, it has become necessary to make a low concentration layer only in the vicinity of the surface of the channel through which current actually flows. Therefore, the technology for forming such an extremely thin single crystal layer is indispensable. Furthermore, the bipolar transistor has a wide range of applications, such as high-speed operation being possible by making the base region thin.
[0170]
FIG. 8 shows a method for manufacturing a thin single crystal silicon layer that can be used in the base region of a bipolar transistor as a second reference example of the present invention.
[0171]
First, as shown in FIG. 8A, the surface of the silicon substrate is washed with a 0.1% HF aqueous solution to remove the natural oxide film 2 on the surface and clean the surface of the substrate. This substrate is transferred to the apparatus of FIG.
[0172]
Next, the temperature is raised to 525 ° C. while flowing hydrogen gas at 10,000 SCCM and 1 Torr. Then, while maintaining the temperature at 525 ° C., silane gas 500 SCCM and 3 Torr were passed for 2 minutes, and an amorphous film was deposited on the substrate by thermal decomposition reaction of silane gas. At this time, the average atomic spacing of the amorphous film was 1.02 times that of the single crystal. However, this average atomic spacing was monitored using an amorphous film deposited on a silicon oxide film provided on a separate substrate. When the thickness of the amorphous film 3 was 80 nm or less, the average atomic spacing gradually increased from 1.02 times that of the single crystal.
[0173]
Further, when diborane is flowed simultaneously with silane gas, a p-type semiconductor layer is formed, and when phosphine is flowed simultaneously, an n-type semiconductor film is formed. Here, the case where only silane gas is flowed is shown.
[0174]
In this way, after the amorphous silicon film 3 is formed by flowing silane gas, the temperature of the amorphous silicon film is raised to 600 ° C. while flowing high purity hydrogen gas again so that the surface of the amorphous silicon film is not oxidized. Held for hours. The same applies when a high purity gas such as argon gas, helium gas or nitrogen gas is used instead of hydrogen gas.^-4You may maintain the high vacuum below Torr. Thus, during heat treatment in a non-oxidizing atmosphere at 600 ° C., crystallization occurs from the underlying silicon substrate by solid phase growth as shown in FIG. 4 At this time, the average atomic spacing of the amorphous silicon is in a relaxed state of 1.02 times that of the single crystal, and as shown in FIG. 1, the silicon atoms freely move from the amorphous surface to cause solid phase growth. Therefore, surplus silicon atoms escape to the surface, and insufficient silicon atoms are compensated from the surface, so that it seems that a high-quality single crystal without crystal defects could be grown.
[0175]
In order to measure the range in which silicon atoms can move, the range where replenishment can reach from the surface, or the range covered by the bonding potential of active silicon atoms on the surface, the average atomic spacing of the amorphous film is changed by changing the film thickness. The defect density was measured in exactly the same manner under other conditions. That is, the growth of the amorphous silicon film and the solid phase growth are performed in the same chamber so that the solid phase growth is performed without the oxide film on the surface, and the amorphous silicon with various thicknesses. The difference in defect density of the single crystal film was measured from the case where the film was formed, transferred to another reactor as before, a natural oxide film was formed on the surface, and then solid phase growth was performed. The result is shown in FIG. As is apparent from this figure, it is desirable that the film thickness of the amorphous silicon film is 80 nm or less, and when it is 80 nm or more, these effects do not reach and crystal defects are observed.
[0176]
Next, by changing the film thickness to change the average atomic spacing of the amorphous film, maintaining a free surface without an oxide film (curve a), once taken out into the atmosphere after the amorphous film is formed, The result of measuring the relationship between the electron mobility and the film thickness of the amorphous film when the oxide film exists on the surface of the amorphous film (curve b) by changing the atmosphere during the solid phase growth to an oxidizing atmosphere. As shown in FIG. In this case, the electron mobility is large when the film thickness of the present invention, which is a formation method without an oxide film, is 80 nm or less, that is, when the average atomic spacing of the amorphous film is 1.02 times or more that of a single crystal. However, in the case of the conventional forming method in which an oxide film exists on the surface, the electron mobility is small. From this figure, it can be seen that the absence of an oxide film and maintaining the average atomic spacing at least 1.02 times that of a single crystal play an extremely important role in electron mobility. For comparison, FIG. 134 shows the state of solid phase growth when the surface of an amorphous film is oxidized and the average atomic spacing is smaller than 1.02 times that of a single crystal. In the crystalline film, atoms are randomly arranged, and as the crystal growth progresses, each atom fits into a regular crystal lattice position. At this time, the number of atoms in random arrangement does not match the number of atoms in regular lattice positions. This is even worse locally, and as shown in FIG. 135, the crystal grows, so that there is a gap between the lattices, or there are not enough atoms at the lattice positions. Nevertheless, even though each atom is amorphous, it has crystals, and its mobility is small and it cannot move freely. Therefore, these remain in the single crystal film as lattice strain, crystal defects, twins, and the like. Therefore, in the case of the conventional method, when crystallizing by solid phase growth after amorphous film formation, a large number of crystal defects exist in the single crystal. These are called twins and stacking faults, and include many point defects, dislocation nets, and screw dislocations.
[0177]
Next, a third reference example of the present invention will be described. In the reference example, an amorphous silicon film was grown in a hydrogen atmosphere. In this example, a turbo molecular pump was used to make 1 × 10 5.^-4While evacuating to a high vacuum of Torr, heat treatment is performed to make a single crystal. That is, using thermal decomposition of silane gas, depositing amorphous silicon at a pressure of 3 Torr, a flow rate of 200 sccm, a flow rate of 525 ° C. and a deposition rate of 10 nm / min, flowing silane gas for 5 minutes, stopping the silane gas, × 10^-4While evacuating to a Torr vacuum, heat treatment was performed at 600 ° C. for 10 hours to form a single crystal, and a 50 nm single crystal thin film was formed. Conventionally, 10 using a rotary pump^-2Exhaust to about Torr, and a small amount of oxygen formed a natural oxide film, but an extremely high vacuum can be obtained by introducing a turbo molecular pump.
[0178]
In this case, crystal defects were not observed with a transmission electron microscope (TEM), and the film thickness was changed. However, any film having a film thickness of 80 nm or less and an average atomic interval of 1.02 times or more of a single crystal is used. No crystal defects were observed by TEM.
[0179]
Next, a fourth reference example of the present invention will be described.
[0180]
In this example, the carrier concentration is 1 × 10.¹⁷cm^-3As shown in FIG. 10, the mobility after single crystallization of the film formed by flowing phosphine simultaneously with the silane gas at the time of film formation of the amorphous film was obtained by Hall measurement. . Whereas an oxide film on the surface as in the prior art, a single crystal having high mobility and good crystallinity could not be obtained even if a thin amorphous was used, the film thickness was 80 nm when using the method of the present invention. Below, that is, when the solid phase growth is performed using an amorphous film having an average atomic interval of 1.02 times or more of that of a single crystal, the crystallinity is drastically improved. I was able to improve.
[0181]
Next, a fifth reference example of the present invention will be described.
[0182]
In this example, in order to measure the dependence on the degree of vacuum during the heat treatment, after the amorphous silicon film having a thickness of 50 nm was formed in the same manner as in the above reference example, the Hall movement of the film heat-treated at 600 ° C. for 10 hours at a different degree of vacuum was performed. The degree was measured. The average atomic spacing of the film immediately after the film formation was 1.025 times that of the single crystal. As a result, the degree of vacuum is 1 × 10.^-3When it became worse than Torr, as shown in FIG. 11, the mobility in the film | membrane after crystallization fell rapidly. When the surfaces of these films are observed by RHEED (Reflection High Energy Electron Diffraction) during heat treatment, 1 × 10^-3It was also found that in a vacuum lower than that of Torr, a diffraction image showing silicon crystals could not be obtained even after crystallization was completed, and the surface was covered with oxide. As a result of examining the time change of the average atomic spacing before and after the solid phase growth, it was 1.03 times that of the single crystal immediately after the film formation, but the average atomic spacing gradually decreased while being left in the furnace, and the solid phase growth. Immediately before, it was found to be contracted to 1.005. This is cited as one of the evidence supporting the effect of the reduction of the average atomic spacing of the present invention.
[0183]
Further, as a sixth reference example of the present invention, a description will be given of a method in which the atmosphere is reduced to prevent oxidation of the amorphous silicon surface during solid phase growth. Oxygen, moisture, etc. are drifting in the furnace due to leakage of air from the joints of pipes or re-evaporation of adsorbed molecules on the walls of the furnace, and this is diluted with hydrogen gas or pushed away to create a reducing atmosphere. did. Here, when the pressure of hydrogen gas is increased and the flow rate is increased, surface oxidation is suppressed, and the average atomic spacing of the deposited amorphous film is maintained until immediately before solid phase growth, so that defects in the single crystal are eliminated. , Mobility will improve. Here, arsenic concentration 2 × 10 as the base substrate¹⁹cm^-3A monocrystalline silicon film is formed by forming an intrinsic amorphous silicon film with a thickness of 20 nm on this n-type silicon substrate and performing heat treatment at 580 ° C. for 1 hour in a reducing atmosphere using hydrogen. Formed. The average atomic spacing of the deposited 20 nm amorphous silicon film was 1.03 times that of the single crystal. However, this value was monitored using a separately deposited amorphous film on silicon oxide.
[0184]
FIG. 12 shows the result of changing the hydrogen flow rate and measuring the relationship between the hydrogen flow rate and electron mobility. As is apparent from this figure, it can be seen that the electron mobility increases as the hydrogen flow rate increases.
[0185]
Similar effects were obtained when an inert gas such as argon gas, helium gas, nitrogen gas, or the like was flowed in addition to the reducing hydrogen atmosphere.
[0186]
An example of the result of analyzing the impurity distribution after the completion of the single crystallization by SIMS is shown in FIG. Undersubstrate is arsenic concentration 2 × 10¹⁹cm^-3However, the 20 nm single crystal thin film formed on the n-type semiconductor by the method of the present invention remained intrinsic without any conductive impurities below the SIMS detection limit.
[0187]
The chemical vapor deposition method (CVD method) based on the thermal decomposition of a gas containing silicon has been described as an example. However, the same effect can be obtained by using an evaporation method, a sputtering method, or the like for forming an amorphous silicon film. It was. It goes without saying that the same effect can be obtained with germanium other than silicon.
[0188]
A method for forming a MOS transistor using this apparatus will be described as a seventh reference example of the present invention.
[0189]
First, as shown in FIG. 14A, after the first semiconductor device is formed on the silicon substrate surface 11, a silicon oxide film 12 is deposited by about 1 μm on the entire surface of the silicon substrate by the CVD method. Here, the first semiconductor device is a MOSFET composed of a gate electrode 6 and a source / drain region 7, and 8 is an element isolation insulating film.
[0190]
Next, as shown in FIG. 14B, after a resist is applied and exposed and developed, the silicon oxide film 12 in a desired region is etched by reactive ion etching, and silicon that becomes a seed crystal at the time of stacking part single crystallization. Expose the substrate surface and strip the remaining resist. Then, the silicon substrate is washed with an acid or the like and carried into an amorphous silicon reaction furnace while keeping the exposed silicon surface clean.
[0191]
In the formation, first, the wafer is carried into the reaction furnace, and then the inside of the reaction furnace is evacuated. Careful attention is given so that a natural oxide film does not grow on the exposed silicon surface that will become a seed crystal when solid phase growth is performed later. Then, the substrate temperature is raised to 450 to 550 ° C.
[0192]
Here, when amorphous silicon is deposited using silane gas, the substrate temperature is kept between 500 and 550 ° C. in order to obtain good quality amorphous silicon, and between 450 and 550 ° C. when disilane gas is used. Keep on. Silane or disilane gas is introduced into the reaction furnace, and amorphous silicon 13 is deposited on the entire surface of the substrate by the thermal decomposition reaction of these silane gases (FIG. 14C). At this time, diborane or phosphine may be mixed into the silane-based gas, and an amorphous silicon film containing boron or phosphorus may be deposited. The film thickness of this amorphous silicon layer is 20 nm or less. In this way, when a desired film thickness of 20 nm or less is obtained, introduction of the silane-based gas into the reaction furnace is stopped and the furnace temperature is lowered. The deposition rate is controlled by the gas flow rate or the like, and the film is formed under the conditions satisfying the deposition rate equation.
[0193]
Subsequently, the inside of the apparatus is continuously evacuated to 10^-7A high vacuum of less than Torr is set, the furnace temperature is raised to about 600 ° C., and the thin amorphous silicon film is crystallized to form a single crystal silicon layer 14 (FIG. 14D). In this step, amorphous silicon is laterally single-crystallized using the surface in contact with the substrate silicon as a seed for solid phase growth. In high vacuum, the average atomic spacing of the amorphous film is maintained at the value at the time of deposition, so the bonding of the amorphous film is kept loose, and the silicon on the surface of amorphous and single crystal silicon Atoms are very easy to move because of imperfect bonds, and migrate by migrating the surface. Furthermore, by using a thin film of 20 nm or less, the influence of the surface migration is spread throughout the film, and the entire atoms in the film are kept in a state of being very mobile. Therefore, the crystallization rate is high, and the single crystallization is performed far from the seed before random crystal nucleation that prevents single crystallization occurs. For example, when crystallization was performed at 600 ° C., single crystallization was performed up to a length of 20 μm. The temperature for crystal growth may be lower. However, a longer time is required. For example, 20 hours or more were necessary at 580 ° C. Further, the concentration in the amorphous silicon is 10²⁰cm^-3When a certain amount of boron or phosphorus was introduced, the crystallization rate increased and the single crystallization region became 100 μm. Furthermore, if an element that is electrically active with respect to silicon, such as high-concentration phosphorus or boron, was previously added to the surface of the underlying insulating film, single crystallization of a wider area could be promoted. The same effect could be obtained even when the insulating film itself was formed of glass containing phosphorus, boron, or the like. By these measures, in addition to the migration of atoms on the surface, the movement of atoms at the lower interface also easily occurs, so the rate of crystal growth has increased, and it is considered that single crystallization has progressed more widely.
[0194]
Further, before the amorphous silicon is single-crystallized, it may be once taken out of the reaction furnace, and boron or phosphorus may be introduced by ion implantation. In this case, it is necessary to release the natural oxide film again after carrying in the furnace again and before the solid phase growth to loosen the average atomic spacing again.
[0195]
As a modification, the amorphous layer may be shaped into a desired shape before single crystallization. In this case, after applying a resist, exposing and developing, the silicon is etched by RIE, and the remaining resist is peeled off. The solid-phase growth rate varies greatly depending on the growth direction, and it has been confirmed that the <100> direction is the fastest. For this reason, the amorphous layer has a long side in the <100> direction as shown in FIG. The wafer is carried into the furnace, and the natural oxide film on the amorphous silicon is peeled off by the above-described reduction reaction. Thereafter, solid phase growth is performed in a high vacuum state.
[0196]
Although the thin and high-quality single crystal silicon thin film 14 is formed by the above steps, the element may be formed using a single crystal thin film having a thickness of 20 nm or less as it is unless particularly necessary. In this case, the mobility is rather large, and NMOS is 1000 cm.^-2Those exceeding / V · sec were also obtained. However, when forming an element, unlike a normal element, a device is required for forming a source / drain contact. First, an insulating film 18 is formed on the single crystal silicon thin film 14, and a contact is opened in a region corresponding to one of the source and drain of the insulating film 18. For this, even if any one of RIE, CDE, fluorine-based aqueous solution, and the like is used, the single crystal film penetrates by over-etching. Therefore, in order to reduce the contact resistance, silicide such as tungsten silicide was used as the wiring instead of the commonly used polycrystalline silicon. For example, tungsten silicide is formed using a mixed gas of tungsten hexafluoride and hydrogen gas. In addition, after the exposed portion of the single crystal thin film in the contact region is cleaned using the present invention, a thin film amorphous silicon having a thickness of 20 nm or less continuously doped at a high concentration may be deposited and crystallized to be used as a wiring. . In any case, good contact characteristics were obtained, and a high mobility element (transistor or the like) could be formed as described above (FIG. 14E).
[0197]
Further, as an eighth reference example of the present invention, an example in which a thicker single crystal layer is formed by using twice deposition of amorphous silicon and crystallization by heat treatment will be described.
[0198]
The first amorphous silicon deposition and crystallization are performed in the same manner as the sixth reference example shown in FIGS. 14A to 14D, and are shown in FIGS. 16A to 16D. Thus, the single crystal silicon film 14 is obtained.
[0199]
Thereafter, second amorphous silicon deposition and crystallization are performed. That is, after the heat treatment for forming the first single crystal silicon film, the reaction furnace temperature is set to 450 ° C. to 550 ° C. without opening the reaction furnace, and a silane-based gas is introduced into the reaction furnace. A crystalline silicon film 13s is deposited (FIG. 16E), and the introduction of gas is stopped. At this point, the silicon substrate 11 may be carried out of the furnace and crystallized using another annealing furnace. Then, the furnace temperature is raised to about 600 ° C., and as shown in FIG. 16F, the amorphous film is monocrystallized in the vertical direction using the previously crystallized film 14 as a seed. When the 200 nm amorphous film 13 s was deposited, it was easily single crystallized in the vertical direction to obtain a single crystal silicon film 14.
[0200]
After that, the silicon substrate is taken out of the vacuum furnace, a silicon oxide film is deposited by CVD, a resist is deposited and exposed and developed, and the desired region of the underlying silicon oxide film is reactive ion etched using this resist as a mask. Etch with Then, the remaining resist is stripped, and then a desired region of silicon that has been monocrystallized is etched by reactive ion etching using the silicon oxide film as a mask. After the silicon oxide film 20 is deposited again by the CVD method, the silicon oxide film is planarized by the bias sputtering method. Thereafter, the silicon oxide film is wet etched until the single crystal silicon layer is exposed (FIG. 16G). In this way, a second single crystal silicon layer is obtained in which element isolation is performed by the silicon oxide film 20, and the total film thickness of the single crystal silicon layer 14 is 220 nm.
[0201]
The following describes the fabrication of the second layer MOS transistor. First, channel doping for threshold control is performed on the second silicon substrate, a CVD silicon oxide film serving as a gate insulating film is deposited to 20 nm, and a CVD polysilicon film serving as a gate electrode is deposited to 200 nm. A resist is applied, exposed and developed, polysilicon is etched by RIE, a gate electrode is formed, and a conductive impurity is ion-implanted into a region to be a source / drain. The dose is determined in consideration of the thickness of the second silicon film. For example, when the film thickness is 50 nm, 1 × 10¹⁵cm^-2Then, 1 × 10 As ions²⁰cm^-3A high concentration of was obtained. Then, activation annealing is performed to activate the conductive impurities. Further, a CVD silicon oxide film is deposited, an opening for forming a source / drain electrode is provided, and an electrode and a wiring layer are formed.
[0202]
In the present invention, the amorphous film may be formed by sputtering or UHV. For example, a silicon substrate having an insulating film in which a part of the silicon substrate is exposed is 10.^-10A high vacuum of less than Torr is maintained, high-purity silicon is used as a target, evaporated by an electron beam, and deposited on the silicon substrate surface. At this time, after an amorphous silicon film having an average atomic interval of 1.03 times and a film thickness of 20 nm is formed on the insulating film by vapor deposition, the silicon substrate is heated at 600 ° C. for 5 hours or more while being kept in a high vacuum. A single crystal silicon thin film could be formed on the insulating film.
[0203]
Next, a first embodiment of the present invention will be described.
[0204]
In this example, as shown in FIG. 17, granular single crystal silicon 205 is formed. Again, in the same manner as in Reference Example 1, in obtaining a silicon single crystal thin film, an amorphous silicon film having an average atomic spacing of 1.03 times or more of the average atomic spacing of the silicon single crystal is used in advance. N in a non-oxidizing atmosphere to suppress the growth and adhesion of an oxide film on the surface of the amorphous film₂And heat-treated.
[0205]
The apparatus for film formation was the same as that shown in FIG. The sequence for forming the thin film was the same as that shown in FIG. However, the sample structure was chosen to be slightly different. That is, in the previous reference example 1, the opening 203 was provided in the silicon oxide film 202 as shown in FIG. 4, but in this example 1, the opening was provided as shown in FIGS. 18 (a) to 18 (c). There wasn't.
[0206]
First, after forming a silicon oxide film 202 as shown in FIG. 18A, an amorphous silicon film 204 is deposited as shown in FIG. This film thickness was 315 angstroms in Reference Example 1, but was 200 angstroms here. However, as reported at the beginning of this Example 1, in the measurement results immediately after film deposition, the average interatomic distance was 1.03 times that of the single crystal silicon substrate.
[0207]
Thereafter, as shown in FIG. 18C, heat treatment is performed at 600 ° C. for 5 hours to form single crystal silicon 205. Here, the recrystallization conditions were the same as those in Reference Example 1. That is, in order to suppress the deposition of the surface natural oxide film, for example, the same furnace was used. Here, as described above, the amorphous silicon film is not in contact with the so-called “seed” exposed portion of the single crystal silicon when it is recrystallized. As a result, as shown in the TEM photograph in FIG. 19, the amorphous portion was aggregated while growing, and extremely high quality single crystal grains having no defects were obtained. As shown in the TEM photograph in FIG. 20, as a result of detailed observation of the single crystal, the <001> silicon axis grows in the vertical direction with respect to the underlying silicon oxide.
[0208]
The present inventors have further found that the grains can be arranged in an arbitrary size by selecting the film thickness, temperature, base, and the like. Incidentally, FIGS. 21A to 21C show results when the initial amorphous silicon film thickness is 200 angstroms, 100 angstroms, and 50 angstroms. In each case, the initial interatomic average interatomic distance was 1.03 times, 1.032 times, and 1.034 with respect to that of the single crystal silicon film. These are all very good single crystals.
[0209]
Next, a second embodiment of the present invention will be described.
[0210]
Here, in obtaining a Ge single crystal thin film, a film having an average atomic interval of an amorphous Ge film of 1.02 times or more of an average atomic interval of a Ge single crystal is used in advance to oxidize the surface of the amorphous film. N in non-oxidizing atmosphere to suppress film growth and adhesion₂And heat-treated. The apparatus shown in FIG. 2 was used as the film forming apparatus as in Reference Example 1.
[0211]
Also, the sequence for film deposition was the same as in FIG. The sample structure was the same as that of Example 1 shown in FIG. 18A as shown in FIG. That is, even in this example, no opening was provided.
[0212]
Then, amorphous germanium 206 was deposited using deposition conditions such that the average atomic spacing of germanium in the film was 1.02 times the average atomic spacing of the Ge single crystal (FIG. 22B). At this time, the film thickness of the amorphous germanium was 115 angstroms, for example.
[0213]
Thereafter, for recrystallization, recrystallization was performed in the same manner as in Reference Example 1 to form a granular single crystal germanium film 207 (FIG. 22C). That is, the same furnace as in Reference Example 1 was used to suppress the deposition of the surface natural oxide film.
[0214]
In this example, since the amorphous germanium film is not in contact with the so-called “seed” single crystal exposed portion in recrystallization, the result is similar to the example shown in FIG. The crystalline part agglomerated during crystal growth, and an extremely good single crystal having no defects was obtained. Moreover, a uniaxial orientation was obtained.
[0215]
The present inventors have further found that the grains can be arranged in an arbitrary size by selecting the film thickness, temperature, base, and the like.
[0216]
That is, the average atomic spacing of the amorphous film is set to 1.02 or more of the single crystal, the surface of the amorphous film is kept in a free state, atoms can move freely in the film, and the chemical potential Focusing on the change in (gypsum free energy), the silicon atoms are moved simultaneously with crystallization to aggregate the atoms.
[0217]
This example will be further described as a third embodiment.
[0218]
First, as shown in FIG. 23A, the surface of the silicon substrate 41 is oxidized in a 950 ° C. water vapor atmosphere to form a silicon oxide film 42 having a thickness of 0.1 μm. Then, an amorphous silicon film 43 having a thickness of 0.02 μm is deposited by the CVD method. Here, the amorphous silicon film was formed at a silane gas of 1 Torr at 525 ° C. for 2 minutes.
[0219]
Thereafter, the silane gas is stopped and heat treatment is continuously performed at 600 ° C. for 30 minutes to form single-crystal particles 44 as shown in FIG. At this time, the argon gas passed through the gas purifier was kept flowing to suppress the surface of the amorphous silicon from being oxidized. By this heat treatment, the amorphous silicon is crystallized and aggregated at the same time to form a single crystal granular layer. The electron microscope (SEM) photograph at this time is shown in FIGS. 24 and 25, and the transmission electron microscope (TEM) photograph of the cross section is shown in FIG. Each grain is aligned in both size and spacing, as can be seen from the photo. Moreover, the size is controlled to the same size with good reproducibility.
[0220]
Next, in this case, the relationship between the film thickness of the amorphous silicon film and the grain size after heat treatment at 600 ° C. for 1 hour was measured. The result is shown in FIG. From this figure, it can be seen that the grain size can be increased if the thickness of the original amorphous silicon film is increased.
[0221]
It is also possible to control the shape of the grains when they are aggregated depending on the degree of familiarity between the base and amorphous silicon.
[0222]
That is, each grain becomes smaller when the silicon oxide film is used as a base. On the other hand, in the case of phosphosilicate glass (PSG), the grains are greatly flattened.
[0223]
Next, when the base is a PSG film, a silicon nitride film, or a silicon oxide film, the relationship between the film thickness of the amorphous silicon film and the diameter of the heat treatment grain at 600 ° C. for 1 hour was measured, and the result is shown in FIG. Show. From this result, it is understood that the diameter of the grains can be controlled also by selecting various bases. In addition, the grain size can be similarly increased by using a BSG, BPSG, AsSG film or the like.
[0224]
Furthermore, the same control can be performed depending on the temperature of the heat treatment and the oxidation degree of the atmosphere.
[0225]
Next, a fourth embodiment of the present invention will be described.
[0226]
First, as shown in FIG. 29A, a silicon oxide film 52 having a film thickness of 0.1 μm is formed on the surface of a silicon substrate 51 by a CVD method using a mixed gas of silane gas and oxygen at a substrate temperature of 450 ° C. An amorphous silicon film 53 having a film thickness of 0.03 μm is deposited by a CVD method using.
[0227]
Thereafter, when the silane gas is stopped and hydrogen gas is kept flowing for 1 hour, the amorphous silicon is crystallized and aggregates to form a single crystal granular body 54 as shown in FIG.
[0228]
When this is oxidized with a mixed gas of hydrochloric acid gas and water vapor at 750 ° C. for 20 hours, a silicon oxide film 55 having irregularities with a period of about 0.05 μm is formed on the surface (FIG. 29C).
[0229]
Thereafter, a polycrystalline silicon film 56 is formed on the upper layer by a CVD method using a silane gas at a substrate temperature of 630 ° C. (FIG. 29D).
[0230]
As a result, it is possible to form an electrode with a surface area of 0.05 μm and a large surface area. When this polycrystalline silicon film is used as an electrode, the conductive impurity may be formed later by ion implantation, but it can also be formed by simultaneously flowing a gas such as diborane. Since all the steps can be performed at 800 ° C. or lower in this manner, the present invention can also be applied to the case where a MOS element or the like is formed in another region.
[0231]
Further, in the step of FIG. 29 (c), film formation with a silane gas is performed at a substrate temperature of 550 ° C., an amorphous silicon film is deposited, and a surface with large irregularities is formed by repeating the steps shown in FIG. 29 (a) again. be able to.
[0232]
Further, even if disilane gas is used instead of silane gas, or an amorphous silicon film is formed by another method such as vapor deposition or MBE, the surface is not oxidized and crystallization is promoted so as to keep a free state. If it is made, the same effect can be acquired. Next, as a fifth embodiment of the present invention, a method of using the present invention for a MOS capacitor will be described.
[0233]
First, as shown in FIG. 30A, a silicon oxide film 62 having a thickness of 0.05 μm is formed on the surface of a silicon substrate 61, and a silicon oxide film is formed by anisotropic ion etching using ions 64 using the resist pattern 63 as a mask. Etch.
[0234]
Thereafter, as shown in FIG. 30B, a silicon oxide film 65 is deposited by 0.25 μm by the CVD method.
[0235]
Further, as shown in FIG. 30C, a resist pattern 66 is formed and anisotropic etching is performed with ions 67.
[0236]
Then, the etching is finished when the etching reaches the silicon substrate 61. In this way, a silicon oxide film having a U-shaped cross section is formed as shown in FIG. Here, the bottom of the silicon oxide film may be left even if overetching is performed to some extent.
[0237]
When the shape processing of the base is completed in this way, first, as shown in FIG. 30E, an amorphous silicon film 68 having a thickness of 0.02 μm is deposited on the entire surface by the CVD method using silane gas. .
[0238]
Then, when the heat treatment is performed at 550 ° C. for 1 hour while the silane gas is stopped and the hydrogen gas is continuously flown, the amorphous silicon on the surface of the silicon oxide film 65 having a U-shaped cross section is crystallized and aggregated to form FIG. As shown in (f), a single crystal granular body 69 is formed. Here, the amorphous silicon does not aggregate on the surface of the silicon substrate 61 and is solid-phase grown in the same crystal orientation as that of the single crystal silicon substrate to form a flat film.
[0239]
When this is oxidized with a mixed gas of hydrochloric acid gas and water vapor at 750 ° C. for 20 hours, a silicon oxide film 70 having irregularities with a period of about 0.05 μm is formed (FIG. 30G).
[0240]
Thereafter, a polycrystalline silicon film 71 as a capacitor electrode, a silicon oxide film 72 as a capacitor insulating film, and a polycrystalline silicon film 73 as a capacitor electrode are formed on the upper layer by a CVD method using silane gas at a substrate temperature of 630 ° C. (FIG. 30 (h)).
[0241]
As a result, it is possible to form a capacitor having a large effective capacity by increasing the surface area by making the surface uneven by 0.05 μm.
[0242]
Next, a ninth reference example of the present invention will be described.
[0243]
In this method, when obtaining a Si single crystal thin film, a silicon oxide film 2 having an opening is formed on the surface of a silicon substrate 1 as shown in FIG. A single crystal is deposited so as to coincide with the average atomic spacing of the single crystal.₂A silicon single crystal is obtained by heat treatment in an atmosphere.
[0244]
FIG. 32 is a diagram showing an outline of a thin film forming apparatus according to a ninth reference example of the present invention. In this apparatus, a viewing window W is formed in a chamber 311, and a laser light source 315 and a spectroscope 316 are installed through the window so that the density of the amorphous film can be continuously observed by Raman scattering spectroscopy. It is characterized by that. That is, the chamber 311 is provided with a source gas introduction port 312 for film deposition, an exhaust port 313, and a sample stage 314 on which a sample on which a thin film is to be formed is placed. In this embodiment, for example, hydrogen H is used as the source gas.₂And SiH₄Alternatively, disilane or the like is introduced through the mass flow controller 317, and a doping gas can be introduced as necessary. In the figure, for the sake of simplification, there is only one introduction port, but this may also be introduced separately to the vicinity of the sample stage as necessary. Further, the pressure in the chamber can be adjusted by the turbo molecular pump 318, and the substrate temperature can be adjusted by the heater 319.
[0245]
A method for forming a thin film using this apparatus will be described.
[0246]
First, a silicon oxide film was deposited in advance on the surface of a p-type single crystal (100) silicon substrate, and an opening was created by photolithography. Prior to the deposition of the thin film, the substrate and the like were cleaned at a predetermined temperature and gas composition.
[0247]
Subsequently, while measuring the average atomic spacing with a spectroscope, SiH₄An amorphous silicon film having a film thickness of 315 Å is deposited under the conditions of partial pressure of 1 Torr and deposition rate of 7 nm / min. Here, the substrate temperature was set to 525 ° C. 480cm from the output of the spectrometer^-1A spectrum having a peak can be obtained, and the average atomic spacing of the amorphous silicon film thus formed is 480 cm.^-1It can be seen that a spectrum with a peak can be obtained, that is, the density is almost the same as that of single crystal silicon. It was also experimentally confirmed that the spectral position reflects the average atomic spacing and density of silicon atoms. That is, for example, when the density is measured by the RBS (Rutherford Backscattering) method for a sample whose spectrum is shifted to the low frequency side by 1.01 times, this density is 1 / 1.01 smaller than the density of the single crystal. As a result, it was confirmed that the average atomic spacing spreads 1.01 times. Here, the average atomic interval of the amorphous film is preferably 0.98 or more and 1.02 of that of the single crystal, preferably 1.01 or less, more preferably 0.995 to 1.005, That is, the closer to 1, the better.
[0248]
Here, as a result of film formation of amorphous silicon while changing the temperature and gas composition, when the film formation rate R is performed under the condition satisfying the following formula, the average interatomic distance is 0.98 to Films up to 1.02 were obtained.
[0249]
logR (A / min) <-10614 / T (K) +14.857 The region indicated by this condition is shown in FIG. In regions other than this condition, a film having an average atomic spacing of less than 1.02 could not be formed.
[0250]
The silicon substrate on which the amorphous film has been formed in this way is taken out of the chamber and nitrogen N as shown in FIG.₂Heat treatment for recrystallization is performed in an atmosphere. This temperature was, for example, 600 ° C. This apparatus is connected to an introduction port and an exhaust port, and the exhaust port is connected to a vacuum pump so that evacuation can be performed. Next, the time dependency of the growth distance from the “seed” to the lateral direction was measured with an optical microscope 321. At this time, the heating rate of the furnace was 50 ° C./min, and the cooling rate was 99 ° C./min. The heat treatment was divided every few minutes, and photographs were taken with an optical microscope to determine the time dependency of the growth distance and changes in the growth rate. FIG. 35 shows the result. As a result, it can be seen that the growth rate is constant and the growth distance extends linearly with time.
[0251]
The observation of the interface between the amorphous silicon and the single crystal silicon at this time, the shape of the so-called growth edge, and the observation of crystal defects in the film were performed using a transmission electron microscope. As a result, as described above, the inventors found out the occurrence of crystal defects such as twins due to the change of the preferential growth surface and the decrease in growth rate.
[0252]
Next, in order to confirm the suppression of this preferential growth plane change, a heat treatment for 600 ° C. for 5 minutes and a long time for 2 hours are prepared for the initial growth, and the cross sections of these samples are accelerated. Observation was performed with a transmission electron microscope (TEM) having a voltage of 400 KV and a resolution of 1 angstrom. FIG. 36 and FIG. 37 show this photograph. FIG. 36 shows a TEM image after 5 minutes, FIG. 37 (a) shows an electron diffraction image after 2 hours, and FIG. 37 (b) shows a TEM image after 2 hours. In particular, in the sample after the heat treatment for 2 hours, crystallization progresses from “seed” to 12 μm, the growth end also maintains the (100) plane well, and the same crystal as the silicon substrate in the electron diffraction pattern It was confirmed that it was a high-quality single crystal free from defects such as orientation twins.
[0253]
A similar evaluation was performed on an amorphous film having an average interatomic distance of 0.98 to 1.02 having a single crystal, and high quality single crystals could be obtained in any case.
[0254]
Furthermore, the residual stress after this amorphous film was crystallized was actually measured by a micro-Raman method to confirm the effect. Here, the spectroscope has been developed by the present inventors. As shown in FIG. 38, the laser beam from the Ar laser 416 is focused on a 1 μm diameter region of the sample surface through a microscope and scattered by 180 degrees. The measured light was introduced into the spectroscope 417 to perform spectroscopic measurement. A multi-channel CCD is used as the light receiving unit, and the spectrum is received at a time and accumulated in a memory so that high sensitivity can be obtained. The measurement conditions were a laser wavelength of 514.5 nm, a sample irradiation energy of 3 mW, and an irradiation spot diameter of 1 μm.
[0255]
Stress (σ) is ~ 520cm^-1Was calculated by the following formula.
[0256]
σ = 2.49 × 10⁹・ (Ω_O−ω_r) (dyn / cm²) Where σ is stress and ω_O(Cm^-1) Is the wave number of the spectral peak of the sample, ω_r(Cm^-1) Indicates the wave number of the spectral peak of the (100) silicon (a) substrate at room temperature. The value of single crystal silicon was used as the elastic strain constant used to calculate this coefficient. FIG. 39 shows the Raman spectrum measured with this spectrometer. The stress was calculated | required using the said Formula from the shift of this spectrum. It can also be seen that the stress is tensile if the peak is shifted to the low stress side. Here, only the shift amount is used. The laser beam was narrowed down to a diameter of 1 μmφ, and an average stress within that range could be obtained. FIG. 40 is a diagram showing the stress distribution obtained as a result. Residual stress was hardly seen even if it was away from the “seed”, and it was confirmed that it was as intended by the present inventors. Therefore, it was reconfirmed that the tensile stress generated in the conventional film was generated because the film contracted.
[0257]
From the above results, by using an amorphous film having a density close to that of a single crystal, stress associated with crystallization does not occur, and therefore the change in the preferential growth surface from the (110) silicon surface to the (111) silicon surface is suppressed. It can be extended far without slowing down the growth rate, and has good crystallinity.
[0258]
Here, prior to the deposition of the amorphous film, it is important to keep the surface of the “seed” part as clean as possible, especially the removal of the natural oxide film, but the removal of the natural oxide film on the surface of the “seed” part is important. A reduction reaction with a reactive gas was used. For example, 850 ° C., SiH₄Partial pressure 7 × 10^-4The natural oxide film could be completely removed by treating with Torr for 30 minutes. It is also important to deposit an amorphous film continuously after removing the natural oxide film. In this example, the atmosphere in the recrystallization step is N.₂However, this may be a hydrogen atmosphere or an argon atmosphere. In this embodiment, the solid phase growth temperature is set higher than the deposition temperature. Conversely, the solid phase growth temperature may be set low and heat treatment may be performed for a long time, or the solid phase growth may be promoted by light. In addition to heat treatment, EB or the like may be used.
[0259]
Next, a tenth reference example of the present invention will be described.
[0260]
In this example, in order to make the density of the amorphous silicon film 83 coincide with the density of the single crystal, the density of the amorphous silicon film after film formation is measured by a microscopic Raman method, and the amount calculated according to this value The silicon ions are ion-implanted.
[0261]
First, as shown in FIG. 41A, an amorphous silicon film having a thickness of 0.2 μm was deposited, and the density was measured by a micro Raman method. As a result, it was found that it was 0.97, and the optimum ion implantation amount was calculated from this value, and 3.75 × 10²⁰atom / cm³Injected. At this time, the acceleration voltage is 80 keV and the dose amount is 8.3 × 10.¹⁴When the atom / cm 2 was set, the density could be 1.00.
[0262]
Then, as shown in FIG. 41C, heat treatment was performed at 600 ° C. for 2 hours to form a single crystal silicon film 3.
[0263]
The single crystal silicon film thus obtained has no crystal defects, has a small residual stress as shown in FIG. 42, and is a good single crystal silicon film as shown in FIG.
[0264]
In the ninth and tenth reference examples, the example using “seed” has been described. Next, as a sixth example of the present invention, an example in which heat treatment is performed without using “seed” is described. explain.
[0265]
First, as shown in FIG. 44, after the silicon oxide film 2 is formed on the surface of the (100) silicon substrate 1, SiH is maintained while keeping the substrate temperature at 515 ° C.₄An amorphous silicon film 3 having a thickness of 20 nm is deposited at a partial pressure of 2 Torr. The average atomic spacing of this amorphous silicon film was 1.03 times that of the single crystal.
[0266]
Thereafter, the amorphous silicon film is applied with an acceleration voltage of 20 keV to 5 × 10 5.¹⁵atom / cm²Of silicon ions were implanted. As a result, the average atomic spacing of the amorphous silicon film was almost the same as the average atomic spacing of the single crystal.
[0267]
Next, the surface of the silicon substrate is immersed in an HF aqueous solution diluted 100 times with pure water for 1 minute to remove the natural oxide film on the surface and clean the surface of the substrate. Thereafter, the substrate is transferred to the heat treatment apparatus shown in FIG. 32 within 5 minutes.
[0268]
Next, the inside of this heat treatment apparatus is 1 × 10^-7After a high vacuum of Torr or lower, the substrate temperature was raised to 550 ° C. and held for 2 hours.
[0269]
Then, after lowering the substrate temperature to near room temperature, the vacuum was broken and the silicon substrate was taken out.
[0270]
The results obtained by observing the results thus obtained with a scanning electron microscope (SEM) are shown in FIGS. 45 (a) and 45 (b) with photographs and schematic views. As is apparent from this figure, uniform and uniform single crystal silicon 4 is formed on the insulating film. The results of measuring the structure of each silicon grain using a transmission electron microscope (TEM) are shown in FIG. As a result, a lattice image was clearly seen in the silicon grains, and it was found that each grain was single crystallized. As a result, a complete single crystal having no crystal defects in the single crystal is obtained. In addition, FIG. 47 shows the results of examining the orientation of these crystal grains by electron diffraction. It was found that every grain exhibited a crystal orientation with a <100> axis in the vertical direction. Since this orientation is a completely new phenomenon, the cause is not yet clear, but all grains show good orientation.
[0271]
On the other hand, FIG. 48 shows a TEM photograph in the case where similar heat treatment is performed without implanting silicon ions. Also in this case, uniform single-crystal silicon having a uniform size is formed on the insulating film. However, when a lattice image of the grains is observed closely, crystal defects such as twins are observed. Further, when the orientation of each grain was examined using electron beam diffraction, no particular orientation was observed. The mechanism of solid phase growth and defect generation of such a grained single crystal is not yet clear, but the inventors have inferred the following mechanism from observation of a TEM image. That is, the “crystal nucleus” of the crystal grain is that the crystal grain has a substantially spherical shape, and the height of the center of the grain matches the film thickness of the amorphous film. Inferred to be occurring on the surface. Single crystallization proceeds from this nucleus. The shape of the growth end of crystallization is composed of an acute angle surface on the insulating film side. When the growth edge proceeds downward (toward the insulating film) to some extent, a large stress is generated at the growth edge due to the difference in density between the amorphous film and the single crystallized film. In order to relieve this stress, the surface of the growth edge shifts and a crystal defect occurs. This is consistent with the simulation results described above. Further, when the injection amount is variously changed, 5 × 10¹⁵atom / cm²The same was true for items that greatly deviated from. In addition, FIG. 49 shows the results of measurement of the correlation with the crystallinity of the single crystal when using various amorphous materials with different implantation amounts and changing the average atomic spacing of the amorphous film. As a result, it was found that the crystallinity was good when the average atomic spacing was 0.98 times to 1.02 times that of the single crystal.
[0272]
Next, a seventh embodiment of the present invention will be described. In this example, irregularities are formed in the insulating film, an amorphous silicon film is formed thereon, and this is crystallized by heat treatment.
[0273]
First, as shown in FIG. 50A, a (100) silicon substrate 1 is prepared, and a silicon oxide film 2 having a film thickness of 300 nm is deposited on this surface.
[0274]
Thereafter, as shown in FIG. 50 (b), a resist pattern is applied to the surface of the silicon oxide film 2, exposed and developed, and the silicon oxide film is etched by about 100 nm using the formed resist pattern as a mask to form fine irregularities. . Then, the resist pattern is peeled off and SiH is maintained while keeping the substrate temperature at 515 ° C.₄An amorphous silicon film 3 having a thickness of 20 nm is deposited at a partial pressure of 0.5 Torr. The average atomic spacing of this amorphous silicon film was 1.01 times that of the single crystal.
[0275]
Next, the inside of this heat treatment apparatus is 1 × 10^-7After a high vacuum of Torr or less, the substrate temperature was raised to 600 ° C. and held for 1 hour.
[0276]
Then, after lowering the substrate temperature to near room temperature, the vacuum was broken and the silicon substrate was taken out.
[0277]
In this way, it was found that silicon single crystal grains having perfectly aligned crystal orientations were formed as shown in FIG. If a device such as a turbo pump was attached to the apparatus used for film formation, the same result could be obtained only by raising the temperature continuously to 600 ° C. after film formation.
[0278]
This phenomenon can be explained as follows. That is, as shown in the enlarged view of FIG. 50 (d), when the base is uneven, the amorphous silicon film deposited in the recess has an insulating film on the side surface and the bottom surface, so that it is <100 in two directions, the horizontal direction and the vertical direction. > Orient so that the axis comes. Since the crystal orientation is suppressed by two axes, any crystal grains exhibit orientation.
[0279]
On the other hand, when an amorphous silicon film on a flat insulating film is monocrystallized to form grains, it is monocrystallized so that there is a <100> axis in the vertical direction. However, since only one axis is oriented, the crystal orientation in the horizontal plane is not determined by rotation as shown in FIG.
[0280]
Further, FIG. 52 shows an example in which linear irregularities are formed at fine intervals on an insulating film, and an amorphous silicon film is deposited thereon by 50 nm. Here, the amorphous silicon film was deposited by controlling the deposition conditions so as to be substantially equal to the density of the single crystal while measuring the density of the amorphous silicon film by the Raman scattering method. As a result, since the amorphous silicon film was formed thick, the single crystal film was not separated into grains and a single crystal film having no defects was obtained.
[0281]
Further, when a second amorphous silicon film is deposited on the single crystal film to a thickness of about 200 nm and heat treatment is performed, it is approximately the same as the single crystallized film obtained by directly depositing on the silicon substrate and performing the heat treatment. A single crystallized film having crystallinity could be obtained.
[0282]
Next, an eighth embodiment of the present invention will be described. Here, the orientation is controlled by applying a minute change to the base material. That is, a single-crystal silicon film is formed by using a silicon nitride film 2a formed on the surface of a silicon substrate in which a fine linear silicon oxide film 2b is formed, forming an amorphous silicon film thereon, and performing heat treatment. Form.
[0283]
First, as shown in FIG. 53A, a silicon nitride film 2a is formed on the surface of a (100) silicon substrate, a linear recess of about 50 nm is formed using a resist pattern as a mask, and a silicon oxide film 2b is deposited thereon. Etchback is performed to fill the recess with the silicon oxide film 2b. Then, an amorphous silicon film having a thickness of 10 nm is deposited on this upper layer. The average atomic spacing of this amorphous silicon film was set to the same level as that of a single crystal. In this case, it is desirable to have the same level, but if it is 0.98 or more and 1.02, more desirably 0.995 or more and 1.005, substantially the same effect can be obtained.
[0284]
Then, this silicon substrate is carried into a vacuum apparatus while paying attention not to generate an oxide film, and subjected to a heat treatment at 530 ° C. for 2 hours. As shown in FIG. 53B, a silicon single crystal crystal grain having a good orientation is obtained. Is generated.
[0285]
This is presumably because, when crystal nuclei are generated on the amorphous silicon surface, the difference in potential at the interface due to the material suppresses in-plane rotation of the crystal nuclei due to some influence.
[0286]
Also in this case, when the second amorphous silicon film is deposited on the upper layer of the single crystal film and heat treatment is performed, the same crystal as the single crystal film obtained by directly depositing on the silicon substrate and performing the heat treatment is obtained. Thus, a complete single crystal film can be formed without the “seed” of the insulating film.
[0287]
If the amorphous film is covered with a silicon nitride film having a thermal expansion coefficient larger than that of silicon and the amorphous film is slightly contracted by thermal stress, the crystallinity can be improved even with a film having an average atomic spacing of 1.02 or more. Could get.
[0288]
Furthermore, the present invention is not limited to silicon, and crystallinity can be significantly improved by aligning the density of the amorphous film such as a semiconductor such as germanium, metal, and silicide with that of the amorphous film.
[0289]
Next, a ninth embodiment of the present invention will be described.
[0290]
In this example, a method of forming silicon grains on the surface and forming irregularities on the electrode surface in order to effectively increase the capacitor capacity will be described.
[0291]
First, as shown in FIG. 54, an element isolation insulating film 82 is formed on the surface of an n-type (100) silicon substrate 81 to form an element region, and then phosphorus ions are implanted to form n as a contact.⁺A diffusion layer 83 is formed, a 500 nm silicon oxide film 84 is formed by a CVD method, and an opening is formed by lithography and dry etching. Then, a polycrystalline silicon film 85 having a thickness of 100 nm is formed by LPCVD, and POCl₃Is diffused by performing a heat treatment at 950 ° C. in an atmosphere, and further, a natural oxide film formed on the surface of the polycrystalline silicon film during the phosphorus diffusion is removed using ammonium fluoride, and 100 × is obtained by lithography and etching. A lower electrode 85 made of a 200 μm phosphorus-doped polycrystalline silicon film is formed. At this time, a thin natural oxide film 86 having a thickness of about 1 nm is formed on the electrode surface.
[0292]
Then, on this upper layer, as shown in FIG.₄An amorphous silicon film 87 having a thickness of about 10 nm is deposited by a CVD method at a substrate temperature of 525 ° C. and a pressure of 1 Torr using a gas.
[0293]
After this SiH₄The gas was exhausted, non-oxidizing Ar gas was introduced, the temperature was raised, and heat treatment was performed at 600 ° C. for 1 hour. As a result, as shown in FIG. 56, the amorphous silicon film 87 is changed to single crystal silicon grains 88, and favorable irregularities are formed on the surface.
[0294]
Further, heat treatment is performed at 800 ° C. for 30 minutes. As a result, the natural oxide film 86 disappears, and the polycrystalline silicon film and the single crystal silicon grains 88 are electrically connected.
[0295]
Then, after removing the natural oxide film between the grains with a 1% HF solution, the silicon nitride film 89 having a thickness of 5.5 nm is formed into SiH.₂Cl₂And NH₃(FIG. 57) and further oxidized in an oxygen atmosphere at 800 ° C. to form a silicon oxide film 90 to form a so-called NO film (FIG. 58).
[0296]
Then, a phosphorus-added polycrystalline silicon film is deposited at a substrate temperature of 630 ° C. by a CVD method using silane gas (FIG. 59), and this is patterned to form the upper electrode 91 (FIG. 60), thereby completing the capacitor.
[0297]
As a result, an electrode with a surface area of 0.05 μm and a large unit area can be formed. Since all the steps can be performed at 800 ° C. or lower in this manner, the present invention can also be applied to the case where a MOS element or the like is formed in another region.
[0298]
Here, the distribution density of the silicon grains is about 200 per square μm, and the calculation of the geometric surface area reveals that the density increases by about 50% compared to the case where no silicon grains are present.
[0299]
56. When the substrate in which amorphous silicon has become a granular single crystal in the step of FIG. 56 is taken out into the atmosphere and the surface is observed by SEM, the amorphous silicon film 87 has a single crystal silicon grain as shown in FIG. As shown in FIG. 62, it was confirmed that single crystal silicon grains 88 of completely separated silicon having a grain size of about 60 nm were formed at intervals of about 20 nm. It was. Since the intergranular distance is smaller than the grain size, it was found that the effect of increasing the surface area by single crystal grains can be obtained remarkably.
[0300]
According to this deposition and heating method, silicon grains can be formed with a wide margin of conditions and good reproducibility. In addition, the grain size, grain spacing, and grain distribution density can be controlled by changing the deposited film thickness of the amorphous silicon, the base material, and the heat treatment temperature. In this example, prior to the heat treatment, the amorphous silicon is made to be the same as the average atomic spacing of the single crystal. Or you may make it become 1.02 times or more of the average atomic space | interval of a single crystal.
[0301]
Next, as an example, FIG. 63 shows SEM photographs of grains formed when the base is silicon oxide, the heat treatment temperature is 600 ° C., and the amorphous silicon film thickness is changed to 5, 10, and 20 nm. FIG. 64 shows the relationship between the particle size and the particle distribution density with respect to the film thickness obtained from the SEM photograph. By controlling the film thickness from this result, the particle size and distribution density can be selected, and the deposited film thickness can be very thin, on the order of 10 nm, and grains can be formed without depending on the electrode shape. It can be easily combined with a three-dimensional electrode structure such as a stack structure or a trench structure.
[0302]
In this method, single crystal grains are formed on the natural oxide film 86, and the natural oxide film 86 is broken into islands by heat treatment as shown in enlarged explanatory views in FIGS. 65 (a) and 65 (b). Further, it has been discovered that a sufficient electrical connection can be obtained by diffusing phosphorus into the single crystal grains from the underlying polycrystalline silicon film 85 and utilizing this.
[0303]
FIG. 66 shows a histogram showing the capacitance and the number of capacitors of the conventional example in which the capacitance of the capacitor thus obtained is measured and silicon grains are not formed. From this result, it can be seen that, according to the capacitor of the present invention, the capacitance is increased 1.56 times with good reproducibility compared with the conventional capacitor.
[0304]
In this example, the natural oxide film is destroyed by heat treatment, but instead of this, even if ion implantation is used, the natural oxide film is destroyed and conductivity is imparted by introducing impurities into the silicon grains. Can do.
[0305]
Furthermore, a silicon nitride film, PSG, BPSG or the like other than a natural oxide film is used as a base. Similarly, grains can be formed on the surface, and conduction between the grains and the electrodes can be obtained by heat treatment or ion implantation. Concerning the material of the grains, conductive fine grains are formed in the same manner when an amorphous thin film of not only silicon but also a semiconductor such as germanium or a metal such as aluminum or gold is heat-treated in a non-oxidizing atmosphere. It is possible.
[0306]
Next, a tenth embodiment of the present invention will be described.
[0307]
In the ninth embodiment, an amorphous silicon film is formed on a natural oxide film and silicon grains are formed by heat treatment. However, silicon grains can be formed not only on an insulating film but also on a conductive film such as carbon. I use that. In this example, an amorphous carbon film is formed on the surface including the trench, an amorphous silicon film is formed on the upper layer, and silicon grains are formed by heat treatment, thereby forming the unevenness on the lower electrode of the trench capacitor. To do. In this case, there is a great advantage that it is not necessary to remove the insulating film after forming the silicon grains.
[0308]
First, as shown in FIG. 67, a silicon oxide film 403 is deposited on the surface of an n-type (100) silicon substrate, opened by lithography and RIE, and a trench T is formed by RIE using this as a mask.
[0309]
Then, as shown in FIG. 68, an amorphous carbon film 405 is formed by CVD using acetylene as a source gas, and after evacuation, in the same chamber, as shown in FIG.₄Gas and PH₄A mixed gas of gas is introduced, and a phosphorus-added amorphous silicon film 407 having a film thickness of about 10 nm is deposited by CVD at a substrate temperature of 525 ° C. and a pressure of 1 Torr.
[0310]
After this SiH₄Gas and PH₄The gas mixture was exhausted, non-oxidizing Ar gas was introduced, the temperature was raised, and heat treatment was performed at 600 ° C. for 1 hour. As a result, as shown in FIG. 70, the phosphorus-added amorphous silicon film 407 changes to single-crystal silicon grains 408, and favorable irregularities are formed on the entire surface including the inner wall of the trench. Although the grain size and grain spacing are different from those of the ninth embodiment, good silicon grains are also formed here. Then, as shown in FIG. 71, a silicon oxide film 409 having a thickness of 10 nm is formed as a capacitor insulating film.
[0311]
Then, a phosphorus-added polycrystalline silicon film is deposited at a substrate temperature of 630 ° C. by a CVD method using silane gas, and this is patterned to form the upper electrode 411 (FIG. 72), thereby completing the capacitor.
[0312]
As a result, it is possible to form an electrode with a surface area of 0.05 μm and a large unit area, and the effective capacitor capacity can be greatly increased. Here, in addition to the effects of the ninth embodiment, the silicon grains can be formed in direct contact with the electrode, so that the step of removing the insulating film is not required and the process is simplified.
[0313]
In the above-described embodiment, the lower electrode is made of carbon. However, after forming the polycrystalline silicon film or the like, the surface may be covered with a carbon film to form silicon grains. The film that forms the base of the silicon grains is not limited to a carbon film, and a metal such as W, Ta, Ni, or Ti, a metal silicon compound such as NiSi or TiSi, or TiN may be used as an electrode or an electrode coating agent. However, conductive fine particles can be formed on the surface in the same manner as on carbon.
[0314]
Next, an eleventh embodiment of the present invention will be described.
[0315]
In the examples shown so far, the heat treatment is continuously performed in the non-oxidizing atmosphere after the formation of the amorphous film, but in this example, the oxide film is formed on the surface of the amorphous film. In this case, silicon grains are formed by removing the natural oxide film using hydrofluoric acid and performing heat treatment. This example will be described below.
[0316]
First, as shown in FIG. 73A, a silicon oxide film 502 having a film thickness of 500 nm is formed on the surface of an n-type (100) silicon substrate 501 by thermal oxidation at 1000 ° C. for 15 minutes, and an SiH film is formed thereon.₄A gas is used to deposit an amorphous silicon film 503 having a film thickness of about 10 nm at a substrate temperature of 525 ° C. and a pressure of 1 Torr by CVD, and is taken out into the atmosphere. At this time, a natural oxide film 502s is formed on the surface. In this state, even if heat treatment is performed at 600 ° C. for 1 hour as in the ninth and tenth embodiments, a polycrystalline silicon thin film is formed and fine silicon grains are not formed.
[0317]
Here, the natural oxide film 502s is then removed with a 5% HF solution to expose the surface of the amorphous silicon film 503 as shown in FIG. 73B, and then the surface is kept from being oxidized again at 25 ° C. The substrate is carried into the vacuum container while maintaining the following.
[0318]
And the inside of the container is 1 × 10^-8After exhausting to Torr, the temperature is raised and heat treatment is performed at 600 ° C. for 1 hour. Thereby, single crystal silicon grains 504 are formed as shown in FIG. Thereafter, the substrate was taken out into the atmosphere and observed with an SEM. As a result, silicon particles were confirmed as shown in FIG.
[0319]
Even if an oxide film is once formed on the surface of the amorphous silicon film in this way, if the oxide film is removed and then re-oxidation is prevented to perform heat treatment in a high vacuum or non-oxidizing atmosphere, the oxide film is continuously formed. Even when heat treatment cannot be performed, silicon grains can be obtained. This is a very effective method in an actual capacitor forming process.
[0320]
In addition, although the said Example demonstrated the application to a capacitor, since it is not limited to a capacitor and an uneven | corrugated surface can be easily formed at low temperature, such as when a surface area needs to be increased, it is very effective for device formation. Is the method.
[0321]
Next, an eleventh reference example of the present invention will be described.
[0322]
In this example, as shown in the manufacturing process diagram of FIG. 75, the source and the source are contained in the single crystal silicon thin film 603 grown by solid phase growth using the window W formed in the silicon oxide film 602 covering the surface of the silicon substrate 601 as a seed. Drain regions S and D are formed, and a gate electrode 605 is formed between them with a gate insulating film 604 interposed therebetween.
[0323]
A feature of the present reference example is that a single crystal thin film having excellent crystallinity as compared with the conventional one is used for the channel region of the MOS element, and thereby, a high-speed operation element that has not been obtained conventionally can be produced. The factor that enables high-speed operation is that the crystallinity is greatly improved, and the fact that the channel region is an extremely thin film of several tens of nm is also very effective. When trying to obtain such an ultra-thin film by a conventional method, it is usual to form a thick amorphous silicon layer, perform solid phase growth and recrystallize, and then etch back to the desired thickness. However, it was extremely difficult to obtain a high-precision film thickness by etching. However, with this method, it is only necessary to control the film thickness when forming an amorphous silicon film. Is possible. Here, although it is not touched on the detailed principle, it is thought to be due to relaxation of the vertical electric field. Furthermore, in this device structure, since the substrate and the channel region are in electrical contact with a very good interface state, the device operation is stabilized by passing a current caused by impact ionization that occurs near the drain to the substrate. can do.
[0324]
In manufacturing, first, a silicon oxide film 602 having a thickness of 500 nm is formed on a silicon substrate by a CVD method using silane gas and oxygen as materials. Next, using a resist as a mask, a part of the silicon oxide film is etched to form a window W, and the silicon substrate 601 is exposed. For the etching, any method such as reactive ion etching or wet etching with hydrofluoric acid may be used, but here, reactive ion etching was used.
[0325]
Subsequently, in order to remove the oxide film on the surface of the silicon substrate in the “seed” part, silane gas was introduced into a high vacuum CVD furnace at 600 ° C., 1 × 10^-6After treatment for Torr for 2 hours, the condition in the furnace was continuously changed to 525 ° C. and 1 Torr, and an amorphous silicon film was deposited to 20 nm. Furthermore, after stopping the introduction of the silane gas, a heat treatment was continuously performed at 600 ° C. for 30 minutes. Through the steps so far, 20 nm of single crystal silicon is embedded in the “seed” portion. In this way, the formation of an amorphous silicon film at 525 ° C. and the crystallization at 600 ° C. were repeated continuously, and the filling of the “seed” portion was completed as shown in FIG. The silicon film other than the “seed” portion was removed by etching.
[0326]
At this time, the amorphous silicon film formed at 525 ° C., measured by Raman spectroscopy, has an average atomic spacing of approximately 1.02 times the atomic spacing of the silicon single crystal, and is continuous in a high vacuum furnace. Even when the crystallization was in progress, this value was maintained until just before the crystallization. When the crystallization proceeded in such a state where the bonding of silicon atoms was loosened, a single crystal with extremely good crystallinity was obtained, and no defects were observed even when examined with a transmission electron microscope.
[0327]
As described above, by using the method of the present invention, the selective epitaxial growth can be performed by using the selective epitaxial growth under the film forming conditions of 850 ° C. and 1 Torr for burying the silicon crystal in the “seed” portion of the conventional selective epitaxial method using dichlorosilane gas as a material. Although good, we again embedded the silicon single crystal using the present invention. This method does not require a high-temperature process such as selective epitaxial growth, and does not cause any problems even if elements are already formed in other regions.
[0328]
Next, an active layer of the element was formed using this “seed” portion. First, a sample having the structure shown in FIG. 75 (a) was placed in a high vacuum CVD furnace, and at 600 ° C. and 1 × 10 6 while introducing silane gas.^-6Torr was treated for 2 hours. Next, the condition in the furnace was continuously changed to 525 ° C. and 1 Torr, and an amorphous silicon film was deposited to 50 nm. Further, after the introduction of silane gas was stopped, heat treatment was continuously performed at 600 ° C. for 30 minutes.
[0329]
Again, the amorphous silicon film deposited at 525 ° C. has an average atomic spacing of approximately 1.02 times the atomic spacing of the silicon single crystal, and is continuously crystallized in a high vacuum furnace. This value was maintained even when When the film after crystallization was examined with a transmission electron microscope, no defects were observed.
[0330]
After forming the single crystal silicon thin film 603 in this way, element isolation was performed using chemical dry etching (CDE). In this element region, regions to be a source and a drain were formed by ion implantation as shown in FIG. 75B, and a gate oxide film 604 and a gate electrode 605 were formed.
[0331]
The CDE and ion implantation used for element isolation were processes at about room temperature, and an oxide film such as a gate oxide film was formed at 450 ° C. by a CVD method using silane gas and oxygen. The gate was formed at 350 ° C. by a CVD method using disilane, diborane, or the like as a material.
[0332]
The element characteristics of the MOS transistor thus formed are shown by a curve a in FIG. Here, for comparison, a curve b is a diagram showing element characteristics of a typical MOS transistor of a conventional example using a 200 nm silicon film not in contact with the substrate. A comparison of the two clearly shows that the degree of increase in drain current with respect to increase in drain voltage is greater in the structure of the present invention. The degree of this increase corresponds to the mobility of the element. When the mobility of this element was measured, for example, in NMOS, 700 cm²V / sec. This is a performance that exceeds conventional bulk devices. In addition, in the figure, the MOS transistor of the conventional example shows an irregular change in element characteristics called “kink”, which is caused by the holes generated by impact ionization stopping in the silicon thin film. it is conceivable that. When an element is used as an LSI circuit, such an irregular change in characteristics is extremely inconvenient in design, but an irregularity of such a characteristic is found at all in an element having a structure created by the method of the present invention. There wasn't.
[0333]
Conventionally, in order to obtain a single crystal thin film having excellent crystallinity, a method of once melting silicon, a method of epitaxial growth at a temperature of about 850 ° C., etc. have been proposed. There was also a solid phase growth method for crystal growth at a low temperature, but there was a problem that the crystallinity was poor and it could not be used for devices. Under such circumstances, according to the present invention, the crystallinity of the silicon thin film was greatly improved by the solid phase growth method using the above-described method.
[0334]
The above processes are all processes at 600 ° C. or lower. For example, even when elements are already formed in other regions such as stacking elements, the elements already formed are not affected by thermal effects such as thermal diffusion. New elements can be additionally formed. Moreover, each element characteristic is superior to that formed on a silicon substrate. FIG. 77 is a table showing the results of measuring the characteristics of the MOS elements already formed on the silicon substrate before and after forming the MOS elements on the insulating film using the method of the present invention. Here, threshold values and mobility are shown as typical examples of the characteristics of MOS elements. First, 1000 n-channel and p-channel MOS elements were formed on a silicon substrate, and the characteristics were measured. Next, by performing all the steps of the present invention, after the MOS element was formed on the insulating film, the characteristics of the MOS element already formed on the silicon substrate were measured again. As shown in the table, neither the threshold value nor the mobility was observed for both the n channel and p channel. This table also shows that the present invention is an extremely effective method for integration and miniaturization of elements.
[0335]
Next, as a twelfth reference example of the present invention, an example in which the present invention is used for forming an SOI element will be described below.
[0336]
In short, the characteristics of this reference example are several tens of minutes from the “seed” portion when a single crystal silicon thin film is formed on an insulating film by a solid phase growth method using a “seed” crystal as shown in FIG. A single crystal is grown to a distance of μm, and an SOI element can be manufactured at an arbitrary position. In the prior art, only a maximum of 2 to 3 μm from the “seed” can be formed, which is almost as large as the size of a single SOI device, and there is almost no freedom in layout of the device.
[0337]
Yet another disadvantage of the prior art is that it is disadvantageous for integration. For example, if an SOI device is to be manufactured by a technique capable of forming a 1 μm pattern, first, 1 μm is used to form a “seed” for making a hole in the oxide film.²Area is required. 1 μm each for source, drain and gate²Therefore, if a single crystal extends only by 3 μm, only one SOI element can be manufactured for one “seed”. At this time, the area occupied by the “seed” reaches 1/3 of the area occupied by the element, which is extremely disadvantageous for integration. In extreme cases, 1/4 of the silicon substrate is used as a “seed” and is wasted. Furthermore, even if a technique capable of forming a pattern with 0.5 μm is used, an area of 1/7 is used as a “seed” and is wasted. In the prior art, many defects such as twins were observed even in a region where a single crystal was grown from the “seed”.
[0338]
In this reference example, when the density of the amorphous material is different from that of single crystal silicon, it was discovered that stress is generated in the film when the amorphous material is crystallized, which inhibits crystal growth. By making the density of this close to that of single crystal silicon, thin film single crystal growth of several tens of μm, which was impossible in the past, was made possible. In addition, since the stress is reduced, the occurrence of crystal defects is suppressed, and defects such as twins are not observed over the entire single crystal region of several tens of μm.
[0339]
In this reference example, first, a silicon oxide film 602 having a thickness of 500 nm was formed on a (100) silicon substrate. The silicon oxide film 602 may be formed by a thermal oxidation method. Here, the silicon oxide film 602 is formed by a CVD method under the conditions of a silane gas of 0.2 Torr, an oxygen gas of 0.8 Torr, and a deposition temperature of 450 ° C. Next, using the resist as a mask, an opening was formed in the silicon oxide film 602 by reactive ion etching. A sample in which an opening is formed in the silicon oxide film 602 and the silicon substrate 601 is partially exposed is treated with a 5% hydrofluoric acid solution for 5 minutes, and then the background is 1 × 10.^-6It introduced into the CVD furnace which can be exhausted to the high vacuum below Torr. After the furnace was heated to 480 ° C., disilane gas was introduced at 200 SCCM and 0.04 Torr to deposit an amorphous film to a thickness of 0.2 μm. When the density of this amorphous film was determined by RBS measurement (Rutherford backscattering measurement), it was almost equal to that of single crystal silicon. Here, for example, when amorphous deposition was performed by increasing the pressure of disilane gas to 0.1 Torr, the density was 0.99 times that of a single crystal. In this case, silicon ions are accelerated by an acceleration voltage of 80 keV, 3 × 10.¹⁴atom / cm²When ion implantation was performed, the density of the silicon single crystal was almost equal. We have also found that when depositing an amorphous silicon film, it is possible to easily form an amorphous film with a density close to a single crystal by optimizing the deposition rate and lowering the temperature of the substrate. .
[0340]
When an amorphous film was deposited in this manner and then heat-treated at 580 ° C. for 20 hours, a single crystal thin film having a structure as shown in FIG. 78A could be formed. The crystallinity of this single crystal thin film was examined by cross-sectional TEM observation using a high-resolution transmission electron microscope. I was able to confirm.
[0341]
Next, a MOS device was fabricated using this single crystal thin film. First, the single crystal thin film was separated into islands by a CDE method using a halogen-based gas. Next, a gate oxide film of 40 nm and a gate electrode of 400 nm were deposited by the CVD method. This was patterned into a gate shape by reactive ion etching. Further, boron and boron ions were implanted into the source and drain regions in the case of PMOS and in the case of NMOS, respectively, and an activation heat treatment was performed at 950 ° C. for 30 minutes.
[0342]
As shown in FIG. 78B, twelve such MOS elements are arranged in the <010> direction from the “seed” at intervals of 5 μm. The characteristics of the device fabricated at a position different from the distance from this “seed” were measured.²V / sec, 600cm for NMOS²A mobility comparable to that of an element fabricated on a silicon substrate of V / sec was obtained. In the prior art, such a high mobility device cannot be formed, and there is a device in which normal MOS operation cannot be obtained with a device located 2 to 3 μm away from the “seed”.
[0343]
FIG. 79 is a diagram showing the results of evaluating the number of crystal defects in a silicon thin film (curve a) and a conventional silicon thin film (curve b) formed by this method using etch pits. Etch pits are observed as pit-shaped depressions when the silicon film surface is treated with a hydrofluoric acid mixed solution and observed with an electron microscope. These pits appear when crystal defects are selectively etched quickly with a hydrofluoric acid mixed solution and coincide with the number of defects. In the conventional film, the number of defects is very large.¹⁰Piece / cm²Also reach. According to the method of the present invention, even at a position 35 μm away from the “seed”, 100 pieces / cm.²I was able to hold down to the following.
[0344]
Further, 100,000 n-channel and p-channel MOS elements having the structure shown in FIG. 79 were formed at different distances from the “seed”, and the characteristics were measured. FIG. 80 shows threshold values, mobility, and standard deviation thereof as typical values of this characteristic. As shown in this figure, the mobility of both the p-channel and the n-channel is almost the same as that of the MOS formed on the silicon substrate, and hardly decreases even if it is away from the “seed”. In addition, the variation in threshold value hardly increased, and by using the present invention, the device characteristics could be improved much more than before even at a position away from the “seed”.
Next, a twelfth embodiment of the present invention will be described.
[0345]
In this example, as shown in the process charts of FIGS. 81A to 81K, a p-type silicon region formed on the substrate surface and an n-type granular single crystal silicon formed thereon by the method of the present invention. In this way, a pn junction is formed to obtain a diode with small variation in characteristics.
[0346]
First, as shown in FIG. 81A, N-type Si (100) is prepared as a silicon substrate 701. The impurity concentration of the silicon substrate 701 is not particularly limited.¹⁵/ Cm³I chose the degree. This silicon substrate 701 is subjected to selective thermal oxidation at 1100 ° C. to form an element isolation region 702 having a thickness of about 350 nm.
[0347]
Next, as shown in FIG. 81B, a thin silicon oxide film 703 having a film thickness of 35 nm was formed in a dry oxidation atmosphere.
[0348]
Thereafter, as shown in FIG. 81 (c), for example, boron impurities are implanted and buried by ion implantation.⁺An electrode region 704 was formed. At this time, for example, a buried epitaxial method may be used as another method. However, in the case of the epitaxial method, it is necessary to slightly change the procedure. This region 704 becomes a part of the extraction diffusion layer of the electrode of the diode formed in the subsequent process.
[0349]
Next, an opening 705 is formed in the silicon oxide film 703 using photolithography as shown in FIG. Thereafter, a mask is formed and ion implantation is performed again using photolithography, and a high concentration p for extraction is formed in one part of the opening 705 as shown in FIG.⁺An impurity layer 706 was formed. In the other part of the other opening, p becomes the other electrode part of the diode as shown in FIG.⁻Region 707 was formed.
[0350]
Next, as shown in FIG. 81 (g), an ultrathin oxide film 708, which is a part of the basis of the constituent elements of the present invention, is formed. As this ultrathin oxide film, for example, a natural oxide film may be used.
[0351]
Next, as shown in FIG. 81 (h), an amorphous silicon film 709, which is also a part of the basis of the present invention, was deposited. Here, the deposition temperature is, for example, 525 ° C., and the deposition gas is, for example, SiH.₄Met. The amorphous film thickness, which is the most important requirement, was 19.8 nm, for example. At this time, the inventors have used PH as a doping gas.₃The deposited film has a high concentration n⁺Impurities were included. This amorphous silicon film 709 is patterned, and is left here as shown in FIG. After that, since it is considered that an oxide film or the like is deposited on the film 709, it was sufficiently removed and inserted into a recrystallization furnace. For example, the temperature was 600 ° C.
[0352]
As shown in FIG. 81 (j), when heat treatment is performed at 600 ° C., the amorphous silicon film 709 is recrystallized to become single crystal silicon 710. This is a feature of the present invention. Moreover, the orientation is the same as that of the substrate, and annealing may be performed separately at this time. However, as shown in FIG. 81 (k), a part of the oxide film contracts and is broken by the heat treatment for recrystallization. The upper and lower crystallinity becomes continuous. This is the gist of the single crystal diode according to the present invention. Then, electrodes 711 and 712 are formed to complete the diode.
[0353]
As described above, why the underlying ultra-thin oxide film partially peeled during single crystal grain growth and was bonded crystallized up and down, and at such a low temperature, why the top and bottom crystals were aligned to the orientation, Since the present inventors have eagerly pursued whether a good crystal was obtained, it will be briefly described here.
[0354]
The inventor has developed a new molecular dynamics simulation system as already introduced. Using this, we approached the essence of the above process phenomenon. Improved the potential expression part and interface creation part between atoms in the molecular dynamics simulator, Si / SiO₂It was made possible to calculate the motion of Si and O atoms including the interface. A part of calculation work is described. Si / SiO₂The initial conditions for creating the interface are as follows. That is, two conventions are provided: (i) no dangling bond is left as an initial condition; (ii) the initial bond length d and the initial bond angle θ are dSi-Si = 2.35 angstroms and dSi-O = 1, respectively. .60 angstrom, θSi = 109.47 °, and θO = 144.0 °. Thereafter, a speed according to Maxwellian is randomly assigned to each of Si and O atoms. Thereafter, all particles were moved according to the equation of motion so as to minimize the energy throughout the system including the interface. Therefore, when the calculation is sufficiently advanced, structural relaxation will occur, and the bond length and bond angle distribution should be obtained. A large amount of output (data such as momentary position, force and velocity and stress near the interface for each atom) was analyzed.
[0355]
The results are as follows. First, recrystallization of the amorphous silicon film 709 grows from the vicinity of the upper surface of the film and proceeds toward the lower-layer thin film oxide film 708. At this time, there is no consistency with the crystal orientation of the substrate 701. It was found that tensile stress accumulates near the growth edge as the growth of the silicon single crystal grows. On the other hand, the compressive stress resulting from the interatomic structure of the substrate 701 and the ultrathin oxide film 708 has also accumulated in the lower thin oxide film 708 from the beginning. Therefore, it was found that a large compressive stress is accumulated in the oxide film 708, and the oxide film 708 is partially broken when the accumulated amount reaches a certain value. Furthermore, it was also found that at this moment, the recrystallized grains 710 exert a force in the direction of decreasing the amount of energy due to the difference in crystal orientation with the silicon substrate 701. Thereafter, it was also found that the recrystallized grains 710 had the same axis as the base substrate 701 almost completely.
[0356]
Thereafter, the characteristics of the single crystal fine diode according to the present invention were evaluated. The result is shown in FIG. In the figure, q is the elementary charge, V is the voltage, and k is the Boltzmann constant. T represents an absolute temperature. First, as can be seen from the figure, good rectification characteristics are observed. Furthermore, although it is in the reverse direction, when viewed from the value of q | V | / kT, the withstand voltage is hardly detected in the measurement range and shows a behavior close to ideal. As described above, the reason why the rectifying characteristics and withstand voltage close to ideal are obtained is not well understood, but there are the following two points as possible items. One is that the crystallinity is good, and the other is that there is no redistribution of impurities and a completely steep type is obtained.
[0357]
For comparison, the present inventors made a pn junction using a conventional technique. The following is a brief report of the preparation procedure and characteristic results.
[0358]
As a conventional example, for example, FIG. 81 (g) may be the same as long as FIG. Thereafter, an amorphous silicon film is deposited in FIG. 81 (h), but here, a polycrystalline silicon deposited film is used. This temperature was, for example, 625 ° C. This temperature, which I want to specify here, is very high. Such temperature treatment is very disadvantageous if there is an element on the ground.
[0359]
After that, ion implantation for mixing was performed aiming at the interface between the substrate and polycrystalline Si, as is often done conventionally. Thereafter, for example, heat treatment was performed at 970 ° C., electrodes were formed, and bonding characteristics were measured. The result is shown in FIG. It can be seen that the withstand voltage is clearly reduced. In this way, examining the cause of the decrease in breakdown voltage, one thing is that the junction region is not completely single crystal, and there are still many that are presumed to be defects during mixing. Yes. Further, the impurity distribution was observed by SIMS, but the steepness was lowered. It is considered that these characteristics deteriorated.
[0360]
Next, a thirteenth embodiment of the present invention is described.
[0361]
In this example, as shown in FIG. 84, polycrystalline silicon having a uniform crystal grain size and extremely good crystallinity inside a grain is formed using granular single crystal silicon formed by solid phase growth. An embodiment in which a thin film transistor having stable element characteristics and no mobility variation is formed will be described.
[0362]
First, after depositing an insulating film on a silicon substrate 901, in obtaining single crystal silicon, a film in which the average atomic spacing of amorphous silicon is made to coincide with the silicon single crystal in advance is used. In order to suppress the growth and adhesion of oxide film on the surface, H in a reducing atmosphere₂The atmosphere was heat treated. The film forming apparatus used was the same as that shown in FIG.
[0363]
First, as shown in FIG. 84A, a silicon oxide film 902 is deposited on a silicon substrate 901 by 500 nm, and then an amorphous silicon film 903 is deposited. This film thickness was 75 nm. Then, as reported at the beginning of this example, in the measurement results immediately after the deposition, the average atomic spacing obtained was 1.005 times that of the single crystal substrate. Thereafter, using the same apparatus as the deposition apparatus, heat treatment was performed at 580 ° C. for 5 hours while suppressing adhesion of the surface natural oxide film to form single crystal silicon. As a result, as shown in FIG. 84B, the amorphous silicon film was crystallized to form granular silicon single crystal grains.
[0364]
Through detailed observation using a TEM photograph, it was observed that the single crystal grains had the <100> axis oriented in the vertical direction, and the size and grain spacing were almost uniform. For example, when the particle size distribution is examined by an SEM photograph capturing the particles from directly above the substrate, as shown in FIG. 85 (a), the particle size is within ± 20%, centering on the maximum appearance frequency of 1500 angstroms. More than 90% of the grains were included. In particular, almost no grains larger than 10% of the maximum appearance frequency were observed. This phenomenon is probably due to the fact that most crystal nuclei are generated simultaneously at a relatively fast time from the start of the heat treatment. In addition, when the distance between the centers of adjacent grains was measured and the grain spacing was examined, as shown in FIG. 85 (b), 90% within ± 10% centered on the grain spacing of 1900 angstroms with the maximum appearance frequency. The above grains were included. In this way, the single crystal grains were uniform in size and interval, and the grains were separated from each other.
[0365]
On this grain, 2000 angstroms of second amorphous silicon 903 was deposited as shown in FIG. The average atomic spacing of this amorphous silicon was 1.005.
[0366]
Thereafter, heat treatment is performed at 580 ° C. for 30 minutes, and as shown in FIG. 84D, the second amorphous silicon is solid-phase grown using the granular single crystal silicon 904 as a crystal seed, and the polycrystalline silicon 905 is It is formed. When the grains of the polycrystalline silicon were examined from the TEM photograph, it was a columnar shape having a width of about 1900 angstroms, and each columnar grain was oriented in the <100> direction in the vertical direction. In addition, as shown in FIG. 86 (a), the crystallinity in the grains of the polycrystalline silicon was better than that of a solid phase growth film formed by normal arbitrary nucleation. The cause of this is not clear, but it is probably because the crystallinity of the single crystal grains used as crystal seeds is very good.
[0367]
For comparison, the crystallinity of the large grain size of the polycrystalline film formed by the normal amorphous film solid phase growth is shown in FIG. 86 (b) as a TEM photograph. There are many defects such as twins inside the grain. Moreover, these defects do not disappear easily unless heat treatment is performed at a high temperature of 1200 ° C. or higher.
[0368]
After the polycrystalline silicon film having the same grain size is formed in this way, the surface of the polycrystalline silicon film is etched and flattened and patterned to obtain a flat surface as shown in FIG. A polycrystalline silicon film 905 was formed into an island shape by RIE or the like. Next, B + channel ion implantation is performed at a dose amount of 1 × 10.¹³atoms / cm^-2FIG. 84 (f) was performed under the condition of 40 keV. Thereafter, the surface of the polycrystalline silicon film 905 was thermally oxidized to form a gate insulating film 906. Since the surface of an ordinary polycrystalline film is composed of grains having various plane orientations, forming a gate insulating film by thermal oxidation has different oxidation rates in each plane orientation, so the oxide film thickness is 10%. It varies to some extent. In this manner, when a transistor is formed with the oxide film thickness variation remaining, the threshold voltage greatly varies. However, when formed by this method, the surface of the polycrystal is almost (100) plane, and as a result of measurement by a TEM photograph, it was suppressed with a variation of about 3%.
[0369]
Next, as shown in FIG. 84 (g), after forming the gate electrode 907, an insulating film is deposited on the side wall of the gate, and As is formed for forming the source / drain conductive layer.⁺2x10 ion implantation¹⁹atoms / cm^-3, 40 keV. Then, after depositing an interlayer insulating film 908 and providing an opening for electrode formation, source / drain electrodes 909 and 910 were formed.
[0370]
When the electrical characteristics of the thin film transistor thus formed were measured, the size of the grain was as large as 1900 angstroms, and there was no grain below 1500 angstroms. Even after coming, the device characteristics were stable. For example, when examining the variation in mobility at room temperature, as shown in FIG. 87, the variation in mobility was significantly reduced as compared with the case of using a conventional solid phase growth film.
[0371]
As shown in FIG. 88, the Vg-electron mobility characteristics when a conventional film is used are greatly different depending on whether or not the grain boundary happens to exist in the channel region. FIG. 89 shows the result of measuring the temperature dependence of the electron mobility in this case. In the conventional film, when the grain boundary exists in the channel region, the mobility greatly decreases as the temperature decreases, and the difference in mobility becomes more remarkable as compared with the case where the grain boundary exists. In contrast, as shown in FIG. 88, the film of this example has stable element characteristics because the grain boundaries are evenly present in the channel region. Also, the temperature dependence was settled in the region shown in FIG.
[0372]
In the above embodiment, the average atomic spacing of the amorphous silicon during the heat treatment was set to be about the same as that of the silicon single crystal, and a single crystal silicon film without distortion was obtained. However, it should be 1.02 or more. May be.
[0373]
In the above embodiment, the first amorphous silicon film deposited on the entire surface is heat-treated to form single crystal grains. However, the first amorphous silicon film may be formed by RIE after deposition. good. Next, this example will be described as a fourteenth embodiment of the present invention.
[0374]
First, after depositing the above-mentioned amorphous silicon film, it is once removed from the deposition apparatus and shaped into a 0.2 μm width line as shown in FIG. 90 (a), and then the natural oxide film on the surface is peeled off. The surface was made clean and carried again into the deposition apparatus. At this time, the average atomic spacing was measured and found to be 1.02. In this state, it was exposed to 550 ° C. for 2 hours in a hydrogen atmosphere and carried out of the apparatus. When the arrangement of the single crystal grains was examined with the SEM photograph, the single crystal grains were arranged in a line as shown in FIG. 90 (b). A second amorphous silicon film 903 is deposited here and shaped as shown in FIG. When the second amorphous silicon film 903 is solid-phase grown using the single crystal silicon grains 904 formed from the first amorphous silicon film 903 as crystal nuclei, the second amorphous silicon film is shown in FIG. As shown in Fig. 4, the polycrystalline film has a so-called bamboo structure in which the grain boundaries run in the vertical direction. Here, as shown in FIG. 90 (e), a transistor was formed in which a channel was formed in parallel to the grain boundary. The grain size of the polycrystalline film was approximately 2000 angstroms. With this structure, the variation in mobility was further improved, and it was possible to control within a very narrow range as shown in FIG.
[0375]
Next, a fifteenth embodiment of the present invention will be shown.
[0376]
Similarly to the fourteenth embodiment, in this example, in obtaining single crystal silicon, a film having an average atomic interval of amorphous silicon of 1.02 times or more that of silicon single crystal is used, and heat treatment is performed to obtain a solid phase. This is an example in which granular single crystal silicon having extremely good crystallinity formed by growth is used to form polycrystalline silicon having a uniform crystal grain size to form a thin film transistor with high mobility and small variation. Here, an element region made of polycrystalline silicon 905 is formed in an upper layer of the gate electrode 907.
[0377]
As shown in FIG. 92A, after depositing an insulating film 902 on a silicon substrate 901, a gate electrode 907 made of a polycrystalline silicon film was formed. Next, a gate insulating film 906 was deposited by a CVD method.
[0378]
Next, as shown in FIG. 92B, an amorphous silicon film 903 is deposited on the gate insulating film 906 so that the average atomic spacing is 1.02 times or more that of single crystal silicon. The deposited film thickness was 40 nm and the average atomic spacing was measured and found to be 1.02 times that of the single crystal. When this substrate was placed in the apparatus shown in FIG. 2 and heat-treated in a non-oxidizing atmosphere at 550 ° C. for 2 hours, granular single crystal silicon was obtained as shown in FIG. 92 (c). Through detailed observation using a TEM photograph, it was observed that this single crystal grain also had the <100> axis oriented in the vertical direction, and the size and grain spacing were almost uniform. As shown in FIG. 93, when the particle size distribution is examined, 90% or more of grains are contained within ± 20% centering on the maximum appearance frequency of 900 angstroms. As shown in FIG. 94, when the grain spacing is examined, 90% or more grains are included within ± 20%, centering on the maximum appearing grain spacing of 1200 angstroms.
[0379]
Next, a second amorphous silicon film 903 was deposited in a thickness of 1200 Å in the same apparatus as shown in FIG. The average atomic spacing of this amorphous film was 1.009 times that of the single crystal. When heat treatment was performed at 600 ° C. for 15 minutes in the deposition apparatus, as shown in FIG. 92E, the second amorphous silicon film 903 was single-crystallized by solid-phase growth using single-crystal silicon grains as crystal seeds. Crystalline silicon was formed. When this polycrystalline silicon was also measured using a TEM photograph, it was a polycrystalline thin film in which the grain sizes were uniform and the <100> axis was preferentially oriented in the vertical direction as in Example 14. After the polycrystalline silicon film having the same grain size was formed, the polycrystalline silicon film was formed into an island shape by RIE or the like as shown in FIG. Next, a dose of 1 × 10¹³atoms / cm²P ions were channel-implanted at 40 keV. Then, heat treatment for activation was performed at 900 ° C. for 30 minutes.
[0380]
Next, in order to form a conductive layer of source / drain, B⁺Ion implantation 3 × 10¹⁵atoms / cm², 20 keV. After depositing an interlayer insulating film 908 and providing openings for forming electrodes, source / drain electrodes 909 and 910 were formed.
[0381]
Thus, in the thin film transistor using single crystal silicon formed by the method of claim 1, the channel region on the base side is also composed of grains having a uniform grain size of about 1200 angstroms. When polycrystalline silicon having a low conductive impurity concentration is deposited by a normal CVD method, the particle size is only about 300 angstroms. For this reason, the carrier mobility becomes very small due to scattering at the grain boundary. In addition, even in polycrystalline silicon formed by solid phase growth of a normal amorphous film, there are many fine grains of gravel at the interface with the base, causing a decrease in mobility. However, in the polycrystalline film formed by this method, there is no fine grain at the base interface which is the channel region, and the crystallinity is remarkably improved. The mobility is also greatly improved. Further, when the oxygen concentration in the film affecting the mobility was measured by SIMS analysis, as shown in FIG. 95, the oxygen concentration was extremely low in the vicinity of the base interface influenced by the film quality of the first amorphous film. As a result, scattering by oxygen atoms was reduced, and a device with high mobility could be produced.
[0382]
Next, a thirteenth reference example of the present invention will be shown.
[0383]
In this example, as shown in FIGS. 96 to 104, a source / drain lifted MOS, that is, an elevated source / drain MOS element, which is formed by using single crystal silicon having extremely good crystallinity formed by solid phase growth will be described. Since a MOS element formed by this method can form a layer containing almost no impurities in the channel region immediately below the gate oxide film, a high mobility transistor can be obtained without impeding carrier travel by impurities. It has the feature of being able to. In addition, the higher the impurity concentration just below the gate oxide film, the stronger the electric field in the vertical direction when forming the inversion layer, and the more strongly the carriers travel on the silicon oxide / silicon interface, resulting in slight irregularities at the interface. However, according to the MOS device of the present invention, there is no such problem.
[0384]
First, as shown in FIG. 96, a field oxide film 802 is formed on the surface of the silicon substrate 801 by selective oxidation. Then, ion implantation for adjusting the threshold voltage is performed as necessary.
[0385]
Then, as shown in FIG. 97, after cleaning the surface of the element region, a non-doped amorphous silicon film 803 having a thickness of 20 nm is deposited. In the measurement results immediately after deposition, the average atomic spacing was 1.03 times that of single crystal silicon.
[0386]
Thereafter, as shown in FIG. 98, in the same apparatus as the deposition apparatus, a heat treatment was performed at 550 ° C. for 1 hour while suppressing the adhesion of the surface natural oxide film to form single crystal silicon 804. At this time, the single crystal 804 is formed on the silicon substrate, but the polycrystalline silicon film 804S is formed on the field oxide film 802.
[0387]
Then, the element region is patterned as shown in FIG. 99 to form a gate oxide film 805 as shown in FIG.
[0388]
Further, as shown in FIG. 101, a polycrystalline silicon film 806 is deposited on this upper layer, and these are patterned as shown in FIG. 102 to form a gate electrode 806.
[0389]
Then, as shown in FIG. 103, ion implantation is performed using the gate electrode 806 as a mask to form source / drains S and D, and further, an interlayer insulating film 807 is formed, and then a source electrode 808, a drain electrode 809, A gate electrode 810 is formed, and the MOS device is completed as shown in FIG.
[0390]
As a result of measuring the relationship between the gate voltage and mobility of the MOS element formed as described above, the characteristic of extremely high mobility can be obtained as shown by a curve a in FIG. For comparison, the measurement result of the conventional example is shown in a curve b. In the conventional method, since single crystal silicon is formed by epitaxial growth at a high temperature, it is inevitable that impurities are doped in the channel region immediately below the gate oxide film by autodoping from the substrate. Since a single crystal silicon film having good crystallinity can be formed at a low temperature, there is no auto-doping from the substrate, and a layer containing almost no impurities can be formed in the channel region immediately below the gate oxide film. In this manner, since a single crystal layer having no impurities which becomes a scatterer for carrier travel can be formed, high mobility can be obtained. Further, the higher the impurity concentration just below the gate oxide film, the higher the electric field in the vertical direction when forming the inversion layer. When the vertical electric field is high, the carriers are more strongly attached to the silicon oxide / silicon interface, and the slight unevenness at the interface also becomes a carrier scatterer, which causes a decrease in mobility. In the formed element structure, the impurity concentration under the gate oxide film can be lowered, so that the mobility can be prevented from being lowered. FIG. 106 shows the result of measuring the relationship between the delay time of the ring oscillator formed using this method and Vdd. This result also shows that high speed operation is possible. In the element of the present invention, in addition to the above effect, the source / drain region is formed on the field oxide film, so that it is possible to prevent the depletion layer from spreading on the substrate side according to the applied voltage. This is because there is no problem of delay.
[0390]
As described above, the ring oscillator formed by using the method of the present invention can greatly increase the speed by the effects of both the improvement of the mobility and the reduction of the source / drain capacitance.
[0392]
Next, a fourteenth reference example of the present invention is shown.
[0393]
In this example as well, a source / drain lifted MOS, that is, an elevated source / drain MOS element, formed using single crystal silicon having extremely good crystallinity formed by solid phase growth will be described. In this method, as shown in FIGS. 107 to 115, a gate electrode is formed in an element region separated by a trench, and only a source / drain region is formed on the upper layer by the solid phase growth of the present invention. It is formed on the surface. This element is characterized in that since the source and drain can be formed at a low temperature, the impurity distribution can be made steep and punch-through is suppressed.
[0394]
In this method as well, as in the thirteenth reference example, a layer containing almost no impurities can be formed in the channel region immediately below the gate oxide film. The transistor can be obtained. In addition, the higher the impurity concentration just below the gate oxide film, the stronger the electric field in the vertical direction when forming the inversion layer, and the more strongly the carriers travel on the silicon oxide / silicon interface, resulting in slight irregularities at the interface. However, according to the MOS device of the present invention, there is no such problem.
[0395]
First, a trench 812 is formed on the surface of a silicon substrate 811 as shown in FIG. 107 by an SOI method, and an insulating film 813 is embedded and element isolation is performed as shown in FIG. 108, and ion implantation for adjusting a threshold voltage is performed as necessary. I do.
[0396]
109, a gate oxide film 814 is formed. Further, as shown in FIG. 110, a polycrystalline silicon film is deposited thereon and patterned to form a gate electrode 815 as shown in FIG. .
[0397]
As shown in FIG. 112, a silicon oxide film 816 is formed on the upper layer of the gate electrode 815 by the CVD method and is left only on the side wall of the gate electrode 815 by the RIE method. Phosphorus ions are implanted to form n on the substrate surface.⁻A layer (not shown) is formed. Then, after further cleaning the substrate surface, a non-doped amorphous silicon film 817 having a thickness of 20 nm is deposited. In the measurement results immediately after deposition, the average atomic spacing was 1.03 times that of single crystal silicon.
[0398]
Thereafter, as shown in FIG. 113, a single crystal silicon 817S was formed by performing heat treatment at 550 ° C. for 1 hour while suppressing the adhesion of the surface natural oxide film in the same apparatus as the deposition apparatus. At this time, a single crystal 817S is formed on the silicon substrate, but a polycrystalline silicon film is formed on the insulating film, and selective etching is performed under etching conditions having selectivity between single crystal silicon and polycrystalline silicon. Is removed by etching to leave only single crystal silicon 817S.
[0399]
Then, a silicon oxide film 818 as a passivation film is formed as shown in FIG. 114, and source / drain electrodes 821 and a gate electrode 822 are formed through the contact holes. As shown in FIG. Complete.
[0400]
The result of measuring the relationship between the gate voltage and the drain current of the MOS transistor thus formed is shown in FIG. For comparison, the measurement result of the conventional example is shown in a curve b. In the transistor shown here, the channel length was 0.23 μm. It can be seen that even though the device is very fine, the sub-threshold region can also have good characteristics. Although it is not clear why the punch-through is sufficiently good in spite of such a fine element, it is considered that the impurity distribution of the source and drain is steep. This is because the process is performed at a particularly low temperature.
[0401]
FIG. 117 shows the relationship between the threshold voltage and the channel length with a curve a. From this result, it can be seen that according to the present invention, the threshold voltage does not decrease even when the channel length is about 0.22 μm. This is also because there is no redistribution of impurities. For comparison, the characteristics of a transistor formed by the conventional method are shown in a curve b. In this transistor, the short channel effect has already appeared with a channel length of about 0.5 μm.
[0402]
Next, a fifteenth reference example of the present invention will be shown.
[0403]
In this example, an example in which a bipolar transistor and a MOS transistor are integrated using the solid phase growth method of the present invention will be described.
[0404]
When MOS transistors and bipolar transistors are compared, MOS transistors have the advantage that they can be integrated on a large scale, but have the disadvantage of slow operation. On the other hand, the bipolar transistor has an advantage that a large current can be obtained in the output and high speed operation is possible, but there is a disadvantage that the device area is large and the integration is disadvantageous. A large-scale integrated circuit that uses the advantages of both of these two types of transistors at the same time is known.
[0405]
In such an integrated circuit, as shown in FIG. 133, an MOS transistor and a bipolar transistor are horizontally arranged on a silicon substrate, and a base of the bipolar transistor and a drain of the MOS transistor are electrically connected to each other, and a drain current is obtained. Can be amplified in a bipolar manner to obtain a large current. However, since the drain and the base are separated from each other, the wiring must be routed, and it requires a large area and must be formed without affecting each element region. There was a problem of requiring a long process.
[0406]
In this example, in order to solve such a problem, a bipolar transistor is formed in single crystal silicon formed by the solid phase growth method of the present invention on the upper layer so that the base is directly connected to the drain of the MOS transistor. .
[0407]
118 to 131 show the manufacturing process, and FIG. 132 shows an equivalent circuit diagram.
[0408]
First, as shown in FIG. 118, a field oxide film 912 is formed on the surface of the silicon substrate 911 by selective oxidation. Then, ion implantation for adjusting the threshold voltage is performed as necessary.
[0409]
Then, as shown in FIG. 119, thermal oxidation is performed to form a 10 nm-thickness silicon oxide film to be the gate insulating film 913, and further, a phosphorus-doped polycrystalline silicon film to be the gate electrode 914 is formed as shown in FIG. These are patterned as shown in FIG.
[0410]
Thereafter, as shown in FIG. 122, a silicon oxide film is formed by the CVD method, and then a silicon oxide film 915 is formed on the side wall of the gate electrode 914 by using the RIE method.¹⁵atoms / cm²Ions are implanted and heat treatment is performed in a nitrogen atmosphere at 900 ° C. for 30 minutes to form source / drain regions 916 as shown in FIG.
[0411]
Then, a 300 nm-thickness silicon oxide film is deposited on the entire surface by CVD as shown in FIG. 124, and a contact hole 918 is formed in the drain region 916 as shown in FIG.
[0412]
Then, as shown in FIG. 126, an amorphous silicon film 919 is deposited to a thickness of about 50 nm so that the average atomic spacing is almost equal to that of single crystal silicon. At this time, phosphine gas PH simultaneously with silane gas₃To obtain an amorphous silicon film containing a small amount of phosphorus in advance.
[0413]
Thereafter, as shown in FIG. 127, in the same apparatus as the deposition apparatus, heat treatment is performed at 600 ° C. for 3 hours while suppressing adhesion of the surface natural oxide film, and n⁻Single crystal silicon 920 was formed. When a monitor device prepared in advance for measuring the single crystallization distance was examined, the crystallization distance was 15 μm. Moreover, when the phosphorus concentration is measured, 8 × 10¹⁷atoms / cm³Met.
[0414]
Then, the element region is patterned as shown in FIG. 128, and boron ions are implanted into a part of the single crystal silicon 920 as shown in FIG.⁻Region 921 was formed.
[0415]
Next, boron is ion-implanted into the emitter / collector region as shown in FIG.⁺A region 922 is formed, and annealing at 850 ° C. for 5 minutes is performed by RTA for impurity activation, and a source electrode 923, a gate electrode 924, an emitter electrode 925, and a collector electrode 926 are formed as shown in FIG. Complete.
[0416]
In this way, it is possible to obtain single crystal silicon having a good crystallinity at a low temperature of 600 ° C. while having a laminated structure, and the interface characteristics with the lower layer are extremely good, and the contact resistance at the connection portion between the drain and the base Is extremely low and the diffusion length of the MOS transistor is not increased.
[0417]
According to this integrated circuit, not only can the element area be greatly reduced because of the laminated structure, but also because the bipolar transistor is formed above the MOS transistor, the bipolar circuit is formed in comparison with the conventional structure shown in FIG. Heat generated in the region is not easily transmitted to the MOS transistor, and does not affect the operating characteristics of the MOS transistor. Further, since the bipolar transistor itself is located in the upper layer, the heat dissipation is good and the temperature rise can be suppressed.
[0418]
【The invention's effect】
In the present invention, since the lower electrode of the capacitor is composed of a granular conductive layer, the capacitor area can be increased by the unevenness of the surface.
[0419]
In addition, a capacitor having a large capacity can be formed very easily by applying heat treatment to shrink the insulating film and electrically connecting the granular second conductive layer to the first conductive layer.
[Brief description of the drawings]
FIG. 1 is an explanatory view showing the principle of forming a semiconductor thin film of the present invention.
FIG. 2 is a view showing a thin film forming apparatus used in the first reference example of the present invention.
FIG. 3 is a diagram showing an outline of a film deposition sequence according to a first reference example of the present invention.
FIG. 4 is a diagram showing a thin film forming process according to a first reference example of the present invention.
FIG. 5 is a graph showing the relationship between the deposition rate and the substrate temperature for obtaining an amorphous silicon film having an average interatomic distance of 1.02 or more in the first reference example of the present invention.
FIG. 6 is a graph showing the result of measuring the relationship between the depth from the surface and the average interatomic distance in the first reference example of the present invention.
FIG. 7 is a comparative diagram showing measurement results of lateral solid-phase growth rate in the method of the first reference example of the present invention and the method of the conventional example.
FIG. 8 is a process chart showing a thin film forming method of a second reference example of the present invention.
FIG. 9 is a graph showing the relationship between the thickness of an amorphous silicon film and the defect density of a single crystal silicon thin film in the second reference example and the conventional example of the present invention.
FIG. 10 is a diagram showing the relationship between the thickness of an amorphous silicon film and electron mobility in the second reference example and the conventional example of the present invention.
FIG. 11 is a diagram showing the relationship between the degree of vacuum during annealing and electron mobility in the second reference example of the present invention.
FIG. 12 is a graph showing the relationship between the hydrogen flow rate during annealing and electron mobility in the second reference example of the present invention.
FIG. 13 is a graph showing the relationship between the depth from the surface and the arsenic concentration in the sixth reference example of the present invention.
FIG. 14 is a manufacturing process diagram of a semiconductor thin film according to a seventh reference example of the invention.
FIG. 15 is a view showing a modification of the manufacturing process of a semiconductor device using the semiconductor thin film.
FIG. 16 is a manufacturing process diagram of a semiconductor thin film according to an eighth reference example of the present invention;
FIG. 17 is a view showing a semiconductor thin film formed in the first embodiment of the present invention.
FIG. 18 is a manufacturing process diagram of a semiconductor thin film according to the first embodiment of the present invention.
FIG. 19 is a photograph showing a single crystal thin film obtained in the semiconductor thin film manufacturing process of the first example of the present invention.
FIG. 20 is a photograph showing a single crystal thin film obtained in the semiconductor thin film manufacturing process of the first example of the present invention.
FIG. 21 is a photograph showing a single crystal thin film obtained in the semiconductor thin film manufacturing process of the first example of the present invention.
FIG. 22 is a manufacturing process diagram of a semiconductor thin film according to a second embodiment of the present invention.
FIG. 23 is a manufacturing process diagram of a semiconductor thin film according to a third embodiment of the present invention.
FIG. 24 is a photograph showing a single crystal thin film obtained in the semiconductor thin film manufacturing process of the third embodiment of the present invention.
FIG. 25 is a photograph showing a single crystal thin film obtained in the semiconductor thin film manufacturing process of the third embodiment of the present invention.
FIG. 26 is a photograph showing a single crystal thin film obtained in the semiconductor thin film manufacturing process of the third embodiment of the present invention.
FIG. 27 is a graph showing the relationship between the thickness of an amorphous film and the diameter of a single crystal grain obtained
FIG. 28 is a diagram showing the relationship between the thickness of an amorphous film and the diameter of a single crystal grain obtained when the base insulating film is different
FIG. 29 is a diagram showing a process for forming a semiconductor thin film according to a fourth embodiment of the present invention.
FIG. 30 is a diagram showing manufacturing steps of the capacitor according to the fifth embodiment of the present invention.
FIG. 31 is an explanatory view showing the principle of forming a semiconductor thin film according to a ninth reference example of the present invention.
FIG. 32 is a view showing a thin film forming apparatus used in a ninth reference example of the present invention.
FIG. 33 shows the relationship between the deposition rate and the substrate temperature for obtaining an amorphous silicon film having an average interatomic distance of 0.98 to 1.02 of single crystal in the ninth reference example of the present invention. Figure
FIG. 34 is a view showing a heat treatment apparatus used in a ninth reference example of the present invention.
FIG. 35 is a diagram showing the time dependence of the growth distance in the present invention.
FIG. 36 is a view showing a cross-sectional TEM photograph in a ninth reference example of the present invention (heat treatment 5 minutes)
FIG. 37 is a diagram showing a cross-sectional TEM photograph of an electron diffraction image in a ninth reference example of the present invention (heat treatment: 2 hours)
FIG. 38 is a view showing a Raman measuring apparatus used in a ninth reference example of the present invention.
FIG. 39 is a graph showing a Raman peak measured with the same apparatus.
FIG. 40 is a diagram showing the stress distribution in the ninth reference example of the present invention.
FIG. 41 is a diagram showing a silicon thin film forming process according to a tenth reference example of the present invention.
FIG. 42 is a diagram showing the stress distribution in the tenth reference example of the present invention.
FIG. 43 is a view showing an SEM image of the silicon thin film formed in the tenth reference example of the present invention.
FIG. 44 shows a sample structure used in the sixth embodiment of the present invention.
FIG. 45 is a view showing an SEM image of silicon grains formed in the sixth example of the present invention.
FIG. 46 shows a TEM image of the silicon grains.
FIG. 47 is a diagram showing an electron diffraction image of the same silicon grain.
FIG. 48 is a comparative view showing a TEM image of silicon grains formed by a conventional method.
FIG. 49 is a diagram showing the correlation between the average atomic spacing of an amorphous film and the crystallinity of a single crystal grain
FIG. 50 is a manufacturing process diagram of a semiconductor thin film according to a seventh embodiment of the present invention.
FIG. 51 is a comparative diagram showing the formation of conventional silicon grains.
FIG. 52 is a view showing a single crystal thin film obtained in the semiconductor thin film manufacturing process of the present invention.
FIG. 53 is a manufacturing process diagram of a semiconductor thin film according to an eighth embodiment of the present invention.
FIG. 54 is a manufacturing process diagram of the capacitor according to the ninth embodiment of the present invention.
FIG. 55 is a manufacturing process diagram of a capacitor according to a ninth embodiment of the present invention.
FIG. 56 is a manufacturing process diagram of the capacitor according to the ninth embodiment of the present invention.
FIG. 57 is a manufacturing process diagram of the capacitor according to the ninth embodiment of the present invention.
FIG. 58 is a manufacturing process diagram of the capacitor according to the ninth embodiment of the present invention.
FIG. 59 is a manufacturing process diagram of the capacitor according to the ninth embodiment of the present invention.
FIG. 60 is a manufacturing process diagram of a capacitor according to the ninth embodiment of the present invention.
61 is a view showing an SEM image of a silicon thin film obtained in the ninth example of the present invention. FIG.
62 shows a TEM image of a silicon thin film obtained in the ninth example of the present invention. FIG.
FIG. 63 is a comparative diagram showing the difference between the film thickness of an amorphous film and the surface state after heat treatment.
FIG. 64 is a diagram showing deposited film thickness and grain distribution density
FIG. 65 is an explanatory view showing a natural oxide film removal step in the ninth embodiment of the present invention;
FIG. 66 is a comparative diagram of the capacitance of the capacitor obtained in the ninth embodiment of the present invention and the capacitance of a conventional capacitor;
FIG. 67 is a manufacturing process diagram of a capacitor according to the tenth embodiment of the present invention.
FIG. 68 is a manufacturing process diagram of a capacitor according to the tenth embodiment of the present invention.
FIG. 69 is a manufacturing process diagram of a capacitor according to the tenth embodiment of the present invention.
FIG. 70 is a manufacturing process diagram of the capacitor according to the tenth embodiment of the present invention.
FIG. 71 is a manufacturing process diagram of a capacitor according to the tenth embodiment of the present invention.
FIG. 72 is a manufacturing process diagram of the capacitor according to the tenth embodiment of the present invention.
FIG. 73 is a process chart for forming a semiconductor thin film according to the eleventh embodiment of the present invention;
74 is a view showing an SEM image of a semiconductor thin film obtained in the same step. FIG.
75 is a view showing a manufacturing process of a semiconductor device according to an eleventh reference example of the present invention; FIG.
FIG. 76 is a diagram showing element characteristics of a MOS transistor obtained in the same step.
FIG. 77 is a diagram showing a change in characteristics of a MOS transistor formed on a base substrate before and after the same process.
FIG. 78 is a manufacturing process diagram of a semiconductor device according to a twelfth reference example of the present invention;
FIG. 79 is a diagram showing the relationship between the distance from the seed of the transistor formed in the same step and the etch pit.
80 is a graph showing the relationship between the distance from the seed of a transistor formed in the same step and the element characteristics;
FIG. 81 is a diagram showing manufacturing steps of the semiconductor device according to the twelfth embodiment of the present invention;
FIG. 82 is a diagram showing element characteristics of the semiconductor device formed in the same step.
FIG. 83 is a diagram showing the junction characteristics of the semiconductor device formed in the same step
FIG. 84 is a diagram showing a manufacturing process of the semiconductor device according to the thirteenth embodiment of the present invention;
FIG. 85 is a graph showing the particle size distribution of the semiconductor thin film obtained in the same step
FIG. 86 is a view showing a planar TEM photograph of a semiconductor thin film obtained by the same process and a conventional process.
87 is a graph showing the results of measuring electron mobility of a transistor formed in the same step. FIG.
88 is a graph showing Vg-Id characteristics of the transistor formed in the same step. FIG.
FIG. 89 is a graph showing the results of measuring the temperature dependence of electron mobility of a transistor formed in the same process and a conventional transistor;
FIG. 90 is a diagram showing manufacturing steps of the semiconductor device according to the fourteenth embodiment of the present invention;
FIG. 91 is a diagram showing a result of measuring electron mobility of a transistor formed in the same step.
FIG. 92 is a diagram showing the manufacturing process of the semiconductor device according to the fifteenth embodiment of the present invention;
FIG. 93 is a graph showing the particle size distribution of the semiconductor thin film obtained in the same step
FIG. 94 is a graph showing a grain spacing distribution of a semiconductor thin film obtained in the same step.
FIG. 95 is a graph showing the oxygen concentration distribution in the film of the semiconductor device obtained in the same step
96 is a manufacturing process diagram of a semiconductor device according to a thirteenth reference example of the present invention; FIG.
FIG. 97 is a manufacturing process diagram of a semiconductor device according to a thirteenth reference example of the present invention;
FIG. 98 is a manufacturing process diagram of a semiconductor device according to a thirteenth reference example of the present invention;
FIG. 99 is a manufacturing process diagram of a semiconductor device according to a thirteenth reference example of the present invention;
FIG. 100 is a manufacturing process diagram of a semiconductor device according to a thirteenth reference example of the present invention;
FIG. 101 is a manufacturing process diagram of a semiconductor device according to a thirteenth reference example of the present invention;
102 is a manufacturing process diagram of a semiconductor device according to a thirteenth reference example of the present invention; FIG.
FIG. 103 is a manufacturing process diagram of a semiconductor device according to a thirteenth reference example of the present invention;
FIG. 104 is a manufacturing process diagram of a semiconductor device according to a thirteenth reference example of the present invention;
FIG. 105 is a graph showing the relationship between the gate voltage and mobility of a transistor obtained in the same step
FIG. 106 is a diagram showing the relationship between the delay time of the ring oscillator obtained in the same process and Vdd.
107 is a manufacturing process diagram of a semiconductor device according to a fourteenth reference example of the present invention; FIG.
FIG. 108 is a manufacturing process diagram of a semiconductor device according to a fourteenth reference example of the present invention;
109 is a manufacturing process diagram of a semiconductor device according to a fourteenth reference example of the present invention; FIG.
FIG. 110 is a manufacturing process diagram of a semiconductor device according to a fourteenth reference example of the present invention;
FIG. 111 is a manufacturing process diagram of a semiconductor device according to a fourteenth reference example of the present invention;
FIG. 112 is a manufacturing process diagram of a semiconductor device according to a fourteenth reference example of the present invention;
FIG. 113 is a manufacturing process diagram of a semiconductor device according to a fourteenth reference example of the present invention;
FIG. 114 is a manufacturing process diagram of the semiconductor device according to the fourteenth reference example;
FIG. 115 is a manufacturing process diagram of a semiconductor device according to a fourteenth reference example of the present invention;
FIG 116 is a graph showing the relationship between the gate voltage and drain current of a transistor obtained by the same device.
FIG. 117 is a graph showing the relationship between the channel size and threshold voltage of a transistor obtained with the same device.
FIG. 118 is a manufacturing process diagram of a semiconductor device according to a fifteenth reference example of the present invention;
FIG. 119 is a manufacturing process diagram of a semiconductor device according to a fifteenth reference example of the present invention;
120 is a manufacturing process diagram of a semiconductor device according to a fifteenth reference example of the present invention; FIG.
FIG. 121 is a manufacturing process diagram of a semiconductor device according to a fifteenth reference example of the present invention;
FIG. 122 is a manufacturing process diagram of a semiconductor device in a fifteenth reference example;
FIG. 123 is a manufacturing process diagram of a semiconductor device according to a fifteenth reference example of the present invention;
FIG. 124 is a manufacturing process diagram of a semiconductor device according to a fifteenth reference example of the present invention;
FIG. 125 is a manufacturing process diagram of a semiconductor device according to a fifteenth reference example of the present invention;
FIG. 126 is a manufacturing process diagram of a semiconductor device according to a fifteenth reference example of the present invention;
FIG. 127 is a manufacturing process diagram of a semiconductor device according to a fifteenth reference example of the present invention;
128 is a manufacturing process diagram of a semiconductor device according to a fifteenth reference example of the present invention; FIG.
FIG. 129 is a manufacturing process diagram of a semiconductor device according to a fifteenth reference example of the present invention;
FIG. 130 is a manufacturing process diagram of a semiconductor device according to a fifteenth reference example of the present invention;
FIG. 131 is a manufacturing process diagram of the fifteenth reference semiconductor device of the present invention;
FIG. 132 is an equivalent circuit diagram of the semiconductor device
FIG. 133 is a diagram showing a conventional semiconductor device
FIG. 134 is a diagram showing a conventional process for forming a semiconductor thin film
FIG. 135 is an explanatory view showing a process of forming a semiconductor thin film of a conventional example.
136 is a diagram showing a basic model of a simulator used for verification of the present invention; FIG.
FIG. 137 is a diagram showing simulator variables used in the verification of the present invention;
FIG. 138 is a diagram showing the basic output of the simulator used for the verification of the present invention;
139 is an electron beam diffraction image of a single crystal thin film sample formed by a conventional method
FIG. 140 is a diagram showing a sample structure for explaining a conventional method
FIG. 141 is an optical micrograph and growth distance of a single crystal thin film obtained by a conventional method.
Diagram showing the time-dependent nature of
FIG. 142 is a diagram showing a TEM image of a semiconductor thin film obtained in the same step
143 is a diagram showing a TEM image of a semiconductor thin film obtained in the same step. FIG.
144 is a diagram showing a TEM image of a semiconductor thin film obtained in the same step. FIG.
145 is a diagram showing a TEM image of a semiconductor thin film obtained in the same step. FIG.
FIG. 146 is a schematic diagram showing the growth of a conventional semiconductor thin film.
FIG. 147 is a diagram showing the stress distribution of a conventional semiconductor thin film
[Explanation of symbols]
1 ... Silicon substrate
2 ... Silicon oxide film
3. Amorphous silicon layer
4. Single crystal silicon layer
6 ... Gate electrode
7 ... Source / drain region
8: Element isolation insulating film
11 ... Silicon substrate surface
12 ... Silicon oxide film
13. Amorphous silicon
14 ... Single crystal silicon
41 ... Silicon substrate
42 ... Silicon oxide film
43 ... Amorphous silicon
44 ... Single crystal silicon grain
51. Silicon substrate
52. Silicon oxide film
53 ... Amorphous silicon
54. Single crystal silicon
61 ... Silicon substrate
62 ... Silicon oxide film
63 ... resist pattern
64 ... Ion
65. Silicon oxide film
66 ... resist pattern
67 ... Ion
69 ... Single crystal granular material
70: Silicon oxide film
71 ... polycrystalline silicon film
72. Silicon oxide film
73 ... polycrystalline silicon film
101 ... Chamber
102 ... Raw material gas inlet
103 ... exhaust port
104 ... Sample stage
105. Beam irradiation means
106: Receiver tube
202 ... Silicon oxide film
203 ... opening
204: Amorphous silicon film
205 ... single crystal silicon film
206: amorphous germanium
207 ... single crystal germanium
311 ... Chamber
312 ... Raw material gas inlet
313: Exhaust port
314 ... Sample stage
315 ... Laser light source
316: Spectroscope
317 ... Mass flow controller
416 ... Ar laser
417 ... Spectroscope

Claims (1)

A first conductive layer forming step of forming a first conductive layer having an insulating film on a surface thereof on a substrate;
An amorphous thin film deposition step for depositing an amorphous thin film on the first conductive layer;
A first heat treatment step of solid phase growth by applying crystallization energy to the amorphous thin film to form a granular single crystal;
A second heat treatment step in which the insulating film is contracted by heat treatment to electrically connect the first conductive layer and the granular single crystal to form a first electrode made of the first conductive layer and the granular single crystal; When,
Forming a capacitor insulating film on the upper layer;
And a first electrode forming step of forming a second electrode so as to sandwich the capacitor insulating film between the first electrode and the first electrode.

Images