JP3777924B2 - Pipeline A / D converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pipeline A / D converter, and more particularly to a pipeline A / D converter capable of reducing the circuit scale.
[0002]
[Prior art]
The conventional pipeline A / D converter quantizes the input signal with a low-resolution A / D converter such as 1 bit, and subtracts the quantized analog value from the input signal to appropriately amplify it to the subsequent stage. An A / D converter is configured by connecting a plurality of output pipeline stages in series.
[0003]
FIG. 4 is a block diagram showing an example of such a conventional 8-bit pipeline A / D converter. In FIG. 4, 1 is a 1.5-bit A / D converter, 2 is a 1.5-bit D / A converter, 3 is a subtractor, 4 is an amplifier having a gain of 2, and 5, 6, 7, 8, 9 , 10 and 11 are storage circuits for storing 2-bit data for 7 to 1 periods, 100 is an analog input signal, and 101 is a digital output signal.
[0004]
1 to 4 constitute a pipeline stage 50a, 50b, 50c, 50d, 50e, 50f and 50g are pipeline stages having the same circuit configuration as the pipeline stage 50a, and 50a to 50g are pipeline A / Ds. Means 51 are configured. Further, 52 is a calculation means, and 5 to 11 and 52 constitute an error collection means 53.
[0005]
The analog input signal 100 is connected to the input terminal of the A / D converter 1 and the addition input terminal of the subtractor 3 constituting the pipeline stage 50 a, and the 2-bit output of the A / D converter 1 is output to the storage circuit 5. And connected to the digital input terminal of the D / A converter 2. The output of the D / A converter 2 is connected to the subtraction input terminal of the subtractor 3, and the output of the subtractor 3 is connected to the amplifier 4.
[0006]
Similarly, the output of the pipeline stage 50a is connected to the pipeline stage 50b, the output of the pipeline stage 50b is connected to the pipeline stage 50c, and the output of the pipeline stage 50c is connected to the pipeline stage 50d.
[0007]
The output of the pipeline stage 50d is connected to the pipeline stage 50e, the output of the pipeline stage 50e is connected to the pipeline stage 50f, and the output of the pipeline stage 50f is connected to the pipeline stage 50g.
[0008]
The 2-bit outputs of the pipeline stages 50b, 50c, 50d, 50e, 50f and 50g are output to the storage circuits 6, 7, 8, 9, 10 and 11, respectively, and the outputs of the storage circuits 5 to 11 are calculated. Connected to the means 52, the computing means 52 outputs a digital output signal 101.
[0009]
Here, the operation of the conventional example shown in FIG. 4 will be described with reference to FIGS. 5, 6, 7, 8, 9, 10, and 11. FIG. 5 is a block diagram showing an example of pipeline A / D means constituted by three pipeline stages for the sake of simplicity. FIG. 6 is a table showing input / output of a 1.5-bit A / D converter. FIG. 7 is a table showing the input / output of the 1.5-bit D / A converter, and FIG.
9 is an explanatory diagram showing a specific example of error correction, FIG. 10 is a timing diagram for explaining the operation of the conventional example shown in FIG. 4, and FIG. 11 is an explanatory diagram for explaining the operation of the conventional example shown in FIG.
[0010]
In FIG. 5, reference numeral 100 denotes the same reference numerals as in FIG. 4, 1a, 1b and 1c denote 1.5-bit A / D converters, 2a, 2b and 2c denote 1.5-bit D / A converters, 3a, 3b and 3c are subtractors, and 4a, 4b and 4c are amplifiers having a gain of two.
[0011]
The 1.5-bit A / D converters 1a to 1c output 2-bit codes based on two threshold voltages. For example, when the full span of the analog input signal 100 is “FS”, “−FS / 8” and “+ FS / 8” are threshold voltages.
[0012]
The input / output of the 1.5-bit A / D converters 1a to 1c has the relationship shown in FIG. Assuming that the input signal is “Vin”, if “−FS ≦ Vin <−FS / 8”, the 2-bit code “00 (= 0)” is set, and “−FS / 8 ≦ Vin <+ FS / 8”. In this case, a 2-bit code “01 (= 1)” is output, and in the case of “+ FS / 8 ≦ Vin <+ FS”, a 2-bit code “10 (= 2)” is output.
[0013]
On the other hand, the 1.5-bit D / A converters 2a to 2c have the relationship shown in FIG. 7, and when the 2-bit input code is “00 (= 0)”, the voltage “−FS / 4” is output. When the 2-bit input code is “01 (= 1)”, a voltage of “0” is output. When the 2-bit input code is “10 (= 2)”, “+ FS / 4” is output. Is output.
[0014]
Here, considering the case where the analog input signal 100 is changed in a full span (-FS / 2 to + FS / 2) as indicated by "PR01" in FIG. 8, A / D conversion of the first pipeline stage is performed. The output code of the device 1a is switched at the threshold voltage “± FS / 8” and becomes a value as shown in “DC01” in FIG. 8 (however, in FIG. 8, it is expressed by a decimal number instead of a 2-bit code). Yes.)
[0015]
At this time, the output of the D / A converter 2a changes according to the table shown in FIG. That is, since “−FS / 4” is output in the region where the input code is “0 (= 00)”, “FS / 4” is added to the analog input signal 100 by the subtractor 3a, and the input code is “1”. Since “0” is output in the (= 01) ”region,“ 0 ”is added to the analog input signal 100 by the subtractor 3a, and“ + FS / 4 ”in the region where the input code is“ 2 (= 10) ”. Since "" is output, "FS / 4" is subtracted from the analog input signal 100 by the subtractor 3a.
[0016]
Since the output of the subtractor 3a is doubled by the amplifier 4a, the output signal of the amplifier 4a is as indicated by "PR02" in FIG. For example, in the region where the input code indicated by “DC01” in FIG. 8 is “0 (= 00)”, “FS / 4” is added to the analog input signal 100 to obtain a doubled signal.
[0017]
Similarly, the output code of the A / D converter 1b of the second pipeline stage is switched at the threshold voltage “± FS / 8”, and becomes a value as indicated by “DC02” in FIG.
[0018]
Then, since the output of the D / A converter 2b is subtracted from the output of the amplifier 4a indicated by "PR02" in FIG. 8 according to the table shown in FIG. 7 and doubled by the amplifier 3b, the output signal of the amplifier 4b is shown in FIG. 8 is shown as “PR03”. For example, in the region where the input code indicated by “DC02” in FIG. 8 is “0 (= 00)”, “FS / 4” is added to the output of the amplifier 4a to obtain a doubled signal.
[0019]
Finally, the output code of the A / D converter 1c in the third pipeline stage is switched at the threshold voltage “± FS / 8”, and becomes a value as indicated by “DC03” in FIG.
[0020]
Further, error collection will be described. In the vicinity of the timing indicated by “PT01” in FIG. 8, the output of the A / D converter 1b switches from “10 (= 2)” to “00 (= 0)”. That is, in the vicinity of “PT01” in FIG. 8, output codes as shown in (1) and (2) in FIG. 9 can be obtained.
[0021]
As shown in (1) of FIG. 9, when the output codes of the first to third pipeline stages are binary numbers “10”, “00” and “01”, the upper bits are shifted to the left by 1 bit. (Double) and adding to the lower bits, an A / D conversion result of “1001 (= 9)” is obtained.
[0022]
On the other hand, even if the output codes of the first to third pipeline stages are “01”, “10” and “01” in binary as shown in (2) in FIG. By shifting (doubled) to the left and adding with the lower bits, an A / D conversion result similar to (1), which is “1001 (= 9)”, is obtained.
[0023]
Such error correction corrects the switching of codes even in the vicinity of “PT01” in FIG.
[0024]
As a result, it is possible to obtain a 4-bit A / D conversion result by performing error correction on the codes obtained in the three pipeline stages. That is, an A / D converter with “the number of pipeline stages + 1” bit resolution can be realized.
[0025]
However, in practice, it is necessary to sequentially store output codes from each pipeline stage and to perform error correction at the same timing.
[0026]
That is, as shown in FIG. 10, since a new code is sequentially output from each pipeline stage, code for 7 to 1 cycle is stored in memory circuit 5 to 11 or delayed by 7 to 1 cycle. As a result, a code having a proper timing can be input to the calculation means 52.
[0027]
In FIG. 10, symbols such as “DU7” correspond to the symbols in FIG. 4, “DU7” is the upper bit of the first pipeline stage, and “DL1” is the lower bit of the seventh pipeline stage. Is shown.
[0028]
For example, in the case where error correction is performed on data such as “*** _ 1 (*** is an arbitrary character string such as DU7)” in FIG. 10, the timing indicated by “PT11” in FIG. Since the timed code by the storage circuits 5 to 11 is input, the arithmetic means 52 shifts (doubles) the upper bit of each pipeline stage to the left by 1 bit as shown in FIG. By adding the bits, an 8-bit A / D conversion result as indicated by “AD7 to AD0” in FIG. 11 is obtained.
[0029]
[Problems to be solved by the invention]
However, as can be seen from FIG. 10, in the conventional pipeline A / D converter, data must be stored until the data necessary for error correction is complete, the amount of data stored in the storage circuit increases, and the circuit scale increases. There was a problem that would become large.
[0030]
In addition, since the error correction is performed at once after the necessary data is prepared, the circuit scale is large, and there is a problem that it is not suitable for high-speed operation. For example, the conventional example shown in FIG. 4 requires an adder that adds 7-bit data and 7-bit data in order to perform error correction.
Therefore, the problem to be solved by the present invention is to realize a pipeline A / D converter capable of reducing the circuit scale.
[0031]
[Means for Solving the Problems]
In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In the pipeline A / D converter,
A 1.5-bit A / D converter for converting the input signal into a digital signal, a 1.5-bit D / A converter for converting the output of the A / D converter into an analog signal, and the input signal to the D A pipeline A / D means in which two stages of pipeline stages composed of a subtractor for subtracting the output of the A / A converter and an amplifier for amplifying and outputting the output of the subtractor are connected;
A first storage circuit for storing digital data from the first pipeline stage, and a lower bit of the first pipeline stage in the output of the storage circuit; A digital adder that adds bits and adds the carry from the lower bit to the upper bit of the first pipeline stage; and the lower bit of the second pipeline stage is added to the output of the digital adder circuit. By providing the error correction means including the second storage circuit that is added and stored as the least significant bit, the circuit scale of the storage circuit can be reduced.
[0032]
The invention according to claim 2
In the pipeline A / D converter according to claim 1,
The memory circuit is
With the D-type flip-flop circuit, the circuit scale of the memory circuit can be reduced.
[0033]
The invention described in claim 3
In the pipeline A / D converter according to claim 1,
The digital adder circuit comprises:
By including the half adder and the AND circuit of the inverted output that performs carry processing, the circuit scale of the memory circuit can be reduced.
[0034]
The invention according to claim 4
In the pipeline A / D converter according to claim 1 ,
The half adder is
The circuit scale of the memory circuit can be reduced by comprising the exclusive OR circuit and the inverted output exclusive OR circuit .
[0037]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a pipeline A / D converter according to the present invention.
[0038]
In FIG. 1, 1-4, 50a-50g, 51 and 100 are assigned the same reference numerals as in FIG. 4, and 12, 14, 16, 18, 20, 22 and 24 are memories for storing 2-bit to 8-bit data. Circuits 13, 15, 17, 19, 21, and 23 are digital adder circuits for adding a plurality of bit data and 1-bit data, 54 is an output circuit, and 101a is a digital output signal. Further, 12 to 24 and 54 constitute an error collection means 55.
[0039]
The analog input signal 100 is connected to the input terminal of the A / D converter 1 and the addition input terminal of the subtractor 3 constituting the pipeline stage 50a, respectively, and the 2-bit data “DU7” and “DL7” of the A / D converter 1 are connected. "Is output to the 2-bit storage circuit 12 and connected to the digital input terminal of the D / A converter 2. The output of the D / A converter 2 is connected to the subtraction input terminal of the subtractor 3, and the output of the subtractor 3 is connected to the amplifier 4.
[0040]
Similarly, the output of the pipeline stage 50a is connected to the pipeline stage 50b, the output of the pipeline stage 50b is connected to the pipeline stage 50c, and the output of the pipeline stage 50c is connected to the pipeline stage 50d.
[0041]
The output of the pipeline stage 50d is connected to the pipeline stage 50e, the output of the pipeline stage 50e is connected to the pipeline stage 50f, and the output of the pipeline stage 50f is connected to the pipeline stage 50g.
[0042]
The 2-bit data output of the storage circuit 12 is connected to the first and second input terminals of the digital adder circuit 13, and the upper bit data “DU6” of the pipeline stage 50 b is the third input terminal of the digital adder circuit 13. Connected to.
[0043]
The lower bit data “DL6” of the pipeline stage 50 b and the 2-bit data output of the digital adder circuit 13 are connected to the 3-bit storage circuit 14, and the 3-bit data output of the storage circuit 14 is the first to first outputs of the digital adder circuit 15. 3, and the upper bit data “DU5” of the pipeline stage 50 c is connected to the fourth input terminal of the digital adder circuit 15.
[0044]
The low-order bit data “DL5” of the pipeline stage 50 c and the 3-bit data output of the digital adder circuit 15 are connected to the 4-bit storage circuit 16, and the 4-bit data output of the storage circuit 16 is the first to first outputs of the digital adder circuit 17. 4, and the upper bit data “DU4” of the pipeline stage 50 d is connected to the fifth input terminal of the digital adder circuit 17.
[0045]
The low-order bit data “DL4” of the pipeline stage 50 d and the 4-bit data output of the digital adder circuit 17 are connected to the 5-bit storage circuit 18, and the 5-bit data output of the storage circuit 18 5, and the higher-order bit data “DU3” of the pipeline stage 50 e is connected to the sixth input terminal of the digital adder circuit 19.
[0046]
The low-order bit data “DL3” of the pipeline stage 50 e and the 5-bit data output of the digital adder circuit 19 are connected to the 6-bit storage circuit 20, and the 6-bit data output of the storage circuit 20 6, the upper bit data “DU2” of the pipeline stage 50 f is connected to the seventh input terminal of the digital adder circuit 21.
[0047]
The low-order bit data “DL2” of the pipeline stage 50f and the 6-bit data output of the digital adder circuit 21 are connected to the 7-bit storage circuit 22, and the 7-bit data output of the storage circuit 22 7, and the upper bit data “DU1” of the pipeline stage 50 g is connected to the eighth input terminal of the digital adder circuit 23.
[0048]
Finally, the lower bit data “DL1” of the pipeline stage 50g and the 7-bit data output of the digital adder circuit 23 are connected to the 8-bit storage circuit 24, and the 8-bit data output of the storage circuit 24 is connected to the output circuit 54. The output circuit 54 outputs a digital output signal 101a.
[0049]
Here, the operation of the embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 2 is an explanatory diagram for explaining the addition operation in each digital adder circuit.
[0050]
In “S001” in FIG. 2, the digital adder circuit 13 adds “DL7”, which is the lower bit of the pipeline stage 50a, which is the output of the memory circuit 12, and the upper bit “DU6” of the pipeline stage 50b to “AD6-1”. ", The carry from the lower bit is added to the upper bit" DU7 "of the pipeline stage 50a and output as" AD7-1 ".
[0051]
The storage circuit 14 stores “AD7-1” and “AD6-1”, which are outputs of the digital addition circuit 13, and the lower bit “DL6” of the pipeline stage 50b.
[0052]
In “S002” in FIG. 2, the digital adder circuit 15 adds the upper bit “DU5” of the pipeline stage 50c to the lower bit “DL6” of the pipeline stage 50b in the output of the storage circuit 14 to obtain “AD5-2”. When a carry occurs in the lower bits, the higher bits “AD6-1” and “AD7-1” are sequentially carried and output as “AD6-2” and “AD7-2”.
[0053]
The storage circuit 16 stores “AD7-2”, “AD6-2” and “AD5-2” which are outputs of the digital adder circuit 15, and the lower bit “DL5” of the pipeline stage 50c.
[0054]
In “S003” in FIG. 2, the digital adder circuit 17 adds the upper bit “DU4” of the pipeline stage 50d to the lower bit “DL5” of the pipeline stage 50c in the output of the storage circuit 16 to obtain “AD4-3”. When a carry occurs in the lower bits, the carry is sequentially performed on the upper bits “AD5-2”, “AD6-2”, and “AD7-2”, and “AD5-3”, “AD6- 3 "and" AD7-3 "are output.
[0055]
Similarly, in “S004” in FIG. 2, the digital adder circuit 23 adds the upper bit “DU1” of the pipeline stage 50g to the lower bit “DL2” of the pipeline stage 50f in the output of the memory circuit 22 to “AD1”. When a carry occurs in the lower bits, the higher bits “AD2-5” to “AD6-5” and “AD7-5” are sequentially carried and “AD2” to “AD6” And “AD7”.
[0056]
Finally, the storage circuit 24 stores “AD7”, “AD6” to “AD1” which are the outputs of the digital adder circuit 23, and stores the lower bit “DL1” of the pipeline stage 50g as the least significant bit “AD0”. . The 8-bit output of the storage circuit 24 is output as a digital output signal 101a via the output circuit 54.
[0057]
In this way, by storing data and adding circuits alternately and performing error correction to pipeline data, there is no need to store data until the data required for error correction is complete, and the circuit scale of the storage circuit Can be reduced.
[0058]
Since error correction is sequentially performed during pipeline processing, an adder circuit using a multi-bit data and one-bit data adder is sufficient, and the circuit scale can be reduced.
[0059]
That is, in the conventional example, the addition means 52 for adding the multi-bit data and the multi-bit data is required, but the addition circuit for the multi-bit data and the 1-bit data can be used. It will also lead to the transformation.
[0060]
For example, FIG. 3 is a configuration block diagram showing a specific example of the adder circuit portion of the embodiment shown in FIG. 3, reference numerals 50a to 50g, 12 to 24, 51, 54, 100, and 101a are assigned the same reference numerals as in FIG. 1, and 12 to 35 and 54 constitute an error correction means 55a.
[0061]
For example, the adder circuit 13 constitutes a half adder by an exclusive OR circuit (hereinafter referred to as EXOR) and an inverted output exclusive OR circuit (hereinafter referred to as EXNOR), and an inverted output logical product circuit. (Hereinafter referred to as NAND) carries out a carry.
[0062]
Similarly, the adder circuit 23 constitutes a 6-bit and 1-bit half adder with EXOR and 6 EXNORs, and carries out carry processing with 6 NANDs.
[0063]
For example, the number of transistors in the configuration shown in FIG. 3 is about 2300, whereas the number of transistors in the configuration of the conventional example shown in FIG. 4 is about 4300, and the ratio is “2300/4300 = 53%”. It can be seen that the circuit scale has been reduced.
[0064]
As a result, it is possible to reduce the circuit scale of the storage circuit by providing the storage circuit and the adder circuit alternately and performing data correction while performing error correction.
[0065]
In the configuration block diagram of FIG. 1 and the like, the 8-bit output of the storage circuit 24 is output via the output circuit 54, but it may of course be directly output.
[0066]
Further, the memory circuit 12 and the like shown in the configuration block diagram of FIG. 1 and the like may be a D-type flip-flop circuit and the like as shown in FIG. Further, it may be a delay means for delaying a certain period.
[0067]
Further, in FIG. 1 and the like, the pipeline A / D means configured by seven pipeline stages is illustrated for the sake of simplicity of explanation, but any number of stages may be used as long as there are a plurality of stages. For example, the minimum configuration is pipeline A / D means composed of two pipeline stages.
[0068]
Similarly, the number of error correction means 55 may be the same as the number of pipeline stages. For example, in the case of pipeline A / D means constituted by two pipeline stages, it is sufficient if there are two storage circuits 12 and 14 and one digital adder circuit 12. If the pipeline stage is “n stages”, “n” storage circuits and “n−1” digital adder circuits may be used.
[0069]
【The invention's effect】
As is apparent from the above description, the present invention has the following effects.
According to the first to fourth aspects of the present invention, it is possible to reduce the circuit scale of the memory circuit by providing the memory circuit and the adder circuit alternately to pipeline the data while performing error correction. .
[Brief description of the drawings]
FIG. 1 is a configuration block diagram showing an embodiment of a pipeline A / D converter according to the present invention.
FIG. 2 is an explanatory diagram for explaining an addition operation in each digital adder circuit;
FIG. 3 is a block diagram showing a specific example of an adder circuit portion;
FIG. 4 is a configuration block diagram showing an example of a conventional pipeline A / D converter.
FIG. 5 is a block diagram showing an example of pipeline A / D means constituted by three pipeline stages.
FIG. 6 is a table showing input / output of a 1.5-bit A / D converter.
FIG. 7 is a table showing input / output of a 1.5-bit D / A converter.
FIG. 8 is an explanatory diagram for explaining an operation and the like in each pipeline stage.
FIG. 9 is an explanatory diagram illustrating a specific example of error collection.
FIG. 10 is a timing chart for explaining the operation of the conventional example.
FIG. 11 is an explanatory diagram for explaining the operation of a conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 1.5 bit A / D converter 2 1.5 bit D / A converter 3 Subtractor 4 Amplifier 5,6,7,8,9,10,11,12,14,16,18,20,22 , 24 Memory circuits 13, 15, 17, 19, 21, 23 Digital adder circuits 50a, 50b, 50c, 50d, 50e, 50f, 50g Pipeline stage 51 Pipeline A / D means 52 Arithmetic means 53, 55 Error correction means 54 Output Circuit 100 Analog Input Signal 101, 101a Digital Output Signal

Claims (4)

In the pipeline A / D converter,
A 1.5-bit A / D converter for converting the input signal into a digital signal, a 1.5-bit D / A converter for converting the output of the A / D converter into an analog signal, and the input signal to the D A pipeline A / D means in which two stages of pipeline stages composed of a subtractor for subtracting the output of the A / A converter and an amplifier for amplifying and outputting the output of the subtractor are connected;
A first storage circuit for storing digital data from the first pipeline stage, and a lower bit of the first pipeline stage in the output of the storage circuit; A digital adder circuit that adds bits and adds the carry from the lower bit to the upper bit of the first pipeline stage, and the lower bit of the second pipeline stage is added to the output of the digital adder circuit. A pipeline A / D converter, comprising: an error correction means including a second storage circuit which is added and stored as the least significant bit . The memory circuit is
Consists of D-type flip-flop circuit
The pipeline A / D converter according to claim 1. The digital adder circuit comprises:
Half adder,
It is composed of an AND circuit of inverted output that performs carry processing
The pipeline A / D converter according to claim 1. The half adder is
An exclusive OR circuit;
It is composed of an exclusive OR circuit with inverted output
The pipeline A / D converter according to claim 1.

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