JP3605291B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and more particularly to a technology effective when applied to a wiring forming technology of a semiconductor integrated circuit device.
[0002]
[Prior art]
As a method of forming wiring of a semiconductor integrated circuit device, for example, there is a process called a damascene method. According to this method, after a trench for forming a wiring is formed in an insulating film, a conductor film for forming a wiring is deposited on the entire surface of the semiconductor substrate, and the conductor film in a region other than the trench is chemically and mechanically polished (CMP). A method of forming a buried interconnect in a trench for forming an interconnect by removing the buried interconnect by chemical mechanical polishing. In the case of this method, particularly, a method of forming an embedded wiring made of a copper-based (copper or copper alloy) conductive material, which is difficult to perform fine etching, has been studied.
[0003]
Further, there is a dual-damascene method as an application of the damascene method. In this method, after forming a groove for forming a wiring and a connection hole for connecting with a lower layer wiring in an insulating film, a conductor film for forming a wiring is deposited on the entire surface of the semiconductor substrate, and further, a region other than the groove is formed. By removing the conductive film by CMP, a buried wiring is formed in a groove for forming a wiring, and a plug is formed in a connection hole. In the case of this method, particularly in a semiconductor integrated circuit device having a multilayer wiring structure, the number of steps can be reduced, and the wiring cost can be reduced.
[0004]
Such a wiring forming technique is described in, for example, JP-A-8-78410, 1996 Symp. VLSI. Tech. Digest pp48-49, Electronic Materials, March 1996, pp22-27, JP-A-8-148560, or IBM J. Pharm. RES. DEVELOP. VOL. 39. NO. 4, pp 419-435, July 1995.
[0005]
[Problems to be solved by the invention]
However, the present inventor has found that there is the following problem in the above-described technology for forming an embedded wiring.
[0006]
That is, there is a problem in that the overall image of the structure and manufacturing when the embedded wiring technology is applied to the semiconductor integrated circuit device is not completely established. In particular, in the above-described dual damascene method, the wiring formation groove and the connection hole are simultaneously buried with the same conductor film, but the connection hole finer than the wiring formation groove is sufficiently and simultaneously formed with the wiring formation groove at the same time. It is becoming difficult to embed the semiconductor device while ensuring excellent electrical characteristics with miniaturization of wirings and connection holes. For example, when copper is used as a wiring material, it is difficult to embed copper in a connection hole by a sputtering method. On the other hand, when the plating method is used, the burying ability is high, but the crystal grains immediately after the formation of copper formed by this method are small, and sufficient electrical characteristics may not be obtained in some cases. Further, although the embedding ability of the plating method is high, there is a limit, and it is difficult to embed fine connection holes having a high aspect ratio. This problem also occurs when wiring grooves having different aspect ratios exist in the same buried wiring layer.
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to provide a technique capable of satisfactorily embedding a conductor film for embedded wiring in a semiconductor integrated circuit device having an embedded wiring structure without using advanced technology.
[0008]
Another object of the present invention is to provide a technique capable of promoting miniaturization of a wiring groove and / or a connection hole in a semiconductor integrated circuit device having a buried wiring structure.
[0009]
Another object of the present invention is to provide a technique capable of improving the reliability of an embedded wiring.
[0010]
Another object of the present invention is to provide a technique capable of incorporating an embedded wiring using a copper-based conductor material into the entire structure of a semiconductor integrated circuit device without causing a problem.
[0011]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0012]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0013]
A method for manufacturing a semiconductor integrated circuit device according to the present invention is a method for manufacturing a semiconductor integrated circuit device having a buried wiring in a wiring layer above a semiconductor substrate,
(A) drilling a connection hole in an insulating film above the semiconductor substrate;
(B) forming a connection conductor film on the insulating film so as to fill the connection hole;
(C) After the step of forming the connection conductor film, the connection conductor film is subjected to a flattening process to remove the connection conductor film other than in the connection hole, thereby forming the connection hole in the connection hole. Forming a connecting conductor,
(D) forming a wiring groove in a wiring forming region of the insulating film after forming the connection conductor portion;
(E) forming a wiring conductor film on the insulating film so as to fill the wiring groove;
(F) After the step of forming the wiring conductor film, the wiring conductor film is subjected to a flattening process to remove the wiring conductor film other than in the wiring groove. And forming a buried wiring therein.
[0014]
Further, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, when the conductive film for wiring is made of copper or a copper alloy, and the conductive film is formed by a sputtering method, the flattening process of the conductive film for wiring is performed. It has a step of performing a heat treatment after the step.
[0015]
Further, the method of manufacturing a semiconductor integrated circuit device according to the present invention is a method of manufacturing a semiconductor integrated circuit device having an embedded wiring in an upper wiring layer of a semiconductor substrate, wherein a dimension formed in the same embedded wiring layer is smaller. When the conductor films are embedded in different wiring grooves, the conductor films are separately embedded in the wiring grooves having different dimensions.
[0016]
Further, a method of manufacturing a semiconductor integrated circuit device of the present invention is a method of manufacturing a semiconductor integrated circuit device having a buried wiring in a wiring layer above a semiconductor substrate,
(A) drilling a wiring groove and a connection hole in an insulating film on an upper layer of the semiconductor substrate;
(B) forming a conductor film made of copper or a copper alloy on the insulating film by sputtering so that the wiring groove and the connection hole are buried;
(C) The conductor film made of copper or a copper alloy is subjected to a flattening process to remove the conductor film made of copper or a copper alloy other than in the wiring groove and the connection hole. A step of embedding a conductor film in the connection hole;
(D) performing a heat treatment after the flattening process of the conductor film made of copper or copper alloy.
[0017]
Further, the semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having an embedded wiring in an upper wiring layer of a semiconductor substrate, wherein the wiring material at a portion where the embedded wiring and the semiconductor substrate are in contact is made of tungsten. , A tungsten alloy, titanium, titanium nitride, aluminum or an aluminum alloy, and a buried wiring in an upper wiring layer made of copper or a copper alloy.
[0018]
Further, the semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having a buried wiring in at least one of the upper wiring layers of the semiconductor substrate, wherein the uppermost wiring layer of the wiring layers The wiring material is made of aluminum or an aluminum alloy, and the embedded wiring in the wiring layer below the wiring material is made of copper or a copper alloy. Further, the semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having a buried wiring in a wiring layer above a semiconductor substrate, wherein a wiring made of aluminum or an aluminum alloy and a wiring made of copper or a copper alloy are formed. In the case of connection, a barrier conductor film is interposed between these joints.
[0019]
Further, the semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having a buried wiring in a wiring layer above a semiconductor substrate, wherein the buried wiring is a layer above a wiring layer of a predetermined buried wiring among the wiring layers. When electrically connecting a wiring and a wiring lower than a wiring layer of the predetermined embedded wiring, a connection provided in a connection hole extending from the wiring of the upper layer to a wiring layer of the predetermined embedded wiring. A conductor portion for connection and a connection conductor portion provided in a connection hole extending from the lower layer wiring to the wiring layer of the predetermined embedded wiring, in a connection groove of the wiring layer of the predetermined embedded wiring. A structure for electrically connecting via a provided relay connecting conductor portion, wherein the relay connecting conductor portion has at least a length in a wiring extending direction of the predetermined embedded wiring, The connection hole is formed to be longer than the length of the connection hole in the wiring extending direction. Those which are.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (Note that components having the same function are denoted by the same reference numerals throughout the drawings for describing the embodiments, and repetitive description thereof will be omitted.) Do).
[0021]
(Embodiment 1)
1 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a main part showing a first layer wiring of the semiconductor integrated circuit device of FIG. 1, and FIGS. FIG. 6 is a cross-sectional view showing a modification of the wiring structure of FIG. 2, FIG. 6 is a cross-sectional view of a main part showing a second layer wiring of the semiconductor integrated circuit device of FIG. 1, and FIG. FIG. 8 to FIG. 12 are cross-sectional views of main parts of a semiconductor integrated circuit device during a manufacturing process, showing a modification, and FIGS. 13 to 18 are semiconductor integrated circuit devices of FIG. It is a partially broken perspective view of the principal part during the manufacturing process of FIG.
[0022]
First, the structure of the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS. The semiconductor substrate 1 is, for example, p ⁻ P-well PW and N-well NW are formed on the top of the silicon (Si) single crystal. The p-well PW contains, for example, boron (B) as a p-type impurity, and the n-well NW contains, for example, phosphorus (P) or arsenic (As) as an n-type impurity.
[0023]
An element isolation part 2 is formed on the semiconductor substrate 1. The element isolation portion 2 is formed by embedding an isolation insulating film 2b made of, for example, silicon oxide or the like in an isolation groove 2a dug above the semiconductor substrate 1. The upper surface of the element isolation portion 2 is flattened so as to substantially coincide with the main surface of the semiconductor substrate 1.
[0024]
In the region of the p-well PW and the n-well NW surrounded by the element isolation part 2, for example, an n-channel type MOS.FET (Metal Oxide Semiconductor Field Effect Transistor; hereinafter simply referred to as nMOS) 3n and a p-channel type MOS. An FET (hereinafter simply referred to as pMOS) 3p is formed. A CMOS (Complementary MOS) is formed by the nMOS 3n and the pMOS 3p. However, the integrated circuit element formed on the semiconductor substrate 1 is not limited to a MOS-FET or a MIS-FET (Metal Insulator Semiconductor Effect Transistor), but can be variously changed, and can be variously changed. A structure in which these integrated circuit elements are formed on the same semiconductor substrate may be used.
[0025]
The nMOS 3n includes a pair of semiconductor regions 3nd formed apart from each other on the p-well PW, a gate insulating film 3ni formed on the semiconductor substrate 1, and a gate electrode 3ng formed thereon. ing. The channel region of the nMOS 3n is formed between the pair of semiconductor regions 3nd in the p well PW.
[0026]
The semiconductor region 3nd is a region for forming the source / drain region of the nMOS 3n, and contains, for example, an n-type impurity such as phosphorus or As. Note that the semiconductor region 3nd may have a structure including a relatively low-concentration semiconductor region disposed on the channel region side and a relatively high-concentration semiconductor region disposed outside the semiconductor region.
[0027]
The gate insulating film 3ni is made of, for example, silicon oxide. The gate electrode 3ng formed thereon is made of, for example, a single film of low-resistance polysilicon. However, the gate electrode 3ng is not limited to a single film of low-resistance polysilicon, but has a so-called polycide structure in which a silicide film such as tungsten silicide is formed on a single film of low-resistance polysilicon. Alternatively, a so-called polymetal structure in which a metal film such as tungsten is formed on a single film of low-resistance polysilicon via a barrier metal film such as titanium nitride, for example, may be used.
[0028]
On the other hand, the pMOS 3p includes a pair of semiconductor regions 3pd formed apart from each other on the n-well NW, a gate insulating film 3pi formed on the semiconductor substrate 1, and a gate electrode 3pg formed thereon. Have. The channel region of the pMOS 3p is formed between the pair of semiconductor regions 3pd in the n-well NW. The semiconductor region 3pd is a region for forming a source / drain region of the pMOS 3p, and contains, for example, boron as a p-type impurity. The semiconductor region 3pd may have a structure having a relatively low-concentration semiconductor region disposed on the channel region side and a relatively-high-concentration semiconductor region disposed outside the semiconductor region.
[0029]
The gate insulating film 3pi is made of, for example, silicon oxide. The gate electrode 3pg formed thereon is made of, for example, a single film of low-resistance polysilicon. However, the gate electrode 3pg is not limited to a single film of low-resistance polysilicon, but has a so-called polycide structure in which a silicide film such as tungsten silicide is formed on a single film of low-resistance polysilicon. Alternatively, a so-called polymetal structure in which a metal film such as tungsten is formed on a single film of low-resistance polysilicon via a barrier metal film such as titanium nitride, for example, may be used.
[0030]
On such a semiconductor substrate 1, an interlayer insulating film 4a made of, for example, silicon oxide whose surface is flattened by, for example, a CMP method is formed, thereby covering the nMOS 3n and the pMOS 3p. Wiring grooves 5a and 5b having different widths and lengths are formed above the interlayer insulating film 4a. The depth of the wiring grooves 5a and 5b is the same, for example, about 0.3 to 1.0 μm, and preferably about 0.5 μm. The aspect ratio of the wiring groove 5a is preferably, for example, about 0.1 to 1.0, and is preferably smaller than 0.7 in consideration of satisfactorily embedding the wiring conductive film. The aspect ratio of the wiring groove 5b is preferably, for example, about 0.5 to 2.5, and is preferably smaller than 1.5 in consideration of embedding the wiring conductor film.
[0031]
As shown in FIGS. 1 and 2, the first-layer wiring 6L is formed in the wiring grooves 5a and 5b in a buried state. The first layer wiring 6L is composed of a relatively thin conductor film 6L1 at the lower portion and side portions, and a relatively thick conductor film 6L2 surrounded by the thin conductor film 6L1.
[0032]
The thin conductor film 6L1 is made of a material having a function of improving the adhesion between the first-layer wiring 6L and the interlayer insulating film 4a and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film 6L2, for example, tungsten (W). , Titanium nitride (TiN), titanium (Ti), tantalum (Ta), tungsten nitride (WN), tungsten nitride silicide (WSiN), titanium nitride silicide (TiSiN), tantalum nitride (TaN), tantalum silicide (TaSiN), etc. Consists of
[0033]
Here, when the thin conductor film 6L1 is formed of tungsten or the like, the wiring resistance can be reduced as compared with the case where the thin conductor film 6L1 is formed of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN, or the like. . Although not particularly limited, in the first embodiment, the thin conductor film 6L1 is made of, for example, TiN. The thick conductor film 6L2 is a member constituting the main body of the first layer wiring 6L, and has a low resistance such as aluminum (Al), Al alloy, tungsten, tungsten alloy, copper (Cu) or Cu alloy. Made of material. As an example of the Al alloy, one obtained by adding one or more elements selected from elements such as Si, Cu, and Ge to a conductor film made of Al can be cited. As an example of the Cu alloy, one obtained by adding one or more elements selected from elements such as magnesium (Mg), Si, and Ti to a conductor film made of Cu is cited. As an example of the tungsten alloy, one obtained by adding one or more elements selected from elements such as Si and N to a conductor film made of tungsten is cited. In the following description, the Al alloy, the tungsten alloy, and the Cu alloy are basically the same as those described above. When the thick conductor film 6L2 is made of Cu or Cu alloy, the wiring resistance can be greatly reduced as compared with the case where it is made of Al or tungsten, and the thick conductor film 6L2 is made of Al or Al alloy. It is also possible to improve the electromigration (EM) resistance of the first-layer wiring 6L as compared with the case where it is configured. Although not particularly limited, in the first embodiment, the thick conductor film 6L2 is made of, for example, Cu.
[0034]
However, the structure of the first layer wiring 6L is not limited to the structure shown in FIGS. 1 and 2 and can be variously changed. For example, the structure shown in FIGS. FIG. 3 shows a structure in which a cap conductor film 6L3 is provided so as to cover the thin conductor film 6L1 and the thick conductor film 6L2. The cap conductor film 6L3 is made of, for example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. This structure can further suppress the diffusion of Cu atoms by applying when the thick conductor film 6L2 is made of Cu or a Cu alloy, thereby further improving the reliability of the semiconductor integrated circuit device. Is possible. Although not particularly limited, it is also suitable for a case where an alloy or the like having a high specific resistance is formed when the wiring material is brought into direct contact with the thick conductive film 6L2 in relation to the wiring material of the upper layer. Note that a structure in which the cap conductor film is provided only on the upper surface of the thick conductor film 6L2 so that the upper surface thereof substantially coincides with the upper surface of the interlayer insulating film 4a may be employed.
[0035]
FIG. 4 shows a structure in which the first-layer wiring 6L is constituted only by the thick conductor film 6L2. That is, the structure has no thin conductive film. FIG. 5 shows a structure in which a cap conductor film 6L3 is provided on the upper surface of the thick conductor film 6L2 in the structure of FIG. This structure is not particularly limited, but is suitable for a case where an alloy or the like having a high specific resistance is formed when the wiring material is brought into direct contact with the thick conductive film 6L2 in relation to the wiring material of the upper layer. .
[0036]
The first layer wiring 6L in the wiring groove 5a is electrically connected to the semiconductor region 3nd of the nMOS 3n or the semiconductor region 3pd of the pMOS 3p through the connecting conductor 7C. Most of the connection conductor 7C is embedded in a connection hole 8a formed in the interlayer insulating film 4a from the bottom surface of the wiring groove 5a toward the upper surface of the semiconductor substrate 1; Is projected into the first layer wiring 6L so as to penetrate the upper and lower surfaces of the first layer wiring 6L. The diameter of the connection hole 8a is, for example, about 0.2 to 1.0 μm, and preferably, for example, about 0.4 μm. Further, the aspect ratio of the connection hole 8a is preferably, for example, about 2 to 6 and smaller than about 4 in consideration of satisfactorily embedding the connection conductor. The upper surface height of the connection conductor 7C is substantially equal to the upper surface height of the first layer wiring 6L.
[0037]
The connection conductor portion 7C is composed of a relatively thin conductor film 7C1 at the lower portion and side portions thereof, and a relatively thick conductor film 7C2 surrounded by the thin conductor film 7C1. The thin conductor film 7C1 is made of a material having a function of improving adhesion between the connection conductor portion 7C and the interlayer insulating film 4a and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film 7C2, for example, tungsten, TiN, It is made of Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN or the like.
[0038]
When the thin conductive film 7C1 is made of tungsten or the like, the wiring resistance can be reduced as compared with the case where the thin conductive film 7C1 is made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN, or the like. Although not particularly limited, in the first embodiment, the thin conductor film 7C1 is made of, for example, tungsten.
[0039]
The thick conductor film 7C2 is a member constituting the main body of the connection conductor 7C, and is made of a low-resistance material such as Al, an Al alloy, tungsten, or a tungsten alloy. Cu or Cu alloy is not used as a constituent material of the thick conductor film 7C2. That is, in the first embodiment, even if Cu or a Cu alloy is used as the constituent material of the buried conductive film 6L2 of the first layer wiring 6L, the constituent material of the connecting conductor portion 7C directly in contact with the semiconductor substrate 1 is used. Does not use Cu or Cu alloy. This makes it possible to reduce the wiring resistance of the first layer wiring 6L and to suppress a connection failure due to the diffusion of Cu atoms to the semiconductor substrate 1 side.
[0040]
When the thick conductor film 7C2 is made of Al or an Al alloy, the resistance of the connecting conductor 7C can be reduced as compared with the case where it is made of tungsten or a tungsten alloy. When the buried conductor film 7C2 is made of tungsten or a tungsten alloy, the EM resistance and the SM resistance of the connecting conductor 7C are improved as compared with the case where the buried conductor film 7C2 is made of Al or an Al alloy. It becomes possible. Although not particularly limited, in the first embodiment, the thick conductor film 7C2 is made of, for example, tungsten. Therefore, in the first embodiment, different kinds of conductor films (Cu and the like for forming the first-layer wiring 6L and tungsten and the like for the connection conductor 7C) are provided in the plane at the height of the first-layer wiring 6L. It has an existing structure. The connecting conductor also forms a part of the wiring.
[0041]
In the above description, the case where the first layer wirings 6L in the wiring grooves 5a and 5b are made of the same material has been described, but the present invention is not limited to this. For example, the constituent material of the thick conductive film 6L2 and the thin conductive film 6L1 embedded in the wiring groove 5b may be different from the constituent material of the thick conductive film 6L2 and the thin conductive film 6L1 embedded in the wiring groove 5a. . This is because, for example, if Cu and the like are simultaneously buried in the wide wiring groove 5a and the narrow wiring groove 5b, the narrow wiring groove 5b may not be sufficiently buried. FIG. 2 shows an example of a structure in which a wide wiring groove 5a is embedded with Cu and a narrow wiring groove 5b is embedded with tungsten or the like by a CVD method or the like. The formation method in this case will be described later.
[0042]
On the interlayer insulating film 4a, an interlayer insulating film 4b in which a silicon oxide film 4b2 having a larger thickness than the silicon nitride film is formed, for example, on a silicon nitride film 4b1 is formed. The silicon nitride film 4b1 functions as a barrier film for preventing diffusion of Cu when the thick conductive film 6L2 or the buried conductive film 7C2 is made of a Cu-based conductive material. When forming a connection hole 8a to be described later, the silicon oxide film 4b2 is etched using the silicon nitride film 4b1 as an etching stopper layer, and then the silicon nitride film 4b2 is etched and removed. When the thick conductor film 6L2 or the buried conductor film 7C2 is made of a conductive material other than Cu, the silicon nitride film 4b1 may not be provided. Over the interlayer insulating film 4b, wiring grooves 5c and 5d having different widths are formed. The depths of the wiring grooves 5c and 5d are the same, for example, about 0.3 to 1.0 μm, and preferably about 0.6 μm. The aspect ratio of the wiring groove 5c is preferably, for example, about 0.1 to 1.0, and is preferably smaller than 0.7 in consideration of satisfactorily embedding the wiring conductor film. The aspect ratio of the wiring groove 5d is preferably, for example, about 0.5 to 2.5, and is preferably smaller than 1.5 in consideration of satisfactorily embedding the wiring conductor film. The silicon oxide film 4b2 is made of, for example, a TEOS (Tetraethoxysilane) film or a SOG (Spin On Glass) film formed by a CVD method. By using the SOG film having a low dielectric constant, the capacitance between wirings can be reduced, and the operation speed of the circuit can be improved.
[0043]
As shown in FIGS. 1 and 6, the second-layer wiring 9L is formed in the wiring grooves 5c and 5d in a buried state. The second-layer wiring 9L is composed of a relatively thin conductor film 9L1 at the lower portion and side portions, and a relatively thick conductor film 9L2 surrounded by the thin conductor film 9L1.
[0044]
The thin conductor film 9L1 is made of a material having a function of improving adhesion between the second-layer wiring 9L and the interlayer insulating film 4b and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film 9L2, for example, tungsten, TiN, It is made of Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN or the like.
[0045]
When the thin conductor film 9L1 is made of tungsten or the like, the wiring resistance can be reduced as compared with the case where the thin conductor film 9L1 is made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. Although not particularly limited, in the first embodiment, the thin conductor film 9L1 is made of, for example, TiN.
[0046]
The thick conductor film 9L2 is a member constituting the main body of the second-layer wiring 9L, and is made of a low-resistance material such as Al, an Al alloy, tungsten, a tungsten alloy, Cu, or a Cu alloy. When the thick conductor film 9L2 is made of Cu or a Cu alloy, the wiring resistance can be greatly reduced as compared with the case where it is made of Al or tungsten. Further, the EM resistance of the second layer wiring 9L can be improved as compared with the case where the thick conductor film 9L2 is made of Al or an Al alloy. Although not particularly limited, in the first embodiment, the thick conductor film 9L2 is made of, for example, Cu.
[0047]
However, the structure of the second-layer wiring 9L is not limited to the structure shown in FIGS. 1 and 6, and can be variously changed. For example, the structure shown in FIGS. You may do it. That is, a structure in which a cap conductor film is provided on the upper surfaces of the thick conductor film 9L2 and the thin conductor film 9L1 may be used. This cap conductor film is made of a material having a barrier function, such as a low-resistance material such as tungsten, or a material such as TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN. This structure can further suppress the diffusion of Cu atoms, particularly when the thick conductor film 9L2 is made of Cu or a Cu alloy, thereby further improving the reliability of the semiconductor integrated circuit device. Is possible. Although not particularly limited, it is suitable for a case where an alloy or the like having a high specific resistance is formed when the wiring material is brought into direct contact with the thick conductive film 9L2 in relation to the wiring material of the upper layer. Note that a structure in which the cap conductor film is provided only on the upper surface of the thick conductor film 6L2 so that the upper surface thereof substantially coincides with the upper surface of the interlayer insulating film 4a may be employed.
[0048]
As another structure, a structure in which the second-layer wiring 9L is constituted only by the thick conductor film 9L2 may be used. That is, the structure has no thin conductive film. As still another structure, a structure in which a cap conductive film is provided on the upper surface of the thick conductive film 9L2 in the structure without the thin conductive film may be used. Although this structure is not particularly limited, it is suitable for a case where an alloy or the like having a high specific resistance value is formed when the wiring material is brought into direct contact with the thick conductive film 9L2 in relation to the wiring material of the upper layer. I have.
[0049]
The second layer wiring 9L formed in the wiring groove 5c is electrically connected to the first layer wiring 6L through the connection conductor 10C. Most of the connection conductor portion 10C is embedded in a connection hole 8b formed in the interlayer insulating film 4b from the bottom surface of the wiring groove 5c toward the upper surface of the first layer wiring 6L. The upper part of the portion 10C protrudes into the second layer wiring 9L so as to penetrate the upper and lower surfaces of the second layer wiring 9L. The diameter of the connection hole 8b is, for example, about 0.2 to 1.2 μm, and preferably, for example, about 0.4. Further, the aspect ratio of the connection hole 8b is preferably about 2 to 6, and is preferably smaller than about 4 in consideration of good embedding of the connection conductor. The upper surface height of the connection conductor 10C is substantially equal to the upper surface height of the second layer wiring 9L, that is, the upper surface height of the interlayer insulating film 4b.
[0050]
The connection conductor portion 10C is composed of a relatively thin conductor film 10C1 at the lower and side portions thereof, and a relatively thick conductor film 10C2 surrounded by the thin conductor film 10C1. The thin conductor film 10C1 is made of a material having a function of improving adhesion between the connection conductor portion 10C and the interlayer insulating film 4b and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film 10C2. It is made of Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN or the like.
[0051]
When the thin conductor film 10C1 is made of tungsten or the like, the wiring resistance can be reduced as compared with the case where the thin conductor film 10C1 is made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN, or the like. Although not particularly limited, in the first embodiment, the thin conductor film 10C1 is made of, for example, tungsten.
[0052]
The thick conductor film 10C2 is a member constituting the main body of the connection conductor 7C, and is made of a low-resistance material such as Al, an Al alloy, tungsten, a tungsten alloy, Cu, or a Cu alloy. When the thick conductor film 10C2 is made of, for example, Cu or a Cu alloy, the resistance of the connection hole conductor 10C can be reduced as compared with the case of being made of Al, an Al alloy, tungsten, or a tungsten alloy, and The EM resistance of the connection conductor 10C can be improved. When the thick conductor film 10C2 is made of Al or an Al alloy, the resistance of the connecting conductor 10C can be reduced as compared with the case where it is made of tungsten or a tungsten alloy. When the buried conductor film 10C2 is made of tungsten or a tungsten alloy, the EM resistance and the SM resistance of the connecting conductor 10C are improved as compared with the case where the buried conductor film 10C2 is made of Al or an Al alloy. It becomes possible. Although not particularly limited, in the first embodiment, the thick conductor film 10C2 is made of, for example, tungsten.
[0053]
In the interlayer insulating film 4b, a connection hole 8c is drilled from the upper surface to the upper surface of the first layer wiring 6L so as to expose a part of the first layer wiring 6L. Is formed in a state where the connecting conductor 10C is embedded. The diameter of the connection hole 8c is, for example, about 0.2 to 1.2 μm, and preferably, for example, about 0.4 μm. Further, the aspect ratio of the connection hole 8c is preferably about 2 to 6, and is preferably smaller than about 4 in consideration of satisfactorily embedding the connection conductor. The connecting conductor 10C has the same structure as that described above, but is not directly connected to the second-layer wiring 9L in FIG. However, the constituent materials of the thick conductor film 10C2 and the thin conductor film 10C1 of the connection conductor portion 10C embedded in the connection hole 8c are changed to the thick conductor film 10C2 and the thin conductor film 10C1 of the connection conductor portion 10C embedded in the connection hole 8b. You may comprise with a conductor material different from a constituent material.
[0054]
In the above description, the case where the second layer wirings 9L in the wiring grooves 5c and 5d are made of the same material has been described, but the present invention is not limited to this. For example, the constituent material of the thick conductive film 9L2 and the thin conductive film 9L1 embedded in the wiring groove 5d is made of a different conductive material from the constituent material of the thick conductive film 9L2 and the thin conductive film 9L1 embedded in the wiring groove 5c. May be. This is because, for example, if Cu and the like are simultaneously buried in the wide wiring groove 5c and the narrow wiring groove 5d, the narrow wiring groove 5d may not be sufficiently buried. FIG. 5 shows an example of a structure in which a wide wiring groove 5c is buried with Cu and a narrow wiring groove 5d is buried with tungsten or the like by a CVD method or the like. The formation method in this case will be described later.
[0055]
On the interlayer insulating film 4b, an interlayer insulating film 4c composed of, for example, a silicon nitride film 4c1 and a silicon oxide film 4c2 is formed like the interlayer insulating film 4b. Over the interlayer insulating film 4c, wiring grooves 5e and 5f having different widths are formed. The depths of the wiring grooves 5e and 5f are the same, for example, about 0.3 to 1.0 μm, and preferably about 0.6 μm. The aspect ratio of the wiring groove 5e is preferably, for example, about 0.1 to 1.0, and is preferably smaller than 0.7 in consideration of satisfactorily burying the wiring conductor film. The aspect ratio of the wiring groove 5f is preferably, for example, about 0.5 to 2.5, and is preferably smaller than 1.5 in consideration of satisfactorily embedding the wiring conductor film.
[0056]
As shown in FIG. 1, the third-layer wiring 11L is formed in the wiring grooves 5e and 5f so as to be buried. The third-layer wiring 11L is composed of a relatively thin conductor film 11L1 at the lower portion and side portions, and a relatively thick conductor film 11L2 surrounded by the thin conductor film 11L1.
[0057]
The thin conductor film 11L1 is made of a material having a function of improving the adhesion between the third-layer wiring 11L and the interlayer insulating film 4c and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film 11L2, such as tungsten, TiN, or the like. It is made of Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN or the like.
[0058]
When the thin conductor film 11L1 is made of tungsten or the like, the wiring resistance can be reduced as compared with the case where it is made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN, or the like. When the thin conductor film 11L1 is made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN, or the like, it is possible to particularly improve the adhesion with the interlayer insulating film 4c. Although not particularly limited, in the first embodiment, the thin conductor film 11L1 is made of, for example, TiN.
[0059]
The thick conductive film 11L2 is a member constituting the main body of the third-layer wiring 11L, and is made of a low-resistance material such as Al, an Al alloy, tungsten, a tungsten alloy, Cu, or a Cu alloy. When the thick conductor film 11L2 is made of Cu or Cu alloy, the wiring resistance can be greatly reduced as compared with the case where it is made of Al or tungsten. Further, the EM resistance of the third-layer wiring 11L can be improved as compared with the case where the thick conductor film 11L2 is made of Al or an Al alloy. Although not particularly limited, in the first embodiment, the thick conductor film 11L2 is made of, for example, Cu.
[0060]
However, the structure of the third-layer wiring 11L is not limited to the structure shown in FIG. 1 and can be variously changed. For example, the structure shown in FIGS. good. That is, a structure in which a cap conductor film is provided on the upper surfaces of the thick conductor film 11L2 and the thin conductor film 11L1 may be used. This cap conductor film is made of a material having a barrier function, such as a low-resistance material such as tungsten, or a material such as TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN. This structure can further suppress the diffusion of Cu atoms, particularly when the thick conductor film 11L2 is formed of Cu or a Cu alloy, thereby further improving the reliability of the semiconductor integrated circuit device. Is possible. Although not particularly limited, it is suitable for a case where an alloy or the like having a high specific resistance is formed when the wiring material is brought into direct contact with the thick conductive film 11L2 in relation to the wiring material of the upper layer. Note that a structure in which the cap conductor film is provided only on the upper surface of the thick conductor film 11L2 such that the upper surface thereof substantially coincides with the upper surface of the interlayer insulating film 4a may be employed.
[0061]
As another structure, a structure in which the third-layer wiring 11L is formed only of the thick conductor film 11L2 may be used. That is, the structure has no thin conductive film. As still another structure, a structure in which a cap conductive film is provided on the upper surface of the wiring groove 5a in a structure without the thin conductive film may be used. This structure is not particularly limited, but is suitable for a case where an alloy or the like having a high specific resistance is formed when the wiring material and the thick conductive film 11L2 are brought into direct contact with each other in relation to the wiring material of the upper layer. .
[0062]
The third-layer wiring 11L formed in the wiring grooves 5e and 5f is electrically connected to the second-layer wiring 9L through the connection conductor 12C. Most of the connection conductor 12C is embedded in a connection hole 8d formed in the interlayer insulating film 4c from the bottom surfaces of the wiring grooves 5e and 5f toward the upper surface of the second layer wiring 9L. The upper portion of the conductor portion 12C protrudes into the third-layer wiring 11L so as to penetrate the upper and lower surfaces of the third-layer wiring 11L. The diameter of the connection hole 8d is, for example, about 0.2 to 1.2 μm, and preferably, for example, about 0.4 μm. Further, the aspect ratio of the connection hole 8d is preferably about 2 to 6, and is preferably smaller than about 4 in consideration of satisfactorily embedding the connection conductor. The upper surface height of the connection conductor 12C is substantially equal to the upper surface height of the third-layer wiring 11L, that is, the upper surface height of the interlayer insulating film 4c.
[0063]
The connection conductor portion 12C is composed of a relatively thin conductor film 12C1 at the lower portion and side portions thereof, and a relatively thick conductor film 12C2 surrounded by the thin conductor film 12C1. The thin conductor film 12C1 is made of a material having a function of improving adhesion between the connection conductor portion 12C and the interlayer insulating film 4c and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film 12C2, for example, tungsten, TiN, It is made of Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN or the like.
[0064]
When the thin conductor film 12C1 is made of tungsten or the like, the wiring resistance can be reduced as compared with the case where it is made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. Although not particularly limited, in the first embodiment, the thin conductor film 12C1 is made of, for example, tungsten.
[0065]
The thick conductor film 12C2 is a member constituting the main body of the connection conductor 12C, and is made of a low-resistance material such as Al, an Al alloy, tungsten, a tungsten alloy, Cu, or a Cu alloy. When the thick conductor film 12C2 is made of, for example, Cu or a Cu alloy, the resistance of the connection hole conductor 12C can be reduced as compared with the case of being made of Al, Al alloy, tungsten, or a tungsten alloy, and The EM resistance of the connection conductor 12C can be improved. When the thick conductor film 12C2 is made of Al or an Al alloy, the resistance of the connecting conductor 12C can be reduced as compared with the case where it is made of tungsten or a tungsten alloy. When the thick conductor film 12C2 is made of tungsten or a tungsten alloy, the EM resistance and the SM resistance of the connecting conductor 12C can be improved as compared with the case where the thick conductor film 12C2 is made of Al or an Al alloy. It becomes possible. Although not particularly limited, in the first embodiment, the thick conductor film 12C2 is made of, for example, tungsten.
[0066]
In the interlayer insulating film 4c, a connection hole 8e is drilled from the upper surface to the upper surface of the second layer wiring 9L so that a part of the second layer wiring 9L is exposed. Is formed in a state where the connecting conductor portion 12C is embedded. The diameter of the connection hole 8e is, for example, about 0.2 to 1.2 μm, and preferably, for example, about 0.5 μm. The aspect ratio of the connection hole 8e is preferably about 2 to 6, and is preferably smaller than about 4 in consideration of satisfactorily embedding the connection conductor. The structure of the connection conductor 12C is the same as that described above, but is not directly connected to the third-layer wiring 11L in FIG. The connection conductor 12C is in contact with and electrically connected to the connection conductor 10C formed in the lower connection hole 8c. That is, the first embodiment has a structure in which the connecting conductor portions 10C and 12C are electrically connected to each other while penetrating the predetermined wiring layer in the wiring layer having the embedded wiring structure. I have. By forming the connecting conductor 12C with the same constituent material as the connecting conductor 10C, the connection resistance can be reduced. That is, the contact resistance and the like can be reduced as compared with the case where the connecting conductor portions 10C and 12C are connected via the second layer wiring 9L made of a different conductive material. Can be.
[0067]
However, the constituent materials of the thick conductor film 12C2 and the thin conductor film 12C1 of the connection conductor portion 12C embedded in the connection hole 8e are changed to those of the thick conductor film 12C2 and the thin conductor film 12C1 of the connection conductor portion 12C embedded in the connection hole 8e. You may comprise with a conductor material different from a constituent material.
[0068]
Also, as shown in FIG. 7, the connection structure between the connection conductor portions 10C and 12C on the right side of FIG. 1 is such that the third layer wiring 11L and the first layer wiring 6L are connected through the interlayer insulating films 4c and 4b. A structure may be employed in which electrical connection is made directly through one connection conductor 12C in the hole 8e1. Thereby, the connection resistance can be reduced.
[0069]
On the interlayer insulating film 4c, an interlayer insulating film 4d composed of a silicon nitride film 4d1 and a silicon oxide film 4d2 is formed, for example, like the interlayer insulating film 4b. On the upper surface of the interlayer insulating film 4d, a fourth layer wiring 13L is formed. The fourth-layer wirings 13L, 13L are made of, for example, Al or an Al alloy, and are electrically connected to the lower-layer third-layer wiring 11L and the connecting conductor portion 12C through connection holes 8f, 8f formed in the interlayer insulating film 4d, respectively. Have been.
[0070]
By using, for example, Al or an Al alloy as a constituent material of the uppermost fourth-layer wiring 13L, a conventional bonding wire connection technique and a conventional bump electrode formation technique can be directly used. That is, the bonding wire and the bump electrode are connected to the uppermost wiring layer. However, by using the conventionally used Al or Al alloy as the uppermost wiring material, the conventional technology for bonding the bonding wire and the bump electrode can be improved. It can be used as it is. Therefore, it is possible to introduce a semiconductor integrated circuit device having a buried wiring structure made of a Cu-based material into an assembly line without any technical change in an assembling process (a wire bonding process or a bump electrode forming process). Become. Therefore, it is possible to promote the cost reduction of a semiconductor integrated circuit device having a buried wiring made of a Cu-based material, and to promote a reduction in manufacturing and development time.
[0071]
The diameter of the connection hole 8f is, for example, about 0.2 to 1.2 μm, and preferably, for example, about 0.5 μm. Further, the aspect ratio of the connection hole 8f is preferably about 2 to 6, and is preferably smaller than about 4 in consideration of satisfactorily embedding the connection conductor. The connection conductor 8C is embedded in the connection hole 8f. The connection conductor portion 14C is composed of a relatively thin conductor film 14C1 at the lower portion and side portions thereof, and a relatively thick conductor film 14C2 surrounded by the thin conductor film 14C1. The connection conductor 14C does not penetrate the fourth-layer wiring 13L.
[0072]
The thin conductor film 14C1 is made of a material having a function of improving the adhesion between the connection conductor portion 14C and the interlayer insulating film 4d and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film 14C2, for example, tungsten, TiN, It is made of Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN or the like. When the thin conductor film 14C1 is made of tungsten or the like, the wiring resistance can be reduced as compared with the case where the thin conductor film 14C1 is made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. Although not particularly limited, in the first embodiment, the thin conductor film 14C1 is made of, for example, tungsten.
[0073]
The thick conductor film 14C2 is a member constituting the main body of the connection conductor portion 14C, and is made of a low-resistance material such as Al, an Al alloy, tungsten, and a tungsten alloy. When the thick conductor film 14C2 is made of Al or an Al alloy, the resistance of the connecting conductor 14C can be reduced as compared with the case where it is made of tungsten or a tungsten alloy. When the thick conductor film 14C2 is made of tungsten or a tungsten alloy, the EM resistance and the SM resistance of the connection conductor 14C can be improved as compared with the case where the thick conductor film 14C2 is made of Al or an Al alloy. It becomes possible. Further, when the thick conductor film 14C2 is made of tungsten or a tungsten alloy, Cu forming the third-layer wiring 11L and Al or Al alloy forming the fourth-layer wiring 13L can be isolated by a thick barrier metal, so that both of them can be separated. It is easy to prevent the resistance from increasing due to the reaction. That is, by embedding a material having a barrier function in the connection hole 8f, the distance between the third-layer wiring 11L made of a Cu-based material and the fourth-layer wiring 13L made of an Al-based material can be isolated. Reaction can be further reduced. Although not particularly limited, in the first embodiment, the thick conductor film 14C2 is made of, for example, tungsten.
[0074]
A surface protection film 15 is formed on the interlayer insulating film 4d, and covers the surface of the fourth layer wiring 13L. The surface protective film 15 is formed by, for example, stacking a protective film 15b on a protective film 15a. The protective film 15a is made of, for example, SiO2, and the protective film 15b thereover is made of, for example, silicon nitride. An opening 16 is formed in a part of the surface protection film 15 so that a part of the fourth-layer wiring 13L is exposed. In the fourth layer wiring 13L, a portion exposed from the opening 16 forms a bonding pad BP. That is, a bonding wire is directly connected to the bonding pad portion BP, and a lead of a package constituting the semiconductor integrated circuit device is electrically connected through the bonding wire. Note that a structure in which a bump electrode made of a lead-tin alloy, gold, or the like is provided on the bonding pad portion BP with a base metal layer interposed therebetween may be adopted. The above-mentioned interlayer insulating films 4a to 4d may be, for example, a coating film formed by an SOG (Spin On Glass) method, an organic film, a CVD film added with fluorine, a silicon nitride film, or a stacked film obtained by stacking them. good.
[0075]
Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.
[0076]
First, a method of forming a buried interconnect made of the same material will be described with reference to FIGS. Here, since the structures of the first layer wiring 6L, the second layer wiring 9L and the third layer wiring 11L are the same, in order to simplify the description, the method of forming the buried wiring using the first layer wiring 6L as a representative example will be described. explain.
[0077]
FIG. 8 is a cross-sectional view of a main part of the semiconductor integrated circuit device during a manufacturing process. In the interlayer insulating film 4a formed on the semiconductor substrate 1, a connection hole 8a for exposing the main surface (semiconductor region 3nd) of the semiconductor substrate 1 is already formed by photolithography and dry etching. The interlayer insulating film 4a is made of, for example, a silicon oxide film, an SOG (Spin On Glass) film, an organic film, a CVD film to which fluorine is added, a silicon nitride film, or a stacked film obtained by stacking them. The surface of the interlayer insulating film 4a is planarized by polishing a silicon oxide film deposited by, for example, a CVD (Chemical Vapor Deposition) method by a CMP method or the like.
[0078]
Subsequently, as shown in FIG. 9, a thin conductor film 7C1 made of, for example, tungsten (W) is deposited on the upper surface of the interlayer insulating film 4a and the side and bottom surfaces of the connection hole 8a by a sputtering method or the like. The thin conductor film 7C1 has a function of improving the adhesion between the connection conductor portion and the interlayer insulating film 4a, and suppresses the diffusion of material gas and the like when forming the thick conductor film 7C2 and the diffusion of constituent atoms of the thick conductor film 7C2. The material is not limited to tungsten and can be variously changed. For example, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN may be used.
[0079]
Thereafter, a thick conductor film 7C2 made of, for example, tungsten or the like is deposited on the thin conductor film 7C1 by a CVD method or the like. Thereby, the conductive film can be satisfactorily filled in the fine connection holes 8a. This thick conductor film 7C2 is not limited to tungsten or the like, but can be variously changed, and may be a low-resistance material such as Al or an Al alloy. The method of forming the thick conductor film 7C2 is not limited to the CVD method, but may be a plating method, a sputtering method, a combination of a plating method and a CVD method, or the like.
[0080]
However, in the second-layer wiring and the third-layer wiring, Cu or a Cu alloy may be used as a material for forming the thick conductor film of the connecting conductor portions 10C and 12C (see FIG. 1) in addition to the above-described materials. good. In this case, as a method of forming the Cu film, for example, a CVD method, a plating method, or the like may be used.
[0081]
Next, the semiconductor substrate 1 is subjected to, for example, CMP (Chemical Mechanical Polishing) to remove the thick conductive film 7C2 and the thin conductive film 7C1 on the interlayer insulating film 4a in a region other than the connection hole 8a. As shown in FIG. 10, a connection conductor 7C is formed in the connection hole 8a.
[0082]
Subsequently, as shown in FIG. 11, after a photoresist pattern 17a for forming a wiring groove is formed on the interlayer insulating film 4a, the interlayer insulating film 4a exposed from the photoresist pattern 17a is used as an etching mask. By removing the portion, a wiring groove 5a and a wiring groove 5b (see FIG. 1) are formed above the interlayer insulating film 4a. At this time, the upper portion of the connection conductor portion 7C previously formed protrudes into the wiring groove 5a.
[0083]
Thereafter, after removing the photoresist pattern 17a, as shown in FIG. 12, a thin conductive film 6L1 made of, for example, TiN is formed on the surface of the interlayer insulating film 4a including the wiring groove 5a and the exposed surface of the connection conductor 7C. Is applied by a sputtering method or the like. The thin conductor film 6L1 is made of a material having a function of improving the adhesion between the first layer wiring and the interlayer insulating film 4a and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film, and is limited to TiN. Instead, various changes can be made. For example, tungsten, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN may be used.
[0084]
Next, a thick conductor film 6L2 made of, for example, Cu is deposited on the thin conductor film 6L1 by a CVD method, a sputtering method, a plating method, or a combination thereof. In this film formation of Cu or the like, it is desirable to adopt a method with as small an overhang as possible and good step coverage. For example, in the sputtering method, a sputtering apparatus in which the distance between the target and the semiconductor wafer is larger than the radius of the semiconductor wafer is suitable. The thickness of the thick conductor film 6L2 is not limited to Cu but may be variously changed. For example, a Cu alloy, Al, an Al alloy, tungsten, or a tungsten alloy may be used.
[0085]
When the conductor film for wiring is formed by a sputtering method, in particular, subsequently, heat treatment is performed on the semiconductor substrate 1 so that constituent atoms (for example, Cu) of the thick conductor film 6L2 flow. The constituent atoms are sufficiently supplied and embedded in the wiring groove 5a. At this time, the heat treatment atmosphere is an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or an atmosphere combining two or more of them. Also, a so-called reflow sputtering method in which this heat treatment is performed during the sputtering of Cu may be employed. Thus, the EM characteristics of the Cu wiring can be improved.
[0086]
Thereafter, the semiconductor substrate 1 is subjected to a CMP process to remove the thick conductor film 6L2 and the thin conductor film 6L1 on the interlayer insulating film 4a in a region other than the wiring grooves 5a and 5b (see FIG. 1). Then, the first layer wiring 6L shown in FIG. 2 and the like is formed.
[0087]
After or before the CMP process, the semiconductor substrate 1 may be subjected to a heat treatment. At this time, the heat treatment atmosphere is an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or an atmosphere combining two or more of them. In the heat treatment step after the CMP treatment, the grain growth of Cu of the thick conductor film 6L2 is promoted to improve the EM resistance, and the damage and oxide film generated on the surfaces of the thin conductor film 6L1 and the thick conductor film 6L2 during the CMP treatment are improved. And smooth its surface. At the same time, the surface contamination of the insulating film 4a is removed and reduced. Thereby, the reliability of the wiring can be improved.
[0088]
Next, a method of forming an embedded wiring made of a different conductor material in the same embedded wiring layer will be described with reference to FIGS. This corresponds to the above-described example of a forming method in the case where wirings made of different types of conductive materials exist in the same wiring layer. In the first embodiment, a case where first layer wiring 6L made of a different kind of conductor material is formed in wiring grooves 5a and 5b will be described as a representative example.
[0089]
FIG. 13 is a perspective view of a main part of the interlayer insulating film 4a during the manufacturing process of the semiconductor integrated circuit device. Above the interlayer insulating film 4a, a wiring groove 5a is formed by photolithography and dry etching.
[0090]
Subsequently, as shown in FIG. 14, a thin conductor film 6L1 made of, for example, TiN is deposited on the surface of the interlayer insulating film 4a including the wiring groove 5a by a sputtering method or the like. The thin conductor film 6L1 is made of a material having a function of improving the adhesion between the first layer wiring and the interlayer insulating film 4a and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film, and is limited to TiN. Instead, various changes can be made. For example, tungsten, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN may be used.
[0091]
Thereafter, a thick conductor film 6L2 made of, for example, Cu is deposited on the thin conductor film 6L1 by a CVD method, a sputtering method, a plating method, or the like. In this film formation of Cu or the like, it is desirable to adopt a method with as small an overhang as possible and good step coverage. For example, in the sputtering method, a sputtering apparatus in which the distance between the target and the semiconductor wafer is larger than the radius of the semiconductor wafer is suitable. The thickness of the thick conductor film 6L2 is not limited to Cu but may be variously changed. For example, a Cu alloy, Al, an Al alloy, tungsten, or a tungsten alloy may be used.
[0092]
In the case where the above-described conductor film for wiring is formed by a sputtering method, in particular, by subsequently performing heat treatment on the semiconductor substrate 1, constituent atoms (for example, Cu) of the thick conductor film are fluidized to form a wiring. The constituent atoms are sufficiently supplied and embedded in the groove 5a. At this time, the heat treatment atmosphere is an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or an atmosphere combining two or more of them. Also, a so-called reflow sputtering method in which this heat treatment is performed during the sputtering of Cu may be employed. This makes it possible to improve the EM characteristics of the Cu wiring.
[0093]
Subsequently, the semiconductor substrate 1 is subjected to a CMP process to remove the thick conductor film 6L2 and the thin conductor film 6L1 on the interlayer insulating film 4a in a region other than the wiring groove 5a, as shown in FIG. Next, the first layer wiring 6L is formed in the wiring groove 5a.
[0094]
After or before the CMP process, the semiconductor substrate 1 may be subjected to a heat treatment. At this time, the heat treatment atmosphere is an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or an atmosphere combining two or more of them. In the heat treatment step after the CMP treatment, the grain growth of Cu of the thick conductor film 6L2 is promoted to improve the EM resistance, and the damage and oxide film generated on the surfaces of the thin conductor film 6L1 and the thick conductor film 6L2 during the CMP treatment are improved. And smooth its surface. At the same time, the surface contamination of the insulating film 4a is removed and reduced. Thereby, the reliability of the wiring can be improved.
[0095]
Thereafter, as shown in FIG. 16, a wiring groove 5b narrower or shorter than the wiring groove 5a is formed on the interlayer insulating film 4a by photolithography and dry etching. At this time, the depth of the wiring groove 5b may be the same as that of the wiring groove 5a, or may be set to a depth different from the depth of the wiring groove 5a. For example, as shown in FIG. 17, the depth of the wiring groove 5b may be greater than the depth of the wiring groove 5a. In this case, although the width of the wiring groove 5b is narrow, it is deep, so that the wiring resistance of the conductive film embedded in the wiring groove 5b can be reduced. Alternatively, the wiring groove 5b may be deepened to reach the lower wiring layer or the semiconductor substrate and used for connection.
[0096]
Next, in the same manner as described above, a thin conductor film made of, for example, tungsten or the like is formed on the upper surface of the first layer wiring 6L in the wiring groove 5a and the surface of the interlayer insulating film 4a including the wiring groove 5b by a sputtering method or the like. To adhere. This thin conductor film is made of a material having a function of improving the adhesion between the first layer wiring and the interlayer insulating film 4a and a barrier function of suppressing the diffusion of atoms constituting the thick conductor film, and is not limited to tungsten. For example, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN may be used.
[0097]
Subsequently, a thick conductor film made of, for example, tungsten or the like is deposited on the thin conductor film by a CVD method or the like. In the film formation of tungsten or the like, it is desirable to adopt a method with as small an overhang as possible and good step coverage. This makes it possible to fill the wiring conductor satisfactorily even in the narrow wiring groove 5b or in the wiring groove 5b deeper than the wiring groove 5a as shown in FIG. This thick conductor film is not limited to tungsten, but can be variously changed. For example, a tungsten alloy, Al, or an Al alloy may be used.
[0098]
Then, the semiconductor substrate 1 is subjected to a CMP process to remove the thick conductor film and the thin conductor film in a region other than the wiring groove 5b, thereby obtaining a width wider than the wiring groove 5a as shown in FIG. In the narrow wiring groove 5b, a first layer wiring 6L composed of a thin conductive film 6L1 and a thick conductive film 6L2 made of a different conductive material from the thin conductive film 6L1 and the thick conductive film 6L2 in the wiring groove 5a is formed. I do.
[0099]
As described above, according to the first embodiment, the following effects can be obtained.
[0100]
(1). After filling the fine connection holes 8a to 8f with a conductive film using a CVD method or the like, wiring grooves 5a to 5f having a larger plane dimension than the connection holes 8a to 8f are formed, and the wiring grooves 5a to 5f are formed. A first layer wiring 6L, a connecting conductor 7C, a second layer wiring 9L, a connecting conductor 10C, a third layer wiring 11L, and a connecting conductor 12C having a buried structure were formed by filling the inside with a conductive film. This makes it possible to satisfactorily embed the conductor film in both the wiring grooves 5a to 5f and the finer connection holes 8a to 8f.
[0101]
(2). In the case where the same wiring layer has wiring grooves or the like having different dimensions, by selecting a method that is easy to embed with a fine wiring groove or the like and a larger wiring groove or the like, and burying the conductor film, It is possible to satisfactorily embed the conductive film in both the wiring grooves.
[0102]
(3). According to the above (1) or (2), it is possible to improve the reliability of connection between wiring layers. Therefore, the yield and reliability of the semiconductor integrated circuit device can be improved.
[0103]
(4). According to the above (1) or (2), miniaturization of the embedded wiring can be promoted. Therefore, miniaturization or high integration of the semiconductor integrated circuit device can be promoted.
[0104]
(5). According to the above (1) or (2), the conductor film can be satisfactorily embedded in the wiring grooves 5a to 5f and the connection holes 8a to 8f without employing a difficult technique.
[0105]
(6). According to the above (1) or (2), even when Cu or Cu alloy or the like is used as the embedded wiring material, it is possible to improve the state of the embedded wiring.
[0106]
(7). The connection conductor portion 7C that is in direct contact with the semiconductor substrate 1 is made of a tungsten-based (tungsten or tungsten alloy) conductor material, and the first-layer wiring 6L connected to the connection conductor portion 7C is a low-resistance Cu-based material. By preventing the diffusion of Cu atoms to the semiconductor substrate 1 side while avoiding the state where the conductive film is buried in the connection holes 8a, the connection failure caused by the diffusion phenomenon can be avoided while maintaining a good state of embedding the conductive film in the connection holes 8a. In addition, it is possible to reduce the wiring resistance of the first layer wiring 6L and improve the signal propagation speed.
[0107]
(8). Since the uppermost fourth layer wiring 13L is made of an Al-based (Al or Al alloy) conductive material, it is possible to directly follow the conventional assembling techniques such as a wire bonding technique and a bump electrode forming technique. Therefore, a semiconductor integrated circuit device having a Cu-based embedded wiring can be easily introduced into an assembling process.
[0108]
(9). By providing the connecting conductor portion 14C made of a tungsten-based conductor material between the fourth-layer wire 13L made of an Al-based conductor material and the third-layer wire 11L made of a Cu-based conductor material therebelow, Since the Al-based conductor material and the Cu-based conductor material can be separated by a thick barrier metal, when the Al-based conductor material and the Cu-based conductor material are brought into direct contact, an alloy layer having a high specific resistance is formed at the contact portion. Can be prevented from being formed, so that the resistance between wiring layers can be reduced.
[0109]
(10). By subjecting the semiconductor substrate 1 to a heat treatment after the CMP processing for forming the embedded wiring made of a Cu-based conductor material, the grain growth of Cu is promoted to improve the EM resistance, and at the same time the wiring processing is performed during the CMP processing. The buried wiring made of a Cu-based conductive material can eliminate the damage and oxide film generated on the surface of the conductive film and smooth the surface and remove and reduce the surface contamination of the insulating film exposed during CMP. Can be improved in reliability.
[0110]
(Embodiment 2)
19 to 23 are cross-sectional views of main parts during a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 24 is a cross-sectional view of main parts of the semiconductor integrated circuit device.
[0111]
The second embodiment differs from the first embodiment in the structure of the connecting conductor and the method of forming the same.
[0112]
First, as shown in FIG. 19, after a photoresist pattern 17b for forming a wiring groove is formed on the upper surface of the interlayer insulating film 4a, an etching process is performed using the photoresist pattern 17b as an etching mask. A wiring groove 5a is formed on the upper part of 4a.
[0113]
Subsequently, after removing the photoresist pattern 17b, as shown in FIG. 20, after forming a photoresist pattern 17c for forming a connection hole on the interlayer insulating film 4a, an etching process is performed using the photoresist pattern 17c as an etching mask. Is performed, a connection hole 8a extending from the bottom surface of the wiring groove 5a toward the semiconductor substrate 1 and exposing a part of the upper surface of the semiconductor substrate 1 is formed in the interlayer insulating film 4a.
[0114]
Thereafter, after removing the photoresist pattern 17c, as shown in FIG. 21, a connection conductor portion 7C made of, for example, tungsten or the like is formed in the connection hole 8a by a selective CVD method or the like. At this time, the upper part of the connection conductor 7C may protrude into the wiring groove 5a. Further, the material of the connecting conductor 7C is not limited to tungsten, but may be variously changed, and may be, for example, a tungsten alloy, Al, or an Al alloy.
[0115]
Next, as shown in FIG. 22, a thin conductor film 6L1 made of, for example, TiN is deposited on the surface of the interlayer insulating film 4a including the wiring groove 5a and the exposed surface of the connection conductor portion 7C by a sputtering method or the like. The thin conductor film 6L1 is made of a material having a function of improving the adhesion between the first layer wiring and the interlayer insulating film 4a and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film, and is limited to TiN. Instead, various changes can be made. For example, tungsten, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN may be used.
[0116]
Subsequently, a thick conductor film 6L2 made of, for example, Cu is deposited on the thin conductor film 6L1 by a CVD method, a sputtering method, a plating method, or the like. In this film formation of Cu or the like, it is desirable to adopt a method with as small an overhang as possible and good step coverage. For example, in the sputtering method, a sputtering apparatus in which the distance between the target and the semiconductor wafer is larger than the radius of the semiconductor wafer is suitable. The thickness of the thick conductor film 6L2 is not limited to Cu but may be variously changed. For example, a Cu alloy, Al, an Al alloy, tungsten, or a tungsten alloy may be used.
[0117]
In the case where the above-described conductor film for wiring is formed by a sputtering method, in particular, by subsequently performing heat treatment on the semiconductor substrate 1, constituent atoms (for example, Cu) of the thick conductor film are fluidized to form a wiring. The constituent atoms are sufficiently supplied and embedded in the groove 5a. At this time, the heat treatment atmosphere is an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or an atmosphere combining two or more of them. Also, a so-called reflow sputtering method in which this heat treatment is performed during the sputtering of Cu may be employed. This makes it possible to improve the EM characteristics of the Cu wiring.
[0118]
Subsequently, the semiconductor substrate 1 is subjected to a CMP process to remove the thick conductor film 6L2 and the thin conductor film 6L1 on the interlayer insulating film 4a in a region other than the wiring groove 5a, as shown in FIG. Next, the first layer wiring 6L is formed in the wiring groove 5a.
[0119]
After or before the CMP process, the semiconductor substrate 1 may be subjected to a heat treatment. At this time, the heat treatment atmosphere is an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or an atmosphere combining two or more of them. In the heat treatment step after the CMP treatment, the grain growth of Cu of the thick conductor film 6L2 is promoted to improve the EM resistance, and the damage and oxide film generated on the surfaces of the thin conductor film 6L1 and the thick conductor film 6L2 during the CMP treatment are improved. And smooth its surface. At the same time, the surface contamination of the insulating film 4a is removed and reduced. Thereby, the reliability of the wiring can be improved.
[0120]
Such an embedded wiring structure may be applied to the second-layer wiring 9L as shown in FIG. That is, the connection conductor portion 10C has a structure made of a conductor film made of, for example, tungsten, a tungsten alloy, Al, an Al alloy, Cu, or a Cu alloy formed by a selective CVD method.
[0121]
According to the second embodiment, the same effects as those of the first embodiment can be obtained.
[0122]
(Embodiment 3)
25 to 28 and FIGS. 29 to 32 are cross-sectional views of main parts of a semiconductor integrated circuit device according to another embodiment of the present invention during the manufacturing process, and FIG. 33 is a cross-sectional view of main parts of the semiconductor integrated circuit device. .
[0123]
FIG. 25 shows the semiconductor integrated circuit device during the manufacturing process. In the interlayer insulating film 4a, the wiring groove 5a and the connection hole 8a are formed by the method described in the second embodiment.
[0124]
First, in the third embodiment, as shown in FIG. 26, a connection conductor 7C made of, for example, tungsten or the like is formed in the connection hole 8a by a selective CVD method. At this time, in the third embodiment, the film forming process is performed to such an extent that the upper portion of the connecting conductor portion 7C projects outside the wiring groove 5a. Further, the material of the connecting conductor 7C is not limited to tungsten, but may be variously changed, and may be, for example, a tungsten alloy, Al, or an Al alloy.
[0125]
Next, as shown in FIG. 27, a thin conductor film 6L1 made of, for example, TiN or the like is formed on the surface of the interlayer insulating film 4a including the wiring groove 5a and the surface of the connection conductor 7C by a sputtering method or the like. The thin conductor film 6L1 is made of a material having a function of improving the adhesion between the first layer wiring and the interlayer insulating film 4a and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film, and is limited to TiN. Instead, various changes can be made. For example, tungsten, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN may be used.
[0126]
Subsequently, a thick conductor film 6L2 made of, for example, Cu is deposited on the thin conductor film 6L1 by a CVD method, a sputtering method, a plating method, or the like. In this film formation of Cu or the like, it is desirable to adopt a method with as small an overhang as possible and good step coverage. For example, in the sputtering method, a sputtering apparatus in which the distance between the target and the semiconductor wafer is larger than the radius of the semiconductor wafer is suitable. The thickness of the thick conductor film 6L2 is not limited to Cu but may be variously changed. For example, a Cu alloy, Al, an Al alloy, tungsten, or a tungsten alloy may be used.
[0127]
In the case where the above-described conductor film for wiring is formed by a sputtering method, in particular, by subsequently performing heat treatment on the semiconductor substrate 1, constituent atoms (for example, Cu) of the thick conductor film are fluidized to form a wiring. The constituent atoms are sufficiently supplied and embedded in the groove 5a. At this time, the heat treatment atmosphere is an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or an atmosphere combining two or more of them. Also, a so-called reflow sputtering method in which this heat treatment is performed during the sputtering of Cu may be employed. Thereby, the EM resistance of the Cu wiring can be improved.
[0128]
Subsequently, the semiconductor substrate 1 is subjected to a CMP process to remove the thick conductor film 6L2 and the thin conductor film 6L1 on the interlayer insulating film 4a in a region other than the wiring groove 5a, as shown in FIG. Next, the first layer wiring 6L is formed in the wiring groove 5a, and the connection conductor 7C is formed.
[0129]
After or before the CMP process, the semiconductor substrate 1 may be subjected to a heat treatment. At this time, the heat treatment atmosphere is an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or an atmosphere combining two or more of them. In the heat treatment step after the CMP treatment, the grain growth of Cu of the thick conductor film 6L2 is promoted to improve the EM resistance, and the damage and oxide film generated on the surfaces of the thin conductor film 6L1 and the thick conductor film 6L2 during the CMP treatment are improved. And smooth its surface. At the same time, the surface contamination of the insulating film 4a is removed and reduced. Thereby, the reliability of the wiring can be improved.
[0130]
Further, in order to form a buried wiring like the structure of FIG. 28, for example, the following may be performed.
[0131]
First, as shown in FIG. 29, a connection hole 8a that exposes a part of the upper surface of the semiconductor substrate 1 is formed in the interlayer insulating film 4a by a photolithography technique and a dry etching technique.
[0132]
Subsequently, as shown in FIG. 30, a connection conductor 7C made of, for example, tungsten or the like is formed in the connection hole 8a by a selective CVD method. At this time, the film forming process is performed so that the upper surface of the connecting conductor portion 7C substantially coincides with the upper surface of the interlayer insulating film 4a. Further, the material of the connecting conductor 7C is not limited to tungsten, but may be variously changed, and may be, for example, a tungsten alloy, Al, or an Al alloy.
[0133]
Thereafter, as shown in FIG. 31, a wiring groove 5a is formed in the interlayer insulating film 4a by photolithography and dry etching. At this time, the upper portion of the connecting conductor 7C is exposed in the wiring groove 5a.
[0134]
Next, as shown in FIG. 32, a thin conductor film 6L1 made of, for example, TiN is deposited on the surface of the interlayer insulating film 4a including the wiring groove 5a and the exposed surface of the connection conductor 7C by a sputtering method or the like. The thin conductor film 6L1 is made of a material having a function of improving the adhesion between the first layer wiring and the interlayer insulating film 4a and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film, and is limited to TiN. Instead, various changes can be made. For example, tungsten, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN may be used.
[0135]
Subsequently, a thick conductor film 6L2 made of, for example, Cu is deposited on the thin conductor film 6L1 by a CVD method, a sputtering method, a plating method, or the like. In this film formation of Cu or the like, it is desirable to adopt a method with as small an overhang as possible and good step coverage. For example, in the sputtering method, a sputtering apparatus in which the distance between the target and the semiconductor wafer is larger than the radius of the semiconductor wafer is suitable. The thickness of the thick conductor film 6L2 is not limited to Cu but may be variously changed. For example, a Cu alloy, Al, an Al alloy, tungsten, or a tungsten alloy may be used.
[0136]
In the case where the above-described conductor film for wiring is formed by a sputtering method, in particular, by subsequently performing heat treatment on the semiconductor substrate 1, constituent atoms (for example, Cu) of the thick conductor film are fluidized to form a wiring. The constituent atoms are sufficiently supplied and embedded in the groove 5a. At this time, the heat treatment atmosphere is an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or an atmosphere combining two or more of them. Also, a so-called reflow sputtering method in which this heat treatment is performed during the sputtering of Cu may be employed.
[0137]
Subsequently, the semiconductor substrate 1 is subjected to a CMP process to remove the thick conductor film 6L2 and the thin conductor film 6L1 on the interlayer insulating film 4a in a region other than the wiring groove 5a, as shown in FIG. As described above, the first-layer wiring 6L is formed in the wiring groove 5a, and the connection conductor 7C is formed.
[0138]
After or before the CMP process, the semiconductor substrate 1 may be subjected to a heat treatment. At this time, the heat treatment atmosphere is an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or an atmosphere combining two or more of them. In this heat treatment step, the EM resistance is improved by promoting the growth of Cu grains of the thick conductor film 6L2, and the damage and oxide film generated on the surfaces of the thin conductor film 6L1 and the thick conductor film 6L2 during the CMP treatment are eliminated. To smooth out. At the same time, the surface contamination of the insulating film 4a is removed and reduced. Thereby, the reliability of the wiring can be improved.
[0139]
Note that such an embedded wiring structure may be applied to the second layer wiring 9L as shown in FIG. That is, the connection conductor portion 10C has a structure made of a conductor film made of, for example, tungsten, a tungsten alloy, Al, or an Al alloy formed by a selective CVD method.
[0140]
As described above, according to the third embodiment, the same effects as those of the first embodiment can be obtained.
[0141]
(Embodiment 4)
FIGS. 34 and 35 are cross-sectional views of main parts of a semiconductor integrated circuit device according to another embodiment of the present invention.
[0142]
In the fourth embodiment, as shown in FIGS. 34 and 35, the connection conductors 7C and 10C are formed of thin conductor films 7C1 and 10C1. That is, the structure is such that the connection holes 8a and 8b are buried with the thin conductor films 7C1 and 10C1. The thin conductor films 7C1 and 10C1 are made of a material having a function of improving adhesion between the connection conductor portions 7C and 10C and the interlayer insulating films 4a and 4b and a barrier function of suppressing diffusion of wiring constituent atoms. , TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN.
[0143]
The diameter of the connection hole 8a is, for example, about 0.1 to 0.4 μm, and preferably, for example, about 0.2 μm. Further, the aspect ratio of the connection hole 8a is preferably about 2 to 10, and is preferably smaller than about 5 in consideration of satisfactorily embedding the connection conductor.
[0144]
The diameter of the connection hole 8b is, for example, about 0.1 to 0.4 μm, preferably, for example, about 0.2 μm. Further, the aspect ratio of the connection hole 8b is preferably about 2 to 10, and is preferably smaller than about 5 in consideration of satisfactorily embedding the connection conductor.
[0145]
Further, the structure of the wiring is not limited to the structure shown in FIGS. 33 and 34, and may be variously changed. For example, the structure shown in FIGS. 3 to 5 described in the first embodiment may be adopted.
[0146]
The method of forming such a buried wiring is the same as that described with reference to FIGS. That is, the method of forming the first layer wiring 6L is as follows, as an example.
[0147]
First, after forming a connection hole 8a in the interlayer insulating film 4a, a thin conductor film 7C1 is deposited on the interlayer insulating film 4a by a sputtering method or the like so as to fill the connection hole 8a. Subsequently, by applying a CMP method or the like to the semiconductor substrate 1, a portion other than the region of the connection hole 8 a in the thin conductor film 7 C 1 is removed, and a connection consisting of only the thin conductor film 7 C 1 is formed in the connection hole 8 a. The conductor portion 7C is formed. Then, after forming a wiring groove 5a in the interlayer insulating film 4a, a wiring conductive film is deposited on the interlayer insulating film 4a by a sputtering method, a CVD method, a plating method, or the like so as to fill the wiring groove 5a. After that, the semiconductor substrate 1 is subjected to a CMP method or the like, thereby removing a portion other than the region of the wiring groove 5a in the wiring conductor film to form the first layer wiring 6L in the wiring groove 5a. .
[0148]
The heat treatment may be performed on the semiconductor substrate 1 after the formation of the thick conductor film 6L1 or after the CMP process. At this time, the heat treatment atmosphere is an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or an atmosphere combining two or more of them. By performing the heat treatment, the grain growth of Cu of the thick conductor film 6L2 is promoted to improve the EM resistance, and at the same time, the damage and the oxide film generated on the surfaces of the thin conductor film 6L1 and the thick conductor film 6L2 during the CMP process are eliminated. Since the surface can be smoothed and the surface contamination of the insulating film 4a can be removed and reduced, the reliability of the wiring can be improved.
[0149]
According to the fourth embodiment, the same effects as those of the first embodiment can be obtained.
[0150]
(Embodiment 5)
36 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention, FIG. 37 is an enlarged cross-sectional view of a main part of the semiconductor integrated circuit device of FIG. 36, and FIG. 38 is a semiconductor integrated circuit shown in FIG. FIG. 39 is an enlarged cross-sectional view of a main part showing a modification of the main part of the circuit device. FIG. 39 is an enlarged cross-sectional view of the main part of the semiconductor integrated circuit device shown in FIG. 37. FIGS. 40 and 41 are semiconductor integrated circuit devices shown in FIG. 42 is an explanatory view schematically showing the main part of the semiconductor integrated circuit device in FIG. 39, FIG. 43 is an explanatory view schematically showing a modification of FIG. 42, FIG. 44 and FIG. 45 is an explanatory view schematically showing a modified example of FIG. 42, and FIGS. 46 to 50 are enlarged cross-sectional views of main parts showing modified examples of main parts of the semiconductor integrated circuit device of FIG. First, the structure of the semiconductor integrated circuit device according to the fifth embodiment will be described with reference to FIGS. The basic overall structure of the fifth embodiment is as follows, for example.
[0151]
First, as a constituent material of the first layer wiring 6L, a conductive material other than Cu or Cu alloy such as tungsten, tungsten alloy, Al or Al alloy is used. As a result, a structure in which the Cu wiring is not brought into direct contact with the semiconductor substrate 1 can be achieved, so that element failure due to diffusion of Cu atoms to the semiconductor substrate 1 side can be suppressed, and the reliability of the semiconductor integrated circuit device can be reduced. It is possible to improve the performance. Further, by increasing the distance between the second and third layer wirings 9L and 11L formed of Cu wiring and the semiconductor substrate 1, diffusion of Cu atoms into the semiconductor substrate 1 can be reduced.
[0152]
Second, for example, Al or an Al alloy is used as a constituent material of the uppermost fourth-layer wiring 13L. This allows the conventional bonding wire connection technology and bump electrode formation technology to be directly followed. That is, the bonding wire and the bump electrode are connected to the uppermost wiring layer. However, by using the conventionally used Al or Al alloy as the uppermost wiring material, the conventional technology for bonding the bonding wire and the bump electrode can be improved. It can be used as it is. Therefore, it is possible to introduce a semiconductor integrated circuit device having a buried wiring structure made of a Cu-based material into an assembly line without any technical change in an assembling process (a wire bonding process or a bump electrode forming process). Become. Therefore, it is possible to promote the cost reduction of a semiconductor integrated circuit device having a buried wiring made of a Cu-based material, and to promote a reduction in manufacturing and development time.
[0153]
Thirdly, for example, Cu or a Cu alloy is used as a constituent material of an intermediate wiring layer (second-layer wiring 9L and third-layer wiring 11L) between the uppermost wiring layer and the lowermost wiring layer. As a result, the wiring resistance and the wiring capacitance can be reduced, the signal propagation speed in the semiconductor integrated circuit device can be improved, and the operation speed can be improved.
[0154]
Fourth, the connection conductors 18C and 19C for connecting the wiring layers made of a Cu-based material are made of a material made of, for example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN, or the like. . As a result, the conductive film can be satisfactorily embedded in the fine connection holes 8g and 8h, so that the reliability of the electrical connection between the wiring layers can be improved.
[0155]
Fifth, the fourth-layer wiring 13L made of an Al-based material and the third-layer wiring 11L made of a Cu-based material are not directly in contact with each other, but a barrier layer (such as the connecting conductor 20C) is interposed therebetween. Thus, when the Al-based material and the Cu-based material are in direct contact, a phenomenon that an alloy layer having a high specific resistance is formed can be suppressed, and thus the propagation speed of a signal flowing through the wiring can be improved. It becomes possible.
[0156]
Sixth, in the wiring layer located at the portion where the connecting conductor portions 19C and 20C are connected, the wiring layer is at least more planar than the connecting conductor portions 19C and 20C along the longitudinal direction of the wiring. The connecting conductor portion (relay connecting conductor portion) 21C formed long in the above was provided, and the above-described connecting conductor portion 19C and the connecting conductor portion 20C were electrically connected. Thereby, the plane area of the connection groove 5g in which the connection conductor portion 21C is formed can be made relatively large, so that the wiring conductor film can be satisfactorily embedded in the groove. In addition, it is possible to increase a margin for planar alignment in the longitudinal direction of the wiring between the connecting conductor 19C and the connecting conductor 20C. Therefore, it is possible to improve the connection reliability of the upper and lower connection conductors 19C and 20C.
[0157]
Next, each component of the semiconductor integrated circuit device according to the fifth embodiment will be described in detail.
[0158]
The first layer wiring 6L formed by being buried in the wiring grooves 5a and 5b includes a relatively thin conductor film 6L1 at the lower and side portions, and a relatively thick conductor film surrounded by the thin conductor film 6L1. 6L2. The thin conductor film 6L1 is made of a material having a function of improving the adhesion between the first-layer wiring 6L and the interlayer insulating film 4a and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film 6L2, for example, tungsten, TiN, It is made of Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN or the like. When the thin conductor film 6L1 is made of tungsten or the like, the wiring resistance can be reduced as compared with the case where the thin conductor film 6L1 is made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. Although not particularly limited, in the fifth embodiment, the thin conductor film 6L1 is made of, for example, tungsten.
[0159]
The thick conductor film 6L2 is a member constituting the main body of the first-layer wiring 6L, and is made of a low-resistance material such as Al, an Al alloy, tungsten, or a tungsten alloy. Although not particularly limited, in the fifth embodiment, the thick conductor film 6L2 is made of, for example, tungsten.
[0160]
However, the structure of the first layer wiring 6L is not limited to the structure shown in FIGS. 36 and 37, and can be variously changed. The structure described in the first embodiment with reference to FIGS. May be. That is, a structure in which a cap conductor film is provided on the thick conductor film 6L2 and the thin conductor film 6L1, a cap conductor film is provided on the thick conductor film 6L2, and the upper surface of the cap conductor film almost coincides with the upper surface of the interlayer insulating film 4a. There is a structure in which a wiring is constituted only by the thick conductor film 6L2, and a structure in which a cap conductor film is provided on the upper surface when a wiring is constituted only by the thick conductor film 6L2. The cap conductor film is made of, for example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN.
[0161]
The first layer wiring 6L of the wiring groove 5a is electrically connected to the semiconductor region 3nd of the nMOS 3n or the semiconductor region 3pd of the pMOS 3p through the connection hole 8a. In the fifth embodiment, a wiring-forming conductor film is integrally embedded in the wiring groove 5a and the connection hole 8a.
[0162]
The method for forming the first layer wiring 6L is the same as, for example, the following method for forming a buried wiring. That is, after the wiring grooves 5a and 5b and the connection holes 8a are formed in the interlayer insulating film 4a by separate photolithography and dry etching techniques, a thin conductor film 6L1 made of, for example, tungsten or the like is deposited by sputtering. On the thin conductive film 6L1, a thick conductive film 6L2 made of, for example, tungsten is formed by a CVD method or the like. As a result, it is possible to satisfactorily embed the conductive film in the fine connection hole 8a. After that, the conductor film other than the wiring grooves 5a and 5b and the connection hole 8a is removed by performing a CMP process to form a first layer wiring 6L having a buried structure.
[0163]
The second layer wiring 9L buried in the wiring grooves 5c and 5d is formed of a relatively thin conductor film 9L1 at the lower and side portions and a relatively thick conductor film surrounded by the thin conductor film 9L1. 9L2. The thin conductor film 9L1 is made of a material having a function of improving adhesion between the second-layer wiring 9L and the interlayer insulating film 4b and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film 9L2, for example, tungsten, TiN, It is made of Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN or the like. When the thin conductor film 9L1 is made of tungsten or the like, the wiring resistance can be reduced as compared with the case where the thin conductor film 9L1 is made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. Although not particularly limited, in the fifth embodiment, the thin conductor film 9L1 is made of, for example, TiN.
[0164]
The thick conductor film 9L2 is a member constituting the main body of the second-layer wiring 9L, and is made of a low-resistance material such as Cu or a Cu alloy. However, the structure of the second layer wiring 9L is not limited to the structure shown in FIG. 36, and can be variously changed, and may have the structure described in the first embodiment with reference to FIGS. . That is, a structure in which a cap conductor film is provided on the thick conductor film 9L2 and the thin conductor film 9L1, a cap conductor film is provided on the thick conductor film 9L2, and the upper surface of the cap conductor film almost coincides with the upper surface of the interlayer insulating film 4b. There is a structure in which a wiring is constituted only by the thick conductor film 9L2, and a structure in which a cap conductor film is provided on the upper surface when a wiring is constituted only by the thick conductor film 9L2. The cap conductor film is made of, for example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN.
[0165]
The second layer wiring 9L in the wiring groove 5c is electrically connected to the first layer wiring 6L through the connection hole 8g. The connection hole 8g is formed so that a part of the upper surface of the first layer wiring 6L is exposed from the bottom surface of the wiring groove 5c toward the upper surface of the first layer wiring 6L. For example, a connection conductor 18C made of tungsten, a tungsten alloy, Al, an Al alloy, or the like is provided.
[0166]
The third-layer wiring 11L formed by being buried in the wiring groove 5e has the same structure as the second-layer wiring 9L, and has a relatively thin lower and side conductor film 11L1 and a thinner conductor film 11L1. And a relatively thick conductor film 11L2 surrounded by the film 11L1. The thin conductor film 11L1 is made of a material having a function of improving the adhesion between the third-layer wiring 11L and the interlayer insulating film 4c and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film 11L2, such as tungsten, TiN, or the like. It is made of Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN or the like.
[0167]
When the thin conductor film 11L1 is made of tungsten or the like, the wiring resistance can be reduced as compared with the case where it is made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN, or the like. Although not particularly limited, in the fifth embodiment, the thin conductor film 11L1 is made of, for example, TiN.
[0168]
The thick conductor film 11L2 is a member constituting the main body of the third-layer wiring 11L, and is made of a low-resistance material such as Cu or a Cu alloy. However, the structure of the third layer wiring 11L is not limited to the structure shown in FIG. 36, and can be variously changed, and may have the structure described in the first embodiment with reference to FIGS. . That is, a structure in which a cap conductor film is provided on the thick conductor film 11L2 and the thin conductor film 11L1, a cap conductor film is provided on the thick conductor film 11L2, and the upper surface of the cap conductor film almost coincides with the upper surface of the interlayer insulating film 4b. There is a structure in which a wiring is constituted only by the thick conductor film 11L2, a structure in which a cap conductor film is provided on the upper surface when a wiring is constituted only by the thick conductor film 11L2, and the like. The cap conductor film is made of, for example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN.
[0169]
The third layer wiring 11L in the wiring groove 5e is electrically connected to the second layer wiring 9L through the connection hole 8h. The connection hole 8h is formed such that a part of the upper surface of the second layer wiring 9L is exposed from the bottom surface of the wiring groove 5e toward the upper surface of the second layer wiring 9L. For example, a connection conductor 19C made of tungsten, a tungsten alloy, Al, an Al alloy, or the like is provided. As shown in FIG. 39 described later, the second layer wiring 9L is provided to extend in, for example, the Y direction, and the pitch between the second layer wirings 9L is designed to have a predetermined value in the X direction. The third layer wiring 11L is provided to extend in, for example, the X direction perpendicular to the Y direction, and the pitch P between the third layer wirings 11L is designed to have a predetermined value in the Y direction.
[0170]
The method for forming the second-layer wiring 9L and the third-layer wiring 11L is the same as, for example, the conventional method for forming a buried wiring. That is, a method of forming the second layer wiring 9L will be described as an example as follows.
[0171]
First, the wiring grooves 5c and 5d and the connection holes 8g are formed in the interlayer insulating film 4b by separate photolithography and dry etching techniques, and then a conductor film made of, for example, tungsten is formed in the connection holes 8g by a selective CVD method or the like. The connection conductor portion 18C is formed by selective growth.
[0172]
Subsequently, a thin conductive film 9L1 made of, for example, TiN or the like is applied by sputtering, and a thick conductive film 9L2 made of, for example, Cu or a Cu alloy is formed on the thin conductive film 9L1 by sputtering, CVD, or the like. It is formed by a plating method or the like. After this step, heat treatment may be performed to satisfactorily fill the wiring trenches 5c and 5d with Cu atoms. This makes it possible to satisfactorily embed the conductor film in the fine connection hole 8g.
[0173]
Thereafter, the semiconductor substrate 1 is subjected to a CMP process to remove the conductor film other than the wiring grooves 5c and 5d, thereby forming a second layer wiring 9L having a buried structure. Heat treatment may be performed on the semiconductor substrate 1 after the formation of the thick conductor film 9L2 or after the CMP process. At this time, the heat treatment atmosphere is an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or an atmosphere combining two or more of them. By performing the heat treatment, the grain growth of Cu of the thick conductor film 9L2 is promoted to improve the EM resistance, and the damage and the oxide film generated on the surfaces of the thin conductor film 6L1 and the thick conductor film 9L2 during the CMP process are eliminated. Since the surface can be made smooth and the surface contamination of the insulating film 4a can be removed and reduced, the reliability of the wiring can be improved.
[0174]
However, the embedded structure of the connection holes 8g and 8h is not limited to the structure shown in FIG. 36 and the like, and can be variously changed. For example, the structure shown in FIG. 38 may be used. That is, in FIG. 38, the connection holes 8g and 8h are filled with the thin conductor films 9L1 and 11L1. The constituent material of the thin conductive film 11L1 in this case is the same as the above-mentioned material, and is made of, for example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN, or the like. The thick conductor films 9L2 and 11L2 are made of, for example, Cu or Cu alloy.
[0175]
In addition, the connection holes 8g and 8h may be formed of a relatively thin conductor film at the lower and side portions thereof and a relatively thick conductor film surrounded by the thin conductor film. In this case, the thin conductor film is made of, for example, tungsten, TiN, or the like. The thick conductor film is made of, for example, tungsten or the like.
[0176]
On the other hand, in the upper part (third wiring layer) of the interlayer insulating film 4c, the above-described wiring groove 5e and a connection groove 5g having the same depth as the wiring groove 5e are formed. The connection groove 5g is formed simultaneously with the wiring groove 5e.
[0177]
As described above, the connection groove 5g is formed to be long along the longitudinal direction of the wiring. This makes it possible to satisfactorily embed the conductor film in the connection groove 5g. That is, when the conductor film is buried in the wiring groove 5e at the same time when the conductor film is buried also in the connection groove 5g in the same wiring layer, the planar shape and dimensions of the connection groove 5g are changed to those of the lower connection conductor portion 19C. If the upper surface has a planar shape and dimensions, the connection groove 5g is so fine that the conductor film may not be sufficiently buried. In order to avoid such inconvenience, the connection groove 5g is formed so that its planar shape becomes longer along the longitudinal direction of the wiring, thereby preventing the mounting density of the wiring from lowering and preventing the conductive film from being lowered. Can be satisfactorily embedded. Therefore, it is possible to satisfactorily connect the upper and lower wiring layers.
[0178]
As shown in FIG. 36, FIG. 40 and FIG. 41, a connecting conductor 21C is provided in the connecting groove 5g. 39 is a plan view of a main part showing a part of the second-layer wiring 9L to the fourth-layer wiring 13L, FIG. 40 is a cross-sectional view of the main part along line BB in FIG. 39, and FIG. It is principal part sectional drawing along CC line. FIG. 40 is a cross-sectional view of the right-side second-layer wiring 9L to fourth-layer wiring 13L in FIG. 36 cut in a direction perpendicular to the paper surface.
[0179]
The connecting conductor 21C has the same structure as the third-layer wiring 11L, and has a relatively thin lower and side conductor film 21C1 and a relatively thick conductor film 21C2 surrounded by the thin conductor film 21C1. It is composed of That is, the connecting conductor portion 21C is configured by the same wiring W as the third layer wiring 11L. The thin conductor film 21C1 is made of a material having a function of improving adhesion between the connection conductor portion 21C and the interlayer insulating film 4c and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film 21C2. It is made of Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN or the like.
[0180]
When the thin conductor film 21C1 is made of tungsten or the like, the wiring resistance can be reduced as compared with the case where the thin conductive film 21C1 is made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN, or the like. Although not particularly limited, in the fifth embodiment, the thin conductor film 21C1 is formed of the same material at the same time as the thin conductor film 11L1 of the third-layer wiring 111L, and is made of, for example, TiN.
[0181]
The thick conductor film 21C2 is a member constituting the main body of the connection conductor 21C, and is made of a low-resistance material such as Cu or a Cu alloy. However, the structure of the connecting conductor portion 21C is not limited to the structure shown in FIGS. 36 to 43, and can be variously changed, and the structure described in the first embodiment with reference to FIGS. May be.
[0182]
That is, a structure in which a cap conductor film is provided on the thick conductor film 21C2 and the thin conductor film 21C1, a cap conductor film is provided on the thick conductor film 21C2, and the upper surface of the cap conductor film almost coincides with the upper surface of the interlayer insulating film 4c. There is a structure in which a wiring is constituted only by the thick conductor film 21C2, a structure in which a cap conductor film is provided on the upper surface when a wiring is constituted only by the thick conductor film 21C2, and the like. The cap conductor film is made of, for example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. As shown in FIG. 39 and FIG. 42, by configuring the planar shape of the connecting conductor portion 21C such that the longitudinal direction (X direction) of the wiring is larger than the wiring width in the Y direction, the upper and lower connecting conductors are formed. The positioning margin of the portions 19C and 20C can be increased in the X direction. Thereby, the positioning margin of the upper and lower connection conductors 19C and 20C can be increased in the X direction without increasing the wiring pitch P of the third layer wiring 11L in the Y direction, so that the wiring density can be increased. And high integration can be realized. In addition, the wiring length in the longitudinal direction of the wiring is equal to or longer than the wiring width, and by setting the wiring width to about twice or less the wiring width, the alignment margin can be increased without using a dock bone, and the embedding margin can be increased. There is no need to increase the wiring pitch, and high integration can be achieved.
[0183]
Further, as shown in FIG. 43, the planar shape of the connection conductor 21C may be such that it becomes longer in the longitudinal direction of the wiring and in a direction intersecting the wiring direction (the wiring width direction, ie, the Y direction). good. However, also in this case, the configuration is such that the longitudinal direction (X direction) of the wiring is larger than the wiring width in the Y direction. In this case, the alignment margin of the upper and lower connection conductors 19C and 20C can be increased in both the longitudinal direction and the width direction of the wiring. For this reason, since the positioning accuracy at the time of forming the connection hole 8f for embedding the connection conductor portion 20C can be eased, the connection hole 8f can be easily formed. Further, even if the plane position of the connection hole 8f is slightly shifted from the design value, the connection conductor 20C and the connection conductor 21C can be connected well.
[0184]
Further, as shown in FIGS. 44 and 45, the structure described in the first embodiment may be adopted. That is, the connection conductor portion 19C has a structure in which an upper portion protrudes into the connection conductor portion 21C. In this case, it is formed by the same method as described in the first embodiment and the like. That is, after the connection conductor 19C is buried in the connection hole 8h (see FIG. 36) formed in the interlayer insulating film 4c, the connection groove 5g (see FIG. 36) is formed, and then the conductor film is deposited. Then, a CMP process is further performed to form the connection conductor 21C in the connection groove 5g.
[0185]
The fourth layer wiring 13L has a normal wiring structure as in the first embodiment. The fourth layer wiring 13L is electrically connected to the third layer wiring 11L or the connecting conductor 21 through the connecting conductor 20C in the connection hole 8f. The connection conductor 20C is made of, for example, tungsten or a tungsten alloy formed by a selective CVD method.
[0186]
That is, in the fifth embodiment, the fourth-layer wiring 13L made of an Al-based material does not directly contact the third-layer wiring 11L or the connecting conductor 21C made of a Cu-based material, but is made of a tungsten-based material. It is structured to be electrically connected via the connecting conductor 20C. Thus, the structure is such that it is possible to prevent direct contact between Al and Cu and prevent an alloy layer having a high specific resistance from being formed at the contact portion.
[0187]
However, the structure for preventing the formation of such an alloy layer is not limited to the structure shown in FIG. 36, and various changes can be made, and the structures shown in FIGS. 46 to 54 may be used. That is, FIG. 46 shows a structure in which the fourth-layer wiring 13L is constituted by the thin conductor film 13L1 and the thick conductor film 13L2 stacked thereover. The thin conductor film 13L1 is made of a material having a function of improving the adhesion between the fourth-layer wiring 13L and the interlayer insulating film 4d and a barrier function of suppressing diffusion of constituent atoms of the thick conductor film 13L2, for example, tungsten (W). , TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. The thick conductor film 13L2 is made of, for example, Al or an Al alloy.
[0188]
In the structure of FIG. 47, a connection conductor portion 20C1 made of, for example, tungsten or a tungsten alloy formed by a selective CVD method or the like is provided on an exposed surface of the third layer wiring 11L exposed from the connection hole 8f, and In the connection hole 8f, a connection conductor 20C2 made of, for example, Al or an Al alloy is provided on the connection conductor 20C1. The third-layer wiring 13L is electrically connected to the third-layer wiring 11L through the connecting conductor portion 20C (20C2, 20C1). The third-layer wiring 13L and the connection conductor 20C may be formed simultaneously. That is, in this structure, the contact portion between the fourth-layer wiring 13L and the connecting conductor 20C2 made of an Al-based material and the third-layer wiring 11L made of a Cu-based material is connected to the connecting conductor 20C1 made of tungsten or the like. It has a structure provided. This can prevent an alloy layer having a high specific resistance from being formed at the contact portion. In addition, since the connecting conductor 20C2 that constitutes most of the connecting conductor 20C is made of a low-resistance Al-based material, compared to the structure of FIG. 36 in which all of the connecting conductors are made of tungsten or the like. It is possible to reduce the resistance of all the connecting conductors 20C.
[0189]
In the structure of FIG. 48, a cap conductor film 11L3 is provided above the second layer wiring 11L. The cap conductor film 11L3 is made of, for example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. The thick conductor film 13L2 is made of, for example, Al or an Al alloy. In the connection hole 8f, a conductor film made of Al or an Al alloy or the like formed integrally with the fourth layer wiring 13L is embedded. Also in this case, a thin conductor film 11L3 made of tungsten or the like is provided at a contact portion between the fourth layer wiring 13L made of an Al-based material and the third layer wiring 11L made of a Cu-based material. Since the formation of an alloy layer having a high specific resistance can be prevented and the inside of the connection hole 8f is filled with a low-resistance Al-based material, the resistance of the interlayer connection portion can be reduced as compared with the case of FIG. Is possible.
[0190]
In the structure of FIG. 49, the connection hole 8f is buried with a thin conductor film 13L1. The constituent material of the thin conductor film 13L1 in this case is the same as the above-mentioned material, and is made of, for example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN, or the like. The thick conductor film 13L2 is made of, for example, Al or an Al alloy.
[0191]
In the structure of FIG. 50, in the structure of FIG. 49, thick conductor films 13L2a and 13L2b are stacked on a thin conductor film 13L1 in order from the bottom. The lower thick conductive film 13L2a is made of, for example, tungsten or a tungsten alloy, and is formed by, for example, a CVD method or a sputtering method. The upper conductor film 13L2b on the upper layer side is made of, for example, Al or an Al alloy, and is formed by, for example, a CVD method or a sputtering method.
[0192]
In the structure of FIG. 51, a connection conductor portion 14C for connecting the fourth layer wiring 13L, BP made of Al and the third layer wiring 11L made of Cu is made of tungsten (W) formed by, for example, a sputtering method. It comprises a barrier metal (thin conductor film) 14C1 such as TiN and a plug (thick conductor film) 14C2 such as tungsten (W) formed by CVD. With this structure, the contact resistance can be reduced.
[0193]
In this structure, after a barrier metal is deposited by, for example, a sputtering method, tungsten (W) is deposited by, for example, a CVD method so as to be embedded in the connection hole 8f, and thereafter, the barrier metal 14C1 and the plug 14C2 are connected by CMP or etch back. It can be formed only in the hole 8f. Further, the connecting conductor portion 14C may be composed of only the plug 14C2 in which TiN is embedded by, for example, a CVD method.
[0194]
In the structure of FIG. 52, in the structure of FIG. 51, the fourth layer wirings 13L and BP are formed by forming a thick conductor film 13L2 made of an Al-based material and a thin film formed of a refractory metal or a metal compound such as TiN or tungsten (W). And the conductor film 13L1. Thereby, reliability can be further improved.
[0195]
In the structure of FIG. 53, in the structure of FIG. 51, after depositing a barrier metal and tungsten (W) in the connection hole 8f, an Al-based material is deposited without plug processing to form a barrier such as tungsten or TiN. Fourth layer wirings 13L and BP are constituted by metal (thin conductor film) 13L1, thick conductor film 13L2a made of tungsten (W), and thick conductor film 13L2b made of Al. In this manner, by forming a laminated wiring with an Al alloy without plug processing, simplification by eliminating the plug polishing step and improvement in reliability by the laminated structure can be achieved.
[0196]
In the structure of FIG. 54, a thick conductive film 13L2a made of, for example, TiN and a thick conductive film 13L2b made of, for example, TiN are formed without providing the barrier metal (thin conductive film) 13L1 in the structure of FIG. These constitute the fourth layer wiring 13L, BP. For example, since the TiN film 13L2b formed by the CVD method has better adhesion to the interlayer insulating film than the tungsten (W) film, the barrier metal 13L1 does not need to be provided, and the number of manufacturing steps can be reduced. As in the structure shown in FIG. 53, by leaving the plug wiring without using a plug, and forming a laminated wiring with an Al alloy, simplification by eliminating the plug polishing step and improvement in reliability by the laminated structure can be achieved.
[0197]
The structure of the connecting conductor 14C shown in FIG. 51 may be applied to the connecting conductors 10C, 12C, 18C, 19C, and 20C. FIG. 55 shows a structure in which the structure of the connecting conductor 14C shown in FIG. 51 is applied to the connecting conductors 19C and 20C shown in FIGS. The thin conductor films 19C1 and 20C1 have the same configuration as the barrier metal 14C1, and the thick conductor films 19C2 and 20C2 have the same configuration as the plug 14C2.
[0198]
FIG. 56 shows a structure in which the third layer wirings 11L and 21C shown in FIG. 55 are formed by dual damascene. In this structure, after connecting holes 5g and 8h are formed, a barrier metal is deposited by a sputtering method, and then, for example, Cu is thinly formed by a sputtering method, for example, and then the connecting holes 5g and 8h are further formed by an electrolytic plating method. It is formed so as to be embedded in. After that, the third layer wirings 11L and 21C composed of the thin conductor film 21C1 made of the barrier metal and the thick conductor film 21C2 made of Cu are formed by the CMP method or the like. By forming the third layer wiring 21C to be longer than the connection hole 8h in a plane at least along the longitudinal direction of the wiring, the effective aspect ratio when the connection holes 5g and 8h are simultaneously buried with, for example, Cu is reduced. For example, Cu can be easily embedded.
[0199]
FIGS. 57 and 58 show modifications in which the connecting conductor 21C shown in FIGS. 39 to 41 is shifted in the longitudinal direction (X direction). FIG. 57 is a plan view of a main part showing a part of the second-layer wiring 9L to the fourth-layer wiring 13L, and FIG. 58 is a cross-sectional view of the main part along line CC in FIG. 57. Thereby, even if the second layer wiring 9L is formed at the position of the pitch P1 of the adjacent second layer wiring 9L, the connecting conductor portion 21C can be provided.
[0200]
FIG. 59 shows a modification in which the connecting conductor 21C shown in FIGS. 39 to 41 is thickened only in a place where the connection hole 8f is arranged, in a direction perpendicular to the longitudinal direction (X direction) so as not to change the pitch p. Here is an example. The connection conductor 21C shown in FIG. 59 may be applied to the connection conductor 21C shown in FIGS. 57 and 58.
[0201]
(Embodiment 6)
FIG. 60 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIGS. 61 and 62 are cross-sectional views of the main part during a manufacturing process of the semiconductor integrated circuit device of FIG.
[0202]
First, the structure of the semiconductor integrated circuit device according to the sixth embodiment will be described with reference to FIG. The first layer wiring 6L is made of a conductive material other than copper (Cu) such as, for example, tungsten (W), and the second layer wiring 9L and the third layer wiring 11L are made of Cu as in the fifth embodiment. It is composed of a system conductive material.
[0203]
The first layer wiring 6L is used as a wiring for connecting the inside of a logic circuit constituted by, for example, a MIS • FET or a wiring for connecting between logic circuits, and is relatively compared with the second layer wiring 9L and the third layer wiring 11L. It is configured with a short wiring length.
[0204]
The second layer wiring 9L and the third layer wiring 11L are used, for example, for wiring connecting logic circuits, and are configured so that one extends in the X direction and the other extends in the Y direction.
[0205]
By forming the first layer wiring 6L with a W film, the first layer wiring 6L can be formed in a fine pattern, high integration can be achieved, and EM resistance can be increased.
[0206]
Further, since a Cu-based conductive material is not used for the first layer wiring 6L, diffusion of Cu into the semiconductor substrate 1 can be reduced, and reliability can be improved.
[0207]
When the second-layer wiring 9L and the third-layer wiring 11L are made of a Cu-based conductive material, the specific resistance of the wiring is reduced, and high-speed operation becomes possible.
[0208]
Each of the connection conductors 7C, 18C, 19C, 20C, and 21C has a barrier metal (thin conductor film) 14C1 made of W or the like formed by sputtering, for example, similarly to the connection conductor 14C shown in FIG. (Thick conductor film) 14C2 made of the same.
[0209]
The fourth layer wiring 13L and the fifth layer wiring 102 are made of, for example, an aluminum (Al) -based conductive material.
[0210]
The fourth-layer wiring 13L has a laminated structure in which barrier metals (thin conductor films) 13L1 and 13L3 such as W and TiN sandwich a thick conductor film 13L2 made of Al or an Al alloy.
[0211]
Electrically connecting the fourth-layer wiring 13L made of an Al-based conductive material and the third-layer wiring 11L made of a Cu-based conductive material via a connecting conductor portion 20C made of W. Thereby, it is possible to prevent the formation of an alloy layer having a high specific resistance at the contact portion by Al and Cu. The fourth-layer wiring 13L may have a wiring structure shown in FIGS.
[0212]
The fifth-layer wiring 102 is electrically connected to the fourth-layer wiring 13L without passing through the connecting conductor, but is not limited thereto, and may be connected between the fourth-layer wiring 13L and the third-layer wiring 11L. Similarly, the fifth-layer wiring 102 and the fourth-layer wiring 13L may be electrically connected via a connecting conductor having the same structure as the connecting conductor 20C.
[0213]
Further, the fifth layer wiring 102 may have a laminated structure similarly to the fourth layer wiring 13L.
[0214]
An insulating film 104 made of, for example, a silicon oxide film is formed on the fifth layer wiring 102, and a lower electrode 106 is formed in an opening formed in the insulating film 104. The fifth layer wiring 102 is electrically connected to a bump electrode 108 made of a solder bump via a lower electrode 106, and the lower electrode 106 is made of, for example, a barrier metal.
[0215]
Hereinafter, a method of forming the first layer wiring 6L and the connecting conductor 7C will be briefly described with reference to FIGS.
[0216]
After forming a connection hole 8a in the interlayer insulating film 4a as in FIG. 8, a thin conductor film 7C1 made of W or the like is deposited by a sputtering method or the like as shown in FIG. Is deposited so as to be embedded in the connection hole 8a.
[0217]
Next, as shown in FIG. 62, the deposited film is polished by, for example, a CMP method to bury a thin conductive film 7C1 made of W or the like and a thick conductive film 7C2 made of W or the like in the connection hole 8a.
[0218]
For example, after a W film is deposited by a PVD (Physical Vapor Deposition) method, the first layer wiring 6L is formed by patterning by etching. Here, the first-layer wiring 6L is formed of a W film formed by the PVD method, but various modifications such as a laminated structure in which a W film formed by the CVD method or the like is formed on the W film formed by the PVD method are possible.
[0219]
Next, after depositing a silicon oxide film by, for example, a CVD method, the silicon oxide film is polished by a CMP method to form an interlayer insulating film 4b having a planarized surface.
[0220]
Subsequent steps are formed in the same manner as in the first to fifth embodiments described above.
[0221]
Although the semiconductor integrated circuit device of the sixth embodiment uses the bump electrode 108, as shown in FIG. 63, even if the bonding wire 110 is electrically connected to the bonding pad formed by the fifth layer wiring 102. good.
[0222]
Although the semiconductor integrated circuit device according to the sixth embodiment is composed of five wiring layers, it is composed of seven wiring layers, and the second to fifth wiring layers are made of a Cu-based conductive material. And the sixth to seventh layer wirings may be made of an Al-based conductive material. In this case, the second layer wiring and the fourth layer wiring are configured to extend in the same direction, and the third layer wiring and the fifth layer wiring are configured to extend in the same direction. Used as wiring to connect between. Further, in the sixth embodiment, at least the connection conductor is provided along the longitudinal direction of the wiring at least in the third wiring layer located at the portion where the connection conductor portion 19C and the connection conductor portion 20C are connected. Although the connecting conductor 21C is formed longer than the portions 19C and 20C in a plane, a structure corresponding to the connecting conductor 21C may be provided in the second, third, fourth, and fifth layers.
[0223]
FIG. 64 shows a planar layout of the semiconductor integrated circuit device shown in the first to sixth embodiments. The gate arrays 200 are repeatedly arranged, and each of the gate arrays 200 is arranged in combination with integrated circuit elements such as MIS-FETs, bipolar transistors, and resistors.
[0224]
By changing the wiring patterns of the first layer wiring to the fifth layer wiring, various logic circuits are formed, and a semiconductor integrated circuit device having a predetermined logic is formed.
[0225]
FIG. 65 shows a semiconductor integrated circuit device having a gate array 200 and a RAM 400 as a memory.
[0226]
Further, as shown in FIG. 66, units 400, 500, 600, and 700 having various functions may be freely arranged according to the performance of the LSI.
[0227]
As described above, according to the fifth and sixth embodiments, in addition to the effects (8) to (10) obtained in the first embodiment, the following effects can be obtained.
[0228]
(1). A conductive film is filled in the fine connection holes 8a to 8f by using a CVD method or the like, and then the conductive film is filled in the wiring grooves 5a to 5f having a larger plane dimension than the connection holes 8a to 8f, thereby embedding the structure. Of the first layer wiring 6L, the second layer wiring 9L and the third layer wiring 11L, the conductive film is satisfactorily embedded in both the wiring grooves 5a to 5f and the finer connection holes 8a to 8f. It becomes possible. When the conductive films are simultaneously filled into the fine connection holes 8a to 8f and the wiring grooves 5a to 5f located thereon by using the CVD method or the plating method, the wiring grooves 5a to 5f are formed. By making the plane dimensions larger than the connection holes 8a to 8f, it becomes possible to satisfactorily embed the conductor film.
[0229]
(2). According to the above (1), it is possible to improve the reliability of the connection between the wiring layers. Therefore, the yield and reliability of the semiconductor integrated circuit device can be improved.
[0230]
(3). According to the above (1), miniaturization of the embedded wiring can be promoted. Therefore, miniaturization or high integration of the semiconductor integrated circuit device can be promoted.
[0231]
(4). According to the above (1), the conductor film can be satisfactorily embedded in the wiring grooves 5a to 5f and the connection holes 8a to 8f without employing a difficult technique.
[0232]
(5). According to the above (1), even when Cu or a Cu alloy or the like is used as the embedded wiring material, the embedded state can be improved.
[0233]
(6). The first layer wiring 6L that is in direct contact with the semiconductor substrate 1 is made of a tungsten-based conductor material, so that the state of embedding the conductor film in the connection hole 8a is maintained well while Cu atoms are introduced into the semiconductor substrate 1 side. It is possible to avoid element failure due to the diffusion phenomenon. Further, by forming the first layer wiring 6L with a tungsten-based conductor material, it is possible to reduce wiring resistance and improve electromigration (hereinafter also referred to as EM) resistance.
[0234]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.
[0235]
For example, a silicide layer such as tungsten silicide or titanium silicide may be provided at a contact portion of the semiconductor substrate with the connection conductor.
[0236]
The number of wiring layers is not limited to four to seven, but may be variously changed, and may be three or four or more.
[0237]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0238]
(1). According to the method of manufacturing a semiconductor integrated circuit device of the present invention, after the connection hole is sufficiently filled with the conductor film, the wiring groove is formed and is filled with the conductor film. In addition, it is possible to satisfactorily embed the conductor film in both of the finer connection holes.
[0239]
(2). According to the method of manufacturing a semiconductor integrated circuit device of the present invention, when the same wiring layer has wiring grooves or the like having different dimensions, the wiring grooves and the like are buried with fine wiring grooves and the like and larger wiring grooves and the like. By embedding the conductor film by selecting a method that is easy to perform, it becomes possible to satisfactorily embed the conductor film in both the wiring grooves.
[0240]
(3). According to the above (1) or (2), it is possible to improve the reliability of connection between wiring layers. Therefore, the yield and reliability of the semiconductor integrated circuit device can be improved.
[0241]
(4). According to the above (1) or (2), miniaturization of the embedded wiring can be promoted. Therefore, miniaturization or high integration of the semiconductor integrated circuit device can be promoted.
[0242]
(5). According to the above (1) or (2), the conductor film can be satisfactorily embedded in the wiring groove and the connection hole without employing a difficult technique. Therefore, it is possible to promote the cost reduction of the semiconductor integrated circuit device having the embedded wiring.
[0243]
(6). According to the above (1) or (2), even when Cu or a Cu alloy or the like is used as the buried wiring material, the buried state can be improved.
[0244]
(7). According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a Cu-based conductive material formed by a sputtering method or the like on an insulating film including a wiring groove is flattened to thereby form a Cu-based material in a region other than the wiring groove and the like. After removing the conductive material to form the buried wiring, heat treatment is performed to promote Cu grain growth to improve EM resistance, and to damage caused on the surface of the Cu-based conductive film during the planarization process. To improve the reliability of buried wiring made of Cu-based conductor material because it can eliminate the oxide film and the like, smooth the surface, and remove and reduce the contamination of the insulating film surface exposed during CMP. Becomes possible.
[0245]
(8). According to the semiconductor integrated circuit device of the present invention, there is provided a semiconductor integrated circuit device having a buried wiring in an upper wiring layer of a semiconductor substrate, wherein a wiring material at a portion where the buried wiring and the semiconductor substrate are in contact is made of tungsten. , A tungsten alloy, aluminum or an aluminum alloy, and a buried wiring in a wiring layer thereover made of copper or a copper alloy. To prevent the device from being diffused to the semiconductor substrate side to avoid element failure caused by the diffusion phenomenon, and to improve the signal propagation speed by reducing the overall wiring resistance of the semiconductor integrated circuit device. It becomes.
[0246]
(9). According to the semiconductor integrated circuit device of the present invention, there is provided a semiconductor integrated circuit device having a buried wiring in a wiring layer above a semiconductor substrate, wherein a wiring material of an uppermost wiring layer of the wiring layers is aluminum or an aluminum alloy. And the embedded wiring in the lower wiring layer is made of copper or a copper alloy, so that the assembling techniques such as the conventional wire bonding technique and the bump electrode forming technique can be directly followed. Therefore, a semiconductor integrated circuit device having an embedded wiring made of a copper-based conductor material can be easily introduced into an assembling process.
[0247]
(10). According to the semiconductor integrated circuit device of the present invention, there is provided a semiconductor integrated circuit device having a buried wiring in an upper wiring layer of a semiconductor substrate, wherein a wiring made of aluminum or an aluminum alloy and a wiring made of copper or a copper alloy are In the case of connection, a plug is interposed as a barrier conductor film at the joint thereof, so that when the aluminum-based conductor material and the copper-based conductor material are directly contacted, the contact portion has a high specific resistance. Since the formation of the alloy layer can be prevented, the connection resistance between the wiring layers can be reduced.
[0248]
(11). According to the above (8) to (10), the embedded wiring made of a copper-based conductor material can be incorporated into the entire structure of the semiconductor integrated circuit device without causing any trouble.
[0249]
(12). Further, according to the semiconductor integrated circuit device of the present invention, at least a length of the relay connection conductor in the wiring extending direction of the predetermined embedded wiring is equal to a length of the connection hole in the wiring extending direction. By being formed to be longer than the length, the connection groove for forming the relay connection conductor can be made relatively large, so that the conductor film can be satisfactorily embedded in the connection groove. . Therefore, the reliability of the electrical connection between the upper and lower wiring layers can be improved, and the yield and reliability of the semiconductor integrated circuit device can be improved.
[Brief description of the drawings]
FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view of a principal part showing a first layer wiring of the semiconductor integrated circuit device of FIG. 1;
FIG. 3 is a sectional view showing a modification of the wiring structure of FIG. 2;
FIG. 4 is a sectional view showing a modification of the wiring structure of FIG. 2;
FIG. 5 is a sectional view showing a modification of the wiring structure of FIG. 2;
6 is a fragmentary cross-sectional view showing a second-layer wiring of the semiconductor integrated circuit device of FIG. 1;
FIG. 7 is a cross-sectional view of a main part of the semiconductor integrated circuit device, showing a modification of connection between wiring layers of the semiconductor integrated circuit device of FIG. 1;
8 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step thereof;
9 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step thereof;
10 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step thereof;
11 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step thereof;
12 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step thereof;
13 is a partially cutaway perspective view of a main part during a manufacturing step of the semiconductor integrated circuit device of FIG. 1;
14 is a partially cutaway perspective view of a main part during a manufacturing step of the semiconductor integrated circuit device of FIG. 1;
15 is a partially cutaway perspective view of a main part of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step thereof;
16 is a partially cutaway perspective view of a main part during a manufacturing step of the semiconductor integrated circuit device of FIG. 1;
FIG. 17 is a partially cutaway perspective view of a main part of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step thereof;
18 is a partially cutaway perspective view of a main part of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step thereof;
FIG. 19 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step thereof;
20 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 19;
21 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 19;
FIG. 22 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 19;
23 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 19;
FIG. 24 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 25 is an essential part cross sectional view of the semiconductor integrated circuit device of another embodiment of the present invention during a manufacturing step;
26 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 25;
27 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 25;
FIG. 28 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 25;
FIG. 29 is an essential part cross sectional view of the semiconductor integrated circuit device of another embodiment of the present invention during a manufacturing step;
30 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 29;
FIG. 31 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 29;
32 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 29;
FIG. 33 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 34 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 35 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 36 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 37 is an enlarged sectional view of a main part of the semiconductor integrated circuit device of FIG. 36;
38 is an enlarged fragmentary cross-sectional view showing a modification of the main part of the semiconductor integrated circuit device shown in FIG. 37.
39 is a fragmentary plan view of the semiconductor integrated circuit device shown in FIG. 37;
40 is an enlarged sectional view of a principal part of the semiconductor integrated circuit device shown in FIG. 39.
41 is an enlarged sectional view of a principal part of the semiconductor integrated circuit device shown in FIG. 39.
FIG. 42 is an explanatory view schematically showing a main part of the semiconductor integrated circuit device of FIG. 39;
FIG. 43 is an explanatory diagram schematically showing a modified example of FIG. 42;
FIG. 44 is an explanatory diagram schematically showing a modified example of FIG. 42.
FIG. 45 is an explanatory diagram schematically showing a modified example of FIG. 42;
FIG. 46 is an enlarged cross-sectional view of a main part showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;
FIG. 47 is an enlarged cross-sectional view of a main part showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;
FIG. 48 is an enlarged fragmentary cross-sectional view showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;
FIG. 49 is an essential part enlarged cross-sectional view showing a modification of the essential part of the semiconductor integrated circuit device of FIG. 36;
FIG. 50 is an enlarged cross-sectional view of a main part showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;
51 is an enlarged cross-sectional view of a main part showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;
52 is an enlarged cross-sectional view of a main part showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;
FIG. 53 is an enlarged fragmentary cross-sectional view showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;
FIG. 54 is an enlarged cross-sectional view of a main part showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;
FIG. 55 is a cross-sectional view showing a modification of the semiconductor integrated circuit device of FIG. 41.
FIG. 56 is a sectional view showing a modification of the semiconductor integrated circuit device of FIG. 41;
FIG. 57 is a sectional view showing a modification of the semiconductor integrated circuit device of FIG. 39;
FIG. 58 is an enlarged cross-sectional view of a main part of the semiconductor integrated circuit device shown in FIG. 57;
FIG. 59 is a plan view showing a modification of the semiconductor integrated circuit device of FIG. 39.
FIG. 60 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention;
61 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 60 during a manufacturing step thereof;
62 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 60 during a manufacturing step thereof;
63 is a fragmentary cross-sectional view showing a modification of the semiconductor integrated circuit device of FIG. 60;
FIG. 64 is a plan view showing a layout of a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 65 is a plan view showing a layout of a modification of the semiconductor integrated circuit device of FIG. 64;
FIG. 66 is a plan view showing a layout of a modification of the semiconductor integrated circuit device of FIG. 64;
[Explanation of symbols]
1 semiconductor substrate
2 Element separation unit
2a Separation groove
2b Separation insulating film
3n n-channel type MOS-FET
3nd semiconductor region
3ni gate insulating film
3ng gate electrode
3p p channel type MOS ・ FET
3pd semiconductor area
3pi gate insulating film
3pg gate electrode
4a-4d interlayer insulating film
5a-5f Wiring groove
5g connection groove
6L 1st layer wiring
6L1 Thin conductive film
6L2 thick conductor film
7C Connection conductor
7C1 Thin conductive film
7C2 Thick conductor film
8a to 8f Connection hole
9L Second layer wiring
9L1 Thin conductive film
9L2 thick conductor film
10C Connection conductor
10C1 Thin conductive film
10C2 Thick conductor film
11L Third layer wiring
11L1 Thin conductive film
11L2 Thick conductor film
12C Connection conductor
12C1 Thin conductive film
12C2 Thick conductor film
13L 4th layer wiring
13L1 Thin conductive film
13L2 thick conductor film
14C connection conductor
14C1 Thin conductive film
14C2 thick conductor film
15 Surface protective film
15a Protective film
15b protective film
16 opening
17a-17c Photoresist pattern
18C connection conductor
19C Connecting conductor
19C1 Thin conductive film
19C2 Thick conductor film
20C Connecting conductor
20C1 Thin conductive film
20C2 Thick conductor film
21C Connection conductor (connection conductor for relay)
21C1 Thin conductive film
21C2 Thick conductor film
102 5th layer wiring
108 Bump electrode
110 Bonding wire
200 gate array

Claims (3)

In a wiring layer above the semiconductor substrate, a wiring material of a plug portion connecting the embedded copper wiring made of a copper-based conductive material and the semiconductor substrate is formed in the TiN film having a barrier function and the TiN film. The uppermost wiring above the copper buried wiring is made of aluminum or an aluminum alloy, and the uppermost aluminum wiring layer and the copper burying are formed. A semiconductor integrated circuit device, wherein a plug for connecting the built-in wiring is formed of a TiN or Ti film having a barrier function and tungsten formed in the TiN or Ti film. A semiconductor integrated circuit device having a plurality of wiring layers over a semiconductor substrate, a wiring material of the uppermost upper wiring layer formed of aluminum or an aluminum alloy, between the uppermost wiring layer and the lowermost wiring layer at least one wiring layer among the wiring layers are made of copper or a copper alloy, to come in contact with the first plug and before Symbol semiconductors board for connecting the wiring layer made of the copper or copper alloy and the uppermost wiring layer Wherein the lowermost wiring layer integrally formed with the second plug includes a TiN or Ti film having a barrier function and tungsten formed in the TiN or Ti film. Semiconductor integrated circuit device. In a semiconductor integrated circuit device having a wiring layer on a semiconductor substrate,
A first wiring layer made of a copper-based material;
A second wiring layer formed above the first wiring layer and made of an aluminum-based material;
A third wiring layer formed below the first wiring layer and made of a conductive material other than a copper-based material, wherein the first wiring layer and the second wiring layer are tungsten-based And electrically connected via a barrier conductor film formed by being embedded in a connection hole formed in an interlayer insulating film between the first wiring layer and the second wiring layer, A semiconductor integrated circuit device, wherein the second wiring layer is electrically connected to a bonding wire or a bump electrode, and the third wiring layer is made of a tungsten-based conductive material and is connected to the semiconductor substrate.

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