JP3679544B2 - Nonvolatile semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device capable of storing multilevel data by a memory cell transistor having a floating gate.
[0002]
[Prior art]
In an electrically erasable programmable ROM (EEPROM) in which a memory cell is composed of a single transistor, each memory cell is formed by a double-gate transistor having a floating gate and a control gate. . In the memory cell transistor having such a double gate structure, data is written by accelerating hot electrons generated on the drain region side of the floating gate and injecting them into the floating gate. Data is read by detecting a difference in operating characteristics of the memory cell transistor depending on whether or not charge is injected into the floating gate.
[0003]
FIG. 7 is a plan view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate, and FIG. 8 is a sectional view taken along line XX. This figure shows a split gate structure in which a part of the control gate is arranged side by side with the floating gate.
A plurality of isolation regions 2 made of a selectively thick oxide film (LOCOS) are formed in a strip shape on the surface region of the P-type silicon substrate 1, and an element region is defined. A floating gate 4 is disposed on the silicon substrate 1 so as to straddle between adjacent isolation regions 2 with an oxide film 3 interposed therebetween. The floating gate 4 is arranged independently for each memory cell. The oxide film 5 on the floating gate 4 is formed thick at the center of the floating gate 4, and the end of the floating gate 4 has an acute angle. As a result, electric field concentration is likely to occur at the end of the floating gate 4 during the data erasing operation. On the silicon substrate 1 on which a plurality of floating gates 4 are arranged, control gates 6 are arranged corresponding to each column of floating gates 4. This control gate 6 is arranged so that a part thereof overlaps with the floating gate 4 and the remaining part contacts the silicon substrate 1 through the oxide film 3. In addition, the floating gate 4 and the control gate 6 are arranged so that adjacent columns are symmetrical with each other. N-type first diffusion layer 7 and second diffusion layer 8 are formed in the substrate region between control gates 6 and the substrate region between floating gates 4. The first diffusion layer 7 is surrounded by the isolation region 2 between the control gates 6 and is independent of each other, and the second diffusion layer 8 is continuous in the direction in which the control gate 6 extends. These floating gate 4, control gate 6, first diffusion layer 7 and second diffusion layer 8 constitute a memory cell transistor. Then, the aluminum wiring 10 is arranged on the control gate 6 through the oxide film 9 in a direction intersecting with the control gate 6. The aluminum wiring 10 is connected to the first diffusion layer 7 through the contact hole 11.
[0004]
In the case of such a memory cell transistor having a double gate structure, the on-resistance value between the source and the drain varies depending on the amount of charge injected into the floating gate 4. Therefore, by selectively injecting charges into the floating gate 4, the on-resistance value of a specific memory cell transistor is changed stepwise, and the resulting difference in operating characteristics of each memory cell transistor is associated with stored data. I am doing so. For example, by setting the amount of charge injected into the floating gate 4 in four stages and reading the on-resistance value of the memory cell transistor in the same four stages, one memory cell transistor has four values (for two bits). ) Data can be stored.
[0005]
FIG. 9 is a circuit diagram of the memory cell portion shown in FIG. This figure shows a case where memory cells are arranged in 4 rows × 4 columns.
In the memory cell transistor 20 having a double gate structure, the control gate 6 is connected to the word line 21, and the first diffusion layer 7 and the second diffusion layer 8 are connected to the bit line 22 and the source line 23, respectively. Each bit line 22 is connected to a data line 25 via a selection transistor 24, and the data line 25 is connected to a read circuit 27 via a resistor 26. Each bit line 22 is connected to a sense amplifier (not shown) that reads a voltage value. Each source line 23 is connected to a power line 28, and a write circuit 29 is connected to the power line 28. Usually, the control gate 6 itself formed in common in each memory cell transistor 20 is used as the word line 21, and the aluminum wiring 10 connected to the first diffusion layer 7 is used as the bit line 22. The second diffusion layer 8 extending in parallel with the control gate 6 is used as the source line 23.
[0006]
The row selection information LS1 to LS4 is generated based on the row address information, and activates a specific row of the memory cell transistor 20 by selecting one of the word lines 21. The column selection signals CS1 to CS4 are generated based on the column address information, and activate a specific column of the memory cell transistor 20 by turning on one of the selection transistors 24. As a result, one of the plurality of memory cell transistors 20 arranged in a matrix is designated according to the row address information and the column address information and connected to the data line 25.
[0007]
When multi-value information (or analog information) is written to the memory cell transistor 20, charge injection (writing) and injection amount confirmation (reading) are repeated in a short cycle in order to increase recording accuracy. In other words, the memory cell transistor 20 is written little by little, each time reading is performed, and writing is stopped when the read result matches the content of the data to be stored.
[0008]
For example, as shown in FIG. 10, the write clock φW is generated so that the clock rises for a certain period at a certain period. This write clock φW is applied from the write circuit 29 to the memory cell transistor 20 via the power line 28 and the source line 23. At this time, the data line 25 is pulled down to the ground potential in synchronization with the write clock φW. Therefore, while the write clock φW is rising, a current flows from the source line 23 to the bit line 22 through the selected memory cell transistor 20, and charge is injected into the floating gate 4 by this current.
[0009]
On the other hand, for example, as shown in FIG. 10, the read clock φR is generated so that a pulse rises in the gap period of the write clock φW, and is applied to the memory cell transistor 20 from the read circuit 27 via the resistor 26 and the bit line 22. Is done. At this time, the power line 28 is pulled down to the ground potential in synchronization with the read clock φR. Therefore, a current flows from the data line 25 to the power line 28 through the resistor 26 and the selected memory cell transistor 20, and the potential of the bit line 22 depends on the ratio between the on-resistance value of the memory cell transistor 20 and the resistance value of the resistor 26. Changes. The potential at this time is read by the sense amplifier connected to the bit line 22, and the above-described write and read cycles are repeated until the result becomes a value corresponding to information to be written.
[0010]
[Problems to be solved by the invention]
In the above-described memory device that stores multi-value information or analog information, writing with higher accuracy becomes possible as one step of the writing cycle is reduced. However, if one step is reduced, the write cycle required for the write amount of the memory cell to reach a desired level increases, which causes a problem that the write speed becomes slow.
[0011]
In general, one step of the write cycle is set to be small when the storage accuracy is more important than the operation speed, and conversely when the operation speed is more important than the storage accuracy. As described above, the setting of one step of the write cycle is performed according to the purpose of use of the memory device. However, the write characteristics are not necessarily uniform among a plurality of memory cells provided in parallel. However, it is difficult to set an optimal state, and the degree of freedom of setting is small.
[0012]
Therefore, an object of the present invention is to maintain a writing operation of a memory device that records multilevel information or analog information at high speed and with high accuracy, and to simplify setting of operating conditions.
[0013]
[Means for Solving the Problems]
The present invention has been made to solve the above-described problems. The first feature is that an electrically independent floating gate is provided, and an on-resistance is set according to the amount of electric charge accumulated in the floating gate. A memory cell transistor whose value is changed, a bit line connected to the drain side of the memory cell transistor, a source line connected to the source side of the memory cell transistor, and grounding the bit line from the source line A write circuit that applies a write clock to the memory cell transistor at a constant cycle, and a resistor having a predetermined resistance value with respect to the bit line by grounding the source line within a gap period of the write clock A read circuit that applies a read clock having a constant peak value, and the bit in synchronization with the operation of the read circuit. And a determination circuit that compares the potential of the bit line with a determination value corresponding to the stored information or a preliminary determination value lower than the determination value, and the write circuit is configured to perform a first operation until the read potential of the bit line reaches the preliminary determination value. A write clock having a peak value of 1 is generated, and a write clock having a second peak value lower than the first peak value from when the read potential of the bit line exceeds the preliminary determination value until reaching the determination value Is to generate.
[0014]
According to the present invention, a high-voltage write clock is applied until just before the memory cell transistor enters a desired write state, and then a low-voltage write clock is applied to complete the write. At the start of the write operation, a large amount of writing is performed by applying a single write clock, and a small amount of writing is performed by applying a single write clock from the middle to the end of the write operation.
[0015]
The second feature is that the memory cell transistor has an electrically independent floating gate, and the on-resistance value is changed in accordance with the amount of charge accumulated in the floating gate, and the memory cell transistor. A bit line connected to the drain side of the memory cell, a source line connected to the source side of the memory cell transistor, and grounding the bit line to the memory cell transistor from the source line at a constant cycle. A write circuit for applying a write clock having a peak value, and a read having a constant peak value via a resistor having a predetermined resistance value to the bit line by grounding the source line within a gap period of the write clock Read circuit for applying a clock and reading of the bit line in synchronization with the operation of the read circuit And a determination circuit that compares the position with a determination value corresponding to stored information or a preliminary determination value lower than the determination value, and the write circuit includes a first circuit until the read potential of the bit line reaches the preliminary determination value. And a second current amount smaller than the first current amount is supplied from when the read potential of the bit line exceeds the preliminary determination value to the determination value.
[0016]
According to the present invention, the write clock is applied so that a large current flows until just before the memory cell transistor enters a desired write state, and then the write clock is applied so as to allow a small current to flow to complete the writing. At the start of the write operation, a large amount of writing is performed by applying a single write clock, and a small amount of writing is performed by applying a single write clock from the middle to the end of the write operation.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device of the present invention. In this figure, for the sake of simplification, memory cell transistors 40 are arranged in 4 rows × 1 column.
The memory cell transistor 40 has the same structure as the memory cell transistor 20 shown in FIG. 7, has a floating gate and a control gate, and changes the on-resistance value according to the amount of charge injected (accumulated) into the floating gate. . The word line 41 is arranged corresponding to each column of the memory cell transistors 40, and the control gates of the memory cell transistors 40 are connected to the word lines 41, respectively. Row selection signals LS1 to LS4 supplied from a row decoder (not shown) that receives row selection information are applied to the word line 41, and any one row is selectively activated. The bit line 42 extends in the column direction in which the memory cell transistors 40 are arranged, and the drain side of each memory cell transistor 40 is connected. The source line 43 is arranged extending in a direction crossing the bit line 42, and the source side of each memory cell transistor 40 is connected. Thus, each memory cell transistor 40 is connected in parallel to the bit line 42 and is supplied with a predetermined potential from the bit line 42 and the source line 43 for each of write, read and erase operations.
[0018]
The data line 45 is connected to the bit line 42 via the column selection transistor 44 that operates in response to the column selection information LS1, and is connected to the read circuit 51 via the read load resistor 46 having a certain resistance value. The The data line 45 is grounded via a switching transistor 47 that operates in response to the current control signal S0 supplied from the write circuit 52. The power line 48 is connected to each source line 43 and connected to the write circuit 52.
[0019]
The read circuit 51 generates a read clock φR and applies a constant voltage from the data line 46 and the bit line 42 to the memory cell transistor 40 through the resistor 46 at a constant period. This read clock φR is the same as the read clock φR shown in FIG. 10, and has a constant period according to the write clock φW while maintaining a constant peak value. The write circuit 52 generates a write clock φW, and applies the first voltage or the second voltage from the power line 48 and the source line 43 to the memory cell transistor 40 at a constant period. The write circuit 52 generates a current control signal S 0 in synchronization with the write clock φW and applies it to the switching transistor 47.
[0020]
The determination circuit 53 reads the potential of the bit line 42 in accordance with the operation of the read circuit 51, makes the potential of the bit line 42 a potential (determination value) corresponding to write information and a potential slightly lower than this potential (preliminary determination value). And the comparison result is output as a determination signal D. For example, when storing four values (for two bits) of information in the memory cell transistor 40, as shown in FIG. 2, intermediate values VR1 and VR2 among the determination values VR0 to VR3 corresponding to the four states of the stored information. Preliminary judgment values VP1 and VP2 that are slightly lower than the above are set. At the start of the write cycle, the potential of the bit line 42 is compared with the preliminary determination values VP1 and VP2, and after the potential of the bit line 42 exceeds the preliminary determination values VP1 and VP2, the potential is compared with the determination values VR1 and VR2. Configure as follows. For the maximum determination value VR3, it is not necessary to sequentially check the writing state when writing the maximum value, and for the minimum determination value VR0, the writing operation itself is not required for writing the minimum value. There is no need to set a preliminary judgment value.
[0021]
By the way, the preliminary determination values VP1 and VP2 are set according to the write characteristics of the memory cell transistor 40. That is, the bit line 42 that changes in one write cycle does not change until the read potential of the bit line 42 changes from the preliminary determination values VP1 and VP2 to the determination values VR1 and VR2 in one write cycle. Preliminary determination values VP1 and VP2 are set so as to give a sufficiently large difference with respect to the change amount of the read potential.
[0022]
In the four-value storage shown in FIG. 2, when writing the intermediate value “0, 1” or “1, 0”, the write circuit 52 generates the write clock φW and the current control signal S0 as shown in FIG. To do. That is, as shown in FIG. 3, the write circuit 52 selects the high voltage VH and sets the write clock φW until the read potential of the bit line 42 reaches the preliminary determination values VP1 and VP2 from the start of writing. Keep the peak value high. Subsequently, when the read potential exceeds the preliminary determination values VP1 and VP2, the low voltage VL is selected, and the peak value of the write clock φW is kept low until reaching the respective determination values VR1 and VR2. When the read potential reaches the determination values VR1 and VR2, the output of the write clock φW is stopped and the write operation is terminated. The operations of these write circuits 52 are controlled in response to a determination signal D output from the determination circuit 53. The read circuit 51 generates a read clock φR that is the same as the read clock φR shown in FIG. 10 and applies a constant potential to the bit line 42 during the gap period of the write clock φW.
[0023]
FIG. 4 is a circuit diagram showing a second embodiment of the nonvolatile semiconductor memory device of the present invention. In this figure, the memory transistor 40, word line 41, bit line 42, source line 43, selection transistor 44, data line 45, read load resistor 46, and power line 48 are the same as in FIG. The read circuit 51 and the determination circuit 53 are also the same as those in FIG. 1, and the potential of the bit line 42 is compared with the determination value and the preliminary determination value set corresponding to the stored information for each read operation.
[0024]
The data line 45 is connected to the read circuit 51 via a read load resistor 46 having a constant resistance value, and operates in response to the current control signals S1 and S2 supplied from the write circuit 54. Two switching transistors 49a and 49b are grounded. The write circuit 54 generates a write clock φW having a constant peak value, and applies a constant voltage from the power line 48 and the source line 43 to the memory cell transistor 40 at a constant period. At the same time, the write circuit 52 generates current control signals S1 and S2 synchronized with the write clock φW and applies them to the first and second switching transistors 49a and 49b.
[0025]
In the storage of the four values shown in FIG. 2, when writing the intermediate value “0, 1” or “1, 0”, the write circuit 52, as shown in FIG. 5, writes the write clock φW and the current control signals S1, S2. Is generated. That is, as shown in FIG. 5, the write circuit 52 synchronizes with the write clock φW until the read potential of the bit line 42 reaches the preliminary determination values VP1 and VP2, as shown in FIG. S2 is activated together, and both the first and second switching transistors 49a and 49b are turned on. As a result, the capacity of current flowing from the bit line 42 to the ground side is increased. When the read potential of the bit line 42 exceeds the preliminary determination values VP1 and VP2, the current control signal S2 is fixed and only the current control signal S1 is raised, and only the first switching transistor S1 is turned on. As a result, the current capacity flowing from the bit line 42 to the ground side is limited to about ½. Subsequently, when the read potential of the bit line 42 reaches the determination values VR1 and VR2, the output of the write clock φW is stopped and the current control signals S1 and S2 are both stopped, and the write operation is ended. The operations of these write circuits 54 are controlled in response to a determination signal D output from the determination circuit 53. The read circuit 51 generates a read clock φR that is the same as the read clock φR shown in FIG. 10 and applies a constant potential to the bit line 42 during the gap period of the write clock φW.
[0026]
In the memory cell transistor 40, when a current flows from the source line 43 to the bit line 42 side by applying the write clock φW, charges are injected into the floating gate of the memory cell transistor 40 in accordance with the write current. Since the injection amount follows the voltage and write current value of the write clock φW, writing (charge injection) corresponding to the write current is performed for the write clock φW having a constant peak value. Therefore, during the period in which both the switching transistors 49a and 49b are on, a sufficient write current flows and a large number of write operations are performed on the memory cell transistor 40 once. During the period when only the first switching transistor 49a is on, the write current is about ½, so that a small amount of data is written to the memory cell transistor 40 once. Thus, high-speed writing with a large current is performed at the start of writing, and precise writing with a small current is performed at the end of writing.
[0027]
In the memory device described above, writing with a high voltage or a large current is performed immediately before the memory cell transistor 40 reaches a desired writing level. Therefore, as shown in FIG. 6, the read potential of the bit line 42 reaches the preliminary determination value VP in a short time. Then, after the preliminary determination potential VP is exceeded, it gradually changes until reaching the determination potential VR. As for the write operation to the memory cell transistor 40, it is conceivable to control the write amount by switching the write voltage, and to control the write amount by switching the write current. The write current may be switched together.
[0028]
In the above embodiment, the case where four values (for two bits) of information are stored in the memory cell transistor 40 is illustrated, but the storage information is not limited to four values, but eight values (for three bits), 16 values (for 4 bits) or more are also possible. In this case, the determination circuit 53 is configured to set a preliminary determination value for each intermediate value excluding the maximum value and the minimum value.
[0029]
【The invention's effect】
According to the present invention, when multi-value information or analog information is stored in a memory cell transistor, the writing speed can be increased. Alternatively, highly accurate writing can be performed without reducing the writing speed. Therefore, it becomes easy to set the write condition for the memory cell transistor, and the degree of freedom for setting the condition is expanded.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device of the present invention.
FIG. 2 is a diagram illustrating a relationship between a determination value of 4-level write information and a preliminary determination value.
FIG. 3 is a waveform diagram of a write clock and a current control signal according to the first embodiment.
FIG. 4 is a circuit diagram showing a second embodiment of a nonvolatile semiconductor memory device of the present invention.
FIG. 5 is a waveform diagram of a write clock and a current control signal according to the second embodiment.
FIG. 6 is a diagram illustrating a relationship between a read potential and a write elapsed time.
FIG. 7 is a plan view showing a structure of a memory cell of a conventional nonvolatile semiconductor memory device.
8 is a cross-sectional view taken along line XX of FIG.
FIG. 9 is a circuit diagram showing a configuration of a conventional nonvolatile semiconductor memory device.
FIG. 10 is a waveform diagram of a write clock and a read clock.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Isolation region 3, 5, 9 Oxide film 4 Floating gate 6 Control gate 7 Drain region 8 Source region 10 Aluminum wiring 11 Contact hole 20, 40 Memory cell transistor 21, 41 Word line 22, 42 Bit line 23, 43 Source lines 24, 44 Select transistors 25, 45 Data lines 26, 46 Read load resistors 27, 51 Read circuits 28, 48 Power lines 29, 52, 54 Write circuits 47, 49a, 49b Switching transistors 53 Determination circuit

Claims (5)

A memory cell transistor having an electrically independent floating gate and changing an on-resistance value according to the amount of charge accumulated in the floating gate; a bit line connected to the drain side of the memory cell transistor; A source line connected to the source side of the memory cell transistor; a write circuit that applies a write clock having a constant peak value between the source line and the bit line; and a gap between the write clocks A readout circuit that reads out the readout potential corresponding to the on-resistance value of the memory cell transistor within the period, and the readout potential in synchronization with the operation of the readout circuit, or the judgment potential corresponding to the stored information or lower than this judgment value includes a decision circuit for comparing the pre-determined value, the said write circuit, read out the A first current amount is supplied until the potential reaches the preliminary determination value, and a second current amount that is smaller than the first current amount until the read potential exceeds the preliminary determination value and reaches the determination value. the nonvolatile semiconductor memory device, wherein the supply. A memory cell transistor having an electrically independent floating gate and changing an on-resistance value according to the amount of charge accumulated in the floating gate; a bit line connected to the drain side of the memory cell transistor; A source line connected to the source side of the memory cell transistor; a write circuit that applies a write clock having a constant peak value between the source line and the bit line; and a gap between the write clocks A readout circuit that reads out the readout potential corresponding to the on-resistance value of the memory cell transistor within the period, and the readout potential in synchronization with the operation of the readout circuit, or the judgment potential corresponding to the stored information or lower than this judgment value A determination circuit for comparing with a preliminary determination value, and the write circuit The current amount and the peak value of the write clock are set to the first setting until the potential reaches the preliminary determination value, and the current amount and the peak value of the write clock until the determination value is reached after the read potential exceeds the preliminary determination value. Is a second setting . A non-volatile semiconductor memory device.   A memory cell transistor having an electrically independent floating gate and changing an on-resistance value according to the amount of charge accumulated in the floating gate; a bit line connected to the drain side of the memory cell transistor; A source line connected to the source side of the memory cell transistor and a write circuit for grounding the bit line and applying a write clock having a constant peak value from the source line to the memory cell transistor at a constant period A read circuit that grounds the source line and applies a read clock having a predetermined peak value to the bit line via a resistor having a predetermined resistance value within a gap period of the write clock, and the read circuit In synchronism with the operation of A determination circuit for comparing with a preliminary determination value lower than a constant value, and the write circuit supplies a first current amount until the read potential of the bit line reaches the preliminary determination value, and reads the bit line. A non-volatile semiconductor memory device characterized in that a second current amount smaller than the first current amount is supplied until the potential reaches the determination value after the potential exceeds the preliminary determination value.   The write circuit includes a current limiting circuit that limits current flowing from the bit line to the ground side in at least two stages when the bit line is grounded, until the read potential of the bit line reaches the preliminary determination value. The current is limited in a first stage, and the current is limited in a second stage that is larger than the first stage until the bit line read potential exceeds the preliminary determination value and reaches the determination value. The nonvolatile semiconductor memory device according to claim 3.   4. The difference in the preliminary judgment value with respect to the judgment value is larger than the potential of the bit line that changes corresponding to the amount of writing to the memory cell transistor in one write clock. Nonvolatile semiconductor memory device.

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