JP3659872B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention, IC, regarding the insulation board on which electronic components are mounted, such as a semiconductor chip such as an LSI on a semiconductor device in which a plurality order.
[0002]
[Prior art]
In recent years, electronic devices are becoming lighter, thinner and shorter, and high-function integration and high-speed signal processing are progressing. Along with this, the shape of the semiconductor device is also changed from a shape in which lead terminals, which are conductive wirings, are pulled out in a gull-wing shape from the side surface of the package such as QFP (Quad Flat Package), for example, BGA (Ball Grid Array) or the like. In such a shape that an electrode is formed using gold bumps or the like on the lower surface side of such a package, the area occupied by the semiconductor device when mounting such a semiconductor device on a mother substrate can be remarkably reduced. It has moved.
[0003]
As a semiconductor device further downsized than the BGA, for example, a CSP (Chip) in which a semiconductor chip as an electronic component is mounted on a rigid substrate as an insulating substrate made of ceramics using a technique such as a flip chip mounting method. Size Package) is drawing attention.
[0004]
[Problems to be solved by the invention]
However, according to the conventional semiconductor device as described above, the area occupied by one such semiconductor device on the mother substrate can be reduced by reducing the size of the package. With the addition of new functions, the number of semiconductor devices mounted on the mother board continues to increase, and there is a problem that the mother board becomes larger corresponding to this.
[0005]
In addition, in such a semiconductor device, not only the mother substrate becomes large, but the length of the lead terminals from the main semiconductor device to other semiconductor devices becomes extremely long, resulting in signal delay, signal distortion, and consumption. This leads to an increase in electric power and the like, resulting in inconvenience that it is difficult to obtain predetermined electrical performance. In particular, in a media device whose circuit system is increased in speed and capacity, the reduction of the lead terminal length is an important issue.
[0006]
Furthermore, even if the mother board is reduced in size, the number of semiconductor devices that can be mounted in the mounting area for one semiconductor device on the mother board is one, so that the semiconductor device that can be mounted on the mother board. There was also a risk of limiting the score.
[0007]
As one method for solving such a problem, conventionally, as disclosed in, for example, JP-A-10-223683, JP-A-63-61150, JP-A-7-106509, etc., a semiconductor chip is mounted. Wiring, solder balls, inner leads, via holes, and through holes are provided on the insulating film and insulating sheet, and the insulating film and insulating sheet are sequentially laminated, and wiring and soldering are performed between the insulating film and insulating sheet. There has been proposed a conductive connection through a ball, an inner lead, a via hole, a through hole, or the like.
[0008]
However, with this, it is difficult to visually check the connection state between the insulating film and the insulating sheet, and it is necessary to seal part or all of the laminated insulating film and insulating sheet with resin. Even if some defects occur, it becomes difficult to repair and there are still insufficient problems.
[0009]
Further, as disclosed in JP-A-7-14979 and the like, leadless chip carriers mounted with a semiconductor memory are sequentially stacked in a mounting case via an insulating sheet, and these stacked chip carriers are There has also been proposed a conductive connection in which an end face through-hole electrode formed on the side surface and a signal line in the mounting case are brought into contact with each other.
[0010]
However, even in this case, it is difficult to visually check the connection state between the stacked chip carriers, and in order to connect each chip carrier to each other, a mounting case, a signal line inside the case, and the like are separately required. However, the number of parts increases and the configuration becomes complicated, and there is still an insufficient problem.
[0011]
Therefore, the first problem of the present invention is to easily inspect the connection state between the stacked semiconductor devices in the semiconductor device, and to simplify the configuration by reducing the number of parts of the semiconductor device, The purpose is to simply and reliably conduct conductive connection between the laminated insulating substrates.
[0012]
The second problem is to prevent the conductive wiring from being bent when connecting the one end of the conductive wiring and the electrode of the electronic component.
[0013]
The third problem is to stably stack a plurality of insulating substrates on which electronic components are mounted. The fourth problem is to prevent the stacked insulating substrates from collapsing before conducting connection. There is.
[0014]
A fifth problem is to prevent a plurality of conductive wirings from being scattered. A sixth problem is to position the insulating substrates when stacking a plurality of insulating substrates on which electronic components are mounted. It is to make it simple.
[0015]
A seventh problem is to withstand the stress concentration generated between the conductive wirings at the corners of each insulating substrate due to internal strain caused by heat during conductive connection.
[0016]
The eighth problem is to form an alignment mark for positioning without increasing the number of parts, and the ninth problem is to easily form the alignment mark for positioning.
[0017]
[Means for Solving the Problems]
Therefore, the invention described in claim 1 is to achieve the above first to third problems.
Conductive wiring is arranged in a predetermined pattern on one surface of the insulating substrate, connected to one end of the conductive wiring, and electronic components are flip-chip mounted. The other end of the conductive wiring is insulated While protruding from the peripheral edge of the substrate and bent into a predetermined shape,
A plurality of the insulating substrates on which the electronic components are mounted are sequentially stacked, and the insulating substrate in the upper layer is sequentially stacked on the adjacent electronic components in the lower layers, and the insulating substrates other than the uppermost layer or the lowermost layer are stacked. When the first insulating substrate on which the first conductive wiring is disposed and the insulating substrate on the uppermost layer or the lowermost layer is the second insulating substrate on which the second conductive wiring is disposed, The other end portion of the second conductive wiring extends to the lowermost layer or the uppermost layer on the opposite side and is electrically connected to the other end portion of the first conductive wiring.
This is a semiconductor device.
[0020]
According to a second aspect of the present invention, in order to achieve the fourth problem described above, in the semiconductor device according to the first aspect, the adjacent insulating substrate and the electronic component underneath are stacked with an adhesive interposed therebetween. It is composed, characterized in that.
[0021]
According to a third aspect of the present invention, in order to achieve the fifth problem described above, in the semiconductor device according to the first or second aspect, the second conductive property is provided at the other end of the second conductive wiring. It is characterized by being provided with an anti-scattering member for bundling the wiring.
[0022]
According to a fourth aspect of the present invention, there is provided a semiconductor device according to the first, second, or third aspect, wherein the insulating substrates are stacked at four corners of each insulating substrate in order to achieve the sixth problem. It has a projection for positioning.
[0023]
According to a fifth aspect of the present invention, there is provided the semiconductor device according to the first , second , third , or fourth aspect, wherein each of the insulating substrates includes the first and the second in order to achieve the seventh problem. The conductive wiring at the end of the conductive wiring is characterized in that it is wider than the other conductive wiring.
[0024]
According to a sixth aspect of the present invention, in order to achieve the eighth problem described above, in the semiconductor device according to the fifth aspect , a positioning alignment mark is formed on a wide conductive wiring. And
[0025]
The invention described in claim 7 is characterized in that, in order to achieve the ninth problem described above, in the semiconductor device according to claim 6, the alignment mark is a round hole.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0027]
1 and 2 are a schematic perspective view and a longitudinal sectional view showing an external appearance of a semiconductor device according to the present invention. In the illustrated semiconductor device, an insulating substrate 10 on which a semiconductor chip 12 such as an IC or an LSI, which is an electronic component, is mounted so that the upper insulating substrate 10 is sequentially stacked on the lower semiconductor chip 12, for example, an adhesive. It is formed by interposing. Further, on the other side of the lowermost insulating substrate 10 in the semiconductor device, the electrodes 10A for conducting connection between the semiconductor device and the mother board or the like, formed by arranging in a predetermined arrangement.
[0028]
Each of the insulating substrates 10 is made of glass epoxy, polyimide, or the like. Conductive wirings 11 are arranged in a predetermined pattern on one surface, and an electrode 12A of the semiconductor chip 12 is flipped on one end portion 11A of the conductive wiring 11. Modules MO1 to MO4 are formed by being mounted by a chip mounting method or a TAB method.
[0029]
Further, the other end portion 11B of the conductive wiring 11 of each insulating substrate 10 of the semiconductor device having such a multilayer module structure protrudes at the peripheral portion of the insulating substrate 10 and, for example, the other surface of the insulating substrate 10 It is formed by being bent downward and curved toward the side.
[0030]
Here, the insulating substrate 10 other than the uppermost layer or the lowermost layer is the first insulating substrate 10b provided with the first conductive wiring 11a, and the uppermost or lowermost insulating substrate 10 is the second insulating substrate 10b. Assuming that the second insulating substrate 10b is provided with the conductive wiring 11b, the uppermost second insulating substrate 10b of each insulating substrate 10 as shown in FIG. 3, or as shown in FIG. the other end portion 11B of the second conductive lines 11b of the second insulating substrate 10b of the bottom layer, while protruding at the peripheral portion of the second insulating substrate 10b, opposite the lowermost or uppermost layer first The conductive wiring 11a is formed to extend to the other end 11B.
[0031]
In this semiconductor device, the other end portion 11B side of the second conductive wiring 11b of the uppermost or lowermost second insulating substrate 10b and the first conductive wiring 11a of each first insulating substrate 10a . The other end portion 11B of the semiconductor device is conductively connected at the peripheral portion of the semiconductor device.
[0032]
In the case of this embodiment, the tip of the other end portion 11B of the second conductive wiring 11b extending from the uppermost or lowermost second insulating substrate 10b is the same as the insulating substrate 10, for example. A scattering prevention member 13 made of a material for bundling the second conductive wirings 11b is provided, so that each second conductive wiring 11b has a certain pitch accuracy. It has a fixed structure.
[0033]
In order to obtain such a laminated structure, the modules MO1, MO2, MO3, and MO4 each having the semiconductor chip 12 mounted on the insulating substrate 10 are sequentially bonded to the upper insulating substrate 10 and the lower semiconductor chip 12 with an adhesive. Then, the conductive wirings 11 of the respective layers are sequentially joined in the vertical direction by the second conductive wirings 11b to complete the electrical connection between the respective layers. At this time, in the semiconductor chips 12 of the modules MO1 to MO3, the joints between the electrodes of the semiconductor chips 12 and the conductive wirings 11 are sealed with a sealing resin FJ made of an insulating material or the like.
[0035]
In this manner, in this semiconductor device, each semiconductor chip 12 is electrically connected to each other through the conductive wirings 11 of each insulating substrate 10 and is electrically connected to the electrodes on the mother substrate via the lowermost electrode 10A. It is made to connect.
[0036]
Incidentally, the wiring pattern of the conductive wiring 11 formed on the insulating substrate 10 of each layer is not necessarily the same wiring pattern when the semiconductor chip 12 to be mounted is different. Further, the wiring configuration is different.
[0037]
The insulating substrate 10 and the semiconductor chip 12 have a thickness of several tens [μm] to several hundreds [μm]. The semiconductor chip 12 is formed by a mechanical polishing method such as grinding or polishing on the back surface on which no element is formed in a wafer state or a chip state, a chemical polishing method such as a method of dissolving with an etchant mainly composed of HF liquid, or these The film is polished to a desired thickness by a CMP method using the above method.
[0038]
Furthermore, as shown in FIGS. 5A and 5B, the bent portion of the other end portion 11B of the conductive wiring 11 in each insulating substrate 10 is a state in which the end portion of each insulating substrate 10 is notched. And can be formed by bending with a predetermined jig 20.
[0039]
Furthermore, in this semiconductor device, as shown in FIG. 6, the conductive wiring located at least at the end (closest to the corner) in the plurality of first conductive wirings 11a arranged side by side on the first insulating substrate 10a. the 11D of width, may be wider than the width of the other conductive wire 11E located inside the conductive wire 11D.
[0040]
As a result, when stress concentration occurs in the first conductive wiring 11a due to the difference in expansion between the semiconductor chip 12 and the first insulating substrate 10a , they can be prevented from breaking, and high Reliability can be obtained. Note that the width of the first conductive wiring 11a varies depending on the dimensions of the first insulating substrate 10a and the environmental conditions, but the wider width may be 1.2 times or more larger than the narrower width. desirable. Similarly, for the second conductive wiring 11b of the second insulating substrate 10b, the second conductive wiring at the end may be formed wider than the other second conductive wiring.
[0041]
Further, FIG. 6 shows a configuration in which positioning protrusions 15 are provided at at least four corners of the first insulating substrate 10a . In this way, the positioning protrusion 15 is formed integrally with the first insulating substrate 10a so as to protrude beyond the outer dimensions. Incidentally, in FIG. 6, the description has been given using the first insulating substrate 10a of a layer other than the uppermost or lowermost second insulating substrate 10b in which the second conductive wiring 11b is formed long, but the present invention is not limited thereto. By the way.
[0042]
With such a configuration, the conductive wiring 11 is positioned inside the positioning protrusion 15. And it can prevent beforehand that the conductive wiring 11 bent from the periphery of the insulating substrate 10 contacts an external component, or damages a conductive wiring during operation. Also, the positioning projections 15, the mechanical conductive lines, not only can be electrically protected, can also be used for alignment between the insulating substrate 10 when stacking the insulating substrate 10, positioning If the tip of the projection 15 is a contour for alignment, the alignment can be facilitated.
[0043]
In addition to this, the positioning projections 15 can be formed as long as the outer dimensions of the insulating substrate 10 and the lowermost insulating substrate 10 having the electrodes 10A for connection to the electrodes of the mother substrate are substantially the same. Not only is the alignment easy, but also when the protective resin is formed in the bent conductive wiring region, that is, the side surface region of the insulating substrate, the lowermost insulating substrate 10 and the positioning protrusions 15 of the other insulating substrate 10 are positioned. If the outer dimensions are substantially the same, the protective resin can be easily formed, and the thickness of the protective resin can be uniformly formed.
[0044]
Further, in this semiconductor device, the connection of the conductive wiring 11 between the laminated insulating substrates 10 is performed by, for example, arranging a solder material on the conductive wiring 11 and reflowing the solder material, thereby bending the conductive material. Since the conductive wiring 11 and the conductive wiring 11 on the insulating substrate 10 located below the conductive wiring 11 are in contact with each other, the connection can be easily made by melting the solder.
[0045]
Further, for example, solder can be melted in a solder tank provided with a heater, and the laminated modules MO1 to MO4 can be immersed in the molten solder for connection.
[0046]
Thus, in the step of immersing in the molten solder in the solder bath, when pulling up the semiconductor device from the molten solder, at least one corner of the hexagonal semiconductor device and the molten solder surface If the angle θ formed by is set to 30 ° to 60 °, a short circuit between adjacent conductive wirings 11 connecting the insulating substrates 10 can be prevented.
[0047]
Furthermore, an external connection electrode 10A for connection to the mother substrate is formed on the other surface side of the lowermost insulating substrate 10. 1, 2 and 4, solder balls are formed as the electrode 10A, and a so-called CSP (Chip Size Package), BGA (Ball Grid Array) structure is shown. The lowermost insulating substrate 10 and the conductive wiring 11 formed thereon are manufactured by the same method as that for the upper insulating substrate 10.
[0048]
【The invention's effect】
As described above, according to the present invention, in the semiconductor device formed by sequentially laminating a plurality of insulating substrates on which electronic components are mounted, the conductive wiring between the insulating substrates is connected at the periphery of these insulating substrates. Accordingly, the connection location can be visually confirmed from the outside, the inspection of the connection location can be extremely facilitated, and the conductive connection between the insulating substrates can be reliably performed.
[0049]
In addition, the first conductive wirings between the first insulating substrates are laminated by the second conductive wiring extending from the peripheral edge of the uppermost layer or the lowermost second insulating substrate . By connecting at the periphery of the insulating substrate, it is possible to connect without adding new connection parts, and the connection location of the semiconductor device can be visually confirmed from the outside. Thus, the conductive connection between the insulating substrates can be easily and reliably performed.
[0050]
Furthermore, since the connection is performed on the side surfaces of the laminated insulating substrates, repair can be easily performed even if a defect occurs in a part of the laminated insulating substrates. In addition, since the conductive wiring for connection is formed so as to protrude from the side surface of the insulating substrate, the connection can be realized collectively and reliably using a simple process such as solder dipping or solder reflow. A costly module can be realized.
[0051]
Still further , the conductive wiring is disposed on the insulating substrate, and the electronic component is flip-chip mounted, so that the insulating substrate can connect the one end of the conductive wiring to the electrode of the electronic component. It is possible to prevent the conductive wiring from being bent and deformed.
[0052]
Furthermore , by laminating the upper insulating substrate on the lower electronic component of each insulating substrate, it is possible to enhance the stability when laminating a plurality of insulating substrates.
[0053]
According to the second aspect of the present invention, the adhesive is interposed between the insulating substrate adjacent to the stacking direction and the electronic component, so that the plurality of stacked insulating substrates are broken before the conductive connection. It can be prevented in advance.
[0054]
According to the invention of claim 3 , by providing the anti-separation member at the tip of the other end side of the second conductive wiring, the conductive wiring is prevented from separating, Each second conductive wiring can be fixed so as to have a certain pitch accuracy.
[0055]
According to the fourth aspect of the present invention, since the positioning protrusions are provided at the four corners of the insulating substrate, the positioning protrusions can be used to facilitate alignment when the upper and lower insulating substrates are stacked. And high alignment accuracy can be obtained. Moreover, it becomes the external shape reference | standard at the time of resin molding of a mounting body, and accurate resin molding can also be performed.
[0056]
Furthermore, since the positioning projections are provided so as to protrude beyond the conductive wiring between the laminated insulating substrates, an external force is applied to the conductive wiring to prevent the conductive wiring from being deformed or damaged in advance. Can do.
[0057]
According to the invention of claim 5 , since the conductive wiring at the end of the array of the plurality of conductive wirings on the insulating substrate is wider than the other conductive wiring, the expansion of the electronic component and the insulating substrate Due to this difference, it is possible to prevent breakage when stress is applied to the conductive wiring, and to improve reliability in connection.
[0058]
According to the eighth aspect of the present invention, since the alignment marks are provided on the conductive wiring at the end of the conductive wiring, positioning between the upper and lower insulating substrates is performed when a plurality of insulating substrates are stacked. Can be further simplified.
[0059]
According to the sixth aspect of the present invention, since the alignment marks are provided on the conductive wiring at the end of the conductive wiring, positioning between the upper and lower insulating substrates is performed when a plurality of insulating substrates are stacked. Can be further simplified.
[Brief description of the drawings]
FIG. 1 is a schematic perspective view of a semiconductor device according to the present invention.
FIG. 2 is a longitudinal sectional view of the semiconductor device.
FIG. 3 is a schematic perspective view showing the second uppermost insulating substrate.
FIG. 4 is a schematic perspective view showing a second insulating substrate in the lowermost layer.
FIGS. 5A and 5B are schematic cross-sectional views showing a procedure in which conductive wiring protruding from an insulating substrate is bent by a jig, wherein FIG. 5A is before bending, and FIG. 5B is after bending.
FIG. 6 is a plan view showing a first insulating substrate in which positioning protrusions are formed at the four corners of the first insulating substrate and the ends of the conductive wiring are formed wide.
[Explanation of symbols]
MO1 module MO2 module MO3 module MO4 module FJ Sealing resin layer 10 Insulating substrate
10a First insulating substrate
10b Second insulating substrate 10A Electrode 11 Conductive wiring
11a First conductive wiring
11b Second conductive wiring 11A One end 11B The other end 11C Alignment mark
11D End conductive wiring
11E Conductive wiring other than end 12 Semiconductor chip (electronic component)
13 Anti-scattering member 14 Adhesive 15 Protrusion for positioning 20 Jig

Claims (7)

Conductive wiring is arranged in a predetermined pattern on one surface of the insulating substrate, connected to one end of the conductive wiring, and electronic components are flip-chip mounted. The other end of the conductive wiring is insulated While protruding from the peripheral edge of the substrate and bent into a predetermined shape,
A plurality of the insulating substrates on which the electronic components are mounted are sequentially stacked, and the insulating substrate in the upper layer is sequentially stacked on the adjacent electronic components in the lower layers, and the insulating substrates other than the uppermost layer or the lowermost layer are stacked. When the first insulating substrate on which the first conductive wiring is disposed and the insulating substrate on the uppermost layer or the lowermost layer is the second insulating substrate on which the second conductive wiring is disposed, The other end portion of the second conductive wiring extends to the lowermost layer or the uppermost layer on the opposite side and is electrically connected to the other end portion of the first conductive wiring.
A semiconductor device. The semiconductor device according to claim 1 , wherein the adjacent insulating substrate and the electronic component underneath are stacked with an adhesive interposed therebetween. The other end of the second conductive wires, bundling the second conductive wire and provided with a loose preventing member, a semiconductor device according to claim 1 or 2. The four corners of each said insulating substrate, comprising a positioning projection when stacking these insulating substrate, a semiconductor device according to claim 1, 2 or 3. In the respective aforementioned insulating substrate, a conductive wire ends of said first and second conductive lines are made with wider than the other conductive wire, according to claim 1, 2, 3 or 4 A semiconductor device according to 1. 6. The semiconductor device according to claim 5 , wherein an alignment mark for positioning is formed on the wide conductive wiring. The semiconductor device according to claim 6 , wherein the alignment mark is a round hole.

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