JP3535110B2 - Tape carrier package semiconductor device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tape carrier package semiconductor device and a method for manufacturing the same, and more particularly to a structure of a wiring pattern formed on an insulating tape (insulating film).

[0002]

2. Description of the Related Art Starting with mobile phones and personal digital assistants,
As electronic devices have become smaller and lighter, the density of electronic components mounted in those devices has been increasing.

Therefore, in order to increase the density of electronic parts, a semiconductor is formed on a wiring substrate, that is, a so-called tape carrier, in which a metal wiring pattern (metal wiring pattern) is formed on an insulating tape (insulating film). Devices are being implemented. For example, a semiconductor element for driving a liquid crystal display panel is mounted on a wiring board formed by forming a metal wiring pattern (pattern of metal wiring) on an insulating tape (insulating film), that is, a so-called tape carrier. By doing so, it is attempted to achieve high density and thin and lightweight. Such a mounting method is based on COF (Chip on FPC (Flexible)
Printed Cicuit board)) method. A semiconductor device in which a semiconductor element is mounted on such a tape carrier is called a tape carrier package semiconductor device.

An outline of a manufacturing process of a tape carrier package semiconductor device using a conventional mounting method by the COF method will be described with reference to FIGS. 4 and 5.

First, as shown in FIG. 4, a semiconductor element (IC (Integrated Circuit) chip) 101 having an input / output terminal electrode 102, which is an aluminum pad, on its surface.
Is prepared, and a thickness of 10 is provided on the input / output terminal electrode 102.
A gold (Au) bump 103 having a thickness of approximately 18 μm is formed. An insulating film substrate 104 mainly made of a plastic insulating material such as polyimide resin or polyester
A tape carrier 107 having a metal wiring pattern 105 formed on the surface of (insulating tape) is prepared.

Next, the semiconductor element 101 on which the gold bumps 103 are formed is aligned with the tape carrier 107. That is, as shown in FIG. 4, the gold bumps 103 are aligned so that they coincide with predetermined positions of the metal wiring pattern 105.

Here, the metal wiring pattern 105 is mainly composed of a conductor such as copper (Cu), and tin (S) is formed on the conductor surface.
n) Plated or gold (Au) plated. The metal wiring pattern 105 includes inner leads, outer leads, intermediate leads, and the like. The insulating film substrate 104 has a strip shape and is also called a tape carrier. Although not shown, the insulating film substrate 104 has sprockets on both side edges (front and rear edges in the figure) so that the sprocket rollers can move in the longitudinal direction (left and right directions in the figure). There are feed holes (sprocket holes) that mesh with the teeth of the rollers at regular intervals.

After the above-mentioned alignment of the semiconductor element 101 and the tape carrier 107, as shown in FIG. 4, by thermocompression bonding using a bonding tool 106,
The gold bump 103 and the metal wiring pattern 105 on the surface of the insulating film substrate 104 are bonded (bonded).
This joining method is generally referred to as inner lead bonding (ILB).

After inner lead bonding, although not shown, resin sealing is performed using a resin material such as epoxy resin or silicone resin. The resin encapsulation is performed, for example, by a method in which the resin is applied to the periphery of the semiconductor element using a nozzle for ejecting the resin, and heat is applied by a reflow method or the like to cure the resin. After that, a necessary portion is punched out from the continuous tape-shaped insulating film substrate 104 to complete the tape carrier package semiconductor device. This tape carrier package semiconductor device is mounted on a liquid crystal display panel or the like as an individual semiconductor integrated circuit.

The gap between the surface of the semiconductor element 101 facing the tape carrier 107 and the metal wiring pattern 105 during inner lead bonding is determined by the height of the gold bumps 103 formed on the semiconductor element 101. It is generally about 10 to 20 μm.
In this gap, as shown in FIG. 5, the tape carrier 107 is deformed at the time of inner lead bonding, and a contact portion 117 shown as a circled portion in FIG.
The metal wiring pattern 105 and the peripheral edge portion (edge portion) 108 of the semiconductor element 101 may come into contact with each other. This contact may cause a leakage (leakage) current and cause malfunction of the semiconductor device. In addition, FIG.
5 is an enlarged view of the periphery of the contact portion 117 in FIG.

The cause of the deformation of the tape carrier 107 is
It can be explained as follows. That is, the tape carrier 1 due to the thermal stress applied during the inner lead bonding.
When the 07 expands and then contracts, the insulating film substrate 1
04 and the metal wiring pattern 105 are formed of materials having different thermal expansion coefficients, so that non-uniform expansion / contraction occurs. It is considered that the tape carrier 107 is deformed such as waviness as a result of the uneven expansion and contraction.

Further, in FIG. 5, the metal wiring pattern 105 and the semiconductor element 1 are formed by the deformation of the tape carrier 107.
The case where the metal wiring pattern 105 and the peripheral portion 108 contact each other has been described.
It may be caused by other factors. That is, when the semiconductor element 101 is tilted or deviated from a predetermined position, the pressure by the bonding tool 106 may not be uniformly applied to the semiconductor element 101 during inner lead bonding. In such a case, the semiconductor device 10
There is a possibility that excessive pressure will be applied to the peripheral portion 108 of No. 1 and contact with the metal wiring pattern 105.

Most of the surface of the semiconductor element 101 has an insulating surface protective film (passivation film) 109.
Since it is covered with, even if it contacts with the metal wiring pattern 105, a leak current does not occur. However, the peripheral portion 108 of the semiconductor element 101 is covered with the surface protective film 109 due to the influence of the dicing process for dividing the wafer, which is an assembly of a plurality of semiconductor elements including the semiconductor element 101, into one semiconductor element 101. Since it does not exist, a leak current is generated when it comes into contact with the metal wiring pattern 105, which causes malfunction of the semiconductor device.

In this way, the semiconductor element 101 is
In the case of bonding to the metal wiring pattern 105 formed on the film substrate by the method, the peripheral portion 1 of the semiconductor element 101 is inclined due to the inclination or displacement of the semiconductor element 101, deformation of the tape carrier 107 due to thermal stress or excessive pressure at the time of bonding, or the like.
08 and the metal wiring pattern 105 come into contact with each other to generate a leak current, which is extremely likely to cause a defective electrical characteristic.

By the way, techniques for preventing the occurrence of defects due to the contact between the end of the semiconductor element and the metal wiring pattern (referred to as edge touch) are disclosed in JP-A-5-13516 and JP-A-5-63035. ing. Here, the main points of the techniques disclosed in these publications are shown.

In JP-A-5-63035, as shown in FIG. 7, a tape (base material) 201 and a wiring lead 2 are provided.
02 tape carrier and chip (semiconductor device) 2
In a semiconductor device in which 04 and 04 are joined by bumps 205,
By making the inner lead 203 of the wiring lead 202 a bent type (flying lead type), contact between the chip edge 206 of the chip 204 and the wiring lead 202 (edge touch) is prevented. In JP-A-5-63035, pressure is applied to the lead side when inner lead bonding is performed, and edge touch is less likely to occur.

On the other hand, in the technique of Japanese Patent Laid-Open No. 13516/1993, the lead is not structured to prevent edge touch because it does not adopt the form of bending the lead as in Japanese Patent Laid-Open No. 5-63035. Japanese Patent Laid-Open No. 5-13
In the technology of Japanese Patent No. 516, when the leads of the tape carrier 107 are bonded to the gold bumps 103 on the semiconductor element 101 using the bonding tool 106, as shown in FIG. By providing a support ring 113 made of an insulator between the edges of the semiconductor element 101 and the tape carrier 10.
The contact (edge touch) with the lead 7 is prevented.

[0018]

[Patent Document 1] Japanese Unexamined Patent Publication No. 5-63035
The flying lead type described in the publication is a technique for connecting a chip (semiconductor element) 204 and a circuit board,
That is, it is a tape carrier for so-called TAB (Tape Automated Bonding) technology, and thus can be realized. That is, in the tape carrier used for the TAB technique as described in JP-A-5-63035,
Since the tape (base material) 201 is not present on the inner lead 203, it is possible to prevent edge touch by bending the inner lead 203.

However, a semiconductor device in which a semiconductor element is mounted on a tape carrier by the COF method (hereinafter referred to as CO
In (F semiconductor device), since the insulating tape (base material) made of a relatively hard material such as polyimide exists over the entire area of the tape carrier overlapping the semiconductor element, the tape carrier is very difficult to bend. Therefore, it is impossible to prevent edge touch by bending the tape carrier. Therefore, the technique disclosed in Japanese Patent Laid-Open No. 5-63035 has a problem that it cannot be applied to COF semiconductor devices.

Further, in the conventional technique disclosed in Japanese Patent Laid-Open No. 13516/1993, a new material such as a thermosetting resin for providing the support ring 113 is required, whereby a tape carrier package semiconductor device is manufactured. This will increase costs.

The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to cope with a COF semiconductor device and to prevent malfunction due to contact between an end portion of a semiconductor element and a wiring pattern at low cost. Another object of the present invention is to provide a tape carrier package semiconductor device and its manufacturing method.

[0022]

The inventors of the present application have made earnest studies to achieve the above-mentioned object, and as a result, by improving the structure of the wiring pattern, a COF semiconductor device can be dealt with and a semiconductor element at the time of bonding can be obtained. It has been found that it is possible to prevent contact (edge touch) between the end portion of the device and the wiring pattern, and prevent malfunction of the device.

In order to solve the above problems, the tape carrier packaged semiconductor device of the present invention is a tape carrier in which a wiring pattern is formed on an insulating tape, and a semiconductor arranged so as to face the tape carrier. An element, the semiconductor element has a connecting terminal at a position inside the outer periphery of the facing surface on the facing surface facing the tape carrier, and the wiring pattern has a part thereof,
While it is a bonding part that is bonded to the connection terminal via a bump, the other part is an extending part that extends from the vicinity of the bonding part to the outside of the region that overlaps with the facing surface of the semiconductor element. tape carrier package semiconductor device, the upper
A part of the wiring pattern bites into the bump, and in the extended portion of the wiring pattern, a thin portion having a thickness smaller than the thickness of the bonding portion is provided at a position at least overlapping with the outer periphery of the facing surface of the semiconductor element. Is formed and the thickness of the thin part
The difference between the thickness of the junction and the thickness of the joint
The feature is that it is set to be larger than the bite amount .

According to the above structure, the thickness of the gap between the outer periphery of the facing surface of the semiconductor element facing the tape carrier and the wiring pattern can be made wider than before.

That is, for example, in a structure using a general semiconductor element in which the surface on which the connection terminals are formed (the surface facing the tape carrier) is a flat surface,
Let us assume that the semiconductor element and the insulating tape are evenly spaced. Assuming this, if the wiring pattern has a uniform thickness as in the prior art, unless the tape carrier is bent, the gap between the outer circumference of the facing surface of the semiconductor element facing the tape carrier and the wiring pattern is The thickness is equal to the bump thickness. On the other hand, in the configuration of the present invention, since the wiring pattern at a position overlapping the outer periphery of the facing surface of the semiconductor element is formed thinner than the thickness of the joint portion of the wiring pattern, without bending the tape carrier,
The thickness of the gap between the outer periphery of the facing surface of the semiconductor element facing the tape carrier and the wiring pattern is larger than the thickness of the bump.

As described above, since the thickness of the gap between the outer periphery of the facing surface of the semiconductor element facing the tape carrier and the wiring pattern can be made wider than before, the inclination or displacement of the semiconductor element at the time of joining, the heat at the time of joining, and the like. Even if the spacing between the semiconductor element and the insulating tape cannot be kept uniform due to deformation of the tape carrier due to stress or excessive pressure, the outer periphery of the facing surface of the semiconductor element facing the tape carrier and the wiring pattern are It is possible to avoid contact. Therefore, it is possible to prevent the occurrence of leak (leakage) current. As a result, it is possible to provide a tape carrier package semiconductor device in which malfunction due to leakage current is prevented.

Further, in the above structure, it is not necessary to bend the insulating tape as in the structure of Japanese Patent Laid-Open No. 5-63035, so that it can be applied to a COF semiconductor device.

Further, with the above-mentioned structure, Japanese Patent Application Laid-Open No. 5-135 is known.
Unlike the prior art disclosed in Japanese Patent Publication No. 16, the new material such as the thermosetting resin for providing the support ring 113 is not required, so that the manufacturing cost can be reduced.

FIG. 1 of JP-A-5-63035
Then, it seems that the thickness of the lead (inner lead) at the connecting portion of the element is different from the thickness of the lead (intermediate lead, outer lead) at the extended portion. However, JP-A-5-63
In [0010] of Japanese Patent No. 035, the material of the wiring lead consisting of the inner lead, the outer lead, and the intermediate lead is Cu having a thickness of about 35 μm as a base material, and the surface thereof has a thickness of Sn of about 0.4 μm. It is described that plating is performed, and the thickness of these leads is actually the same.

A metal wiring pattern is suitable as the wiring pattern used in the tape carrier package semiconductor device of the present invention, but a wiring pattern made of another conductive material such as a semiconductor or a conductive resin may be used.

Further, in the tape carrier package semiconductor device of the present invention, the entire extension portion may be thinner than the thickness of the joint portion with the semiconductor element, and only a part of the extension portion in the vicinity of the joint portion may be formed. It may be thinner than the thickness of the junction with the semiconductor element.

However, in the tape carrier package semiconductor device of the present invention, the thin portion has a length along the longitudinal direction of the wiring pattern that is longer than the distance between the outer periphery of the facing surface of the semiconductor element and the connection terminal. It is preferably long.

According to the above structure, contact between the outer periphery of the facing surface of the semiconductor element and the wiring pattern can be prevented more reliably.

In the tape carrier package semiconductor device of the present invention, preferably, the thickness of the thin portion is less than half the thickness of the joint portion.

According to the above structure, contact between the outer periphery of the facing surface of the semiconductor element and the wiring pattern can be prevented more reliably.

In order to solve the above-mentioned problems, the method of manufacturing a tape carrier package semiconductor device of the present invention comprises a step of manufacturing a tape carrier by forming a wiring pattern on an insulating tape, and a step inside the outer periphery. For a semiconductor element having a connection terminal, a step of stacking the tape carrier with the bump sandwiched between the connection terminal and a part of the wiring pattern, and applying the pressure and heat to the bump to connect the tape carrier In a method of manufacturing a tape carrier package semiconductor device, which comprises a step of joining a terminal and a wiring pattern with the bump, a step of joining with the bump
Then, the step of making a part of the wiring pattern into the bump to manufacture the tape carrier includes the step of forming a wiring pattern having a uniform thickness on the insulating tape, and the part of the wiring pattern having a different thickness. And the thinner part of the wiring pattern.
The difference in thickness from the thick part is the wiring pattern to the bump
So as to be larger than the biting amount of the wiring pattern, including a step of processing the wiring pattern, in the step of stacking the tape carrier on the semiconductor element, while contacting at least a part of the thick portion of the wiring pattern with the bump, The thin portion of the wiring pattern is made to face the outer circumference of the semiconductor element so that the thickness of the gap between the outer circumference of the facing surface of the semiconductor element facing the tape carrier and the wiring pattern is thicker than the thickness of the bump. Is characterized by.

According to the above method, when the connection terminal and the wiring pattern are joined together, the thickness of the gap between the outer periphery of the facing surface of the semiconductor element and the wiring pattern can be determined without bending the tape carrier. Can be made thicker than that of the conventional structure (thus equivalent to the thickness of the bumps). Thus, when the connection terminals and the wiring pattern are joined by the bumps, the outer circumference of the facing surface of the semiconductor element is inclined due to tilting or displacement of the semiconductor element, deformation of the tape carrier due to thermal stress or excessive pressure during joining, and the like. Even if the gap between the wiring pattern and the wiring pattern is extremely narrowed, it is possible to avoid contact between the wiring pattern and the outer periphery of the facing surface of the semiconductor element that faces the tape carrier, and therefore leakage (leakage) current Can be prevented. As a result, it is possible to stably manufacture the tape carrier package semiconductor device in which the malfunction due to the leak current is prevented.

Further, according to the above method, Japanese Patent Laid-Open No. 5-1351
Unlike the prior art disclosed in Japanese Patent Publication No. 6, no new material such as a thermosetting resin for providing the support ring 113 is required, so that the tape carrier package semiconductor device can be manufactured at low cost.

Further, in the above method, since the insulating tape is not bent unlike the structure of Japanese Patent Laid-Open No. 5-63035, there is an advantage over the method of Japanese Patent Laid-Open No. 5-63035.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A tape carrier package semiconductor device according to an embodiment of the present invention will be described below with reference to FIG. Here, an ideal tape carrier package semiconductor device in which the distance between the semiconductor element and the insulating film is completely uniform will be described.

As shown in FIG. 1, the tape carrier package semiconductor device according to the present embodiment includes a tape carrier 7.
And the semiconductor element 1 arranged to face the tape carrier 7.

The surface of the semiconductor element 1 that faces the tape carrier 7 (hereinafter simply referred to as the facing surface) is a flat surface, and the aluminum for input and output of the semiconductor element 1 is located inside the outer circumference (end) 8. It has an aluminum pad (connection terminal) 2 which is an electrode pad. In addition, as shown in FIG. 2B, a surface protection which is an insulating film for protecting the surface of the semiconductor element 1 is provided on the opposing surface of the semiconductor element 1 except for the aluminum pad 2 portion and the vicinity of the outer periphery 8. A film (passivation film) 9 is formed. further,
Gold (Au) bumps 3 having a thickness of about 10 to 20 μm are formed on the aluminum pads 2 on the surface of the semiconductor element 1. Note that in FIG. 2A, the surface protection film 9 is not shown for simplification of the drawing.

The tape carrier 7 is formed by forming a metal wiring pattern (wiring pattern) 5 on a flat insulating film (insulating tape) 4. The insulating film 4 is a film (film substrate) whose main material is a plastic insulating material such as polyimide resin or polyester. Although not shown, the insulating film 4 has sprocket rollers on both side edges (front and back edges in the figure) so that the sprocket rollers can move in the longitudinal direction (left and right directions in the figure). There are feed holes (sprocket holes) that mesh with the teeth of the machine at regular intervals.

The metal wiring pattern 5 is mainly composed of a metal such as copper (Cu), and the metal surface is plated with tin. The type of plating on the metal surface is not particularly limited and may be gold (Au) plating or the like. Further, when gold is used as the metal, the plating itself can be omitted. The metal wiring pattern 5 has the semiconductor element 1
There are inner leads for connection with, outer leads for connection with an external circuit, intermediate leads connecting these, etc., but since the types are not related to the present invention, detailed description of these types is omitted. To do.

A part of the metal wiring pattern 5 is a bonding portion 10 which is bonded to the aluminum pad 2 via the gold bump 3, while the remaining portion of the semiconductor element 1 is located in the vicinity of the bonding portion 10. The extension portion 11 is extended (routed) outside the area overlapping the facing surface. The extended portion 11 is for connection with another terminal of the semiconductor element 1 or connection with an external circuit.

In the extended portion 11 of the metal wiring pattern 5, a thin portion 1 having a thickness T2 smaller than the thickness T1 of the joint portion 10 is provided around the position where it overlaps with the outer periphery 8 of the facing surface of the semiconductor element 1.
1a is formed in a predetermined size.

The thickness T2 of the thin portion 11a is determined by the semiconductor element 1
It is preferable that the thickness is less than or equal to 1/2 of the thickness T1 of the joint portion 10 with The reason for this will be described below. In order to reliably bond the metal wiring pattern 5 and the gold bump 3, the metal wiring pattern 5 needs to be bitten into the gold bump 3 to some extent. The biting amount (thickness) of the metal wiring pattern 5 into the gold bump 3 is determined in consideration of the thickness T1 of the joint portion 10 of the metal wiring pattern 5.
Usually, the thickness is set to a little less than 1/2 of the thickness T1 of the joint portion 10. At present, the minimum thickness T1 is about 10 μm, and the bite amount is about 4 to 5 μm, but when the thickness T1 becomes about 5 μm in the future, the bite amount is 2 μm.
It is considered to be about m. Then, the difference between the thickness T2 of the thin portion 11a and the thickness T1 of the joining portion 10 (T1-T2).
Is preferably at least larger than the above bite amount. Therefore, the difference (T1−T2) in thickness between the thin portion 11a and the joint portion 10 is larger than 1/2 of the thickness T1 of the joint portion 10, that is, the thickness T2 of the thin portion 11a is in the joint portion 10 with the semiconductor element 1. It is preferable that the thickness is less than 1/2 of the thickness T1.

The thin portion 11a has a length L2 along the longitudinal direction of the metal wiring pattern 5 (longitudinal direction of wirings forming the metal wiring pattern 5; left and right direction in the drawing) of the facing surface of the semiconductor element 1. It is preferably longer than the distance L1 between the outer periphery 8 and the aluminum pad 2.

In this embodiment, the thickness T1 of the metal wiring pattern 5 of the joint portion 10 with the semiconductor element 1 is set to a normal thickness of 10 to 20 μm, and the thickness T2 of the thin portion 11a is joined with the semiconductor element 1. The thickness was set to 5 to 10 μm, which is about ½ of the thickness of the portion 10. In addition, the length L of the thin portion 11a
2 was set to 100 μm.

Next, a method of manufacturing the tape carrier package semiconductor device will be described with reference to FIG.
The conditions of each process used in the manufacturing method of the present embodiment are the same as the conditions used in the conventional ordinary semiconductor integrated circuit mounting process, and the detailed description thereof will be omitted.

First, as shown in FIG. 2, a semiconductor element 1 having an aluminum pad 2 and a gold (Au) bump 3 formed on the inner side of the outer periphery of one surface is manufactured. That is, after forming the surface protective film 9 so as to cover the semiconductor element 1, the semiconductor element 1 is opened by opening a predetermined position of the surface protective film 9.
The aluminum pad 2 is formed on one surface of the. Further, dicing (cutting) for dividing a wafer, which is an assembly of a plurality of semiconductor elements including the semiconductor element 101, into one semiconductor element 101 is performed. At this time, as shown in FIG. 2B, the surface protective film 9 near the outer periphery of one surface of the semiconductor element 1 is removed. Next, gold (Au) bumps 3 are formed on the aluminum pads 2 of the semiconductor element 1.

Further, the metal wiring pattern 5 having the thin portion 11a is formed on the surface of the insulating film 4, and the tape carrier 7 is manufactured. The method for forming the metal wiring pattern 5 having the thin portion 11a is not particularly limited, but after forming the metal wiring pattern having a uniform thickness, a predetermined area of the metal wiring pattern 5 is formed more than other portions. The thin portion 11a may be processed by thinning. By doing so, it is only necessary to add a metal wiring pattern processing step to the normal tape carrier manufacturing step, and no additional material is required.
Can be formed. Further, as a method of processing the metal wiring pattern, the surface layer portion of a predetermined region of the metal wiring pattern having a uniform thickness equal to the thickness T1 of the joint portion 10 has a predetermined thickness (the thickness T1 of the joint portion 10 and the thin portion 11a). Difference with the thickness of
It is advisable to remove only by the etching method.

Then, tin (S
n) Apply plating.

Then, as shown in FIG. 2, the semiconductor element 1 on which the gold bumps 3 are formed is aligned with the metal wiring pattern 5 formed on the insulating film 4. That is, the tape carrier 7 is overlaid on the aluminum pad 2 of the semiconductor element 1 with the gold bumps 3 interposed therebetween so that the gold bumps 3 come into contact with a predetermined portion (bonding portion 10) of the metal wiring pattern 5. At this time, the metal wiring pattern 5 brings the thick joint portion 10 into contact with the gold bump 3 while the semiconductor element 1
The thin portion 11a of the metal wiring pattern 5 is formed so that the thickness of the gap between the outer periphery of the opposing surface facing the tape carrier 7 and the metal wiring pattern 5 is larger than the thickness of the gold bump 3.
Are opposed to the outer periphery of the semiconductor element 1.

After that, the semiconductor element 1 and the tape carrier 7
Inner bonding with. That is, the semiconductor element 1 is connected to the tape carrier 7 by a face-down method by joining (bonding) the gold bumps 3. The gold bumps 3 are joined by thermocompression bonding which applies pressure and heat to the gold bumps 3. In this embodiment, the tape carrier 7 is placed on a stage (not shown), and as shown in FIG.
By pressing the semiconductor element 1 toward the tape carrier 7 (downward in the figure) with the heated bonding tool 6, near the interface between the gold bump 3 and the metal wiring pattern 5 (tin plating layer on the surface of the metal wiring pattern 5). A eutectic reaction of gold and tin (Au.Sn) is caused to bond the gold bump 3 and the metal wiring pattern 5. The bonding conditions are, for example, a heating temperature of the bonding tool 6 of about 400 ° C. and a stage temperature of 100.
The load applied to the semiconductor element 1 by the bonding tool 6 may be 150 to 200 N at about 200 to 200 ° C. Note that in FIG. 2A, the bonding tool 6 is omitted for the sake of simplification of the drawing.

Thereafter, if necessary, a resin material such as an epoxy resin or a silicone resin is used for resin sealing, and a necessary portion is punched out from the continuous tape-shaped insulating film 4 to form a tape carrier package semiconductor device. To complete. The completed tape carrier package semiconductor device is mounted on a liquid crystal display panel or the like. The resin sealing may be performed by, for example, applying a resin around the semiconductor element using a nozzle that discharges the resin, and applying heat by a reflow method or the like to cure the resin.

FIG. 1 shows an ideal tape carrier package semiconductor device in which the distance between the semiconductor element 1 and the insulating film 4 is completely uniform. However, in the current mounting technology, the semiconductor element 1 at the time of bonding is shown. Is inevitable, and the tape carrier 7 is inevitably deformed due to thermal stress or excessive pressure during bonding. Therefore, in an actual tape carrier package semiconductor device, the gap between the semiconductor element 1 and the insulating film 4 is not completely uniform, and the gap between the outer periphery 8 of the facing surface of the semiconductor element 1 and the tape carrier 7 is as shown in FIG. May be narrower than.

Next, the tape carrier 7 is deformed due to the thermal stress during bonding, and the gap between the outer periphery 8 of the semiconductor element 1 facing the outer periphery 8 and the tape carrier 7 is narrowed. Will be described with reference to the cross-sectional view of FIG. Note that FIG.
FIG. 3A is a sectional view showing the overall configuration of this tape carrier package semiconductor device, and FIG.
It is an expanded sectional view near the thin part 11a in the tape carrier package semiconductor device of (a).

In the tape carrier package semiconductor device of the present embodiment, as shown in FIG. 3, the tape carrier 7 at the portion pressing the semiconductor element 1 is lowered due to the thermal stress at the time of inner lead bonding, and the tape carrier 7 Deformation occurs in a portion closer to the semiconductor element 1 (upward in the drawing) on the outer side of the joining portion 10 (deformation portion 12 indicated by a circle in FIG. 3).

As described above, the tilt, displacement, thermal stress,
When such deformation of the tape carrier 7 occurs due to excessive pressure, in the conventional tape carrier package semiconductor device, the peripheral portion 108 of the semiconductor element 101 comes into contact with the metal wiring pattern 105 as shown in FIG. A leak current is generated, causing an electrical failure of the semiconductor device.

On the other hand, in the tape carrier package semiconductor device of the present embodiment, the extended portion 11 of the metal wiring pattern 5 is formed around the position where it overlaps with the outer periphery 8 of the semiconductor element 1 (the semiconductor element of the metal wiring pattern 5). By providing a thin thickness (thin portion 11a) in the immediate vicinity of the joint portion 10,
As shown in FIG. 3, even if the deformation occurs such that the outer portion of the tape carrier 7 approaches the semiconductor element 1, contact between the outer periphery 8 of the facing surface of the semiconductor element 1 and the metal wiring pattern 5 is avoided. be able to.

The tape carrier package semiconductor device of this embodiment is a COF semiconductor device in which the semiconductor element 1 is mounted on the tape carrier 7 by the COF method, and the insulating film 4 is present below the semiconductor element 1. To do.
Therefore, as in the technique disclosed in Japanese Patent Application Laid-Open No. 5-63035, the metal wiring pattern 5 is bent and edge-touched (the outer periphery 8 of the facing surface of the semiconductor element 1 and the metal wiring pattern 5).
It is impossible to prevent (contact with). On the other hand, in the present embodiment, by thinning the portion (extended portion 11) other than the joint portion 10 (the contact portion between the gold bump 3 and the metal wiring pattern 5) in the metal wiring pattern 5, CO
Edge touch in the F semiconductor device can be prevented.

Although the thickness of a part of the extended portion 11 of the metal wiring pattern 5 is thin in the present embodiment, the thickness of the entire extended portion 11 may be thin. Further, in the present embodiment, the thickness of the thin portion 11a of the metal wiring pattern 5 is made thinner than the normal thickness (10 to 20 μm) to be thinner than the thickness of the joint portion 10 of the metal wiring pattern 5. The thickness of the joint portion 10 of the pattern 5 is set to the normal thickness (10
Needless to say, the same effect can be obtained even if the thickness is made thicker than 20 μm.

Further, in this embodiment, after the gold bump 3 is formed on the aluminum pad 2, the metal wiring pattern 5 is formed.
However, the gold bump 3 may be formed on the metal wiring pattern 5 at a position corresponding to the aluminum pad 2 by the transfer bump method and then bonded to the aluminum pad 2.

Further, although the aluminum pad 2 is used as the connection terminal in the present embodiment, a pad made of another conductor may be used as the connection terminal. Further, although the gold bumps 3 are used as the bumps in the present embodiment, bumps made of another conductor such as copper may be used.

[0066]

As described above, the tape carrier package semiconductor device of the present invention includes the tape carrier having the wiring pattern formed on the insulating tape and the semiconductor element arranged so as to face the tape carrier. Equipped with
The semiconductor element has a connecting terminal at a position inside the outer periphery of the facing surface on the facing surface facing the tape carrier, and the wiring pattern has a part thereof connected to the connecting terminal via a bump. In the tape carrier package semiconductor device, the wiring is the joined portion that is joined, while the other portion is an extended portion that extends from the vicinity of the joined portion to the outside of the region overlapping the facing surface of the semiconductor element. Patta
A part of the bump digs into the bump, and a thin portion having a thickness smaller than the thickness of the bonding portion is formed in the extended portion of the wiring pattern at a position at least overlapping with the outer periphery of the facing surface of the semiconductor element. The thickness of the thin part and the joint part
The difference from the thickness is the amount that the wiring pattern digs into the bump.
The configuration is set to be even larger .

According to the above structure, the thickness of the gap between the outer periphery of the facing surface of the semiconductor element facing the tape carrier and the wiring pattern can be made wider than before. Therefore, even when the distance between the semiconductor element and the insulating tape cannot be kept uniform due to the inclination or displacement of the semiconductor element at the time of bonding, the deformation of the tape carrier due to the thermal stress or excessive pressure at the time of bonding, etc. It is possible to avoid contact between the wiring pattern and the outer periphery of the facing surface of the element that faces the tape carrier. Therefore, the above configuration has an effect that it is possible to provide the tape carrier package semiconductor device in which the malfunction due to the leakage current is prevented.

Further, in the above structure, since it is not necessary to bend the insulating tape unlike the structure of Japanese Patent Laid-Open No. 5-63035, it is possible to obtain the effect of being applicable to a COF semiconductor device.

Further, in the above structure, the contact between the outer periphery of the facing surface of the semiconductor element and the wiring pattern can be prevented without adding a new material such as a thermosetting resin, so that the manufacturing cost can be reduced. can get.

Further, in the tape carrier package semiconductor device of the present invention, preferably, the thin portion has a length along the longitudinal direction of the wiring pattern, that is, the outer periphery of the facing surface of the semiconductor element and the connection terminal. It is longer than the distance.

Therefore, the above structure has an effect that it is possible to more reliably prevent the contact between the outer periphery of the facing surface of the semiconductor element and the wiring pattern.

Furthermore, the tape carrier package semiconductor device of the present invention is preferably configured such that the thickness of the thin portion is less than half the thickness of the joint portion.

Therefore, the above structure has an effect that it is possible to more reliably prevent the contact between the outer periphery of the facing surface of the semiconductor element and the wiring pattern.

As described above, the method of manufacturing the tape carrier package semiconductor device of the present invention includes the step of joining the connection terminal and the wiring pattern with the bump by applying pressure and heat to the bump. in the method of manufacturing, engineering joining with the bump
In the process, the step of biting the wiring pattern into the bumps to manufacture the tape carrier includes the step of forming a wiring pattern having a uniform thickness on the insulating tape, And the thinner part of the wiring pattern.
The difference in thickness from the thick part is the wiring pattern to the bump
In the step of stacking the tape carrier on the semiconductor element before bonding, including the step of processing the wiring pattern so that the wiring pattern becomes larger than the biting amount of the wiring pattern, at least a part of the thick portion of the wiring pattern is brought into contact with the bump. While letting
A method of causing a thin portion of the wiring pattern to face the outer circumference of the semiconductor element so that the thickness of the gap between the outer circumference of the facing surface of the semiconductor element facing the tape carrier and the wiring pattern becomes thicker than the thickness of the bump. Is.

According to the above method, the thickness of the gap between the outer periphery of the facing surface of the semiconductor element and the wiring pattern can be increased. Thus, when the connection terminals and the wiring pattern are joined by the bumps, the outer circumference of the facing surface of the semiconductor element is inclined due to tilting or displacement of the semiconductor element, deformation of the tape carrier due to thermal stress or excessive pressure during joining, and the like. Even if the gap between the wiring pattern and the wiring pattern is extremely narrowed, it is possible to avoid contact between the outer periphery of the facing surface of the semiconductor element facing the tape carrier and the wiring pattern. Therefore, the above configuration has an effect that it is possible to stably manufacture the tape carrier package semiconductor device in which the malfunction due to the leakage current is prevented.

Further, in the above method, the contact between the outer periphery of the facing surface of the semiconductor element and the wiring pattern can be prevented without adding a new material, so that the tape carrier package semiconductor device can be manufactured at low cost. can get.

[Brief description of drawings]

1A and 1B are views showing an embodiment of a tape carrier package semiconductor device according to the present invention, in which FIG. 1A is a sectional view showing the whole, and FIG. 1B is an enlarged sectional view showing an outer periphery of a semiconductor element in an enlarged manner. It is a figure.

FIG. 2 is a diagram showing an example of a joining method for manufacturing a tape carrier package semiconductor device according to the present invention,
(A) is a sectional view showing the whole, and (b) is an enlarged sectional view showing the vicinity of the outer periphery of the semiconductor element in an enlarged manner.

3A and 3B are views showing how the tape carrier is deformed in the embodiment of the tape carrier package semiconductor device according to the present invention, where FIG. 3A is a sectional view showing the whole, and FIG. It is an expanded sectional view which expands and shows the outer periphery vicinity.

FIG. 4 is a cross-sectional view showing an example of a joining method for manufacturing a conventional tape carrier package semiconductor device.

5A and 5B are diagrams showing a state where a semiconductor element and a metal wiring pattern are in contact with each other in a conventional tape carrier package semiconductor device, FIG. 5A is a sectional view showing the whole, and FIG. 5B is a semiconductor element and a metal wiring pattern. FIG. 3 is an enlarged cross-sectional view showing the periphery of the contact portion of FIG.

FIG. 6 is a sectional view showing a configuration of a conventional tape carrier package semiconductor device.

FIG. 7 is a cross-sectional view showing the configuration of another conventional tape carrier package semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Aluminum pad (connection terminal) 3 Gold bump (bump) 4 Insulating film (insulating tape) 5 Metal wiring pattern (wiring pattern) 6 Bonding tool 7 Tape carrier 8 Outer periphery 9 Surface protective film 10 Bonding part 11 Extended portion 11a Thin portion 12 Deformation portion T1 Bonding portion thickness T2 Thin portion thickness L1 Distance between the outer periphery of the facing surface of the semiconductor element and the connection terminal L2 Length of the thin portion along the longitudinal direction of the metal wiring pattern

Claims (2)

(57) [Claims] 1. A tape carrier having a wiring pattern formed on an insulating tape, and a semiconductor element arranged so as to face the tape carrier, wherein the semiconductor element faces the tape carrier. Of the wiring pattern has a connecting terminal at a position inside the outer periphery of the facing surface, and a part of the wiring pattern is a bonding portion bonded to the connecting terminal through a bump, while In a tape carrier package semiconductor device in which the portion of the tape carrier package semiconductor device extends from the vicinity of the joint portion to the area outside the facing surface of the semiconductor element, a part of the wiring pattern bites into the bump, and the extended portion of the wiring pattern, so as to overlap with the outer periphery of the facing surfaces of at least a semiconductor element, are thin part is formed having a thickness less than the thickness of the junction, thin The difference between the thickness of the joint thickness between the parts is, distribution of the bumps
Set to be larger than the bite amount of the line pattern.
Tape carrier package semiconductor device characterized by being. 2. A step of manufacturing a tape carrier by forming a wiring pattern on an insulating tape, and a semiconductor element having a connecting terminal at a position inside an outer periphery, wherein the tape carrier is connected to the connecting terminal and the connecting terminal. Tape carrier package semiconductor device including a step of sandwiching a bump between a portion of a wiring pattern and the bump, and a step of joining the connection terminal and the wiring pattern with the bump by applying pressure and heat to the bump In the manufacturing method of, in the step of joining with the bump, a part of the wiring pattern is
The step of digging into the bumps and manufacturing the tape carrier includes the steps of forming a wiring pattern having a uniform thickness on the insulating tape, and making a part of the wiring pattern thinner than other parts , And the thin portion of the wiring pattern
The difference in thickness between the thick portion and the thick portion is the wiring pattern to the bump.
Including a step of processing a wiring pattern so as to be larger than the bite amount of the wiring, and in the step of stacking the tape carrier on the semiconductor element, at least a part of the thick portion of the wiring pattern is brought into contact with the bump. on the other hand, manufacturing method of a tape carrier package semiconductor device which the thin portion of the thickness of the upper Symbol wiring pattern, characterized in that to face the outer periphery of the semiconductor element.