JP3520739B2 - Liquid crystal device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal device. More specifically, it relates to an arrangement structure of terminals for inputting and outputting a signal for inspecting a liquid crystal device substrate of a liquid crystal device.

[0002]

2. Description of the Related Art In a liquid crystal device that displays information by utilizing the orientation state of liquid crystal, pixels are formed in a rectangular pixel portion (screen display area) formed in a matrix and in an area outside the pixel portion. The liquid crystal device substrate includes a data line driving circuit and a scanning line driving circuit that is also formed in an outer region of the pixel portion, and an opposing substrate that is arranged to face the liquid crystal device substrate. The counter substrate and the liquid crystal device substrate are bonded to each other with a gap layer containing a seal layer with a predetermined cell gap therebetween, and liquid crystal is sealed in the inner region of the seal layer.

On the liquid crystal device substrate side, the pixels formed in the above-mentioned pixel portion are supplied with image signals and scanning signals from the data line driving circuit and the scanning line driving circuit through the data lines and the scanning lines, respectively. Display based on. Therefore, if the data line or the scanning line has a defect such as an open or a short circuit, all the corresponding pixels become a display defect.

Therefore, an inspection circuit is formed on the liquid crystal device substrate, and an input / output signal terminal for inputting / outputting an inspection signal to / from the inspection circuit is formed in advance. Before the bonding step with the substrate, an inspection probe is applied to these input / output signal terminals to inspect the data lines and scanning lines for open or short. Conventionally, such input / output signal terminals for inspection are formed on the outer peripheral side of the substrate that does not contribute to display, for example, on the outer peripheral side region of the seal layer, in a region adjacent to the scanning line drive circuit.

[0005]

However, in the conventional liquid crystal device substrate, there is a sufficient margin for arranging the input / output signal terminals in the outer peripheral region of the seal layer, but there is a demand for high definition display. Corresponding to, when the number of pixels is increased,
It is necessary to expand the area where the scan line driving circuit is formed. However, conventionally, since the input / output signal terminal for the inspection signal is formed in the area adjacent to the scanning line driving circuit, there is a problem that the area where the scanning line driving circuit is formed cannot be expanded in this direction.

In view of the above problems, the object of the present invention is to
An object of the present invention is to realize a liquid crystal device capable of expanding the region where a drive circuit is to be formed by optimizing the formation positions of input / output signal terminals for inspection which are not used after the inspection.

[0007]

In order to solve the above problems, according to the present invention, a pixel portion composed of a plurality of pixels formed in a matrix by a plurality of data lines and a plurality of scanning lines, and the pixel portion A data line driving circuit formed on at least one end side of the data line in the outer region, and a pair of scanning line driving circuits formed on one side and the other side of the scanning line in the outer region of the pixel portion. A substrate for a liquid crystal device, a counter substrate arranged to face the substrate for a liquid crystal device, and the pixel unit and the data line driving circuit and the scanning line driving circuit along the outer peripheral edge of the pixel unit. A liquid crystal device having a gap material-containing seal layer formed between the counter substrate and the liquid crystal device substrate, wherein the data line drive circuit is formed on the liquid crystal device substrate. Opposition On the side, the inspection circuit which overlaps with the display screen parting member located inside the seal layer and is connected to the data line, and the region of the seal layer has a discontinuity at the corner of the pixel part. A gap control region formed along the outer peripheral edge of the pixel portion and formed by stacking a plurality of wiring layers formed of a material forming the pixel portion with an insulating film interposed therebetween, and the gap control region including the gap control region. And an inspection terminal connected to the inspection circuit and formed lower than the gap control region.

In the present invention, since the input / output signal terminal for inspection is not used after the liquid crystal device is completed, it is formed on the lower layer side of the seal layer, so that the formation area of the seal layer, which was a dead space, can be effectively used. it can. Therefore, it is possible to omit the portion occupied by the input / output signal terminals for inspection, without increasing the size of the liquid crystal device substrate and reducing the portion occupied by the pixel portion and the seal layer. The formation area of the drive circuit can be expanded. Therefore, with respect to the drive circuit, it is possible to improve the operation speed by expanding the channel width of the TFTs forming the drive circuit or to introduce a large-scale circuit. Conversely, since the peripheral portion of the liquid crystal device substrate can be reduced by omitting the portion that was conventionally occupied by the input / output signal terminal for inspection, the peripheral portion has the same size as the display area. A narrow liquid crystal device can be constructed. Moreover, even if unevenness is formed in the seal layer formation region due to the formation of the input / output signal terminal for inspection,
The input / output signal terminals for these inspections are formed in the gap control region formed along the outer peripheral edge of the pixel portion. Therefore, the cell gap between the liquid crystal device substrate and the counter substrate is With the gap control region, it can be secured with high accuracy. Also, since the input / output signal terminals for inspection are finally covered with the sealing layer and are completely insulated and separated from the liquid crystal side and the counter substrate, the counter substrate through the input / output signal terminals for inspection is used. It is possible to prevent an unnecessary short circuit between the liquid crystal device substrate and the liquid crystal device substrate.

Further, according to the present invention, when the pair of scanning line drive circuits formed outside the seal layer and the signal wiring electrically connected to each other are provided, the inspection circuit occupies the peripheral portion of the seal layer. Since the required space can be omitted, the drive circuit formation region can be expanded. Further, the area overlapping the display screen parting member is conventionally a dead space, and since the inspection circuit is formed therein, it is not necessary to reduce the area occupied by the pixel portion and the seal layer.

Further, according to the present invention, on the outside of the sealing layer,
A shift register circuit of the data line driving circuit, a buffer circuit, and a sample hold circuit that supplies an image signal to the data line based on a sampling signal from the buffer circuit are provided. A material forming the pixel portion is laminated on the data line connected to the sample hold circuit to form a part of the gap control region, and the gap control region is connected to the shift register. And an inspection terminal formed lower than the gap control region.

Further, according to the present invention, the shift register circuit and the buffer circuit of the data line driving circuit, which are provided outside the seal layer, overlap the display screen parting member and the sampling signal from the buffer circuit. A sample hold circuit for supplying an image signal to the data line based on the image signal line, and an image signal line for supplying the image signal on the lower layer side of the seal layer, and the sample hold circuit for the sampling signal from the buffer circuit. A material forming the pixel portion is laminated on a sampling signal input wiring supplied to a circuit to form a part of the gap control region, and the gap control region is connected to the shift register at the discontinuous portion. At the same time, an inspection terminal formed lower than the gap control region may be provided.

The present invention also provides, on the outside of the sealing layer,
The scanning line driving circuit is provided, and on the lower layer side of the seal layer, to the scanning line connected to the scanning line driving circuit,
An inspection in which the material forming the pixel portion is laminated to form a part of the gap control region, and the gap control region is connected to the shift register and formed lower than the gap control region at the discontinuity. And a terminal for use.

Further, according to the present invention, it is preferable that the plurality of wiring layers forming the gap control region form a redundant wiring structure in which they are conducted through a contact hole. Further, according to the present invention, it is preferable that a signal wiring for electrically connecting the pair of scanning line driving circuits is arranged outside the seal layer in which the inspection circuit is provided.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the accompanying drawings.

(Overall Structure of Liquid Crystal Device) FIGS. 1 and 2
3A is a plan view of a liquid crystal device to which the present invention is applied, and FIG. 6B is a cross-sectional view taken along the line H-H '.

As shown in these figures, the liquid crystal device LP
Is formed in a rectangular pixel portion 21 (screen display area) in which pixels to be described later are formed in a matrix, a data line driving circuit 22 formed in an area outside the pixel portion 21, and both sides of the pixel portion 21. A liquid crystal device substrate AM including a pair of scanning line drive circuits 23, and the liquid crystal device substrate AM
The counter substrate OP is arranged so as to oppose to each other. In FIG. 1, the scanning line drive circuit 23 is formed on both end sides of the scanning line, but it may be formed on only one side.
Further, although the data line drive circuit 22 is formed only on one side of the data line, it may be formed on the other end as well.

The counter substrate OP and the liquid crystal device substrate AM are
A predetermined cell gap is separated by a sealing layer GS containing a gap material formed along the outer peripheral edge of the pixel portion 21 in a region corresponding to the pixel portion 21 and the data line driving circuit 22 and the scanning line driving circuit 23. The liquid crystal LC is adhered and the liquid crystal LC is sealed in the inner region of the seal layer GS. Here, since the seal layer GS is partially discontinuous, the discontinuous portion constitutes the liquid crystal injection port 241. Therefore, in the liquid crystal device LP, if the inner region of the seal layer GS is depressurized after the counter substrate OP and the liquid crystal device substrate AM are bonded together, the liquid crystal injection port 24 is obtained.
The liquid crystal LC can be injected under reduced pressure from No. 1, and the liquid crystal injection port 241 is closed with the sealant 242 after the liquid crystal LC is sealed. The sealing layer GS may be made of epoxy resin or various ultraviolet curable resins, and as the gap material to be mixed therein, a cylindrical or spherical glass fiber or glass beads having a diameter of about 2 μm to about 6 μm may be used. it can.

Here, the counter substrate OP is the liquid crystal device substrate A.
Since the size is smaller than M, the peripheral portion of the liquid crystal device substrate AM is attached so as to protrude from the outer peripheral edge of the counter substrate OP. Therefore, the seal layer GS is formed along the outer peripheral edge of the substrate when viewed from the counter substrate OP, but is formed considerably inward from the outer peripheral edge of the substrate when viewed from the liquid crystal device substrate AM. A so-called frame region 26 is located between the seal layer GS and the outer peripheral edge of the substrate, and the frame region 26 is used to configure the data line drive circuit 22 and the scanning line drive circuit 23. Therefore, the scanning line drive circuit 23 and the data line drive circuit 22 are located outside the counter substrate OP and do not face the counter substrate OP.

In the liquid crystal device substrate AM, constant power sources VDDX, VSSX, V are provided on the side portion on the data line drive circuit 22 side.
DDY, VSSY, modulated image signal (image signal line VID1
To VID6), various signals (start signal DY, clock signal CLY, its inverted clock signal CLY bar, start signal DX, clock signals CLX1 to CLX4, and its inverted clock signals CLX1 bar to CLX4 bar) and the like. A large number of mounting terminals 25 are formed of a metal film such as the above, a metal silicide film, or a conductive film such as an ITO film. From these mounting terminals 25, the scanning line driving circuit 23 and the data line driving circuit 22 are connected.
A plurality of signal wirings 28 made of a low resistance metal film such as an aluminum film or a metal silicide film for driving the wirings are routed around, and these signal wirings 28 extend from the seal layer GS to the outer peripheral side of the substrate. In addition, the signal wiring 29 that electrically connects the pair of scanning line driving circuits 23 that face each other with the pixel portion 21 interposed therebetween is also used for data driving with respect to the pixel portion 21.
In the region opposite to the side where the passage 22 is formed, the seal layer GS passes through the substrate outer peripheral side. Note that, between the liquid crystal device substrate AM and the counter substrate OP, the counter electrode potential LCCOM externally input from the mounting terminal 25 is supplied to the counter substrate OP via the vertical conducting material 31.

The counter substrate OP has a liquid crystal LC for the pixel electrodes of each pixel formed on the liquid crystal device substrate AM side.
A common electrode 51 facing each other across the pixel and a black matrix BM1 formed so as to surround each pixel are formed. A black matrix BM2 for parting the display screen is also formed on the counter substrate OP along the inner peripheral edge of the seal layer GS.

(Structures of Liquid Crystal Device Substrate and Pixel Section) FIG. 3 is a block diagram of a liquid crystal device substrate having a built-in drive circuit used in the liquid crystal device of the present embodiment.

As can be seen from FIG. 3, the substrate A for liquid crystal device is used.
In M, a plurality of scanning lines Y (Y ₁ , Y ₂ ,
..) and a plurality of data lines X (X ₁ , X ₂ ...) Form a plurality of pixels PX in a matrix.

All the pixels PX are taken out and as shown in FIGS. 4 and 5, the scanning line Y and the data line X are extracted.
A pixel switching thin film transistor (hereinafter referred to as a TFT) TFT 60 connected to the pixel is formed. The drain electrode of the TFT 60 is a pixel electrode 9a that forms a liquid crystal cell with the liquid crystal LC sandwiched between the drain electrode and the counter electrode 51 of the counter substrate OP. For the liquid crystal cell, the storage capacitor CAP is configured by using the scanning line and the capacitance line 3d in the previous stage.

The pixel switching TFT 60 is shown in FIG.
Further, as can be seen from FIG. 14D, the gate electrode 3a which is a part of the scanning line Y and the source electrode 6a as the data line X are provided through the first contact hole 5a of the first interlayer insulating film 4. Source regions 1b, 1d electrically connected
And the first interlayer insulating film 4 and the first interlayer insulating film 4
The pixel electrode 9 made of an ITO film through the second contact hole 8a formed in the second interlayer insulating film 7 on the upper layer side.
a includes drain regions 1c and 1e electrically connected to each other.

(Structure of Driving Circuit) Referring again to FIG. 3, the data line driving circuit 2 formed on the liquid crystal device substrate AM.
2 is an X-side shift register circuit 221 and a buffer circuit 2
22, TF that operates based on the signal output from the X-side shift register circuit 221 via the buffer circuit 222
A sample and hold circuit 224 including analog switches S ₁ , S ₂ , S ₃ ... Composed of T, and 6 image signal lines VID 1 corresponding to the image signals expanded in 6 phases.
~ VID6 is configured.

FIG. 6 is an equivalent circuit diagram of the inspection circuit and the like formed on the liquid crystal device substrate shown in FIG. 3, and FIG. 7 is a timing chart diagram of pulses generated by the data line drive circuit formed on the liquid crystal device substrate. Is.

As shown in FIG. 6, the data line drive circuit 22
The X-side shift register circuit 221 is composed of, for example, four series to which a common start signal DX is input for each series, and each stage has one transfer inverter 226.
And a clocked inverter 227 for transfer, and a clocked inverter 228 for feedback, and has a static type configuration. Clocked inverter for feedback 2
A dynamic configuration without 28 may be used. Further, it goes without saying that the clocked inverters 227 and 228 may be composed of transmission gates and inverters. Here, as described with reference to FIG. 1, the X-side shift register circuit 221 is supplied with the start signal DX from the outside through the mounting terminal 25 and the clocked inverters 227 and 228 of the respective stages.
Are supplied with clock signals CLX1 to CLX4 and inverted clock signals CLX1 to CLX4 thereof. Therefore, as shown in FIG. 7, in the X-side shift register circuit 221, clock signals CLX1 to CLX4, which are slightly out of phase after the start signal DX is input,
The signal is shifted in synchronization with the rising edges of the inverted clock signals CLX1 bar to CLX4 bar to drive the shift signals (analog switches S ₁ , S ₂ , S ₃ ... Of the sample hold circuit 224). Bit signals Q ₁ , Q ₂ , Q ₃ ...) are generated and output. In FIG. 3, the bit signal Q whose phase is slightly shifted from the X-side shift register circuit 221 to the sample hold circuit 224 via the buffer circuit 222.
_{When 1} , Q ₂ , Q _3, ... Are output, each analog switch S ₁ , S ₂ , S _3, ... Is operated based on the bit signals Q ₁ , Q ₂ , Q ₃ ,. To do. As a result, modulated image signal supplied through the image signal line VID1~VID6 the data lines X ₁ at a predetermined timing, X _2, X ₃
Each pixel PX selected by the scanning signal that is taken in by ... And supplied through the scanning lines Y ₁ , Y ₂ , Y ₃ ...
Will be held in.

Similarly, in the scanning line driving circuit section 23, a Y-side shift register 231 that produces and outputs a shift signal (scanning signal) based on the start signal DY, the clock signal CLY, and its inverted clock signal CLY bar. Is configured.

(Structure of Gap Control Region) FIGS. 8 and 9 are an enlarged view of a corner portion AA and a corner portion BB of the liquid crystal device shown in FIG. 1, respectively.

The liquid crystal device substrate 1 having the above-mentioned structure is
As shown in FIG. 1, when the sealing layer GS is used to bond to the counter substrate OP via a predetermined cell gap, in the present embodiment, the pixel portion 21 is provided below the sealing layer GS in the liquid crystal device substrate AM. The gap control regions 41, 42, 43, 44 are formed along the outer peripheral edge of the. Here, the gap control regions 41, 42, 43, 44
Is a broken portion 40 at the corner portion 210 of the pixel portion 21.
Is configured to have.

Of such a gap control region, as shown in FIG. 8, FIG. 9 and FIG.
The gap control regions 42 and 43 formed between the scanning line driving circuit 23 and the scanning line driving circuit 23 are formed on the front surface side of each scanning line Y and the data line X.
And the wiring layers 421 and 431 formed at the same time are overlapped with each other to be configured along the sides of the pixel portion 21.

Further, as shown in FIGS. 8 and 14D, the gap control region 44 on the side opposite to the side where the scanning line drive circuit 22 is formed with respect to the pixel portion 21 is a wiring layer. 441 is formed at the same time as the scanning line Y, and the wiring layer 442 formed at the same time as the data line X is overlapped on the front surface side of the wiring layer 441 so as to be formed along the side of the pixel portion 21.

Further, as shown in FIG. 9 and FIG. 14D, the gap control region 41 formed between the pixel section 21 and the data line drive circuit 22 extends from the sample hold circuit 224 toward the pixel section 21. A wiring layer 411 formed at the same time as the scanning line Y is formed on the lower layer side of the data line X that extends along the side of the pixel portion 21.

The gap control region 4 thus configured
In Nos. 1, 42, 43, and 44, the two wiring layers are stacked in two layers on the lower layer side of the seal layer GS, so that the wiring layers are one step higher than the surroundings. Also, the overlapping part of these wiring layers is
Since they are lined up with a slight gap between adjacent wiring layers, they form a flat region as a whole. Therefore,
When the seal layer GS is formed in these gap control regions 41, 42, 43, 44, the gap material contained in the seal layer GS is used for the liquid crystal device between the gap control region GS of the liquid crystal device substrate AM and the counter substrate OP. Substrate AM and counter substrate OP
The cell gap between and will be defined with high accuracy.

(Improvement Example of Gap Control Region 41) FIG.
As shown in FIG. 7, on the data line driving circuit 22 side, the X-side shift register circuit 221, the buffer circuit 222, and the image signal line V formed from the outer peripheral edge of the substrate toward the pixel portion 21.
Of the ID1 to VID6 and the sample hold circuit 224, the gap control area 41 may be configured by using the area from the formation area of the image signal lines VID1 to VID6 to the formation area of the sample hold circuit 224. That is,
Many sampling signal input wiring patterns 2 for connecting the buffer circuit 222 and the sample hold circuit 224
25 and the image signal sampling wiring pattern 226 that connects the image signal lines VID1 to VID6 and the sample hold circuit 224.
The wiring layer 412 formed simultaneously with the wiring line 412 and the wiring layer 413 formed simultaneously with the scanning line Y may be stacked in two stages, and the gap control region 41 may be formed by the overlapping portion thereof.
Here, if the formation regions of the image signal lines VID1 to VID6 are also arranged on the lower layer side of the seal layer GS, the image signal lines VID1
Since the wiring layers for the image signal sampling wiring pattern 226 for connecting the VID6 to the sample and hold circuit 224 overlap the image signal lines VID1 to VID6, the wiring layers are two-tiered and can be used for gap control.

When the gap control region 41 is formed in this manner, the sample-hold circuit 224 is arranged inside the seal layer GS, which is equivalent to the seal layer G.
The X-side shift register circuit 22 in the portion outside S
1 and the width L4 of the formation region of the buffer circuit 222 can be expanded. Further, the portion where the sample hold circuit 224 is arranged is a black matrix BM2 for parting the display screen.
Since the hidden portion is effectively used, the width L5 of the sample hold circuit 224 can be expanded. Therefore, according to this embodiment, for the purpose of improving the display quality of the liquid crystal device LP, the on-current of the data line driving circuit 22 is increased due to the expansion of the channel width of the TFT (operating speed). Improvement), or the introduction of a large-scale circuit. That is, the liquid crystal device L of the present embodiment
In P, the formation area of the data line drive circuit 22 is substantially expanded without increasing the size of the liquid crystal device substrate AM and without reducing the area occupied by the pixel portion 21 and the seal layer GS. You can Conversely speaking, the seal layer GS
A sample hold circuit 224 is arranged on the inner side of the image signal line VID1 on the lower layer side of the seal layer GS.
Since ~ VID6 is arranged, X is provided outside the seal layer GS.
Only the side shift register circuit 221 and the buffer circuit 222 need be configured. Therefore, since the peripheral portion of the liquid crystal device substrate AM can be reduced, a liquid crystal device LP having a display region of the same size but a narrow peripheral portion can be configured.

If the entire data line drive circuit 22 is formed inside the seal layer GS, the potential of the direct current component applied to the data line drive circuit 22 may influence the deterioration of the liquid crystal and the disorder of the alignment. In the mode, since the sample hold circuit 224 is arranged in a portion covered with the black matrix BM2 for partitioning the display screen even inside the seal layer GS, even if the alignment of the liquid crystal is disturbed, the display It has the advantage of not degrading quality. Even if a part of the data line drive circuit 22 is overlaid on the seal layer GS, the gap material included in the seal layer GS is present only between the wiring layer and the counter substrate, and the data line drive circuit 22 is not provided.
Since the area where the TFTs forming the above is formed is avoided, the data line driving circuit 22 is not damaged by the gap material. Moreover, if the wiring layers formed in the gap control region 41 are electrically connected vertically through the contact holes, the data lines X and the scanning lines Y can have a redundant wiring structure in this portion, and these signal wirings can be formed by the gap material. The problem of disconnection can be reliably prevented. Further, in a configuration in which an aluminum layer or the like is formed in the outer peripheral area of the liquid crystal device substrate AM and the seal layer GS is formed thereon, when the seal layer GS is photocured, the counter substrate OP must be irradiated with ultraviolet rays. Therefore, there is a constraint that a quartz substrate or the like having a considerably high light transmittance must be used as the counter substrate OP. On the other hand, in the present embodiment, even when ultraviolet rays are irradiated from the liquid crystal device substrate AM side, the ultraviolet rays reach the seal layer GS through the gap between the wiring layers and cure, so that the light transmission of the counter substrate OP is performed. The demand for sex can be relaxed. Therefore, according to this embodiment, there is also an advantage that an inexpensive glass substrate can be used as the counter substrate OP.

(Structure of Inspection Circuit) As shown in FIG. 1, in the liquid crystal device substrate AM of the present embodiment, further, on the side opposite to the side where the data line drive circuit 22 is formed with respect to the pixel portion 21. An inspection circuit 70 for the data line X is also formed in the area overlapping the black matrix BM2 for dividing the display screen.

As shown in FIGS. 3 and 6, this inspection circuit 70 includes TFTs a ₁ , a ₂ ... (Switching circuit for inspection) and these TFTs a ₁ , a ₂ , a ₃ ... Four test signal wirings b ₁ , b ₂ , b ₃ , b ₄ electrically connected to the data lines X ₁ , X _2, ...
It has two inspection signal wirings c ₁ and c ₂ which are conductively connected to the gates of the TFTs a ₁ , a ₂ .

Signal wiring for inspection b₁, B₂, B₃, B
_FourAre TFTa lined up along these wirings.₁, A₂, A
₃... of every fourth TFTa₁, A₂, A₃・
.. is connected to. That is, the inspection signal wiring b₁Is
TFTa₁, A_{1 + 4N}・ ・ (Where N is a positive natural number)
Data line X₁, X_{1 + 4N}.., signal wiring for inspection b connected to
₂Is TFTa₂, A_{2 + 4N}.. through data line X₂, X
_{2 + 4N}.., signal wiring for inspection b connected to₃Is TFTa₃,
a_{3 + 4N}.. through data line X₃, X_{3 + 4N}・ ・ Connected to
Then, the fourth inspection signal wiring b_FourIs TFTa_Four, A_{4 + 4N}・
· Through data line X _Four , X_{4 + 4N}.. is connected to.
Any inspection signal wiring b₁, B₂, B₃, B_FourAlso that
Input / output signal terminal CX for inspection at each end₁, C
X₂, CX₃, CX_Four(Terminal for signal line inspection / Sample ho
Terminal for circuit circuit inspection).

Of the TFTs a ₁ , a ₂ , a ₃ ... Arranged along these wirings, the inspection signal wirings c ₁ , c ₂ are
Four TFTs are set as one group and are alternately connected to each group. That is, the inspection signal wiring c ₁ is T
FTa ₁ , a ₂ , a ₃ , a ₄ , a _{1 + 8N} , a _{2 + 8N} ,
Connect to the gates of a _{3 + 8N} and a _{4 + 8N} , and inspect signal wiring c ₂
Is TFT a ₅ , a ₆ , a ₇ , a ₈ , a _{5 + 8N} , a _{5 + 8N} , a
It is connected to the gates of _{5 + 8N} and a _{5 + 8N} . Each of the inspection signal wirings c ₁ and c ₂ has inspection input / output signal terminals TX ₁ and TX ₂ (signal line inspection terminal / sample and hold circuit inspection terminal) at its ends.

Further, as shown in FIG. 1, the inspection signal wiring drawn from the X-side shift register circuit 221 of the data line drive circuit 22 also has an inspection input / output signal terminal XEP.
₁ , XEP ₂ , XEP ₃ , XEP ₄ (shift register circuit inspection terminals) are provided, and the inspection signal wiring drawn from the Y-side shift register circuit 231 of the scanning line drive circuit 23 is also an input / output signal terminal for inspection YEP. ₁ , YEP ₂ (shift register circuit inspection terminal) are provided.

In this embodiment, the input / output signal terminals CX ₁ , CX ₂ , CX ₃ , CX ₄ , TX ₁ , T for these inspections are used.
X ₂ , XEP ₁ , XEP ₂ , XEP ₃ , XEP ₄ , YE
P ₁ and YEP ₂ are all shown in FIGS. 1, 8, 9 and 1.
0, the pixel portion 2 of the gap control regions 41, 42, 43, 44 formed along the outer peripheral edge of the pixel portion 21.
A discontinuity part 4 of the area corresponding to the corner part 210 of 1
0, and is covered with a sealing layer GS. However, these inspection input / output signal terminals CX ₁ , CX ₂ , C
X ₃ , CX ₄ , TX ₁ , TX ₂ , XEP ₁ , XEP ₂ ,
The inspection process using XEP ₃ , XEP ₄ , YEP ₁ , and YEP ₂ is performed during the manufacturing of the liquid crystal device LP, that is, after manufacturing the liquid crystal device substrate AM and before forming the seal layer GS. Even if the seal layer GS is formed so as to cover these inspection input / output signal terminals after the process,
There is no problem.

Thus, the input / output signal terminal C for inspection
X ₁ , CX ₂ , CX ₃ , CX ₄ , TX ₁ , TX ₂ , XE
P ₁ , XEP ₂ , XEP ₃ , XEP ₄ , YEP ₁ , YE
Since P ₂ is not used after the liquid crystal device LP is completed, if it is formed on the lower layer side of the seal layer GS, the formation area of the seal layer GS, which was a dead space until then, can be effectively used. Therefore, the inspection input / output signal terminals CX ₁ , CX ₂ ,
CX ₃ , CX ₄ , TX ₁ , TX ₂ , XEP ₁ , XE
Since _{P 2, XEP 3, XEP 4} , YEP 1, YEP 2 can be omitted portion occupied conventional channel TFT constituting it is the scanning line driving circuit 23 and the data line driving circuit 22 Improved operation speed due to width expansion,
Alternatively, a large-scale circuit can be introduced. That is, in the liquid crystal device LP of this embodiment, the liquid crystal device substrate A
Without increasing the size of M and reducing the area occupied by the pixel portion 21 and the seal layer GS, the scanning line driving circuit 2
3 and the formation area of the data line drive circuit 22 can be substantially expanded. Conversely speaking, input / output signal terminals CX ₁ , CX ₂ , CX ₃ , CX ₄ , TX ₁ , TX for inspection are used.
₂ , XEP ₁ , XEP ₂ , XEP ₃ , XEP ₄ , YEP
_Since the peripheral portion (frame area 26) of the substrate AM for liquid crystal device can be reduced by omitting the portion that ₁ and YEP ₂ occupy in the past, the liquid crystal in which the peripheral portion is narrow while having the same size display area. The device LP can be constructed. Moreover,
Input / output signal terminals CX ₁ , CX ₂ , CX ₃ , CX for inspection
₄ , TX ₁ , TX ₂ , XEP ₁ , XEP ₂ , XEP ₃ ,
Even if unevenness is formed in this portion due to the formation of XEP ₄ , YEP ₁ and YEP ₂ , these inspection input / output signal terminals CX ₁ , CX ₂ , CX ₃ , CX ₄ , TX ₁ and T _{1 are formed} .
X ₂ , XEP ₁ , XEP ₂ , XEP ₃ , XEP ₄ , YE
P ₁ and YEP ₂ are formed because the gap control regions 41 and 42 formed along the outer peripheral edge of the pixel portion 21,
Since it is the discontinuous portion 40 of 43 and 44, the accuracy of the cell gap between the liquid crystal device substrate AM and the counter substrate OP is not reduced. Moreover, since these inspection input / output signal terminals are formed lower than the gap control region, the accuracy of the cell gap is not affected at all.
In addition, the input / output signal terminals CX ₁ , CX ₂ , C for inspection
X ₃ , CX ₄ , TX ₁ , TX ₂ , XEP ₁ , XEP ₂ ,
Since XEP ₃ , XEP ₄ , YEP ₁ and YEP ₂ are finally covered with the seal layer GS and are completely insulated and separated from the liquid crystal side and the counter substrate OP, input / output signal terminals for these inspections. It is possible to prevent the occurrence of an unnecessary short circuit between the counter substrate OP and the liquid crystal device substrate AM via the.

(Inspection Method of Liquid Crystal Device Substrate) In the manufacturing process of the liquid crystal device LP having such a structure, the data line X
A method of inspecting ₁ , ₂ , X _2, ... For open or short will be described with reference to FIG.

In the present embodiment, the step of inspecting the data line X for open or short is a step in the manufacturing process of the liquid crystal device LP, that is, the input / output signal terminal CX ₁ for inspection,
This is performed while the front surfaces of the CX ₂ , CX ₃ , CX ₄ , and the TFT drive signal input terminals TX ₁ , TX ₂ are not covered with the seal layer GS and are in the open state.

First, the data line X₁, X₂In
Image signal lines VID1 to VI can be used to inspect the presence or absence of disconnection.
For example, DC5V is applied to any of D6. This state
In this state, the data line driving circuit 22 and the scanning line driving circuit 23
Are driven in the same manner as when the liquid crystal device LP performs display.
During this period, I / O signal terminals for inspection using the inspection probe
TX₁From the high level signal (gate potential) for inspection
Line c₁Via TFTa₁, A₂, A₃, A_Four,
a_{1 + 8N}, A_{2 + 8N}, A_{3 + 8N}, A_{4 + 8N}Supply to the gate.
At this time, the input / output signal terminal TX for inspection₂From the low
Level signal (gate potential) for inspection wiring c₂Through
TFTa_Five, A₆, A₇, A₈, A_{5 + 8N}, A_{6 + 8N}, A
_{7 + 8N}, A_{8 + 8N}Feed them to their gates and turn them off (high
Impedance state). Set like this
If set, the bit signal from the X side shift register circuit 221
Issue Q₁, Q₂, Q₃, Q_Four, Q_{1 + 8N}, Q_{2 + 8N}, Q_{3 + 8N},
Q_{4 + 8N}Corresponding to
Analog switch S₁, S₂, S₃, S_Four, S_{1 + 8N}, S
_{2 + 8N}, S_{3 + 8N}, S_{4 + 8N}Sequentially turn on, and the image signal line VID
The potential of 1 to VID6 is the data line X₁, X₂, X₃,
X_Four, X_{1 + 8N}, X_{2 + 8N}, X_{3 + 8N}, X _{4 + 8N}From inspection wiring
b₁, B₂, B₃, B_FourInput / output signal end for inspection via
Child CX₁, CX₂, CX₃, CX_FourOutput in time series
Will be done. Therefore, the input / output signal terminal CX for inspection
₁, CX₂, CX₃, CX_FourApply the inspection probe to the
When the inspection signal is detected, the data line X₁, X₂, X₃,
X_Four, X_{1 + 8N}, X_{2 + 8N}, X_{3 + 8N}, X_{4 + 8N}The opening of the
You can check. That is, the data line X₁, X₂, X₃,
X_Four, X_{1+ 8N}, X_{2 + 8N}, X_{3 + 8N}, X_{4 + 8N}To either
I / O signal terminal CX for inspection₁, C
X₂, CX₃, CX_FourOutput signal for inspection detected from
Is an error signal at the timing corresponding to the corresponding data line X.
No. appears, so which data line X has a disconnection
Can be detected. The data line X_Five, X₆, X₇, X
₈, X_{5 + 8N}, X_{6 + 8N}, X_{7 + 8N}, X_{8 + 8N}About open
When inspecting for the presence of
I / O signal terminal TX₂High level signal from (gate
Potential) for inspection wiring c₂Via TFTa_Five, A₆, A
₇, A₈, A_{5 + 8N}, A_{6 + 8N}, A_{7 + 8N}, A_{8 + 8N}At the gate of
Supply. At this time, the input / output signal terminal TX for inspection₁Or
Et al. Send a low-level signal (gate potential) to the inspection wiring c.
₁Via TFTa₁, A₂, A₃, A_Four, A_{1 + 8N}, A
_{2 + 8N}, A_{3 + 8N}, A_{4 + 8N}Feed the gates of and turn them off
Keep the state (high impedance state).

Next, in order to inspect whether there is a short circuit between the adjacent data lines X, no voltage is applied to any of the image signal lines VID1 to VID6. Further, the data line driving circuit 22 and the scanning line driving circuit 23 are turned off.
Further, a high-level signal (gate potential) is applied to the inspection wirings c ₁ and c ₂ from both the inspection input / output signal terminals TX ₁ and TX ₂ by using the inspection probe and all TFs are applied.
The Ta ₁ , a ₂ , a ₃ ... Are kept in the ON state (low impedance state). In this state, by applying a high level signal to the input and output signal terminals CX _1, CX ₃ for inspection using an inspection probe, input and output signal terminals CX _2, CX for inspection
_A low-level signal is applied to ₄ to detect whether or not a current flows through these inspection input / output signal terminals CX ₁ , CX ₂ , CX ₃ , and CX ₄ . If there is a short circuit between the adjacent data lines X, the input / output signal terminals CX ₁ , CX ₂ , CX ₃ , CX ₄ for inspection, which are connected to the corresponding data lines X, are used.
Since the current is detected from, it is possible to detect that a short circuit has occurred between any of the data lines X.

Next, in order to inspect the leak current of the sample hold circuit 224 formed in the data line drive circuit 22,
For example, D is applied to any of the image signal lines VID1 to VID6.
Apply C12V. In this state, the data line drive circuit 2
2 and the scanning line drive circuit 23 are both turned off. Then, using the inspection probe, the inspection signal input from the inspection input / output signal terminal TX _{1 is set} to the high level, while the inspection signal input from the inspection input / output signal terminal TX _{2 is set} to the low level. In this state, an inspection probe is applied to the inspection input / output signal terminals CX ₁ , CX ₂ , CX ₃ , and CX ₄ , and these inspection input / output signal terminals C are applied.
If currents are detected from X ₁ , CX ₂ , CX ₃ and CX ₄ , then analog switches S ₁ and S of the sample and hold circuit are detected.
The leakage currents of ₂ , S ₃ , S ₄ , S _{1 + 8N} , S _{2 + 8N} , a _{3 + 8N} and a _{4 + 8N} can be detected. On the other hand, while the inspection signal input from the inspection input / output signal terminal TX _{2 is set} to the high level, the inspection signal input from the inspection input / output signal terminal TX _{1 is set} to the low level, If currents are detected from the inspection input / output signal terminals CX ₁ , CX ₂ , CX ₃ , CX ₄ , the analog switches S ₅ , S ₆ , S ₇ , S ₈ , S _{5 + 8N of} the sample and hold circuit 224, S _{5 + 8N} ,
Leakage currents of a _{5 + 8N} and a _{5 + 8N} can be detected.

Next, in order to inspect the leakage current of the inspection circuit 70, for example, DC12V is applied to all of the image signal lines VID1 to VID6. In addition, the data line drive circuit 2
At 2, all the analog switches S ₁ , S ₂ , S ₃ , S _4, ... Of the sample hold circuit 224 are turned on. The scanning line drive circuit 23 is turned off. In this state, a low-level signal (gate potential) is input from all of the input / output signal terminals TX ₁ and TX ₂ for inspection using the inspection probe to all TFTa ₁ through the inspection wirings c ₁ and c ₂ . are supplied to the gates a ₂ , a _3, ... And all of them are kept in the off state (high impedance state). In this state, input / output signal terminals CX ₁ and CX for inspection
₂ , CX ₃ , CX ₄ by applying an inspection probe, and input / output signal terminals CX ₁ , CX ₂ , CX ₃ , CX for these inspections
_{If the} current is detected from _4, the leak current of the inspection circuit 70 can be detected.

When inspecting the X side shift register circuit 221 of the data line driving circuit 22 and the Y side shift register circuit 231 of the scanning line driving circuit 23,
Start signals DX and DY are applied to these shift register circuits.
And clock signals CLX1 to CLX4, inverted clock signals thereof CLX1 bar to CLX4 bar, CLY, and inverted clock signal CLY bar thereof. As a result, in the X-side shift register circuit 221, as shown in FIG. 7, the clock signals CLX1 to CLX1 to CX are slightly shifted in phase.
LX4 and its inverted clock signal CLX1 bar to C
Since shift pulses are generated for every four series based on the LX4 bar, input / output signal terminals for inspection XEP ₁ , XEP ₂ , XE electrically connected to the final stage thereof.
An inspection probe is applied to P ₃ and XEP ₄ , and input / output signal terminals XEP ₁ , XEP ₂ , XEP ₃ and X for these inspections are applied.
The output from EP ₄ may be monitored. Similarly, with respect to the Y-side shift register circuit 231, input / output signal terminals YEP ₁ and YEP for inspection, which are electrically connected to the final stage thereof, are also provided.
A test probe may be applied to EP ₂ and the outputs from these test input / output signal terminals YEP ₁ and YEP ₂ may be monitored.

(Method for Manufacturing Liquid Crystal Device Substrate AM) A method for manufacturing a liquid crystal device substrate according to the present embodiment will be described with reference to FIGS.
This will be described with reference to FIG. These drawings are process cross-sectional views showing the method for manufacturing a substrate for a liquid crystal device of the present embodiment, and in each of the drawings, the left side portion is a cross section taken along the line AA ′ in FIG. ), A cross section along the line CC ′ in FIG. 8 (cross section of the gap control region),
A cross section (cross section of the input / output signal terminal portion for inspection) taken along the line BB ′ of FIG. 8 is shown on the right side portion.

First, as shown in FIG. 11A, directly on the surface of a glass substrate, for example, a transparent insulating substrate 10 made of alkali-free glass or quartz, or the insulating substrate 10 is used.
A thickness of about 200 angstroms to about 2000 angstroms, preferably about 1 angstrom, is formed on the entire surface of a base protective film (not shown) formed on the surface of the substrate by a low pressure CVD method or the like.
After forming the semiconductor film 1 made of a polysilicon film having a thickness of 000 angstroms, as shown in FIG. 11B, it is patterned by using a photolithography technique,
An island-shaped semiconductor film 1a (active layer) is formed on the side of the pixel TFT section. On the other hand, the semiconductor film 1 is completely removed on the side of the gap control region and the input / output signal terminal for inspection. The semiconductor film is formed by depositing an amorphous silicon film and then at a temperature of 500 ° C. to 700 ° C. for 1 hour to 7 hours.
Thermal annealing is performed for 2 hours, preferably 4 hours to 6 hours to form a polysilicon film, or after depositing a polysilicon film, silicon is implanted to amorphize and then recrystallized by thermal annealing. A method of forming a polysilicon film may be used.

Next, as shown in FIG. 11C, a gate insulating film 2 made of a silicon oxide film having a thickness of about 500 Å to about 1500 Å is formed on the surface of the semiconductor film 1a by a thermal oxidation method or the like. . Alternatively,
After forming a thermal oxide film of about 50 angstroms to about 1000 angstroms, preferably 300 angstroms, a silicon oxide film of about 1 is formed on the entire surface by a CVD method or the like.
00 angstroms to about 1000 angstroms,
The gate insulating film 2 may be formed by depositing preferably 500 Å. Further, a silicon nitride film may be used to further increase the breakdown voltage of the gate insulating film 2.

Next, as shown in FIG. 11D, after the polysilicon film 3 for forming the gate electrode and the like is formed on the entire surface of the insulating substrate 10, phosphorus is thermally diffused to make the polysilicon film 3 conductive. Turn into. Alternatively, a doped silicon film in which phosphorus is introduced at the same time as the polysilicon film 3 is formed may be used.

Next, the polysilicon film 3 is formed by photolithography.
As shown in Fig. 12 (A), the pattern
Gate electrode 3a (scan line
Y) is formed. On the other hand, the side of the gap control area
A polysilicon film on the lower wiring layer 3c (scanning line Y,
Wiring layers 411, 441, 413) for inspection purposes
Polysilicon film on the input / output signal terminal side for inspection wiring
3b (inspection signal wiring b ₁, B₂, B₃, B_Four, C₁,
c₂Leave as).

Next, as shown in FIG. 12B, the pixel T
On the side of the FT section and the N-channel TFT section of the drive circuit,
About 0.1 × 10 ¹³ / c using the gate electrode 3a as a mask
Implanting low-concentration impurity ions 100 (phosphorus ions, etc.) at a dose amount of m ² to about 10 × 10 ¹³ / cm ² ,
A low-concentration source region 1b and a low-concentration drain region 1c are formed on the pixel TFT section side in a self-aligned manner with respect to the gate electrode 3a. Here, since it is located right below the gate electrode 3a, the portion where the impurity ions 100 are not introduced becomes the channel region of the semiconductor film 1a as it is. When the ion implantation is performed in this manner, the polysilicon formed as the gate electrode 3a, the polysilicon formed as the lower wiring layer 3c in the gap control region, and the input / output signal terminal for inspection Impurities are also introduced into the polysilicon film formed as the inspection wiring 3b of the portion, so that they become more conductive.

Next, as shown in FIG.
In the FT portion, a resist mask 102 having a width wider than that of the gate electrode 3a is formed so that high-concentration impurity ions 101 (phosphorus ions or the like) are contained at about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10.
Implantation is performed with a dose amount of ¹⁵ / cm ² to form high-concentration source region 1d and drain region 1e.

Instead of these impurity introduction steps, a high-concentration impurity (phosphorus ion or the like) is implanted while the resist mask 102 wider than the gate electrode 3a is formed without implanting a low-concentration impurity, and an offset structure is formed. The source region and the drain region may be formed. Also,
High-concentration impurities (phosphorus ions, etc.) on the gate electrode 3a
It is needless to say that the source region and the drain region having a self-aligned structure may be formed by implanting.

Although not shown, in order to form the P-channel TFT portion of the peripheral driving circuit, the pixel portion and the N-channel TFT portion are covered and protected with a resist, and the gate electrode is used as a mask to set the thickness of about 0.1. × 10 ¹⁵ / cm ² to about 1
By implanting boron ions or the like at a dose of 0 × 10 ¹⁵ / cm ² , P-channel source / drain regions are formed in a self-aligned manner. As in the case of forming the N-channel TFT section, the gate electrode is used as a mask to form about 0.1 ×.
After a low-concentration impurity (boron ion or the like) is introduced with a dose amount of 10 ¹³ / cm ² to about 10 × 10 ¹³ / cm ² to form a low-concentration region in the polysilicon film, A wide mask is formed to remove high-concentration impurities (such as boron ions) from about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ /
The source and drain regions of the LDD structure (lightly doped drain structure) may be formed by implanting with a dose amount of cm ² . Further, without implanting low-concentration impurities, a high-concentration impurity (boron ion or the like) may be implanted with a mask wider than the gate electrode to form the source and drain regions of the offset structure. Good. By these ion implantation steps, a CMOS can be realized, and a peripheral drive circuit can be incorporated in the same substrate.

Next, as shown in FIG. 13A, the gate electrode 3a, the lower wiring layer 3c, and the inspection wiring 3b.
The thickness of the surface of the substrate is about 5000 angstrom to about 1 under the temperature condition of about 800 ° C. by the CVD method or the like.
A first interlayer insulating film 4 made of a 5000 angstrom NSG film (a silicate glass film containing no boron or phosphorus) is formed.

Next, as shown in FIG. 13B, the first portion is formed on the pixel TFT portion side by using the photolithography technique.
Contact holes 5a are formed in portions of the interlayer insulating film 4 corresponding to the source regions 1d.

Next, as shown in FIG. 13C, an aluminum film 6 for forming a source electrode is formed on the surface side of the first interlayer insulating film 4 by a sputtering method or the like. In addition to a metal film such as aluminum, a metal silicide film or a metal alloy film may be used.

Next, as shown in FIG. 13D, the aluminum film 6 is patterned by using the photolithography technique, and the source electrode 6a is formed as a part of the data line X in the pixel TFT section. At the same time, on the side of the gap control region, the upper wiring layer 6c (data line X, wiring layer 41
2, 421, 431, 442) are formed. The aluminum film 6 is completely removed on the side of the input / output signal terminal portion for inspection.

Next, as shown in FIG. 14A, CVD is performed on the surface side of the source electrode 6a and the upper wiring layer 6c.
At least 2 of a BPSG film (silicate glass film containing boron and phosphorus) having a thickness of about 500 Å to about 15,000 Å and an NSG film having a thickness of about 100 Å to about 3,000 Å under a temperature condition of about 400 ° C. Second including layers
The inter-layer insulating film 7 is formed.

Next, as shown in FIG. 14B, the pixel T
On the FT portion side, the second contact hole 8a is formed in a portion of the second interlayer insulating film 7 and the first interlayer insulating film 4 corresponding to the drain region 1e by using a photolithography technique and a dry etching method. To form. On the side of the inspection signal input terminal portion, a large contact hole 8b is formed in the second interlayer insulating film 7 and the first interlayer insulating film 4 to expose the inspection wiring 3b.

Next, as shown in FIG. 14C, on the surface side of the second interlayer insulating film 7, the ITO film 9 (having a thickness of about 400 angstroms to about 2000 angstroms for forming the drain electrode) is formed. Indium Tin Ox
(FIG. 14D) after forming the (ide) by a sputtering method or the like.
As shown in, IT using photolithography technology
The O film 9 is patterned, and the pixel electrode 9 is formed in the pixel TFT section.
a is formed. In the inspection signal input terminal portion, the inspection signal input terminal 9b (inspection input / output signal terminal CX ₁ ,
CX ₂ , CX ₃ , CX ₄ , TX ₁ , TX ₂ , XEP ₁ ,
XEP ₂ , XEP ₃ , XEP ₄ , YEP ₁ , YEP ₂ )
To form. Here, the pixel electrode 9a, is not limited to the ITO film, it is also possible to use a transparent electrode material made of refractory metal oxides such as SnO _X film and ZnO _X film, any of these materials For example, step coverage in the contact hole is also practical.

After the liquid crystal device substrate AM is manufactured in this manner, the above-mentioned inspection step is performed, and after this inspection step is completed, a method such as printing a sealing material such as polyimide for forming the sealing layer GS. A sealing layer forming step for forming the liquid crystal device AM, a bonding step for bonding the liquid crystal device AM and the counter substrate OP, and a liquid crystal sealing process for sealing the liquid crystal from the liquid crystal sealing hole 241 between the liquid crystal device substrate AM and the counter substrate OP, The liquid crystal device 1 is formed by sequentially performing a sealing step of closing the liquid crystal sealing hole 241 with the sealing material 242. Therefore,
After the inspection process is completed, the inspection signal input terminals 9b are covered with the seal layer GS. However, since these inspection signal input terminals 9b are not used other than for the inspection process, the inspection signal input terminals 9b are not used. The input terminal 9b may be embedded in the lower layer side of the seal layer GS.

Here, the inspection signal input terminal 9b is made of ITO.
Since it is a film, even if the inspection probe is applied to the inspection signal input terminal 9b in the inspection process, the surface of the inspection signal input terminal 9b is not scratched and a protrusion is not formed on the surface of the terminal. When the protrusion penetrates the seal layer GS and touches the counter substrate OP, the liquid crystal device substrate AM and the counter substrate O are formed.
Although a short circuit may occur with P, in the present embodiment, since a hard ITO film is used for the inspection signal input terminal 9b, such a problem does not occur.

If the inspection probe is not scratched, the inspection signal input terminal 9b will be I.
Not limited to the TO film, a chromium film, a titanium film, a metal film such as a tantalum film, or an alloy film thereof may be used. In this case, such a metal film is used for the data line X, the scanning line Y, or the pixel switching TFT of each pixel PX.
If it is used for 60, the manufacturing cost can be reduced by forming the film by also using those forming steps. In addition, a metal film such as a chromium film, a titanium film, or a tantalum film forming the inspection signal input terminal 9b is formed on the data line X,
Scan line Y or T for pixel switching of each pixel PX
The film may be formed in a step different from the step of forming the FT60.

(Improvement Example of Manufacturing Method) In the above-mentioned embodiment, FIG.
As shown in FIG. 3 (A), the polysilicon film 3 is patterned to make it conductive, and the wiring for inspection 3b (inspection signal wirings b ₁ and b _{1) is formed at} the input / output signal terminal portion for inspection.
_{2, b 3, b 4,} c 1, c 2) as was used for the test wiring 3b, may be used an aluminum film, which is the data line X and the simultaneously formed. However, the aluminum film forming the inspection wiring 3b and the input / output signal terminal 9 for inspection
The electrical connection to the ITO film forming b is poor. Therefore, in this example, up to the step shown in FIG.
1A to 1C are performed in the same manner as the steps described with reference to FIG.
As shown in FIG. 5B, when the contact hole 5a is formed in the first interlayer insulating film 4, the contact hole 5b is also formed on the side of the input / output signal terminal portion for inspection.
Then, as shown in FIG. 15C, after the aluminum film 6 for forming the data line (source electrode) is formed on the surface side of the first interlayer insulating film 4 by the sputtering method or the like, As shown in D), when the aluminum film 6 is patterned by using the photolithography technique, the aluminum film 6 is left as the inspection signal wiring 6b also on the inspection input / output terminal portion side.

From then on, FIG.
Similar to the steps described with reference to (A), (B), (C), and (D), first, a large contact hole 8b is formed in the second interlayer insulating film 7 and the first interlayer insulating film 4. do it,
The inspection wiring 3b is exposed (see FIGS. 16A and 16B). Next, as shown in FIG. 16C, an ITO film 9 having a thickness of about 400 angstroms to about 2000 angstroms for forming a drain electrode is formed on the surface side of the second interlayer insulating film 7 by a sputtering method or the like. 16D, the ITO film 9 is patterned by using the photolithography technique, and the inspection signal input terminal 9b (inspection input / output signal terminals CX ₁ , CX ₂ , CX) is formed.
₃ , CX ₄ , TX ₁ , TX ₂ , XEP ₁ , XEP ₂ , X
EP ₃ , XEP ₄ , YEP ₁ , YEP ₂ ) are formed.

According to this structure, since the inspection wiring 3b made of the polysilicon film is provided with the inspection wiring 6b made of the aluminum film, the two-layer structure is formed, so that the electrical characteristics are improved. Moreover, the inspection wiring 3b made of the aluminum film is the inspection wiring 3b made of the polysilicon film.
I / O signal terminal 9 for inspection made of ITO film through
Since it is electrically connected to b, the aluminum film and IT
The problem of poor electrical connection with the O film does not surface.

(Example of Use of Liquid Crystal Device) An example of use of the liquid crystal device according to the above-described embodiment in an electronic device when the liquid crystal device is of a transmissive type will be described with reference to FIGS. 17 to 21.

As shown in the block diagram of FIG. 17, an electronic apparatus constructed by using the liquid crystal device of the above-mentioned form has a display information output source 1000, a display information processing circuit 1002, a display drive device 1004, a liquid crystal device 1006, a clock. Generation circuit 1
008, and a power supply circuit 1010.
The display information output source 1000 includes a memory such as a ROM and a RAM, a tuning circuit that tunes and outputs an image signal and the like, and processes and outputs display information based on a clock signal from the clock generation circuit 1008. To do. The display information output circuit 1002 is, for example, an amplification / polarity inversion circuit or a phase expansion circuit. It is configured to include a rotation circuit, a gamma correction circuit, a clamp circuit, or the like, and drives the liquid crystal device 1006. The power supply circuit 1010 supplies electric power to each circuit described above.

An electronic device having such a configuration is shown in FIG.
20, a personal computer (PC) for multimedia, and an engineering workstation (EWS) shown in FIG.
And a mobile phone, a word processor, a television, a viewfinder type or a monitor direct-viewing type video tape recorder, an electronic notebook, an electronic desk calculator, a car navigation device, a POS terminal, a device including a touch panel, and the like.

The projection type display device shown in FIG. 18 is a projection type projector using a liquid crystal device as a light valve, and uses, for example, a three-prism optical system.
18, in the liquid crystal projector 1100, the projection light emitted from the lamp unit 1102 of the white light source is provided inside the light guide 1104, and a plurality of mirrors 1106 are provided.
And two dichroic mirrors 1108
Three liquid crystal devices 1110R and 1110R that separate the three primary colors of R, G, and B (light separation means) and display images of the respective colors.
Guided to 110G and 1110B. Then, the lights modulated by the respective liquid crystal devices 1110R, 1110G, and 1110B are incident on the dichroic prism 1112 (light combining means) from three directions. In the dichroic prism 1112, the light of red R and blue B is 9
Since the green G light is bent by 0 ° and goes straight, the lights of the respective colors are combined, and a color image is projected on a screen or the like through the projection lens 1114.

The personal computer 12 shown in FIG.
00 is a main body 1204 including a keyboard 1202
And a liquid crystal device 1206 (liquid crystal display screen).

A pager 1300 shown in FIG. 20 has a light guide 1306 having a liquid crystal device substrate 1304 and a backlight 1306a in a metal frame 1302.
Circuit board 1308, first and second shield plates 131
0, 1312, two elastic conductors 1314, 1316,
And a film carrier tape 1318. The two elastic conductors 1314 and 1316 and the film carrier tape 1318 connect the liquid crystal device substrate 1304 and the circuit substrate.

Here, the liquid crystal device substrate 1304 is one in which liquid crystal is sealed between two transparent substrates 1304a and 1304b, and at least a dot matrix type liquid crystal device is constituted by this. The drive circuit 1004 shown in FIG. 21 or the display information processing circuit 1002 in addition to this can be formed on one transparent substrate. Circuits not mounted on the liquid crystal device substrate 1304 are the liquid crystal device substrate 13
In the example shown in FIG. 20, it can be mounted on the circuit board 1308.

Since FIG. 20 shows the structure of the pager, a circuit board 1308 is provided in addition to the liquid crystal device board 1304.
However, when the liquid crystal device is used as one component for electronic equipment and the display drive circuit is mounted on the transparent substrate, the minimum unit of the liquid crystal device is the liquid crystal device. The substrate 1304. Alternatively, the liquid crystal device substrate 1304 fixed to a metal frame 1302 as a housing can be used as a liquid crystal device which is one component for electronic equipment. Instead of these, as shown in FIG. 21, the IC chip 13 is formed on a polyimide tape 1322 having a conductive film of metal formed on one of the two transparent substrates 1304a and 1304b constituting the liquid crystal device substrate 1304.
TCP (Tape Carrier P
It can also be used as a liquid crystal device, which is one component for electronic connection, by connecting an ackage 1320.

The present invention is not limited to the above embodiments, but can be implemented in various modified forms within the scope of the present invention of forming the seal layer in the wiring layer forming region.

[0083]

As described above, in the liquid crystal device according to the present invention, the gap control region formed along the outer peripheral edge of the pixel portion is inspected on the lower side of the seal layer in the liquid crystal device substrate. It is characterized in that an input / output signal terminal for is formed. Therefore, according to the present invention, since the input / output signal terminal for inspection is not used after the liquid crystal device is completed, by forming it on the lower layer side of the seal layer, the formation area of the seal layer, which was a dead space, is effective. Available. Therefore, it is possible to omit the portion occupied by the input / output signal terminals for inspection, without increasing the size of the liquid crystal device substrate and reducing the portion occupied by the pixel portion and the seal layer. The formation area of the drive circuit can be expanded. Therefore, it is possible to introduce a large-scale circuit into the drive circuit. Further, it is possible to configure a liquid crystal device having a narrow peripheral portion. In addition, even if unevenness is formed in the seal layer formation region due to the formation of the inspection input / output signal terminals, these inspection input / output signal terminals are formed along the outer peripheral edge of the pixel portion. Since the gap control region is formed by the gap, the cell gap between the liquid crystal device substrate and the counter substrate can be secured with high accuracy by the gap control region. Also, since the input / output signal terminals for inspection are finally covered with the sealing layer and are completely insulated and separated from the liquid crystal side and the counter substrate, the counter substrate through the input / output signal terminals for inspection is used. It is possible to prevent an unnecessary short circuit between the liquid crystal device substrate and the liquid crystal device substrate.

In the present invention, when the inspection circuit is formed in the region overlapping with the black matrix for parting the display screen, the space occupied by the inspection circuit in the peripheral portion of the seal layer can be omitted. The formation area of can be expanded. Further, the area overlapping the black matrix for dividing the display screen is a dead space in the related art, and the inspection circuit is formed there. Therefore, it is not necessary to reduce the area occupied by the pixel portion and the seal layer.

In the present invention, when the signal wiring is configured to pass through the outer peripheral side of the seal layer with respect to the seal layer, it is possible to prevent unevenness from being formed in the seal layer formation region. There is an advantage that the cell gap between the counter substrate and the counter substrate can be easily controlled.

[Brief description of drawings]

FIG. 1 is a plan view of a liquid crystal device to which the present invention is applied.

FIG. 2 is a sectional view taken along the line HH ′ of FIG.

3 is a block diagram showing a configuration of a liquid crystal device substrate used in the liquid crystal device shown in FIG.

4 is an equivalent circuit diagram of a pixel formed on the liquid crystal device substrate shown in FIG.

5 is an enlarged view of a pixel formed on the liquid crystal device substrate shown in FIG.

6 is an equivalent circuit diagram such as an inspection circuit formed on the liquid crystal device substrate shown in FIG.

7 is a timing chart of pulses generated by the data line driving circuit formed on the liquid crystal device substrate shown in FIG.

8 is an enlarged view of a corner portion AA of the liquid crystal device shown in FIG.

9 is an enlarged view of a corner portion BB near the corner of the liquid crystal device shown in FIG.

FIG. 10 is a corner portion BB of the liquid crystal device shown in FIG.
It is another enlarged view of FIG.

11 is a process cross-sectional view showing the method of manufacturing the substrate for liquid crystal device shown in FIG.

12 is a process cross-sectional view of each process performed subsequent to the process shown in FIG. 11 in the method for manufacturing a substrate for a liquid crystal device shown in FIG.

13 is a process cross-sectional view of each process performed subsequent to the process shown in FIG. 12 in the method for manufacturing a substrate for a liquid crystal device shown in FIG.

14 is a process cross-sectional view of each process performed subsequent to the process shown in FIG. 13 in the method for manufacturing a substrate for a liquid crystal device shown in FIG.

15 is a process cross-sectional view of each process performed in place of the process shown in FIG. 14 in another method for manufacturing the liquid crystal device substrate shown in FIG.

16 is a process cross-sectional view of each process performed subsequent to the process shown in FIG. 15 in another manufacturing method of the liquid crystal device substrate shown in FIG.

FIG. 17 is a block diagram of an electronic device using a liquid crystal device to which the present invention is applied.

FIG. 18 is an explanatory diagram showing an optical system of a projection display device using a liquid crystal device to which the invention is applied.

FIG. 19 is an explanatory diagram of a personal computer using a liquid crystal device to which the present invention is applied.

FIG. 20 is an explanatory diagram of a pager using a liquid crystal device to which the present invention has been applied.

21 is an explanatory diagram of a liquid crystal display substrate used in the pager of FIG.

[Explanation of symbols]

21 Pixel Part 22 Data Line Driving Circuit 23 Scanning Line Driving Circuit 25 Mounting Terminal 26 Frame Regions 28, 29 Signal Wiring 40 Gap Control Region Discontinuities 41, 42, 43, 44 Gap Control Region 60 Pixel Switching TFT 210 Pixel Unit Corner portion 221 X side shift register circuit 224 Sample hold circuit AM Liquid crystal device substrate BM1 Black matrix BM2 Display screen cutout black matrix CX ₁ , CX ₂ , CX ₃ , CX ₄ Input / output signal terminal GS inspection layer LC liquid crystal LP liquid crystal device OP counter substrate PX Pixels Q ₁ , Q ₂ , Q ₃ ... Bit signals S ₁ , S ₂ , S ₃ ... Analog switch TX ₁ , TX ₂ input / output signal terminals VID ₁ for inspection VID6 image signal lines _{X (X 1, X 2 ···} ) data lines _{XEP 1, XEP 2, XEP 3} , EP ₄ output signal terminal Y for inspection (Y _1, Y ₂ ···) scanning lines YEP _1, YEP ₂ O signal terminals a ₁ for inspection, a ₂ · · · inspection TFT (inspection switching circuit ) B ₁ , b ₂ , b ₃ , b ₄ inspection signal wiring c ₁ , c ₂ inspection signal wiring

Claims (8)

(57) [Claims] 1. A pixel portion composed of a plurality of pixels formed in a matrix by a plurality of data lines and a plurality of scanning lines, and at least one end side of the data line in an outer region of the pixel portion. A liquid crystal device substrate including a data line driving circuit and a pair of scanning line driving circuits formed on one side and the other side of the scanning line in an outer region of the pixel portion, and arranged to face the liquid crystal device substrate. Formed between the counter substrate and the pixel portion, the data line driving circuit and the scanning line driving circuit along the outer peripheral edge of the pixel portion, and between the counter substrate and the liquid crystal device substrate. A liquid crystal device having a sealed layer containing a gap material, the display being positioned on the inner side of the seal layer on the opposite side of the liquid crystal device substrate on which the data line drive circuit is formed. Screen closed An inspection circuit connected to the data member and connected to the data line, and formed in the region of the seal layer along the outer peripheral edge of the pixel portion with a discontinuity in the corner portion of the pixel portion. A gap control region formed of the constituent materials and formed by stacking a plurality of wiring layers via an insulating film, and formed at a position lower than the gap control region and connected to the inspection circuit at the discontinuous portion of the gap control region. A liquid crystal device, comprising: 2. The inspection terminal is configured by laminating an inspection wiring made of a material of a gate electrode of a thin film transistor forming the pixel portion with an inspection wiring made of a material of a pixel electrode forming the pixel portion. The liquid crystal device according to claim 1. 3. A shift register circuit of the data line driving circuit, a buffer circuit, and a sample hold circuit for supplying an image signal to the data line based on a sampling signal from the buffer circuit are provided outside the seal layer. On the lower layer side of the seal layer, the data line connected to the sample hold circuit is laminated with a material forming the pixel portion to form a part of the gap control region, and the gap control region is formed. 3. The liquid crystal device according to claim 1, further comprising an inspection terminal which is connected to the shift register and is formed lower than the gap control region in the discontinuous portion. 4. A shift register circuit and a buffer circuit of the data line driving circuit, which are provided outside the seal layer, overlap with the display screen parting member, and an image signal based on a sampling signal from the buffer circuit. And a sample and hold circuit for supplying the image signal to the data line, and an image signal line for supplying the image signal on the lower layer side of the seal layer and the sampling signal from the buffer circuit for supplying to the sample and hold circuit. A material forming the pixel portion is laminated on the sampling signal input wiring to form a portion of the gap control region, and the gap control region is connected to the gap register at the gap portion of the gap control region. The inspection terminal formed lower than a region is provided, The claim 1 or 2 characterized by the above-mentioned. Liquid crystal device. 5. The scanning line driving circuit is provided outside the sealing layer, and the pixel portion is formed on the scanning line connected to the scanning line driving circuit on the lower layer side of the sealing layer. A material is laminated to form a part of the gap control region, and an inspection terminal connected to the shift register and formed lower than the gap control region is provided in the gap control region of the gap control region. The liquid crystal device according to claim 1, wherein the liquid crystal device is a liquid crystal device. 6. The wiring layer forming the gap control region is formed of a material of the gate electrode of the thin film transistor forming the pixel section and the data line. The liquid crystal device according to item. 7. The liquid crystal device according to claim 1, wherein the plurality of wiring layers forming the gap control region form a redundant wiring structure which is electrically connected through a contact hole. 8. The signal wiring for electrically connecting the pair of scanning line driving circuits is arranged outside the sealing layer on which the inspection circuit is provided. The liquid crystal device according to item 1.