JP3515973B2 - Semiconductor storage device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a nonvolatile memory cell composed of a floating gate type field effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, an EEPROM is known as a non-volatile memory capable of writing and erasing. 25A and 25B show a conventional general E
It is a figure which shows the structure of the unit cell of EPROM, and the principle of erasing (charge injection) and writing (charge extraction). E
The unit cell of the EPROM is composed of a memory transistor and a select transistor connected in series. For example, a high-concentration n-type impurity is introduced into an active region in a p- type semiconductor substrate 101 to form a drain region 102 of a select transistor and an n + region 103 functioning as a source region of a select transistor and a drain region of a memory transistor. And a source region 104 of the memory transistor are formed. Then, the select gate 107 of the select transistor is formed on the semiconductor substrate 101 via an insulating film.
And a floating gate 105 of the memory transistor are formed, and a control gate 106 of the memory transistor is further formed on the floating gate 105 via an insulating film. A particularly thin tunnel oxide film 110 is interposed between the floating gate 105 and a part of the n + region 103 functioning as the drain region of the memory transistor.

As shown in FIG. 25A, when injecting electrons into the floating gate 105, a low voltage of 0 V is applied to the drain region 102 of the select transistor and the select gate 10 is operated.
When a high voltage of 20 V is applied to the control gate 106 and the control gate 106, respectively, the select transistor is turned on and electrons flow from the drain region 102 to the N + region 103. Then, the electrons are generated by FN tunneling through the tunnel oxide film 110. It is injected into the floating gate 105.

As shown in FIG. 25 (b), the floating gate 1
When the electrons are extracted from 05, a low voltage of 0 V is applied to the control gate 106 and the select gate 10 of the select transistor is selected.
When a high voltage of 20 V is applied to the drain region 102 and the drain region 102, electrons in the floating gate 105 are extracted to the n + region 103 via the tunnel oxide film 110 and then flow to the drain region 102 of the select transistor.

In the above general conventional EEPROM, the F region is formed between the drain region and the gate electrode of the memory transistor.
Write using the movement of electrons by N tunneling,
This is a technology for erasing. Note that whether the state in which electrons are injected into the floating gate 105 is the erased state or the written state can be arbitrarily defined and is not uniformly determined.

On the other hand, the EEP is adapted to perform writing by using a principle different from that of the above general conventional EEPROM.
ROMs have also been proposed.

For example, the present inventor has proposed a device for performing source side injection as shown in FIG.
-226662 publication). In this structure, as shown in the figure, a thickness of 10 is formed on the P-type silicon substrate 200.
The gate insulating film 201 made of a silicon oxide film of about nm
The floating gate 202 and the select gate 203 are formed via the. An insulating film 204 made of a silicon oxide film is formed between the gates 202 and 203 and on the sidewalls, and an oxide film (Oxi) is formed on the gates 202 and 203.
de), nitride film (Nitride) and oxide film (Oxi)
A control gate electrode 208 made of a polysilicon film is provided via an ONO composite insulating film made of de). In addition, a drain region 205 and a source region 206, which are impurity diffusion layers, are formed in regions inside the P-type silicon substrate 200 located on the sides of the gates 202 and 203, respectively.

By adopting such a structure, during the operation of injecting electrons into the floating gate 202, the control gate 20 is
8 to a high positive voltage of about 12 to 17 V, and select gate 2
When 03 is set to a low positive voltage of about 1 to 2 V, a weak inversion layer is formed below the select gate 203, and a depletion layer is formed in the substrate below the floating gate 202. That is, a high potential gap is generated between the inversion layer below the source side end of the floating gate 202 and the depletion layer adjacent thereto. Then, electrons can be injected into the floating gate 202 by utilizing this potential gap. According to such a method, the select transistor and the memory transistor can be integrated into a high-density fine structure, and the writing speed is higher than that of the conventional EEPROM despite the relatively low drain voltage (5 V in this case). Will be possible.

[0009]

However, in the semiconductor memory device shown in FIG. 26, the method of injecting electrons into the floating gate by utilizing the source side injection method has the following problems.

First, according to the source side injection method, writing can be performed with a relatively low drain voltage (about 5 V). But 3
When a V-system power supply voltage is used, considering the variation in the threshold voltage of the transistor and the temperature compensation, the memory cell is required to have a function capable of sufficiently writing with a drain voltage of about 2V. Injection in the power system is difficult.

Therefore, in order to compensate for this drawback, it is considered that only the drain voltage needs to be boosted above the power supply voltage. However, the injection current when the source side injection method is used is about 10 μA, which is an order of magnitude less than the mA order current in the most general channel hot electron injection, but the number of memory cells that can be injected at one time is small. There is a limit.

Further, although the cause has not been sufficiently clarified,
It was found that the peculiar deterioration of the memory function occurs when the memory is injected using the source side injection method. Therefore, there is only a function capable of repeating tens of thousands of write and erase cycles.

The present invention has been made in view of the above problems, and an object thereof is to perform writing and erasing in a semiconductor memory device having a nonvolatile memory cell composed of a floating gate type transistor and a manufacturing method thereof. It is to improve the number of times of writing and erasing and improve the reliability while reducing the required power supply voltage.

[0014]

In order to achieve the above-mentioned object, the means taken by the present invention is to erase electrons from a region located between a source and a drain in a semiconductor substrate to a floating gate.
It is performed by injecting by N tunneling, and writing is performed by extracting from the floating gate to the drain side by FN tunneling.

The first semiconductor memory device of the present invention is a semiconductor memory device having at least one memory cell mounted on a semiconductor substrate, wherein the memory cells are separated from each other in a region of the first conductivity type of the semiconductor substrate. The second formed
Conductive type first diffusion layer, second diffusion layer and third diffusion layer
A layer , the first diffusion layer and the third diffusion layer on the semiconductor substrate .
A floating gate formed on a region between the diffusion layers, the first which is formed between the floating gate and the semiconductor substrate
The insulating film, a select gate formed on a region between the second diffusion layer and the third diffusion layer on the semiconductor substrate, the select gate, and the semiconductor substrate. A second insulating film interposed between the floating gate, the control gate formed above the floating gate, a third insulating film interposed between the floating gate and the control gate, and above the select gate. comprising a dummy gate formed in, and a fourth insulating film interposed between the dummy gate and the select gate, the floating
When injecting electrons into the gate electrode, the first diffusion layer is used.
The bit line connected to
The conductor substrate is set to the first potential, and the control gate is set to the above.
The second electric potential which is higher than the first electric potential of the semiconductor substrate.
Of the first diffusion layer in the semiconductor substrate.
From the region located between the third diffusion layer and the third diffusion layer,
FN tunneling to the factory .

With this structure, instead of the injection mechanism on the source side, it is possible to inject electrons into the floating gate using FN tunneling, and the current required for injecting and extracting electrons is reduced to about 1 nA per cell. It Then, by reducing the current required for injection, even if the drain voltage is boosted from the power supply voltage and electrons are injected into many memory cells at one time, there is no power shortage, and the semiconductor memory device It is possible to reduce the voltage. Also,
Drain using conventional general FN tunneling
Compared to a semiconductor memory device that injects and extracts electrons between floating gates, electrons pass through different portions of the first insulating film during injection and extraction of electrons, so the durability of the first insulating film is improved. Is improved.

Word line connected to the control gate
And a source line connected to the second diffusion layer.
Preferably.

The third insulating film and the fourth insulating film are formed by patterning the same insulating film, and the floating gate and the select gate are the same first conductor film. The control gate and the dummy gate are formed by patterning the same second conductor film, so that each gate is formed by only two conductor films. Can be configured, and the cost can be reduced.

It is preferable that the control gate has the same width as the floating gate, and the dummy gate has the same width as the select gate.

The first insulating film has a thickness of 5 nm or more and a thickness of 10 nm.
It is preferably composed of a silicon oxide film having a thickness of less than m.

The dummy gate is formed over a plurality of memory cells, and a gate lead-out line for contacting a portion of the select gate near the end of the memory cell array where the dummy gate is removed is formed. Is preferred.

A second semiconductor memory device of the present invention is a semiconductor
Semiconductor with at least one memory cell mounted on a substrate
In the memory device, the memory cell is the semiconductor substrate.
Formed in a first conductivity type region of the
A conductive type first diffusion layer and a second diffusion layer, and
One end of the first diffusion layer and the first and second diffusion layers on the body substrate.
Floating gate formed over and between the diffusion layers of
Is formed between the floating gate and the semiconductor substrate.
The first insulating film and the first diffusion film on the semiconductor substrate.
Spans one end of the layer and the region between the first and second diffusion layers
Formed by the selection gate, the selection gate and the semiconductor
The second insulating film interposed between the body substrate and the floating gate.
Of the control gate formed in close proximity to at least a part of the
The third insulation between the over bets, the upper Symbol floating gate and a control gate
When injecting electrons into the floating gate electrode, which has an edge film
Has a bit line connected to the first diffusion layer
Is open and the above semiconductor substrate is set to the first potential
The control gate to the first potential of the semiconductor substrate.
And set to a second potential, which is a high potential, and
There is a position between the first diffusion layer and the second diffusion layer in the plate.
By the FN tunneling from the area to be placed to the floating gate
Is carried out.

A third semiconductor memory device of the present invention is a semiconductor
Semiconductor with at least one memory cell mounted on a substrate
In the memory device, the memory cell is the semiconductor substrate.
Formed in a first conductivity type region of the
Conductive type first diffusion layer, second diffusion layer and third diffusion layer
A layer, the first diffusion layer and the third diffusion layer on the semiconductor substrate.
Floating gate formed between the floating gate and
Insulating film formed between the substrate and the semiconductor substrate
And the second diffusion layer and the third diffusion layer on the semiconductor substrate.
The select gate formed between the diffusion layer and the select gate
A second insulating film interposed between the semiconductor substrate and the semiconductor substrate,
Formed near at least part of the floating gate
Between the floating gate and the control gate
A third insulating film is provided between the floating gate electrode and an electron.
Is connected to the first diffusion layer when injecting
The bit line is open and the above semiconductor substrate is the first
Set to a potential, and the control gate is connected to the first of the semiconductor substrate.
Set to the second potential, which is higher than that of
The first diffusion layer and the third diffusion layer in the semiconductor substrate
FN tunnel from the area located between
Done by ring.

A fourth semiconductor memory device of the present invention is a semiconductor memory device having at least one memory cell mounted on a semiconductor substrate, wherein the memory cells are separated from each other within a region of the first conductivity type of the semiconductor substrate. The second formed
A conductive type first diffusion layer and a second diffusion layer, and a region formed between the first diffusion layer and the second diffusion layer on the semiconductor substrate and formed through a gate insulating film. A select gate, a floating gate formed on both sides of the select gate via a first insulating film, the select gate and the floating gate
A control gate formed over the second insulating film,
A tunnel insulating film formed between the semiconductor substrate and the floating gate is provided, and when injecting electrons into the floating gate electrode, the bit line connected to the first diffusion layer is opened. , The semiconductor substrate is set to a first potential, the control gate is set to a second potential which is higher than the first potential of the semiconductor substrate, and the first potential in the semiconductor substrate is set. FN tunneling is performed from the region located between the diffusion layer and the second diffusion layer to the floating gate.

In the above first to fourth semiconductor memory devices
Te, the first diffusion layer, the drain region, the second diffusion layer is preferably a source region.

A first method of manufacturing a semiconductor memory device according to the present invention is the method of manufacturing a first semiconductor memory device described above, wherein a gate insulating film capable of FN tunneling is formed on a semiconductor substrate on which element isolation is formed. Forming step (a), forming a first conductor film on the gate insulating film (b),
A step (c) of selectively removing a portion of the first conductor film located above the element isolation to form a rectangular opening, and the step of (c), followed by the first conductivity. A step (d) of forming an insulating film on the body film, a step (e) of forming a second conductor film on the insulating film, and a patterning of the second conductor film to form a control gate. And a step (f) of forming a dummy gate, a step (g) of patterning the first conductor film to form a floating gate and a select gate, and at least one of both ends of the dummy gate. In the step (g), and a step (i) in which a gate lead-out line that contacts the portion of the select gate where the dummy gate is removed is formed. , Above first
Is formed by dividing the element isolation by the opening formed in the conductor film and separating each memory cell, and the select gate is formed over a plurality of memory cells.

After the step (g), a step (h) of removing at least one of both ends of the dummy gate, and a gate extraction for contacting a portion of the select gate where the dummy gate is removed. The method may further include the step (i) of forming wiring.

The gate insulating film has a thickness of 10 nm at 5 nm or more.
It is preferably composed of a silicon oxide film having a thickness of less than m.

The dummy gate is preferably formed over a plurality of memory cells.

After the step (g), a step (h) of removing at least one of both ends of the dummy gate, and a gate extraction for contacting a portion of the select gate where the dummy gate is removed. The method may further include the step (i) of forming wiring.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) First, a first embodiment will be described with reference to the drawings.

FIG. 1 shows an EEPRO according to the first embodiment.
It is sectional drawing which shows the structure of M. As shown in the figure, the P-type silicon substrate 1 is provided with a drain region 2 and a source region 3 which are N-type impurity diffusion layers formed apart from each other. Then, on the P-type silicon substrate 1 between the source region 3 and the drain region 2, a select gate 6 made of a first-layer polysilicon film with a gate insulating film 5 interposed therebetween.
Is provided. In addition, O is provided on both sides of the select gate 6.
Sidewalls obtained by anisotropically etching the second-layer polysilicon film deposited via the insulating film 8 made of an NO film are formed. Above the drain region 2 of these two sidewalls is formed. The part in is the floating gate 7
Function as. A relatively thick silicon oxide film 8a is formed on the select gate 6. Further, a control gate 9 formed of a polysilicon film deposited via an insulating film 10 made of an ONO film is provided on the selection gate 6 and the floating gate 7. A tunnel oxide film 4 having a thickness of about 10 nm is formed between the drain region 2 and the floating gate 7.

FIG. 2 is a circuit diagram partially showing the structure of an EEPROM memory cell array formed by arranging the memory cells shown in FIG. As shown in FIG. 2, this memory cell array has a large number of memory cells Mmn arranged in a matrix, and in each column, the drain regions of the memory cells adjacent to each other are formed in a common region and The source region is formed in a common region. The respective parts of the memory cell shown in FIG. 1 are connected in the circuit as follows. Control gate 9 of each memory cell
Are connected to word lines WL1, WL2, ... Which extend along the rows and are adjacent to each other, for example, memory cell M1.
The drain regions 2 of M1 and M21 are connected to a common bit line BL1 extending along the column. Further, a source line for connecting the source regions 3 shared by the memory cells in the two rows is provided, and the two source lines are further shared by one, corresponding to four word lines. Source line SSL for every four rows
1, SSL2, ... Are provided. Further, the selection gates 6 of the memory cells arranged in a common row are connected to the selection lines SL1, SL2, ... Which extend along the row.

In the memory cell array of the semiconductor memory device of the present invention, the source line connection method is as follows.
The method of connecting the source lines in this embodiment is not limited.

Next, the writing and erasing operations to the memory cell will be described with reference to Table 1 and FIGS. Table 1 is a table showing a method of setting the potential in each operation of writing, erasing and reading to the memory cell M42, and FIGS. 3 to 7 concretely show the potential of each part corresponding to each operation of Table 1. FIG.

[0036]

[Table 1]

-Write (pull-out) operation-In the write operation, each select line SL1, SL
2, ... are set to 0V and each source line SSL1, SS
With L2, ... Opened and the silicon substrate 1 grounded, the drain region of the memory cell M42 to be written is connected to the word line WL4 to which the control gate of the memory cell M42 to be written is connected. The potential of the bit line BL2 is set high enough to allow the FN tunnel current to flow. By setting in this way, the electrons accumulated in the floating gate 7
That is, it is pulled out to the bit line BL2. In that case,
There are the following method 1 and method 2 for setting potentials of word lines, bit lines, selection lines, and the like.

(Method 1) As shown in FIG. 3, the memory cell M into which the memory is written
The potential of the word line WL4 connected to 42 is -10V
And other word lines WL1, WL2, WL3, WL
Bit lines B connected to the memory cell M42 by setting the potentials of 5, ... (non-selected word lines) to 0V, respectively.
The potential of L2 is set to a positive value of 5V and the other bit lines BL1,
BL3, ... are set to open respectively. Further, all the selection lines SL1, SL2, ... Are grounded and all the source lines SSL1, SSL2 ,.

(Method 2) As shown in FIG. 4, the word line WL4 connected to the memory cell M42 for writing is grounded, and the potentials of the other word lines WL1, WL2, WL3, WL5, ...
, The potential of the bit line BL2 connected to the memory cell M42 is set to 12V, and the potential of the other bit line B2 is set to 12V.
Set L1, BL3, ... to open. Further, the potentials of all the selection lines SL1, SL2, ... Are set to 0V and all the source lines SSL1, SSL2 ,.

By the above potential setting method, electrons are selectively extracted from the floating gate of only the memory cell M42 arranged at the intersection of the word line WL4 and the bit line BL2, that is, the memory cell M42 is set to the write state. Will be possible.

-Erase (Injection) Operation-To put all the memory cells commonly connected to at least one word line in the memory cell array into the erased state, set the potential of the word line to a positive high value,
The potential of the silicon substrate is set to a low potential, and the potential difference between the control gate and the silicon substrate is set large enough to allow the FN tunnel current to flow between the floating gate and the silicon substrate. Thereby, in all the memory cells commonly connected to at least one word line in the memory cell array, electrons are injected into the floating gate from the region located between the source and the drain in the silicon substrate through the tunnel insulating film. .

It is preferable that at least one of the source / drain regions has the same potential as the silicon substrate. In order to inject carriers (electrons in this case) from the substrate, a supply source of injected carriers is required, and it is necessary to supply carriers from either the source or the drain. At this time, the voltage applied to the source / drain is set to be the same as that of the substrate, whereby the potential gap between the floating gate at the injection site, the tunnel film and the substrate becomes the steepest, and the injection efficiency becomes high. For example, if the potential of the drain region is set to the same low potential as the substrate,
Since the drain region itself faces the floating gate with the tunnel oxide film interposed therebetween, the above-mentioned object can be easily achieved. However, since a column decoder normally exists in the drain region, and making the potential of this column decoder positive and negative makes the circuit structure complicated, it may be advantageous to set a low potential from the source region. is there.
Although the source region and the floating gate are separated from each other, as shown in Table 1 above, for example, when the potential on the substrate side is set to -8V, the potential of the select gate is set to -4V and the selected memory cell is set. , The potential of the substrate region below the select gate is sufficiently inverted to set the potential of the substrate region facing the source side end of the floating gate to −8V.
Can be kept at 8V. In that case, the potential of the source region of the non-selected memory cell is set to −4V (that is, half the potential of the source region of the selected memory cell), and the potential of the select gate is set to 0V, thereby setting the floating gate. Keep the potential of the substrate area facing the source side end of -4V,
It is possible to prevent the erase operation.

At this time, as a concrete method of setting the voltages of the word line, the silicon substrate, the bit line, etc., there are the following methods, for example.

(Method 1) As shown in FIG. 5, four word lines WL2 to WL5
Is set to about 10V, the potential of the source line SSL2 corresponding to the four word lines WL2 to WL5 is set to -8V, and the four word lines WL2 to W5 are set.
Set the potential of the select lines SL2 to SL5 corresponding to L5 to -4
Set to V. Then, the potential of the silicon substrate 1 is set to -8V.
Set to a degree. On the other hand, non-selected selection lines SL1, S
.. and word lines WL1, WL6, .. are grounded, and unselected source lines SSL1, SSL3 ,.
Set to 4V and all bit lines BL1, BL2
Open ... By setting such a potential,
Electrons are collectively injected into the floating gates of the memory cells connected to the four word lines WL2 to WL5. In addition,
To put all the memory cells in the erased state, set the potentials of all the word lines to 10 V in the state shown in FIG.
The potentials of all the source lines SSL1, SSL2, ... May be set to -8V, and the potentials of all the select lines SL1, SL2 ,.

In the erasing method as described above, this memory cell array can perform sector erasing for every four word lines WL2 to WL5 or batch erasing of all memory cells, and the minimum erasing unit is four word lines. It becomes the number of memory cells connected to.

(Method 2) As shown in FIG. 6, the potential of the selected word line WL4 is set to 1
Unselected word lines WL1 and WL set to about 5V
2, WL3, WL5, ... Are grounded, and the silicon substrate 1 is also grounded. And all bit lines BL1, BL
2, open all select lines SL1, S
L2, ... and all source lines SSL1, SSL
Ground 2, ... When all the memory cells are to be erased, the potentials of all the word lines may be set to 15V in the state shown in FIG.

By the above erasing method, this memory cell array can perform sector erasing for each word line WL1, WL2, ... Or batch erasing of all memory cells, and the minimum erasing unit is a word for one line. It is the number of memory cells connected to the line.

-Read Operation-As shown in FIG. 7, a memory cell M to be read.
The potential of the word line WL4 connected to 42 is set to Vcc
(For example, about 2.5 to 3.3V), ground the other word lines WL1, WL2, WL3, WL5, ...
The potential of the bit line BL2 connected to the memory cell M42 is set to 1V and the other bit lines BL1, BL3.
Are opened, the potential of the selection line SL4 connected to the memory cell M42 is set to Vcc, and the other selection lines SL1, SL2, SL3, SL5, ... And all the source lines SSL1, SSL2 ,. And
The silicon substrate 1 is also grounded.

FIG. 8 is a characteristic diagram showing the relationship between the pulse width of a signal and the threshold voltage when electrons are extracted (written) according to the method 1 of the present embodiment. Also in each of the conventional methods, since the FN tunneling of the electrons from the floating gate to the drain region is used to extract the electrons from the floating gate, almost the same characteristics can be obtained also in the conventional semiconductor memory device. To be The current required to extract the electrons is about 1 nA / cell.

FIG. 9 is a threshold corresponding to the pulse width of a signal and the amount of charge in the floating gate at the time of electron injection by the method 1 (solid curve) of the present embodiment and conventional source side injection (dashed line). It is a characteristic view which shows the relationship with value voltage Vth. In another embodiment of the present invention, the FN from the region located between the source and the drain in the silicon substrate to the floating gate is also used.
Since tunneling is used, almost the same characteristics can be obtained. In the case of source-side injection, the time required to inject a certain amount of charge is extremely short and high-speed injection is possible, but the current required for injection is as large as about 10 μA / cell, whereas
In the present invention, the current required for injection is extremely small, about 1 nA / cell. Here, the total allowable current is 100 μA
In the case of conventional source-side injection, 1
It can be injected into only about 0 memory cells. On the other hand, according to the present invention, it is possible to perform batch injection into about 100,000 memory cells.

From the above data, the following can be said when the present invention is compared with the source side injection method. There is no substantial difference between the present invention and the conventional method in the time and current required to extract the electrons from the floating gate. However, the current required for injecting electrons into the floating gate in the EEPROM of the present invention is EEP by the source side injection method.
It is about 1/10000 of the current in the ROM. Therefore, in the present invention, either injection or erasure of electrons to the floating gate can be performed collectively on a large number of memory cells. That is, batch writing and batch erasing are possible for many memory cells. On the other hand, in the source side injection method, if electron injection into the floating gate is defined as erase, batch erase in word line units cannot be performed. Therefore, injection of electrons into the floating gate is usually used as write. The number of memory cells that can be written is extremely small.

Further, in the case of the conventional EEPROM in which electrons are injected from the drain region to the floating gate, FN tunneling is performed through the same portion of the oxide film in both the extraction and injection of electrons. The oxide film is greatly damaged by tunneling, and the number of times writing and erasing can be repeated is reduced. On the other hand, in the present embodiment, since writing and erasing are performed via different portions of the oxide film respectively, the life is improved.

Therefore, according to the present embodiment, the FN tunnel current can be used for both writing (pulling out) and erasing (injection). Then, in the injection operation using the FN tunnel current, by injecting the electrons from the substrate side as described above, it becomes possible to inject with a smaller current as compared with the conventional source side injection. Therefore, the number of memory cells that can be injected at the same time dramatically increases, and high-speed operation of the entire system becomes possible. This also means that a lower power supply voltage can be boosted and used as a power supply for writing / erasing.

Further, in the structure of the memory cell of the EEPROM according to this embodiment, the floating gate 7 is formed in a self-aligned manner with respect to the select gate 6, so that an extremely high density E
There is an advantage that an EPROM can be formed.

In addition, by adopting the structure and driving method of the memory cell array as in the present embodiment, in order to prevent excessive writing (that is, electrons are excessively pulled out from the floating gate and the memory cell is always turned on). The write verify that is required in the conventional FN writing and FN erasing method memory cell array becomes unnecessary. This is because the memory cell employed in the present invention has a region not covered with the floating gate, that is, a region covered only with the select gate, between the source and drain regions. Therefore, this also contributes to the reduction of the writing time of the entire system. Further, by adopting the operation of the present invention, since the mechanism (FN current) that is the most stable and has the least write / erase damage at the present time can be used, a dramatic increase in the number of rewrites can be expected.

In particular, as in the present embodiment, the select lines are arranged to extend not along the columns but along the rows, so that the bit lines extend orthogonally to the bit lines extending along the columns. On the other hand, if the select line extends along the column like the bit line, a leak current may flow between the source and the bit line through the select line in the non-selected memory cell portion during reading. The leak current may cause erroneous reading such that the selected memory cell is judged to be in the written state even though it is in the erased state. On the other hand, in the relationship between the selection line and the bit line as in the present embodiment, the erroneous reading as described above can be reliably prevented.

(Second Embodiment) FIG. 10 is a sectional view showing the structure of an EEPROM memory cell according to a second embodiment. The structure of the memory cell according to the present embodiment is that the control selection gate 12 which is an integrated control gate and selection gate is provided.
Further, the gate oxide film 5 is made considerably thicker than in the first embodiment.

In the structure as in this embodiment, the select line SL and the word line WL in a certain memory cell are brought into conduction. Therefore, for example, in the electron extraction operation from the floating gate according to the method 1 shown in FIG. 3, -10 V is applied to the selection line SL4. That is, in the memory cell shown in FIG. 10, the potential of the control selection gate 12 is set to a low potential value −10 V, the potential of the drain region 2 is set to 5 V, and the electrons of the floating gate 7 are moved to the drain region 2 side. Be pulled out.
At that time, since the source area 3 is open,
Electrons do not move between the control selection gate 12 and the source region 3 and no trouble occurs. Similarly, no trouble occurs in the write operation according to the method 2 shown in FIG.

In the erase operation shown in FIGS. 5 and 6, a voltage of about 15 to 18 V is applied between the control selection gate 12 and the silicon substrate 1. If the lower insulating film 5 is made sufficiently thicker than the insulating film below the floating gate 7, electrons will not be transferred between the gate and the substrate, and no trouble will occur.

Further, in the read operation shown in FIG. 7, since the potentials of the word line WL4 and the select line SL4 connected to the memory cell M42 to be read are both set to Vcc, the word line and the select line become conductive. There is no problem even if you do.

When the control selection gate in which the control gate and the selection gate are integrated is provided as in the present embodiment, the write, erase, and read operations are the same as those described above.
The same operation as that in the above embodiment can be adopted. Further, in the structure of the present embodiment, the control gate and the select gate are integrated, so that a higher density E
An EPROM can be formed.

Further, by adopting the structure of this embodiment, the word line and the selection line can be integrated into one wiring, and the integration degree can be remarkably improved.

(Third Embodiment) Next, an EEPROM according to a third embodiment will be described with reference to FIGS.

FIG. 11 is a sectional view showing the structure of the memory cell in the EEPROM of the first type of the third embodiment. As shown in the figure, the first type EEPRO
In the case of M, the select gate 6 and the floating gate 7 patterned from the same polysilicon film are formed on the P-type silicon substrate 1 via the gate insulating films 5 and 4 each having a thickness of about 5 to 10 nm. ing. An insulating film 8 made of a silicon oxide film is formed between the gates 6 and 7 and on the side walls, and an oxide film (Oxi) is formed on the gates 6 and 7.
de), nitride film (Nitride) and oxide film (Oxi)
A control gate 9 made of a polysilicon film is provided via an ONO composite insulating film 10 made of de). Also,
A drain region 2 and a source region 3, which are impurity diffusion layers, are formed in regions of the P-type silicon substrate 1 located on the sides of the gates 6 and 7, respectively.

This structure is similar to the structure of the EEPROM already proposed by the present inventor shown in FIG. 27, but in this embodiment, the thickness of the gate insulating film is made as thin as 5 to 10 nm and the source side implantation is performed. It is different in that it is configured so that the implantation can be performed by FN tunneling from a region located between the source and the drain in the silicon substrate 1 without using the mechanism. In this way, by injecting the electrons into the floating gate 7 by using the FN tunneling instead of the source side injection, basically the same effect as that of the first embodiment can be exhibited. it can. Moreover, such a structure has an advantage that the manufacturing cost is lower than that of the first embodiment, in that the semiconductor memory device can be formed by the process of the two-layer polysilicon film.

FIG. 12 is a sectional view showing the structure of the memory cell of the second type EEPROM of the third embodiment. The memory cell of the second type EEPROM has a relatively large distance between the control gate 6 and the floating gate 7 as compared with the first type EEPROM, or only the thin insulating film 10 is formed on the gates 6 and 7. Obtained when forming. In this case, the drain region 2 and the source region 3
At the time of implanting the impurity ions to form the diffusion layer 11, the diffusion layer 11 is also formed in the region in the silicon substrate 1 located between the gates 6 and 7. However, even in the case of this structure, basically the same effect as that of the first type EEPROM can be obtained.

FIGS. 13 and 14 are cross-sectional views showing the structure of the memory cells of the third and fourth type EEPROMs of the third embodiment, respectively. The control gate 9 of the EEPROM has a structure formed only on the floating gate 7. That is, according to the third and fourth type EEPROMs, the function of the control gate 9 can be exerted even if the control gate 9 does not exist above the selection gate 6, and the parasitic capacitance between the control gate and the selection gate can be exerted. Is reduced, so that there is an advantage that the reading speed becomes faster.

FIG. 15 is a sectional view showing the structure of a memory cell of an EEPROM of the fifth type in the third embodiment. In this type of EEPROM, the distance between the floating gate 7 and the select gate 6 of the memory cell of the fourth type of EEPROM is increased so that the control gate 9 covers the upper surface and both side surfaces of the floating gate 7, and It is separated from the selection gate 6. According to the fifth type of EEPROM, since the distance between the floating gate 7 and the selection gate 6 is set large, the control gate 9 does not come close to the selection gate 6 even if the misalignment occurs. Therefore, the parasitic capacitance can be surely reduced. Further, since the capacitance between the control gate 9 and the floating gate 7 becomes large, there is an advantage that the function of injecting electrons into the floating gate 7 and the function of emitting electrons can be enhanced.

Next, FIG. 16 shows the second embodiment of this embodiment.
It is a circuit diagram which shows partially the structure of the structure of the memory cell array in a 4th type and a 5th type. As shown in FIG. 16, in each memory cell, the select transistor and the memory transistor are separated, but the drain regions of adjacent memory cells are formed in a common region, and the source regions of adjacent memory cells are formed. It is basically the same as the structure of the memory cell array shown in FIG. 2 in that it is formed in a common region. The respective parts of the memory cell shown in FIGS. 12, 14 and 15 are connected as follows in the circuit. The control gate 9 of each memory transistor has word lines WL1, WL2, ...
Memory cells connected to each other and adjacent to each other, for example, a memory cell M
The drain regions 2 of 11 and M21 are connected to a common bit line BL1 extending along the column. Further, a source line for connecting the source regions 3 shared by the memory cells in the two rows is provided, and the two source lines are further shared by one, corresponding to four word lines. Common source lines SSL1, SSL2, ... Are provided for every four rows. Further, the selection gates 6 of the memory cells arranged in a common row are connected to the selection lines SL1, SL2, ... Which extend along the row. The diffusion layer 11 between the memory transistor and the select transistor is not connected to any signal line.

Next, writing and erasing operations to the memory cell M22 will be described with reference to FIGS.

-Write (pull-out) operation-In the write operation, each select line SL1, SL
2, ... are set to 0V and each source line SSL1, SS
With L2, ... Opened and the silicon substrate 1 grounded, the drain region of the memory cell M22 to be written is connected to the word line WL2 to which the control gate of the memory cell M22 to be written is connected. The potential of the bit line BL2 is set high enough to allow the FN tunnel current to flow. By setting in this way, the electrons accumulated in the floating gate 7
That is, it is pulled out to the bit line BL2. In that case,
There are the following method 1 and method 2 for setting potentials of word lines, bit lines, selection lines, and the like.

(Method 1) As shown in FIG. 17, the potential of the word line WL2 connected to the memory cell M22 in which the memory is written is set to −10.
Are set to V, the potentials of the other word lines WL1, WL3, WL4, ... Are set to 0V, respectively, and the potential of the bit line BL2 connected to the memory cell M22 is set to a positive value of 5V, and the other bit lines BL1, BL3. Set each to open. In addition, all select lines SL1, SL2
... is grounded and all source lines SSL1, SSL
Open 2, ...

(Method 2) As shown in FIG. 18, a memory cell M22 for writing data
Is connected to the ground, the potential of the other word lines WL1, WL3, WL4, ... Is set to 6V, and the potential of the bit line BL2 connected to the memory cell M22 is set to 12V and other bits are set. Line BL1,
Set BL3, BL4, ... to open. Further, all the selection lines SL1, SL2, ... Are grounded and all the source lines SSL1, SSL2 ,.

By the above potential setting method, electrons are selectively extracted from the floating gate of only the memory cell M22 arranged at the intersection of the word line WL2 and the bit line BL2, that is, the memory cell M22 is set to the write state. Will be possible.

-Erase (Injection) Operation-When all the memory cells commonly connected to at least one word line in the memory cell array are set to the erased state, the potential of the word line is set to a positive high value,
The potential of the silicon substrate is set to a low potential, and the potential difference between the control gate and the silicon substrate is set large enough to allow the FN tunnel current to flow. Thereby, in all the memory cells commonly connected to at least one word line in the memory cell array, electrons are injected into the floating gate from the region located between the source and the drain in the silicon substrate through the tunnel insulating film. . It is preferable that at least one of the source / drain regions has the same potential as the silicon substrate. For the above reason. At that time, as a specific method of setting the voltages of the word line, the silicon substrate, the bit line, etc., there are the following methods, for example.

(Method 1) As shown in FIG. 19, four word lines WL2 to WL
5 (word line WL5 is not shown) is set to a potential of about 10V, and these four word lines WL2-
The potential of the source line SSL2 corresponding to WL5 is -8V
, The potentials of the selection lines SL2 to SL5 (the selection line SL5 is not shown) corresponding to the four word lines WL2 to WL5 are set to −4 V, and the potentials of the non-selected source lines SSL1 and the like are set to −. Set to 4V. Then, the potential of the silicon substrate 1 is set to about -8V.
On the other hand, unselected selection lines SL1 and the like and word lines W
L1 etc. are grounded and all bit lines BL1, BL
Open 2, ... By setting such a potential, electrons are collectively injected into the floating gates of the memory cells connected to the four word lines WL2 to WL5. When all memory cells are to be erased, all the word lines WL1 and WL1 in the state shown in FIG.
2, source potential of 10V, all source lines SSL
The potentials of 1, ... Are set to −8 V, and all selection lines SL1,
The potentials of SL2, ... May be set to -4V, respectively.

In the erase method described above, this memory cell array can perform sector erase for every four word lines WL2 to WL5 or batch erase of all memory cells, and the minimum erase unit is four word lines. It becomes the number of memory cells connected to.

(Method 2) As shown in FIG. 20, the potential of the selected word line WL2 is set to about 15 V and the unselected word lines WL1 and W
L3, WL4, ... Are grounded, and the silicon substrate 1 is also grounded. And all bit lines BL1, BL2, ...
To open all select lines SL1, SL2
... and all the source lines SSL1, SSL2, ... are grounded. When all memory cells are to be erased, the potentials of all word lines WL1, WL2, ... May be set to 15V in the state shown in FIG.

By the above erasing method, this memory cell array can perform sector erasing for each word line WL1, WL2, ... Or batch erasing of all memory cells, and the minimum erasing unit is one word. It is the number of memory cells connected to the line.

-Read Operation-As shown in FIG. 21, the potential of the word line WL2 connected to the memory cell M22 to be read is set to Vcc.
Set to other word lines WL1, WL3, WL4, ...
Is grounded, the potential of the bit line BL2 connected to the memory cell M22 is set to 1 V, and the other bit lines BL1,
BL3, ... Are set to open, the potential of the select line SL2 connected to the memory cell M22 is set to Vcc, and the other select lines SL1, SL3, SL4, ... And all the source lines SSL1, SSL2 ,.

According to the potential setting method as described above, also in this embodiment, basically the same writing, erasing and reading as in the first embodiment can be performed and the same effect can be exhibited. it can.

(Fourth Embodiment) Next, a fourth embodiment will be described. FIG. 22 is a cross-sectional view of the memory cell of the EEPROM according to the fourth embodiment. As shown in the figure, a select gate 6 and a floating gate 7 are formed on a silicon substrate 1 via gate oxide films 5 and 4, respectively, and a drain region 2 is formed in the silicon substrate 1 located beside the floating gate 7. However, the source region 3 is formed in the silicon substrate 1 located on the side of the select gate 6, and the diffusion layer 11 is formed in the silicon substrate 1 located between the gates 6 and 7, respectively. The same as the EEPROM of the fifth type in the above embodiment. Here, in the EEPROM of the present embodiment, the control gate 9a and the dummy gate 9b are formed on the floating gate 7 and the select gate 6 via the insulating films 10a and 10b, respectively. The control gate 9a and the dummy gate 9b are patterned from the same second-layer polysilicon film, and have the same width as the floating gate 7 and the select gate 6, respectively. The insulating films 10a and 10b are patterned from the same ONO film. The surfaces of the silicon substrate 1 and each gate are covered with an insulating film 13.

Next, FIG. 23 shows the EEPR according to this embodiment.
FIG. 9 is a plan view for explaining the manufacturing process for the OM memory cell array. However, the state shown in FIG. 23 does not exist in the middle of the manufacturing process. Also, FIG.
(A)-(c) are respectively XXIVa-XXIV shown in FIG.
It is sectional drawing in the a line, the XXIVb-XXIVb line, and the XXIVc-XXIVc line. Hereinafter, FIGS. 23 and 24 (a) to (c)
The manufacturing process and structure of the EEPROM according to the present embodiment will be described with reference to FIG.

In the manufacturing process, after the element isolation 20 made of an oxide film is formed on the silicon substrate 1, a gate oxide film is formed, and a polysilicon film 21 of the first layer is further formed thereon.
(A shaded portion as a whole) is formed. Then, each element isolation 20 of the first-layer polysilicon film 21 is
The rectangular opening 21 is formed by selectively removing the upper portion.
a is formed. Then, although not shown, a second-layer polysilicon film is deposited on the first-layer polysilicon film via an insulating film. Further, although not shown, a portion of the second-layer polysilicon film including a portion above the select gate and corresponding to the right end in the figure is selectively removed. This facilitates formation of the gate lead-out wiring 23 from the select gate 6 as shown in FIG. The second-layer polysilicon film is patterned to form the control gate 9a and the dummy gate 9b.
Further, the first-layer polysilicon film 21 is also patterned at the same time to form the floating gate 7 and the select gate 6.
At this time, as shown in FIG. 24B, the floating gate 7 is divided on the element isolation 20 due to the opening 21a formed in the first-layer polysilicon film 21, and is separated for each memory cell. It will be in a state of being. After that, B on the entire surface of the substrate
After depositing an interlayer insulating film 24 made of a PSG film or the like and forming a contact window, a metal film such as aluminum is deposited on the entire surface. Further, by patterning this metal film, the bit line 22 connected to the drain region 2 and the select gate 6 are formed.
Select gate lead-out wiring 23 connected to (2
4 (a) and (c)). Although not shown, the source line connected to the source region 3 is formed in an upper wiring layer.

Also in this embodiment, the writing and erasing methods are the same as those in the third embodiment, and when erasing, electrons are transferred from the region located between the source and the drain in the silicon substrate 1 to the floating gate 7. Is configured to be injected. Therefore, basically, the same effect as that of the third embodiment can be exhibited. In addition, since the control gate and the floating gate are simultaneously formed using the resist film as a mask, the mask of the control gate and the floating gate is different from that of the EEPROM of the fifth type (see FIG. 15) in the third embodiment. The margin considering the shift is not necessary, and the size of the memory cell can be reduced. Further, since there is no portion where the control gate 9 and the silicon substrate 1 are close to each other via the insulating film as shown in FIG. 15, there is no portion where a high electric field is applied to the insulating film on the silicon substrate 1 during writing and erasing. , The reliability will be higher.

A dummy gate 9 is provided on the selection gate 6.
Even if b is present, as shown in FIG. 24C of this embodiment, gate extraction for contacting the select gate 6 in the portion where the second-layer polysilicon film near the end of the memory cell array is removed Forming the wiring 23 does not make it difficult to take out a signal from the selection gate 6 (selection line SL).

[0087]

According to the semiconductor memory device of the present invention, the select gate and the floating gate are arranged in parallel on the semiconductor substrate located between the first and second diffusion layers in the semiconductor substrate. A first insulating film capable of FN tunneling is interposed between the diffusion layer and the substrate and the floating gate, and the FN tunneling is used to float from a region located between the first and second diffusion layers in the semiconductor substrate. Since it is possible to inject electrons into the gate and extract electrons from the floating gate to the first diffusion layer, lower voltage of the semiconductor memory device, improvement of writing speed, and prevention of deterioration of the tunnel insulating film. Therefore, the reliability can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a memory cell of an EEPROM according to a first embodiment.

FIG. 2 is an electric circuit diagram of a memory cell array of the EEPROM according to the first embodiment.

FIG. 3 is an EEPROM system 1 according to the first embodiment.
FIG. 6 is an electric circuit diagram showing a voltage setting state of each unit when writing is performed by the method.

FIG. 4 is a EEPROM method 2 according to the first embodiment;
FIG. 6 is an electric circuit diagram showing a voltage setting state of each unit when writing is performed by the method.

FIG. 5 is an EEPROM system 1 according to the first embodiment.
FIG. 6 is an electric circuit diagram showing a voltage setting state of each part when erasing is performed by.

FIG. 6 is a method 2 of the EEPROM in the first embodiment.
FIG. 6 is an electric circuit diagram showing a voltage setting state of each part when erasing is performed by.

FIG. 7 is an electric circuit diagram showing a voltage setting state of each part when reading from the EEPROM in the first embodiment.

FIG. 8 is a diagram showing a relationship between a pulse width of a signal and a threshold when electrons are extracted from the floating gate of the memory cell of the EERPOM according to the present invention.

FIG. 9 is a diagram showing a relationship between a pulse width of a signal and a threshold value when injecting electrons into a floating gate of a memory cell of EERPOM according to the present invention.

FIG. 10 is a cross-sectional view showing a structure of an EEPROM memory cell according to a second embodiment.

FIG. 11: EE in the first type of the third embodiment
It is sectional drawing which shows the structure of the memory cell of PROM.

FIG. 12 EE in the second type of the third embodiment
It is sectional drawing which shows the structure of the memory cell of PROM.

FIG. 13: EE in the third type of the third embodiment
It is sectional drawing which shows the structure of the memory cell of PROM.

FIG. 14 EE in the fourth type of the third embodiment
It is sectional drawing which shows the structure of the memory cell of PROM.

FIG. 15 EE in the fifth type of the third embodiment
It is sectional drawing which shows the structure of the memory cell of PROM.

FIG. 16 is an electric circuit diagram of a memory cell array of an EEPROM according to the third embodiment.

FIG. 17 is an electric circuit diagram showing a voltage setting state of each part when writing is performed by the method 1 of the EEPROM according to the third embodiment.

FIG. 18 is an electric circuit diagram showing a voltage setting state of each part when writing is performed by the method 2 of the EEPROM in the third embodiment.

FIG. 19 is an electric circuit diagram showing a voltage setting state of each part when erasing by the method 1 of the EEPROM in the third embodiment.

FIG. 20 is an electric circuit diagram showing a voltage setting state of each part when erasing by the method 2 of the EEPROM in the third embodiment.

FIG. 21 is an electric circuit diagram showing a voltage setting state of each part when reading the EEPROM in the third embodiment.

FIG. 22 is a sectional view showing the structure of an EEPROM memory cell according to a fourth embodiment.

FIG. 23 is a plan view for explaining the manufacturing process for the memory cell of the EEPROM in the fourth embodiment.

24 is a XXIVa-XXIVa line and XX shown in FIG. 23, respectively.
It is sectional drawing in the IVb-XXIVb line and the XXIVc-XXIVc line.

FIG. 25 is a cross-sectional view showing the structure of a conventional general EEPROM memory cell.

FIG. 26 is an EEPROM using conventional source-side injection.
3 is a cross-sectional view showing the structure of the memory cell of FIG.

[Explanation of symbols]

1 Silicon substrate 2 drain region 3 Source area 4 Tunnel oxide film 5 Gate insulation film 6 selection gates 7 floating gate 8 Silicon oxide film 9 control gate 10 ONO film M memory cell WL word line SL selection line BL bit line SSL source line

Front page continued (51) Int.Cl. ⁷ identification code FI H01L 29/792 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/8247 G11C 16/02 G11C 16/04 H01L 27 / 115 H01L 29/788 H01L 29/792

Claims (14)

(57) [Claims] 1. A semiconductor memory device in which at least one memory cell is mounted on a semiconductor substrate, wherein the memory cell is of a second conductivity type and is formed in a region of the first conductivity type of the semiconductor substrate so as to be separated from each other. First spread of
A layer, a second diffusion layer and a third diffusion layer , a floating gate formed on a region of the semiconductor substrate between the first diffusion layer and the third diffusion layer, and the floating gate a first insulating and film, and a select gate formed over a region between said second diffusion layer and the third diffusion layer on the semiconductor substrate which is formed between the above semiconductor substrate, A second intervening between the select gate and the semiconductor substrate
An insulating film, a control gate formed above the floating gate, and a third interposed between the floating gate and the control gate.
And the insulating film, and the dummy gate formed above the select gate, and a fourth insulating film interposed between the dummy gate and the select gate, due to injection of electrons into the floating gate electrode In the first
The bit line connected to the diffusion layer of
Then, the semiconductor substrate is set to the first potential, and the control gate is set.
Is higher than the first potential of the semiconductor substrate.
To the first potential in the semiconductor substrate.
From a region located between the diffusion layer of the
What is done by FN tunneling to the floating gate
A semiconductor memory device characterized by: 2. The semiconductor memory device according to claim 1.
hand, A word line connected to the control gate, A source line connected to the second diffusion layer
A semiconductor memory device characterized by being present. 3. The semiconductor memory device according to claim 1, wherein the third insulating film and the fourth insulating film are formed by patterning the same insulating film, and the floating gate. And the select gate are formed by patterning the same first conductor film, and the control gate and the dummy gate are formed by patterning the same second conductor film. A semiconductor memory device characterized by: 4. The semiconductor memory device according to claim 1, wherein the control gate has the same width as the floating gate, and the dummy gate has the same width as the select gate. A semiconductor memory device having: 5. The semiconductor memory device according to claim 1, wherein the first insulating film is composed of a silicon oxide film having a thickness of 5 nm or more and less than 10 nm. A semiconductor memory device characterized by: 6. The semiconductor memory device according to claim 1, wherein the dummy gate is formed over a plurality of memory cells, and the select gate has an end of a memory cell array. A semiconductor memory device characterized in that a gate lead-out wiring is formed in contact with a portion where the dummy gate is removed near the portion. 7. At least one memory on a semiconductor substrate
In a semiconductor memory device equipped with cells, The memory cell is a region of the first conductivity type of the semiconductor substrate.
A first diffusion of a second conductivity type formed separately in the interior
A layer and a second diffusion layer, On the semiconductor substrate, one end of the first diffusion layer and the first diffusion layer
Floating formed over the area between the first and second diffusion layers
The gate, A first gate formed between the floating gate and the semiconductor substrate;
1 insulating film, On the semiconductor substrate, one end of the first diffusion layer and the first diffusion layer
The selective gate formed over the region between the first and second diffusion layers
And A second intervening between the select gate and the semiconductor substrate
Insulation film, Formed near at least part of the floating gate
Control gate, A third insulating film is provided between the floating gate and the control gate.
Prepare, When injecting electrons into the floating gate electrode, the first
The bit line connected to the diffusion layer of
Then, the semiconductor substrate is set to the first potential, and the control gate is set.
Is higher than the first potential of the semiconductor substrate.
To the first potential in the semiconductor substrate.
From the region located between the second diffusion layer and the second diffusion layer
What is done by FN tunneling to the floating gate
A semiconductor memory device characterized by: 8. At least one memory on a semiconductor substrate
In a semiconductor memory device equipped with cells, The memory cell is a region of the first conductivity type of the semiconductor substrate.
A first diffusion of a second conductivity type formed separately in the interior
A layer, a second diffusion layer and a third diffusion layer, On the semiconductor substrate, the first diffusion layer and the third diffusion layer
A floating gate formed between the layer and A first gate formed between the floating gate and the semiconductor substrate;
1 insulating film, On the semiconductor substrate, the second diffusion layer and the third diffusion layer
A select gate formed between the layer and A second intervening between the select gate and the semiconductor substrate
Insulation film, Formed near at least part of the floating gate
Control gate, A third insulating film is provided between the floating gate and the control gate.
Prepare, When injecting electrons into the floating gate electrode, the first
The bit line connected to the diffusion layer of
Then, the semiconductor substrate is set to the first potential, and the control gate is set.
Is higher than the first potential of the semiconductor substrate.
To the first potential in the semiconductor substrate.
From a region located between the diffusion layer of the
What is done by FN tunneling to the floating gate
A semiconductor memory device characterized by: 9. A semiconductor memory device in which at least one memory cell is mounted on a semiconductor substrate, wherein the memory cell is of a second conductivity type and is formed in a region of the first conductivity type of the semiconductor substrate so as to be separated from each other. A first diffusion layer and a second diffusion layer, and a select gate formed on the semiconductor substrate on a region between the first diffusion layer and the second diffusion layer via a gate insulating film. A floating gate formed on both sides of the select gate via a first insulating film, and a second insulating film on the select gate and the floating gate.
And a tunnel insulating film formed between the semiconductor substrate and the floating gate. When injecting electrons into the floating gate electrode, the first gate is formed.
The bit line connected to the diffusion layer is opened, the semiconductor substrate is set to the first potential, and the control gate is set to the second potential which is higher than the first potential of the semiconductor substrate. Set the first in the semiconductor substrate
The semiconductor memory device is characterized in that it is performed by FN tunneling from a region located between the diffusion layer and the second diffusion layer to the floating gate. 10. A semiconductor memory device in the serial <br/> mounting any one of claims 1 to 9, said first diffusion layer, the drain region, said second diffusion layer, A semiconductor memory device characterized by being a source region. 11. A method of manufacturing a semiconductor memory device according to claim 1.
A method, to form (a) forming a gate insulating film capable of FN tunneling on a semiconductor substrate element isolation is formed, a first conductive film on the gate insulating film ( b), a step (c) of selectively removing a portion of the first conductor film located on the element isolation to form a rectangular opening, and after the step (c), Step (d) of forming an insulating film on the first conductive film, and step (e) of forming a second conductive film on the insulating film.
And (f) forming the control gate and the dummy gate by patterning the second conductor film, and patterning the first conductor film to form the floating gate and the select gate. In the step (g), the floating gate is divided on the element isolation by the opening formed in the first conductor film, and is separated for each memory cell. Formed,
The method of manufacturing a semiconductor memory device, wherein the select gate is formed over a plurality of memory cells, and the dummy gate is formed over a plurality of memory cells. 12. The method of manufacturing a semiconductor memory device according to claim 11 , wherein after the step (g), a step (h) of removing at least one of both ends of the dummy gate, and the select gate. A method of manufacturing a semiconductor memory device, further comprising: a step (i) of forming a gate lead-out wiring that contacts the portion where the dummy gate is removed. 13. The method of manufacturing a semiconductor memory device according to claim 11 , wherein the gate insulating film is formed of a silicon oxide film having a thickness of 5 nm or more and less than 10 nm. Manufacturing method. 14. The method of manufacturing a semiconductor memory device according to claim 11 , wherein the dummy gate is formed over a plurality of memory cells. Manufacturing method.