JP3577715B2 - ATM communication system and ATM multi-link communication method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an ATM communication system and an ATM multi-link communication method, and more particularly to an ATM (Asynchronous Transfer Mode) cell header using a HEC (Header Error Control) area in a cell header. The present invention relates to an ATM communication system and an ATM multi-link communication method suitable for achieving synchronization.
[0002]
[Prior art]
Today, communication using ATM cells, which decomposes all information such as voice / data / video into 53-byte cells and transfers the data in a network, has permeated the social infrastructure. For example, an ATM megalink service provided by NTT (Nippon Telegraph and Telephone Corporation) is set at a lower price than a normal dedicated line service.
[0003]
On the other hand, a user who uses the leased line service including the ATM megalink service is required to provide INS64 (International Telecommunication Union-Telecommunication Standardization Sector and TTC (The Telecommunications Company) for the purpose of backup in case of failure. Since the speed of the channel to be handled is 64 kbit / s, a dial-up line such as a standardized basic interface service or an INS 1500 (a primary rate interface service standardized by ITU-T and TTC) is used. We have contracted and secured a communication route even in the event of a failure.
[0004]
However, when communication is performed using a plurality of B channels in the INS 64 or INS 1500 (multi-link communication), the plurality of transmitted B channels do not always arrive with the same time delay. In some circumstances, a high-speed leased line cannot be contracted, and a plurality of low-speed leased lines may be contracted to replace the line. In this case, the same problem as the dial-up line occurs.
[0005]
In recent years, in the Internet and the like, where traffic is explosively increasing, in order to solve the above-described problem, the problem is solved by using PPP-MP (PPP multi-link protocol; defined by RFC1717 and RFC1990). I have. Also, in ATM communication, there are techniques such as IMA (inverse multiplexing in ATM; defined by ATM Forum).
[0006]
As a conventional example relating to the above-described multi-link communication system using ATM, for example, a technique described in Japanese Patent Application Laid-Open No. 5-191434 has been proposed. The technology described in the publication is intended to improve the communication quality by forming a virtual channel for accommodating a subscriber, and has a multi-link control header in which ATM multi-link group identification information is inserted. An ATM cell is transmitted from an ATM transmitting section, and the ATM multi-link group corresponding to the ATM multi-link communication path identifying information obtained by analyzing the ATM multi-link group identification information of the received ATM cell by the ATM receiving section. An ATM multi-link communication system characterized by performing a reception process of an ATM cell transmitted via an ATM communication path of the above-mentioned.
[0007]
[Problems to be solved by the invention]
However, the IMA technology in the conventional ATM communication described above has the following problems.
[0008]
A first problem is that a special ATM cell (ICP cell: IMA control protocol cell) is inserted at regular intervals to synchronize links. By inserting a special ATM cell, the bandwidth available to the user is reduced correspondingly.
[0009]
The second problem is that the content of a special ATM cell (ICP cell) is set not in the header part but in the payload part, so that the processing tends to be complicated.
[0010]
An object of the present invention is to insert synchronization information into the HEC part of an ATM cell header when synchronizing between multiple links, so that at the time of n multi-link communications, the bandwidth per link n It is an object of the present invention to provide an ATM communication system and an ATM multi-link communication method capable of securing twice the bandwidth.
[0011]
[Means for Solving the Problems]
According to the present invention, in an ATM transmission circuit for transmitting ATM cells using a plurality of links, an ATM cell string is demultiplexed into a plurality of ATM cell strings and a plurality of ATM cell strings obtained by demultiplexing are mutually separated. An ATM transmission circuit is provided, comprising means for inserting synchronization information into the HEC area of each ATM cell at the same timing.
[0012]
Further, according to the present invention, an ATM receiving circuit that receives ATM cells from a plurality of links detects an ATM cell in which synchronization information is inserted into the HEC area among ATM cells in an ATM cell string received from each link. ATM receiving means for multiplexing ATM cells received from a plurality of links after synchronizing links so that ATM cells having synchronization information inserted in the HEC area have the same timing. A circuit is provided.
[0014]
[Action]
The ATM communication system of the present invention inserts synchronization information into a header error control (HEC) portion of an ATM cell header instead of transmitting a special ATM cell when synchronizing between multiple links. There is no effect on the communication bandwidth available to the user. For this reason, if the user performs n multi-link communications, the user can secure a band that is n times the band per link. Synchronization information between multiple links is set in the header of the ATM cell. For this reason, since the synchronization information can be found by a relatively simple procedure, a complicated procedure for interpreting the payload portion of the ATM cell is not required when synchronizing between multiple links.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
[This embodiment]
Next, embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
(1) Configuration Description As shown in FIGS. 1 and 2, the ATM communication system according to the embodiment of the present invention comprises a cell transmission circuit 2, a synchronization information insertion circuit 10, a delay circuit 12, a selection circuit 13, a separation circuit 14, 1 transmission timing generation circuit 20, a second transmission timing generation circuit 21, a first cell transmission circuit 30, a second cell transmission circuit 31, a n-th cell transmission circuit 32, and a cell reception circuit. Circuit 4, first cell receiving circuit 40, second cell receiving circuit 41, nth cell receiving circuit 42, first cell synchronizing circuit 50, second cell synchronizing circuit 51, nth cell synchronizing circuit 52 , A multiplexing circuit 60, a synchronization information deleting circuit 61, a delay circuit 63, an HEC calculating circuit 62, a selecting circuit 64, a first receiving timing generating circuit 70, and a receiving circuit 3 including a second receiving timing generating circuit 71. Is There.
[0017]
1 and 2, in the transmission circuit 1, the synchronization information insertion circuit 10 selects n consecutive ATM cells into which synchronization information for inverting each bit of the HEC is inserted. By the circuit 13 and the separation circuit 14, the first cell transmission circuit 30 to the n-th cell transmission circuit 32 transmit the signals sequentially to the links 1 to n. At this time, the selection circuit 13 and the separation circuit 14 transmit the n × (m−1) consecutive ATM cells from the delay circuit 12 to the link 1 through the first cell transmission circuit 30 to the n-th cell transmission circuit 32. To n sequentially, and thereafter, this is repeated.
[0018]
In the receiving circuit 3, the first cell receiving circuit 40 to the n-th cell receiving circuit 42 establish cell synchronization of ATM cells received from the links 1 to n. At this time, the ATM cells having synchronization information obtained by inverting each bit of the HEC, which appear every m cells, are not out of synchronization. The first cell synchronization circuit 50 to the n-th cell synchronization circuit 52 detect the ATM cell in which the synchronization information received every m cells is inserted, and multiplex the ATM cells based on the timing from the second reception timing generation circuit 70. The signals are transmitted to the circuit 60 in order. The selection circuit 64 selects n consecutive ATM cells in which each bit of the HEC is inverted again by the synchronization information deletion circuit 61 at a fixed interval, and sends them to the cell reception circuit 4.
[0019]
By configuring the transmission circuit 1 and the reception circuit 3 as described above, it is possible to obtain an effect that continuous ATM cells transmitted by the cell transmission circuit 2 can be received by the cell reception circuit 4 without changing the order. ing.
[0020]
More specifically, the transmission circuit 1 includes a synchronization information insertion circuit 10 that inverts each bit of the HEC portion of the continuous ATM cell from the cell transmission circuit 2. Consecutive ATM cells received by the synchronization information insertion circuit 10 from the cell transmission circuit 2 include not only valid cells but also empty cells (idle cells) inserted and extracted for speed matching in the physical layer. ing. The synchronization information insertion circuit 10 unconditionally inverts each bit of the HEC part in the ATM cell header.
[0021]
The header portion of each ATM cell is composed of a 5-byte area, and the fifth byte is allocated to a header error control (HEC) byte. In the HEC, the cyclic redundancy code (CRC) calculation results from the first byte to the fourth byte of the ATM cell header are inserted. On the receiving side, the ATM cell header is calculated based on the same calculation method as the transmitting side. To determine if there is an error. The synchronization information is transmitted to the receiving side by using the HEC portion and inverting each bit of the HEC at regular intervals. Since the quality of recent transmission lines is very good and the probability of occurrence of bit errors in the transmission lines is low, erroneous synchronization does not occur even if the present communication system is used.
[0022]
The delay circuit 12 is a circuit for delaying a continuous ATM cell from the cell transmission circuit 2 by the same time as the time taken by the synchronization information insertion circuit 10, and the selection circuit 13 transmits each ATM cell transmitted from the cell transmission circuit 2. An ATM cell in which synchronization information is inserted into an ATM cell and an ATM cell in which synchronization information is not inserted arrive at the same time.
[0023]
The selection circuit 13 does not insert the ATM cell into which the synchronization information from the synchronization information insertion circuit 10 has been inserted and the synchronization information from the delay circuit 12 according to the instruction of the selection signal created by the first transmission timing generation circuit 20. One of the ATM cells is selected and sent to the separation circuit 14.
[0024]
When transmitting the continuous ATM cells from the cell transmission circuit 2 using the links 1 to n, the selection signal generated by the first transmission timing generation circuit 20 includes n ATM cells with the synchronization information inserted therein. After that, a selection signal for selecting n × (m−1) ATM cells into which no synchronization information is inserted, and thereafter repeating this. The above m is an arbitrary value that is determined in advance between the transmitting circuit 1 and the receiving circuit 3.
[0025]
The separation circuit 14 sequentially orders the continuous ATM cells received from the selection circuit 13 from the first cell transmission circuit 30 to the n-th cell transmission circuit 32 according to the instruction of the selection signal from the second transmission timing generation circuit 21. Send to
[0026]
When transmitting a continuous ATM cell from the cell transmission circuit 2 using the links 1 to n, the selection signal generated by the second transmission timing generation circuit 21 has the synchronization information selected by the selection circuit 13 inserted therein. The first cell among the n consecutive ATM cells is sent to the first cell transmission circuit 30, and then sent to the second cell transmission circuit 31 to the n-th cell transmission circuit 32 in order. Are repeated selection signals.
[0027]
The receiving circuit 3 has a first cell receiving circuit 40 to an n-th cell receiving circuit 42 for establishing cell synchronization of continuous ATM cells received from the links 1 to n. At this time, the ATM cells having synchronization information obtained by inverting each bit of the HEC, which appear every m cells, are not out of synchronization.
[0028]
In the first cell synchronization circuit 50 to the n-th cell synchronization circuit 52, the first cell reception circuit 40 to the n-th cell reception circuit 42 receive continuous ATM cells for which ATM cell synchronization has been established, and receive m cells. The ATM cell in which the synchronization information is inserted, which appears for each ATM cell, is detected, and based on the synchronization signal instructed from the second reception timing generation circuit 71, the ATM cell in which the synchronization information is inserted is sequentially sent to the multiplexing circuit 60. send.
[0029]
The multiplexing circuit 60 sequentially selects ATM cells received from the first cell synchronization circuit 50 to the n-th cell synchronization circuit 52 according to a selection signal instructed from the second reception timing generation circuit 71. The synchronization information deletion circuit 61 unconditionally inverts each bit of the HEC part in the ATM cell header and deletes the synchronization information.
[0030]
The delay circuit 63 is a circuit for delaying the continuous ATM cells from the multiplexing circuit 60 by the same time as the time taken by the synchronization information deleting circuit 61. The selecting circuit 64 provides each ATM cell transmitted from the multiplexing circuit 60 The ATM cell from which synchronization information has been deleted and the ATM cell from which synchronization information has not been deleted arrive at the same time.
[0031]
Selection circuit 64, the selection signal instructed from the first reception timing generation circuit 70, is sent from the synchronization information deletion circuit 61, the ATM cell information is deleted synchronization is sent from the delay circuit 63, sync One of the ATM cells whose information is not deleted is selected and sent to the cell receiving circuit 4.
[0032]
That is, the multi-link communication system in the ATM according to the present embodiment adopts the above-described configuration, and synchronizes the links using the HEC area in the ATM cell header, thereby achieving the multi-link communication in the ATM. Is realized.
[0033]
(2) Description of Operation Next, the operation of the embodiment of the present invention will be described in detail with reference to FIGS.
[0034]
FIG. 3 shows that synchronization information is inserted into continuous ATM cells transmitted from the cell transmission circuit 2 of the transmission circuit 1 and transmitted in order from the first cell transmission circuit 30 to the n-th cell transmission circuit 32. It is an image. Consecutive ATM cells transmitted from the cell transmission circuit 2 are referred to by repeating numbers 1-1 to mn for convenience. The transmission circuit block 15 is configured by the circuit described in FIG.
[0035]
As described above, the cells are sequentially transmitted one by one from the first cell transmission circuit 30 to the n-th cell transmission circuit 32, and the synchronization information is inserted in the first cell of the m blocks. As shown in FIG. 3, the ATM cells into which the synchronization information is inserted all appear at the same time on each link.
[0036]
FIG. 4 is an image in which the ATM cell transmitted in FIG. 3 reaches the receiving circuit 3 through an external network. Since the delay time of each link is different, for example, an ATM cell into which synchronization information is inserted as shown in FIG. 4 is received with a shift between the links. If the received ATM cells are multiplexed as they are, the continuous ATM cells from the cell transmission circuit 2 in FIG. 3 cannot be restored, so that communication cannot be established. The first cell synchronization circuit 50 to the n-th cell synchronization circuit 52 shown in FIG. 4 detect the ATM cell in which the synchronization information is inserted, and in accordance with the instruction from the second reception timing generation circuit 71, the ATM cell in which the synchronization information is inserted. Output cells aligned.
[0037]
FIG. 5 shows a state in which the synchronization information of the ATM cells output together from each circuit is deleted and rearranged in order.
[0038]
In this way, the order of the ATM cells received via the external network is correctly restored when the cells are received by the cell receiving circuit 4 of the receiving circuit 3.
[0039]
As described above, according to the embodiment of the present invention, the synchronization information is inserted into the HEC portion of the ATM cell header instead of transmitting a special ATM cell when synchronizing between multiple links. However, there is no effect on the communication band available to the user. For this reason, if the user performs n multi-link communications, the user can secure a band that is n times the band per link. Also, since the synchronization information between the multi-links is set in the header of the ATM cell, the synchronization information can be found by a relatively simple procedure. Eliminates the need for complicated procedures to interpret the cell payload.
[0040]
[Other embodiments]
In the above embodiment, the means for transmitting the synchronization information uses the inversion method of each bit of the HEC. However, the present invention is not limited to the inversion method of each bit of the HEC. A method such as addition may be used. In this case, the same effect as in the above embodiment can be obtained.
[0041]
【The invention's effect】
As described above, according to the present invention, the transmitting apparatus inserts synchronization information for inverting each bit of the header error control into the header error control area of the ATM cell header, and outputs the continuous ATM information in which the synchronization information is inserted. The cells are sequentially transmitted to a plurality of links, and the receiving device establishes cell synchronization of the ATM cells received from the plurality of links, detects the ATM cells in which the synchronization information is inserted, and controls the header error of the ATM cell header. Since the synchronization information is deleted by inverting each bit in the area and the ATM cell in which each bit in the header error control area is inverted is controlled at a constant interval, the following effects are obtained.
[0042]
The first effect is that the synchronization information is inserted into the header error control (HEC) portion of the ATM cell header instead of transmitting a special ATM cell when synchronizing between multiple links. Does not affect the available communication bandwidth. For this reason, if the user performs n multi-link communications, the user can secure a band that is n times the band per link.
[0043]
As a second effect, since the synchronization information between the multi-links is set in the header portion of the ATM cell, the synchronization information can be found by a relatively simple procedure. This eliminates the need for complicated procedures for interpreting the payload portion of the ATM cell.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a transmission circuit of an ATM communication system according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration example of a receiving circuit of the ATM communication system according to the embodiment of the present invention.
FIG. 3 is a block diagram showing a transmission circuit of an ATM communication system according to an embodiment of the present invention, in which synchronization information is inserted into continuous ATM cells transmitted from a cell transmission circuit, and transmitted from a first cell transmission circuit to an n-th cell transmission circuit; It is explanatory drawing which shows the image transmitted in order.
FIG. 4 is an explanatory diagram showing an image in which an ATM cell transmitted from a transmission circuit of an ATM communication system according to an embodiment of the present invention reaches a reception circuit through an external network.
FIG. 5 is an explanatory diagram showing a state in which, in the receiving circuit of the ATM communication system according to the embodiment of the present invention, the synchronization information of the ATM cells output from each circuit is deleted and rearranged again in order.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 transmission circuit 3 reception circuit 10 synchronization information insertion circuit 13 selection circuit 14 separation circuit 30 first cell transmission circuit 31 second cell transmission circuit 32 n-th cell transmission circuit 40 first cell reception circuit 41 second cell Receiving circuit 42 nth cell receiving circuit 50 first cell synchronizing circuit 51 second cell synchronizing circuit 52 nth cell synchronizing circuit 61 synchronization information deleting circuit 64 selection circuit

Claims (4)

In an ATM transmission circuit for transmitting an ATM cell using a plurality of links,
  Means for demultiplexing the ATM cell string into a plurality of ATM cell strings and inserting synchronization information into the HEC area of each ATM cell at the same timing among a plurality of ATM cell strings obtained by demultiplexing. An ATM transmission circuit characterized by the following. In an ATM receiving circuit for receiving ATM cells from a plurality of links,
  Among the ATM cells in the ATM cell string received from each link, the ATM cells having the synchronization information inserted in the HEC area are detected, and the ATM cells having the synchronization information inserted in the HEC area are linked at the same timing. An ATM receiving circuit comprising means for multiplexing ATM cells received from a plurality of links after synchronization between them is established. In an ATM transmission method for transmitting an ATM cell using a plurality of links,
  Demultiplexing the ATM cell string into a plurality of ATM cell strings and inserting synchronization information into the HEC area of each ATM cell at the same timing among a plurality of ATM cell strings obtained by demultiplexing. Characteristic ATM transmission method. In an ATM receiving method for receiving ATM cells from a plurality of links,
  Among the ATM cells in the ATM cell string received from each link, the ATM cells having the synchronization information inserted in the HEC area are detected, and the ATM cells having the synchronization information inserted in the HEC area are linked at the same timing. Multiplexing ATM cells received from a plurality of links after synchronizing the ATM cells with each other.

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