JP3567317B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technology effective when applied to a semiconductor integrated circuit device, and further to a semiconductor integrated circuit device incorporating a tri-state output buffer. For example, the present invention relates to a CMOS or Bi operated by a low-voltage power supply of 3V system. The present invention relates to a technology effective for use in a semiconductor integrated circuit device of a CMOS process.
[0002]
[Prior art]
In the field of semiconductor integrated circuit devices for logic, 3V-based semiconductor integrated circuit devices that operate at a + 3.3V power supply voltage lower than a standard + 5V power supply voltage have been used in order to achieve higher integration density, higher speed, and lower power consumption. Are provided.
[0003]
In order to use this 3V semiconductor integrated circuit device connected to a bus line of a standard 5V system, a tristate output buffer capable of operating normally even when a 5V amplitude system signal is reversely applied to the output. (For example, see “Nikkei Micro Devices” published by Nikkei BP, pp. 83-88).
[0004]
[Problems to be solved by the invention]
However, the present inventors have clarified that the above-described technique has the following problems.
[0005]
That is, when the output of the tri-state output buffer of the 3V semiconductor integrated circuit device is connected to the bus line of the 5V system, the output is obtained by turning off both the p-channel MOS transistor and the n-channel MOS transistor forming the CMOS output stage. Is in a high impedance state, a pn junction parasitic diode is formed in the forward direction from the drain region to the well region of the p-channel MOS transistor forming the pull-up drive side of the output stage, so that the internal 3 V The current flows backward toward the system power supply potential.
[0006]
In order to prevent the current from flowing backward due to the parasitic diode, the present inventors have studied to separate the well region of the p-channel MOS transistor, which forms the pull-up drive side of the output stage, from the power supply potential. In other words, the well region (so-called back gate) of the p-channel MOS transistor is normally connected to the power supply potential (source side). By separating this from the power supply potential, the backflow of the current due to the parasitic diode is prevented. We considered that.
[0007]
However, even if the well region is separated from the power supply potential, if the drain voltage of the p-channel MOS transistor exceeds the reverse threshold value between the drain and the gate, the p-channel MOS transistor itself is turned on, and the p-channel MOS transistor itself is turned on. A current flows from the output to the internal 3V power supply potential through the activated p-channel MOS transistor.
[0008]
As described above, in the conventional semiconductor integrated circuit device, when the output is connected to a relatively high-voltage power supply system and used, specifically, the output of the 3V semiconductor integrated circuit device is connected to the standard 5V system. However, in the case of connecting the bus line to a high-impedance state, it is not possible to reliably prevent the current from flowing back from the output to the power supply potential when the output is in a high impedance state. Was.
[0009]
An object of the present invention is to set the output to a high impedance disinebule state even when the output of a 3 V system semiconductor integrated circuit device is used by connecting it to a bus line of a standard 5 V system. It is an object of the present invention to provide a technique for surely preventing a current from flowing backward from an output to a power supply potential.
[0010]
The above and other objects and features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0011]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0012]
That is, a well control circuit interposed between the power supply potential and the output and separating the well region of the p-channel MOS transistor serving as the pull-up drive side of the output stage from the power supply potential when disabling is enabled. A voltage bypass circuit for bypassing between the drain and the gate of the p-channel MOS transistor so that the voltage between the drain and the gate of the p-channel MOS transistor does not exceed a threshold value when applied; This is to provide an input separation circuit that is separated from the preceding circuit.
[0013]
According to the above-described means, it is possible to prevent the backflow of the current due to the parasitic diode between the drain and the well and to cause the drain voltage of the p-channel MOS transistor to exceed the reverse threshold between the drain and the gate. Backflow of current can also be prevented.
[0014]
Thus, for example, even when the output of a 3V semiconductor integrated circuit device is used by connecting it to the bus line of a standard 5V system, when the output is brought into a high impedance disinebule state, The object of reliably preventing the current from flowing backward from the output to the power supply potential is achieved.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0016]
In the drawings, the same reference numerals indicate the same or corresponding parts.
[0017]
FIG. 1 shows an embodiment of a semiconductor integrated circuit device to which the technology of the present invention is applied, wherein 1 is an output stage, 2 is a preceding circuit, and 3 is a tristate control circuit.
[0018]
The output stage 1 is configured by a CMOS circuit including a p-channel MOS transistor P1 and an n-channel MOS transistor N1. The p-channel MOS transistor P1 is interposed between the power supply potential Vcc (+3 V) and the output terminal 11 and forms an output pull-up drive side. The n-channel MOS transistor N1 is interposed between the output terminal 11 and the ground reference potential GND (0 V) and forms an output pull-down drive side. As shown in FIG. 2, the p-channel MOS transistor P1 on the pull-up drive side has a well region n1 separated from Vcc (source side).
[0019]
The pre-stage circuit 2 includes CMOS logic gates G1 and G2 and a CMOS inverter Iv2. When the enable signal E is at H (high level), the p-channel MOS transistor P1 and the n-channel MOS transistor N1 of the output stage are input signals. A signal for complementary on / off control is output according to A.
[0020]
The tristate control circuit 3 includes CMOS inverters Iv31 and Iv32, p-channel MOS transistors P2, P3, P4 and P5, and n-channel MOS transistors N2, N3 and N4. When the enable signal E is at L (low level). Then, the p-channel MOS transistor P1 and the n-channel MOS transistor N1 of the output stage 1 are both turned off regardless of the state of the input signal A.
[0021]
Here, the p-channel MOS transistors P1 to P5 are formed in a common well region n1.
[0022]
The p-channel MOS transistor P2 is interposed between the well region n1 of P1 and Vcc and connects the well region n1 of P1 to Vcc when enabled (E = H), and the well region when disabled (E = L). A well control circuit for separating n1 from Vcc (source of P1) is formed.
[0023]
The p-channel MOS transistor P3 has its gate connected to Vcc, its drain and source connected between the drain and gate of P1, and when a high voltage (+ 5V) is applied to the output terminal 11. , P1 so that the voltage between the drain and the gate of P1 does not exceed the threshold value, a voltage bypass circuit for bypassing the drain and the gate of P1 is formed.
[0024]
The p-channel MOS transistor P4 and the n-channel MOS transistor N2 connect the gate of the P1 to the pre-stage circuit 2 (output of the CMOS logic gate G1) when enabled, and disconnect the P1 gate from the pre-stage circuit 2 when disabled. Form an isolation circuit.
[0025]
The p-channel MOS transistor P5 and the n-channel MOS transistor N3 form a MOS switch circuit for connecting the gates of the p-channel MOS transistors P2 and P4 forming the well control circuit and the input separation circuit to the output terminal 11 when disabled. I do.
[0026]
FIG. 2 schematically shows the element structure of a p-channel MOS transistor P1 serving as a pull-up drive side of the output stage 1, wherein 101 is a p-type semiconductor substrate, 102 is an n-type well diffusion layer (well region n1). ) And 103 are p-type source / drain diffusion layers, 104 is a gate oxide film, 105 is a surface oxide film, 106 is a gate electrode, and 107 is an electrode lead wiring.
[0027]
In the figure, a parasitic diode Ds by a pn junction is formed between a p-type source / drain diffusion layer 103 and an n-type well diffusion layer 102. In the conventional case, the current may flow backward from the output terminal 11 to the power supply potential Vcc (+3 V) through the parasitic diode Ds. However, in the present invention, as described above, the n-type well diffusion layer 102 is disabled. Sometimes, it is cut off from Vcc to prevent the backflow of the current due to the parasitic diode Ds.
[0028]
Further, as shown in FIG. 1, when a high voltage (+5 V) is reversely applied to the output terminal 11, the p-channel MOS transistor P3 whose gate is connected to Vcc (+3 V) is turned on, whereby P1 is turned on. Is bypassed. Thereby, the backflow of the current due to the drain voltage of P1 exceeding the reverse threshold value between the drain and the gate is also prevented.
[0029]
Next, the operation of the main part will be described.
[0030]
In FIG. 1, first, when the enable signal E is set to H to set the enable state, the p-channel MOS transistor P1 serving as the pull-up drive side of the output stage 1 is supplied via the logic gate G1 and the MOS transistors N2 and P4. ON / OFF control is performed by the input signal A. The n-channel MOS transistor N1 serving as a pull-up drive side of the output stage 1 is turned on / off complementarily to the p-channel MOS transistor P1 by an input signal A provided via a logic gate G2 and an inverter Iv2. Controlled. Thereby, the output stage 1 logically drives the output terminal 11 to H or L according to the input signal A.
[0031]
In this case, the p-channel MOS transistor P1 of the output stage 1 performs on / off operation with its well region n1 connected to Vcc (+3 V) via the p-channel MOS transistor P2.
[0032]
Next, when the disable signal is set by setting the enable signal E to L, the outputs of the logic gates G1 and G2 are fixed to H irrespective of the state of the input signal A. As a result, both the p-channel MOS transistor P1 and the n-channel MOS transistor N1 of the output stage 1 are set to the off state, and the output is in the high impedance open state.
[0033]
At the same time, the p-channel MOS transistor P2 is turned off, and the well region n1 of the p-channel MOS transistor P1 is disconnected from Vcc. Thereby, the reverse flow path of the current from the output terminal 11 via the parasitic diode Ds is cut off.
[0034]
Here, when a voltage (+5 V) higher than the power supply potential Vcc (+3 V) is reversely applied to the output terminal 11, the reverse applied voltage (+5 V) causes the gate of the p-channel MOS transistor P <b> 3 to have a drain-based reverse. Before the threshold voltage (5V-3V) rises, the reverse threshold rises to the gate of P3, and P3 is turned on. By the on operation of P3, the gate side of p-channel MOS transistor P1 is turned on. A voltage (+5 V) substantially the same as that on the drain side (output terminal 11 side) is applied to (n2). As a result, the gate of P1 is prevented from rising at the reverse threshold voltage, and can be kept off.
[0035]
At this time, the respective drain sides (n2) of the n-channel MOS transistor N2 and the p-channel MOS transistor P4 interposed between the gate of the p-channel MOS transistor P1 and the logic gate G1 are also connected via the p-channel MOS transistor P3. Thus, a high voltage (+5 V) at the output terminal 11 is applied.
[0036]
However, the source (n3) of the n-channel MOS transistor N2 is connected to the output of the logic gate G1 and is fixed at H, and the power supply potential Vcc (+3 V) is applied to the gate (n3). As a result, the threshold voltage does not rise at the gate, and therefore, the off state is maintained. The p-channel MOS transistor P4 is also gated by applying a high voltage (+ 5V) at the output terminal 11 to the gate side (n4) via a switch circuit including an n-channel MOS transistor N3 and a p-channel MOS transistor P5. And the threshold voltage does not rise, and therefore also maintains the off state. N3 and P5 operate as switch circuits, and are turned on when in the disabled state.
[0037]
As described above, according to the present invention, in the disable state, even if a voltage higher than the power supply potential Vcc is reversely applied to the output terminal 11, the p-channel MOS transistor P1 serving as the pull-up drive side of the output stage 1 can be used. It is possible to prevent the current from flowing backward due to the parasitic diode Ds. At the same time, it is possible to prevent the current from flowing backward due to the drain voltage of the p-channel MOS transistor P1 exceeding the reverse threshold value between the drain and the gate.
[0038]
Thus, for example, even when the output of a 3V semiconductor integrated circuit device is used by connecting it to the bus line of a standard 5V system, when the output is brought into a high impedance disinebule state, It is possible to reliably prevent a current from flowing backward from the output to the power supply potential.
[0039]
As described above, the invention made by the inventor has been specifically described based on the embodiments. However, it is noted that the present invention is not limited to the above embodiments, and that various changes can be made without departing from the gist of the invention. Not even. For example, n-channel MOS transistor N1 serving as the bull-down drive side of output stage 1 may be a bipolar transistor.
[0040]
In the above description, the case where the invention made by the present inventor is applied to a semiconductor integrated circuit device for logic, which is a field of use as a background, has been mainly described. However, the present invention is not limited to this case. The present invention can also be applied to a digital mixed type semiconductor integrated circuit device.
[0041]
【The invention's effect】
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0042]
That is, for example, even when the output of the 3V-system semiconductor integrated circuit device is used by connecting it to the bus line of a standard 5V-system, when the output is set to a high impedance disinebule state, The effect is obtained that the current can be reliably prevented from flowing backward from the output to the power supply potential.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing one embodiment of a main part of a semiconductor integrated circuit device to which the technique of the present invention is applied.
FIG. 2 is a schematic diagram showing an element structure of a p-channel MOS transistor forming a pull-up drive side of an output stage.
[Explanation of symbols]
Reference Signs List 1 output stage 11 output terminal 2 pre-stage circuit 3 tri-state control circuit G1, G2 logic gates Iv2, Iv31, Iv32 inverters P1 to P5 p-channel MOS transistors N1 to N4 n-channel MOS transistor Vcc internal power supply potential (+ 3V)
GND Ground reference potential 101 P-type semiconductor substrate 102 N-type well diffusion layer (well region n1)
103 p-type source / drain diffusion layer 104 gate oxide film 105 surface oxide film 106 gate electrode 107 electrode extraction wiring Ds parasitic diode

Claims (6)

A semiconductor integrated circuit device incorporating a tri-state output buffer that takes an enable state for driving an output to H (high level) or L (low level) and a disable state for making an output high impedance, wherein the tri-state output is provided. The buffer is a p-channel MOS transistor interposed between the power supply potential and the output and serving as a pull-up drive side of the output stage. The buffer connects the well region to the power supply potential when enabled, and connects the well region to the power supply potential when disabled. A well control circuit for disconnecting the p-channel MOS transistor from the drain so that the voltage between the drain and the gate of the p-channel MOS transistor does not exceed the threshold value when a voltage exceeding the power supply potential is reversely applied to the output. A voltage bypass circuit and the p-channel MOS when enabled While connecting the gate of the transistor to the preceding circuit, the semiconductor integrated circuit device characterized by having an input isolation circuit to decouple the gate of the p-channel MOS transistor when disenable the pre-stage circuit. A second p-channel MOS transistor is formed in the well region common to the well region of the p-channel MOS transistor forming the pull-up drive side of the output stage, and the second p-channel MOS transistor causes the well region to be connected to the power supply potential. 2. The semiconductor integrated circuit device according to claim 1, wherein a well control circuit for turning on / off the connection is formed. A third p-channel MOS transistor is formed in a well region common to the well region of the p-channel MOS transistor serving as the pull-up drive side of the output stage, and the drain of the p-channel MOS transistor is formed by the third p-channel MOS transistor. 3. The semiconductor integrated circuit device according to claim 1, wherein a voltage bypass circuit is formed to bypass between the drain and the gate so that the voltage between the gates does not exceed the threshold value. A fourth p-channel MOS transistor is formed in a well region common to the well region of the p-channel MOS transistor forming the pull-up drive side of the output stage, and the p-channel MOS transistor is enabled by the fourth p-channel MOS transistor when enabled. 4. The semiconductor integrated circuit according to claim 1, wherein an input separation circuit is formed to connect the gate of the p-channel MOS transistor to the preceding circuit when disconnecting the gate of the p-channel MOS transistor from the preceding circuit. apparatus. A well control circuit and an input separation circuit are formed by a p-channel MOS transistor formed in a well region common to a well region of a p-channel MOS transistor serving as a pull-up drive side of an output stage. 5. The semiconductor integrated circuit device according to claim 1, further comprising a switch circuit for connecting each gate of a p-channel MOS transistor forming an input separation circuit to an output terminal side. 6. The semiconductor integrated circuit according to claim 1, wherein the output stage is a CMOS output stage including a p-channel MOS transistor serving as a pull-up drive side and an n-channel MOS transistor serving as a pull-down drive side. apparatus.

Images