JP3561556B2 - Manufacturing method of mask - Google Patents

Description

【００３３】
ｙ方向の内部節点を、
【００３４】
【数２】

【００３５】
とする。このとき、ｘ方向について、
【００３６】
【数３】

【００３７】
ｙ方向について、
【００３８】
【数４】

【００３９】
が成り立つと仮定する。スプライン関数Ｓ（ｘ，ｙ）は一組の基底関数を用いて表すことができる。この基底関数は１次元の基底関数のテンソル積でつくることができる。必要な基底関数をつくるために、ｘ方向に２ｍ個の付加節点
【００４０】
【数５】

【００４１】
を、ｙ方向にも同様に２ｍ個の付加節点
【００４２】
【数６】

【００４３】
を、それぞれ導入する。これにより、スプライン関数Ｓ（ｘ，ｙ）は、
【００４４】
【数７】

【００４５】
と表せる。ここで、Ｎｍｉ（ｘ）、Ｎｍｊ（ｙ）は、
【００４６】
【数８】

【００４７】
を満たし、それぞれ正規化されたｍ階（（ｍ−１）次）のＢ−スプライン（あるいは、ｆｕｎｄａｍｅｎｔａｌ ｓｐｌｉｎｅ）である。Ｂ−スプラインの値は次の漸化式によって計算できる。
【００４８】
【数９】

【００４９】
【数１０】

【００５０】
（数７）式が与えられた測定値の補間関数となるためには、
【００５１】
【数１１】

【００５２】
となればよい。（数１１）式はＣｉｊを未知数とする連立１次方程式であり、（数３）式、（数４）式、（数５）式の条件により一意的な解を有する。（数１１）を解くことによりＳ（ｘ，ｙ）を求めることができる。
【００５３】
ある位置（Ｘｓ，Ｙｓ）における補間値Ｄｘｓの計算は、以下のようにすればよい。まず、（Ｘｓ，Ｙｓ）が入る小領域Ｒ、
【００５４】
【数１２】

【００５５】
を見つける。すると、Ｂ−スプラインの局所性から、
【００５６】
【数１３】

【００５７】
により、補間値Ｄｘｓ＝Ｓ（Ｘｓ，Ｙｓ）が求まる。この値を用いてマスクパタン位置を補正すればよい。
【００５８】
あるいは、ディストーション誤差測定結果を用いてある一定の誤差値変化毎に領域を分類し、各領域毎に補正量を定めても良い。例えば、図３に模式的に示したように、誤差値０［ｎｍ］を中心にディストーション誤差１０［ｎｍ］毎にマスクパタン領域を分類し、例えば誤差が１５［ｎｍ］から２５［ｎｍ］となる領域内のマスクパタンに対してはマスクパタン位置を−１０［ｎｍ］補正するようにすれば良い。図３では、一例として２０［ｎｍ］角チップ内においてディストーション誤差−５［ｎｍ］以上＋５［ｎｍ］未満の第１の領域６１、誤差＋５［ｎｍ］以上＋１５［ｎｍ］未満の第２の領域６２、以下、第３の領域６３は誤差＋１５［ｎｍ］以上＋２５［ｎｍ］未満、第４の領域６４は誤差＋２５［ｎｍ］以上＋３５［ｎｍ］未満、第５の領域６５は−１５［ｎｍ］以上−５［ｎｍ］未満、第６の領域６６は誤差−２５［ｎｍ］以上−１５［ｎｍ］、第７の領域６７は誤差−３５［ｎｍ］以上−２５［ｎｍ］未満の領域を表している。各領域内の誤差値は、第１の領域６１では０［ｎｍ］、第２の領域６２、第３の領域６３、第４の領域６４、第５の領域６５、第６の領域６６、第７の領域６７ではそれぞれ＋１０［ｎｍ］、＋２０［ｎｍ］、＋３０［ｎｍ］、−１０［ｎｍ］、−２０［ｎｍ］、−３０［ｎｍ］を用いる。マスクパタン位置はこの値を用いて補正すればよい。この方法を誤差のｘ、ｙ両成分に対して行なえばよい。
【００５９】
また、より簡略な補正方法としては、図４に模式的に示したように測定点３３の周辺にある第１の補正領域３１を設定し、この領域内での補正値はこの測定点での測定値を用いてこれを補償するようにマスクパタン位置を補正してもよい。この場合、第１の補正領域３１と第２の補正領域３２との境界でマスクパタン位置補正値が不連続に変化する恐れがあるために、マスクパタン位置補正後のマスクにおいてマスクパタンが不連続になる恐れがある。しかし、通常上記ずれ量は数１０［ｎｍ］以下でマスク製造時にマスクパタンを描画する電子線描画装置等のパタン描画装置の解像限界以下の微小量であるので、連続したマスクパタンを形成することが可能である。
【００６０】
ところで、縮小投影露光法は基板上にマスクパタンを縮小して転写する方法である。このときのマスクパタン縮小比は現在は５：１が主流であるが、この他にも４：１あるいは２．５：１も用いられている。マスク上の寸法はマスクパタン縮小比の逆数倍になるので、例えば縮小比５：１の場合、基板上に０．４［μｍ］パタンを転写するためのマスクパタンの寸法は２．０［μｍ］となる。マスクパタン位置も同様に、ウエハ上の転写パタン位置を３０［ｎｍ］移動させるにはマスク上でマスクパタン位置を１５０［ｎｍ］移動させればよい。すなわち、ウエハ上寸法の縮小比の逆数倍の精度でマスクパタン位置を補正することが可能である。
【００６１】
さらに、マスクパタンを重ね合わせ転写する基板上にあらかじめ形成されたパタンが熱処理工程等のウエハ処理プロセスによりパタン位置歪みを生じている場合、歪み量を予め測定するか、あるいは計算により歪み量を予測する。得られた結果を用いて上記パタン位置歪みに応じてマスクパタン位置をさらに補正する工程３（図１）を行なう。
【００６２】
以上で述べたようにしてマスクパタン位置を補正してマスクを製造する工程４（図１）を行なう。さらに、製造したマスクと前記露光装置とを組み合わせて用いてマスクパタンを転写する工程５（図１）を行なうことにより、露光装置に依存した転写パタン位置の変位やウエハ歪みによる被転写パタン位置のずれを補正したパタン転写が可能となる。この結果、重ね合わせ誤差を小さく抑えることができる。
【００６３】
以上で述べた方法を用いて、各露光装置毎にマスクを製造してパタン転写に用いることが好ましい。しかし、同じパタンを転写するためのマスクを各露光装置毎に製造することは、コストの点からは好ましくない。そこで、ディストーション誤差の差が重ね合わせ許容誤差と比較して十分に小さい露光装置の組合せがある場合、一つのマスクをこれら露光装置間で共有することも可能である。このためには、図５に示したように、あらかじめディストーション誤差の差が許容範囲内におさまるような露光装置の組み合わせを求める工程５１、上記工程５１により求まった露光装置のディストーション誤差の平均値を求める工程５２、工程５２で求まったディストーション誤差平均値を用いてマスクパタン位置を補正したマスクを製造する工程５３、を処理すれば良い。このようにして製造したマスクを上記露光装置の組み合わせ内で用いてパタンを転写する工程５４を行なうことにより、重ね合わせ精度を許容値に抑えることが可能である。
【００６４】
重ね合わせ精度をさらに向上するためには、熱処理等のウエハプロセスにより生じたウエハ歪によるパタン歪も補正することが必要である。ウエハプロセスによりウエハ歪が生じていた場合、この歪量をあらかじめ測定しておくか、あるいは計算によりウエハ歪みをあらかじめ予測しておき、マスク製造時に得られた歪量に応じてマスクパタン位置を補正してやればよい。
【００６５】
ところで、光リソグラフィ法以外の実用化されているリソグラフィー法として、電子線直接描画法がある。電子線描画法の場合は、基板を搭載した基板ステージの移動と電子線の偏向により、パタンを描画あるいは転写する。下地パタン上に重ね合わせ描画する場合、例えば、描画チップの４すみに重ね合わせ描画用の位置マークパタンを配置しておき、これらの位置を検出して描画位置を補正してパタンを描画する。従って、下地の被重ね合わせパタンが投影露光装置で転写されていて、ディストーション誤差のために４すみのマークパタン位置が変位していたとすると、マークパタン位置誤差のために描画パタン位置も誤差を生じてしまう。
【００６６】
電子線描画装置側でこの誤差の補正を行なうことも可能であるが、各露光装置それぞれの誤差特性やウエハロット毎の補正値を電子線描画装置に入力しなければならない。これに対して、上記方法はマスクと露光装置との組み合わせを決めれば良いので、工程がより簡便である。
【００６７】
【実施例】
以下、本発明の実施例について説明する。
【００６８】
（実 施 例 １）
本実施例は、最小設計寸法０．２５［μｍ］、チップサイズ２０［ｍｍ］×２０［ｍｍ］の２５６メガビットＤＲＡＭ（ダイナミックランダムアクセスメモリ）級の半導体大規模集積回路の回路パタン加工工程について説明する。
【００６９】
本実施例では、ＮＡ＝０．５５のＫｒＦエキシマレーザステッパ（投影露光装置）〔縮小比５：１、露光波長２４８［ｎｍ］〕を用いてパタン転写した。
【００７０】
本実施例で用いた第１のＫｒＦエキシマレーザステッパの２０［ｎｍ］角露光チップ内でのディストーション誤差の測定結果を図６に模式的に示す。本実施例では、２０［ｎｍ］角チップ内の５行５列（５ｍｍピッチ）の格子点でのディストーション誤差を測定した。図では、ベクトルの向き及び長さで各格子点位置でのディストーション誤差測定値を模式的に示している。図７は各格子点位置でのディストーション誤差測定結果を示したものである。行及び列の番号は、各格子点位置をチップの左上側から数えた番号を示している。測定の結果、ウエハ面上２次元ｘｙ座標系において、露光フィールド内の位置２１（１行１列目の位置）においてｘ方向に−１０［ｎｍ］、ｙ方向に＋４４［ｎｍ］のディストーション誤差が測定された。
【００７１】
上記ディストーション誤差測定結果を用いてマスクパタン位置を補正した。例えば、位置２１に対応するマスク上の位置２１’に配置されたマスクパタン位置をｘ方向に＋５０［ｎｍ］、ｙ方向に−２２０［ｎｍ］シフトさせた。ディストーション誤差の測定点間位置では、隣接測定点のディストーション誤差測定値をスプライン関数を用いて補間して求めた誤差値を補正するようにマスクパタン位置を補正した。他の位置についても同様にマスクパタン位置を補正して、第１のマスクを製造した。
【００７２】
以上のようにして製造したマスクを用いて、第１の回路パタンを所定の工程を処理した基板上に転写した。所定の回路パタン加工工程を処理した後、第２のステッパを用いて第２の回路パタンを転写した。
【００７３】
本実施例で用いた第２のＫｒＦエキシマレーザステッパの２０［ｍｍ］角露光チップ内でのディストーション誤差の測定結果を図８に模式的に示す。本実施例では、２０［ｍｍ］角チップ内の５行５列（５［ｍｍ］ピッチ）の格子点でのディストーション誤差を測定した。図では、ベクトルの向き及び長さで各格子点位置でのディストーション誤差値を模式的に示している。
【００７４】
図９は各格子点位置でのディストーション誤差測定結果を示したものである。行及び列の番号は各格子点位置をチップの左上側から数えた番号を示している。
【００７５】
測定の結果、ウエハ面上２次元ｘｙ座標系において、露光フィールド内の位置３１（３行１列目の位置）においてｘ方向に−３４［ｎｍ］、ｙ方向に−２２［ｎｍ］のディストーション誤差が測定された。
【００７６】
以上の測定結果を用いてマスクパタン位置を補正した。例えば位置３１に対応するマスク上の位置３１’に配置されたマスクパタン位置をｘ方向に＋１７０［ｎｍ］、ｙ方向に−１１０［ｎｍ］シフトさせた。また、他のマスクパタン位置についても第１のマスクと同様に補正して、第２のマスクを製造した。
【００７７】
以上のようにして製造したマスクを用いて第２の回路パタンを第１の回路パタン上に重ね合わせて転写した。転写したパタンを走査型電子顕微鏡を用いて検査した結果、第１の回路パタンと第２の回路パタンの重ね合わせ誤差は所望の重ね合わせ誤差許容範囲１００［ｎｍ］以下であり、良好な重ね合わせ精度で第２の回路パタンを転写することができた。
【００７８】
本実施例で製造した大規模集積回路の一部分である、ＭＯＳトランジスタ部の一部分の断面構造を図１６に模式的に示す。本実施例で転写した第１のマスクは素子分離パタン７１を形成する工程で用い、また、第２のマスクはゲート配線パタン７２を形成する工程で用いた。
【００７９】
以上のようにしてパタン転写することにより、ディストーション誤差によるパタン配置誤差を抑えることができる。これにより、重ね合わせ誤差をより小さく抑えることが可能である。従って、固体素子の製造工程歩留まりを向上させることができる。
【００８０】
さらに、重ね合わせ誤差を小さくできることから、重ね合わせずれに起因した素子特性のばらつきも抑えることができるので、製造工程歩留まりを向上させるとともに高性能な固体素子の製造も可能である。
【００８１】
なお、図１６において、７０は基板、７３は絶縁膜、７４はソース領域、７５はドレイン領域である。
【００８２】
（実 施 例 ２）
本実施例は、最小設計寸法０．２５［μｍ］、チップサイズ２０［ｍｍ］×２０［ｍｍ］の２５６メガビットＤＲＡＭ（ダイナミックランダムアクセスメモリ）級の大規模集積回路の回路パタン加工工程について説明する。
【００８３】
本実施例では、ＮＡ＝０．５５のｋｒＦエキシマレーザステッパ（投影露光装置）〔縮小比５：１、露光波長２４８［ｎｍ］〕を用いて実施例１と同じ第１の回路パタンを所定の工程を処理した基板上に転写した。
【００８４】
本実施例で用いたＫｒＦエキシマレーザステッパの２０［ｍｍ］角露光チップ内でのディストーション誤差を測定した。本実施例では、第１の実施例と同様に２０［ｍｍ］角チップ内の５行５列（５［ｍｍ］ピッチ）の格子点でのディストーション誤差を測定した。
【００８５】
上記測定結果と、実施例１で用いたＫｒＦエキシマレーザステッパのディストーション誤差測定結果との差を図１０に示す。測定結果から、本実施例で用いたステッパと第１の実施例で用いた第１のステッパとのディストーション誤差の差は±３０［ｎｍ］以内で、許容重ね合わせ誤差１００［ｎｍ］の３分の１以下であった。そこで、本実施例では第１の実施例で製造した第１のマスクを用いて第１の回路パタンを転写した。
【００８６】
転写したパタンを走査型電子顕微鏡を用いて検査した結果、第１の回路パタンとそれ以前の工程で形成されていた下地パタンとの重ね合わせ誤差は所望の重ね合わせ誤差許容範囲１００［ｎｍ］以下であり、良好な重ね合わせ精度で第１の回路パタンを転写することができた。
【００８７】
（実 施 例 ３）
本実施例は、最小設計寸法０．２５［μｍ］、チップサイズ２０［ｍｍ］×２０［ｍｍ］の２５６メガビットＤＲＡＭ（ダイナミックランダムアクセスメモリ）級の大規模集積回路の回路パタン加工工程について説明する。
【００８８】
本実施例では、実施例１と同様にしてＮＡ＝０．５５のＫｒＦエキシマレーザステッパ（投影露光装置）〔縮小比５：１、露光波長２４８［ｎｍ］〕で用いる第１の回路パタン転写用のマスクを製造した。製造したマスクおよび上記ステッパを用いて、第１の回路パタンを所定の工程を処理した基板上に転写した。所定の回路パタン加工工程を処理した後、第２のステッパを用いて第２の回路パタンを転写した。
【００８９】
本実施例では、実施例１と同じ第２のＫｒＦエキシマレーザステッパを用いて第２の回路パタンを転写した。図９は各格子点位置でのディストーション誤差測定結果を示したものである。行及び列の番号は、各格子点位置をチップの左上側から数えた番号を示している。
【００９０】
測定の結果、ウエハ面上２次元ｘｙ座標系において、露光フィールド内の位置３１（３行１列目の位置）においてｘ方向に−３４［ｎｍ］、ｙ方向に−２２［ｎｍ］のディストーション誤差が測定された。
【００９１】
以上の測定結果を用いてマスクパタン位置を補正した。例えば、位置３１に対応するマスク上の位置３１’に配置されたマスクパタン位置をｘ方向に＋１７０［ｎｍ］、ｙ方向に−１１０［ｎｍ］シフトさせた。また、他のマスクパタン位置についても第１のマスクと同様に補正して、第２のマスクを製造した。
【００９２】
以上のようにして製造したマスクを用いて第２の回路パタンを第１の回路パタン上に重ね合わせて転写した。転写したパタンを走査型電子顕微鏡を用いて検査した結果、基板が歪んでいたために図１５に示したような重ね合わせ誤差が生じていることがわかった。図の横軸はチップ中心を原点としたｘｙ座標系のｘ軸上の位置を、縦軸は重ね合わせずれ量を表し、基板上のある一つの転写チップの測定結果を示している。また、図中の点線はこのチップ内の重ね合わせずれ量測定値の平均値を表している。図示した以外のチップでは、重ね合わせずれ量の平均値は−７０［ｎｍ］から＋４３［ｎｍ］の範囲でばらついていた。測定結果から、所望の重ね合わせ許容範囲±８０［ｎｍ］以下の重ね合わせずれ値が得られていないことがわかり、また、図１５に示されたように基板歪による重ね合わせずれ量は２０［ｎｍ］程度と重ね合わせずれ許容範囲と比較して大きかったので、重ね合わせ誤差測定結果を用いて第２のマスクのマスクパタン位置をさらに補正することとした。すなわち、図１５に示した重ね合わせ誤差を補正するように、ディストーション誤差測定結果を用いて補正したマスクパタン位置をさらに補正した。以上のようにしてパタン位置を補正したマスクパタンデータを用いて第２の回路パタン転写用の第２のマスクを再度製造した。
【００９３】
以上のようにして製造したマスクを用いて第２の回路パタンを第１の回路パタン上に重ね合わせ転写した。転写したパタンを走査型電子顕微鏡を用いて検査した結果、第１の回路パタンと第２の回路パタンの重ね合わせ誤差は所望の重ね合わせ誤差許容範囲±８０［ｎｍ］以下であり、良好な重ね合わせ精度で第２の回路パタンを転写することができた。
【００９４】
以上のようにしてパタン転写することにより、ディストーション誤差と基板歪によるパタン配置誤差を抑えることができる。これにより、重ね合わせ誤差をより小さく抑えることが可能である。従って、固体素子の製造工程歩留まりを向上させることができる。
【００９５】
さらに、重ね合わせ誤差を小さくできることから、重ね合わせずれに起因した素子特性のばらつきも抑えることができるので、製造工程歩留まりを向上させるとともに高性能な固体素子の製造も可能である。
【００９６】
（実 施 例 ４）
本実施例は、最小設計寸法０．３［μｍ］、チップサイズ２０［ｍｍ］×２０［ｍｍ］の６４メガビットＤＲＡＭ（ダイナミックランダムアクセスメモリ）級の大規模集積回路の回路パタン加工工程について説明する。
【００９７】
本実施例では、ＮＡ＝０．６３のｉ線ステッパ（投影露光装置）〔縮小比５：１、露光波長３６５［ｎｍ］〕を用いて第１の回路パタンを所定の工程を処理した基板上に転写した。
【００９８】
本実施例で用いたｉ線露光装置の２０［ｍｍ］角露光チップ内でのディストーション誤差の測定結果を図１１に示す。本実施例では、２０ｍｍ角チップ内の５行５列（５［ｍｍ］ピッチ）の格子点でのディストーション誤差を測定した。
【００９９】
以上の測定結果を用いてマスクパタン位置を補正してマスクを製造した。製造したマスクを用いて第１の回路パタンを転写した。
【０１００】
所定の回路パタン加工工程を処理した後、今度は電子線直接描画装置を用いて第２の回路パタンを転写した。重ね合わせ描画した際に用いた位置マークパタンの配置位置を図１２に模式的に示す。重ね合わせ描画用のマークパタン１１をチップ１０の４隅に配置した。このマークパタンは上記第１の回路パタン加工時に同時に形成されたものである。
【０１０１】
上記位置マークパタンを検出してパタン描画位置を補正しながら第２の回路パタンを描画、転写した。パタン転写後、第１の回路パタンと第２の回路パタンとの重ね合わせ誤差を走査型電子線顕微鏡を用いて測定したところ、重ね合わせ誤差が１００［ｎｍ］より大きくなっている部分は見られなかった。すなわち、２つのパタンの重ね合わせ誤差は、重ね合わせ誤差許容範囲の１００［ｎｍ］以下であり、所望の重ね合わせ精度が達成された。
【０１０２】
以上で述べたようにして大規模集積回路素子を製造することにより、所望の重ね合わせ精度で所定のパタンを加工することができるため、高い歩留まりで素子を製造することが可能である。
【０１０３】
（実 施 例 ５）
本実施例は、実施例１と同様にしてディストーション誤差を測定し、測定結果からスプライン関数を用いてスプライン曲面によりパタン転写領域内の任意の位置でのｘおよびｙ方向のディストーション誤差を求めた。これにより求めた値を誤差値１０［ｎｍ］毎の領域に分割し、各領域を誤差量を補正するようにマスクパタン位置を補正した。なお、領域を分割する際の誤差値の変化量は１０［ｎｍ］に限るものではないが、マスクパタン位置の補正精度を考慮すると、少なくとも固体素子製造工程での必要重ね合わせ精度以下としなければならない。
【０１０４】
本実施例におけるマスクパタン位置の補正方法を図３を用いて説明する。図３ではディストーション誤差値のｘ成分を表したが、ｙ成分についても同様に表すことができる。図３において、マスク上の領域６１はディストーション誤差値が−５［ｎｍ］以上５［ｎｍ］未満の領域、領域６２はディストーション誤差値が５以上１５［ｎｍ］未満の領域、以下領域６３、領域６４はそれぞれ１５以上２５［ｎｍ］未満、２５以上３５［ｎｍ］未満の領域を表している。同様に、領域６５は−１５以上−５［ｎｍ］未満、領域６６は−２５以上−１５［ｎｍ］未満、領域６７は−３５以上−２５［ｎｍ］未満の領域を表している。なお、本実施例で用いた露光装置では、露光領域内でのディストーション誤差のｘ成分は±３５［ｎｍ］未満であった。
【０１０５】
そこで、マスク製造時に領域６１内をマスクパタン描画する際、ｘ方向成分に対してマスクパタン位置の補正は行なわなかった。また、領域６２内を描画する場合、ｘ方向成分に対して−１０［ｎｍ］描画位置を補正した。他の領域についても同様に、各領域のディストーション誤差範囲の中間値を補正するようにマスクパタン描画位置を補正した。なお、ｙ方向成分に対しても同様に補正した。
【０１０６】
以上のようにして製造したマスクを用いて、第１の回路パタンを所定の工程を処理した基板上に転写した。所定の回路パタン加工工程を処理した後、今度は電子線直接描画装置を用いて第２の回路パタンを転写した。重ね合わせ描画した際に用いた位置マークパタンの配置位置は実施例３と同様に図１２に模式的に示した位置とした。また、重ね合わせ描画用のマークパタン１１をチップ１０の４隅に配置した。このマークパタン１１は上記第１の回路パタン加工時に同時に形成されたものである。
【０１０７】
上記位置マークパタンを検出してパタン描画位置を補正しながら第２の回路パタンを描画、転写した。パタン転写後、第１の回路パタンと第２の回路パタンとの重ね合わせ誤差を走査型電子線顕微鏡を用いて測定したところ、重ね合わせ誤差が１００［ｎｍ］より大きくなっている部分は見られなかった。すなわち、２つのパタンの重ね合わせ誤差は、重ね合わせ誤差許容範囲の１００［ｎｍ］以下であり、所望の重ね合わせ精度が達成された。
【０１０８】
以上で述べたようにして大規模集積回路素子を製造することにより、所望の重ね合わせ精度で所定のパタンを加工することができるため、高い歩留まりで素子を製造することが可能である。
【０１０９】
（実 施 例 ６）
本実施例は、最小設計寸法０．２５［μｍ］、チップサイズ２０［ｍｍ］×２０［ｍｍ］の２５６メガビットＤＲＡＭ（ダイナミックランダムアクセスメモリ）級の大規模集積回路の回路パタン加工工程について説明する。
【０１１０】
本実施例では、ＮＡ＝０．５５のＫｒＦエキシマレーザステッパ（投影露光装置）〔縮小比５：１、露光波長２４８［ｎｍ］〕を用いて第１の回路パタンを所定の工程を処理した基板上に転写した。所定の回路パタン加工工程を処理した後に、第２のステッパを用いて第２の回路パタンを転写した。
【０１１１】
本実施例では、実施例１と同じ第２のＫｒＦエキシマレーザステッパを用いて第２の回路パタンを転写した。図９は各格子点位置でのディストーション誤差測定結果を示したものである。行及列の番号は、各格子点位置をチップの左上側から数えた番号を示している。測定の結果、ウエハ面上２次元ｘｙ座標系において、例えば露光フィールド内の位置３１（３１行１列目の位置）においてｘ方向に−３４［ｎｍ］、ｙ方向に−２２［ｎｍ］のディストーション誤差が測定された。
【０１１２】
一方、基板上に形成された回路パタンの位置が素子製造工程により、図１７に示したようにチップ内で複雑に歪むことが事前の検討からわかった。ここで、図１７のグラフの横軸はチップ中心を原点とし、チップの各辺に平行な方向に２次元ｘｙ座標系をとったときのｙ軸上の位置を表わしている。また、縦軸は回路パタンを加工するために転写したレジストパタン位置からの、素子製造工程によるこの回路パタン位置のずれ量を表わしている。図は２０［ｍｍ］角のチップ８１内の１５［ｍｍ］角領域８２内にウエハ歪みを生じさせる材料を加工した回路パタンが配置されている場合を表わしている。
【０１１３】
図１８は、領域８２の中心位置をチップ８１の中心位置と一致させて配置し、領域８２の寸法を０［ｍｍ］角から２０［ｍｍ］角まで変化させたときの、２０［ｍｍ］角チップ８１のチップ寸法の伸縮率（チップ倍率変更率）を表わしたものである。図の横軸は、領域８２の寸法を表わしている。ここで、領域８２内の上記回路パタンはｘ方向に対して周期的なラインアンドスペースパタンと同様の回路パタンであった。図１８に示されるように、ｘ方向とｙ方向とでチップ８１の伸縮率の差が最大０．５［ｐｐｍ］程度生じていることもわかった。
【０１１４】
本実施例では、領域８２のサイズは１５［ｍｍ］角であったので、ｘ方向のチップ倍率誤差が−０．６［ｐｐｍ］、ｙ方向のチップ倍率誤差が−０．９［ｐｐｍ］生じるとして、マスクパタンのチップ寸法を補正した。なお、伸縮率−０．６［ｐｐｍ］はチップ上寸法１８［ｍｍ］に対して約１１［ｎｍ］の縮みに対応する。。さらに図１７に示したように、パタン位置がチップ内で変化するので、この位置ずれを補正するようにマスク上の回路パタン位置を補正した。さらに、上述のディストーション誤差を補正するように、実施例１と同様にしてマスクパタンデータをさにら補正した。
【０１１５】
以上のようにして補正したマスクパタンデータを用いて第２の回路パタン転写用の第２のマスクを製造した。
【０１１６】
製造したマスクを用いて第２の回路パタンを第１の回路パタン上に重ね合わせ転写した。転写したパタンを走査型電子顕微鏡を用いて検査した結果、第１の回路パタンと第２の回路パタンの重ね合わせ誤差は所望の重ね合わせ誤差許容範囲±８０［ｎｍ］以下であり、良好な重ね合わせ精度で第２の回路パタンを転写することができた。
【０１１７】
以上のようにしてパタン転写することにより、ディストーション誤差と基板歪みによるパタン配置誤差を抑えることができる。これにより、重ね合わせ誤差をより小さく抑えることが可能である。従って、固体素子の製造工程歩留まりを向上させることができる。
【０１１８】
さらに、重ね合わせ誤差を小さくできることから、重ね合わせずれに起因した素子特性のばらつきも抑えることができるので、製造工程歩留まりを向上させると共に高性能な固体素子の製造も可能である。
【０１１９】
なお、本発明の実施例で使用されるステッパ（投影露光装置）の構成の例を図１９に示す。
【０１２０】
図１９に示すように、光源１３１から発する光は、フライアイレンズ１３２、コンデンサレンズ１３３、ミラー１３４及びコンデンサレンズ１３３を介してマスク１３６を照明する。マスク１３６上には異物付着によるパターン転写不良を防止するためのペリクル１３７が設けられている。マスク１３６上に描かれたマスクパタンは、投影レンズ１３８を介して試料基板であるウエハ１３９上に投影される。なお、マスク１３６はマスク位置制御手段１４７で制御されたマスクステージ１４８上に載置され、その中心と投影レンズ１３８の光軸とは正確に位置合わせがなされている。ウエハ１３９は、試料台１４０上に真空吸着されている。試料台１４０は、投影レンズ１３８の光軸方向すなわちＺ方向（縦方向）に移動可能なＺステージ１４１上に載置され、さらにＸＹステージ１４２上に搭載されている。Ｚステージ１４１及びＸＹステージ１４２は、主制御系１４９からの制御命令に応じてそれぞれの駆動手段１１３、１１４によって駆動されるので、所望の露光位置に移動可能である。その位置はＺステージ１４１に固定されたミラー１４６の位置として、レーザ測長機１４５で正確にモニターされている。また、ウエハ１３９の表面位置は、通常の露光装置が有する焦点位置検出手段で計測される。計測結果に応じてＺステージ１４１を駆動させることにより、ウエハ１３９の表面は常に投影レンズ１３８の結像面と一致させることができる。
【０１２１】
以上、本発明者によってなされた発明を、上記実施例に基づき具体的に説明したが、本発明は、上記実施例に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。
【０１２２】
【発明の効果】
本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。
【０１２３】
以上本発明によれば、ディストーション誤差による重ね合わせ精度劣化を抑え、高重ね合わせ精度でパタンを転写することができる。
【図面の簡単な説明】
【図１】本発明によるマスク製造工程を示す工程図である。
【図２】本発明によるマスクパタン補正方法を示す模式図である。
【図３】本発明によるマスクパタン補正方法を示す模式図である。
【図４】本発明によるマスクパタン補正方法を示す模式図である。
【図５】本発明によるマスク製造工程を示す工程図である。
【図６】本発明の実施例１における第１のステッパのディストーション誤差測定結果を示す模式図。
【図７】本発明の実施例１における第１のステッパのディストーション誤差測定結果を示す図である。
【図８】実施例１における第２のステッパのディストーション誤差測定結果を示す模式図である。
【図９】本発明の実施例１における第２のステッパのディストーション誤差測定結果を示す図である。
【図１０】本発明の実施例２における２台のステッパのディストーション誤差の差の測定結果を示す図である。
【図１１】本発明の実施例３におけるステッパのディストーション誤差測定結果を示す図である。
【図１２】本発明の実施例３における位置マークパタンの配置を示す模式図である。
【図１３】本発明によるマスクパタン補正方法を示す模式図である。
【図１４】本発明によるマスクパタン補正方法を示す模式図である。
【図１５】本発明の実施例３において測定した重ね合わせ誤差測定結果を示す図である。
【図１６】大規模集積回路に塔載されるＭＯＳトランジスタ部の一部分の断面構造を示す模式図である。
【図１７】基板上に形成された回路パタンのパタン位置ずれ量を示す模式図である。
【図１８】基板上に形成されたチップの２次元方向の伸縮変化率を示す模式図である。
【図１９】本発明の実施例で使用されるステッパの構成の例を示す概略構成図である。
【符号の説明】
１…ディストーション誤差を測定する工程、２…上記結果を用いてマスクパタン位置を補正する工程、３…基板上のパタン位置歪に応じてマスクパタン位置を補正する工程、４…マスクを製造する工程、５…マスクパタンを転写する工程、
１０…チップ、１１…位置マーク、
２１−１，２１−２，２１−３，２１−４，２１−５，２１−６，２１−７，２１−８，２１−９，２２−１，２２−２，２２−３，２２−４，２２−５，２２−６，２２−７，２２−８，２２−９…測定値、２３…パタン位置、２４，２５…誤差値、
３１…第１の補正領域、３２…第２の補正領域、３３…測定点、４１…マスクパタン、
４２…図形、２−１，４２−２，４２−３，４２−４，４２−５…図形、４３…図形の中心位置、４３−１，４３−２，４３−３，４３−４，４３−５：図形の中心位置、
５１…露光装置の組み合せを求める工程、５２…上記露光装置群のディストーション誤差の平均を求める工程、５３…マスクパタン位置を補正したマスクを製造する工程、５４…製造したマスクを用いてパタン転写する工程、
６０…チップ、６１…第１の領域、６２…第２の領域、６３…第３の領域、６４…第４の領域、６５…第５の領域、６６…第６の領域、６７…第７の領域、
７０…基板、７１…素子分離パタン、７２…ゲート配線パタン、７３…絶縁膜、７４…ソース領域、７５…ドレイン領域である。[0001]
[Industrial applications]
The present invention relates to a technique for manufacturing an exposure mask used for forming a fine pattern in various solid-state devices such as a semiconductor device, a superconductor device, a magnetic device, and an optical integrated circuit device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, for forming a fine pattern in a solid-state device such as a large-scale semiconductor integrated circuit, a reduction projection exposure method, which is one of optical lithography methods, has been mainly used. This method is a method in which a mask pattern formed on a mask or a reticle (hereinafter, collectively referred to as a mask) is reduced and transferred onto a substrate using an imaging optical system.
[0003]
The minimum pattern size transferred onto the substrate using the above-described reduced projection exposure method is, for example, about 0.3 to 0.4 [μm] in a 64 Mbit dynamic random access memory (64 [M bit] DRAM) and 256 [M bits]. ] In the case of DRAM, the size has been reduced to 0.3 [μm] or less. In order to manufacture a solid-state device such as a semiconductor, it is necessary to form a plurality of patterns with high accuracy. The overlay error at this time is generally required to be one third to one fourth or less of the minimum processing size. Therefore, for high integration, it is necessary to make the minimum processing size finer and also to make the overlay accuracy higher.
[0004]
The main factors affecting the overlay accuracy in the optical lithography method include exposure apparatus accuracy, mask accuracy, and wafer process (wafer distortion, alignment exposure mark shape deterioration, resist coating unevenness, etc.).
[0005]
Among these, regarding the wafer process, there are, for example, distortion during heat treatment and wafer distortion due to superposition of materials having different coefficients of thermal expansion.
[0006]
Regarding the exposure apparatus accuracy, for example, recently, an exposure apparatus that can obtain a performance of 60 [nm] or less by an average of the overlay shift amount + 3σ (σ is the standard deviation of the overlay shift value distribution) has been announced. .
[0007]
However, the above values are the performances when overlay exposure is performed by each exposure apparatus alone, and the overlay exposure accuracy among a plurality of projection exposure apparatuses is further deteriorated due to differences between the apparatuses. A major cause of the deterioration of the overlay accuracy at this time is an error of the imaging optical system due to a manufacturing error.
[0008]
As an error of the imaging optical system that greatly affects the overlay accuracy, there is a distortion error (imaging characteristic including a magnification error and a distortion of a projection optical image). This appears as an error that the position of the projection optical image projected on the substrate via the imaging optical system is transferred to a position displaced from the position corresponding to the mask pattern to be originally transferred.
[0009]
In each projection exposure apparatus, for example, the shift amount is set to 50 [nm] or less so that the distortion error value is as small as possible and the shift amount from the ideal position is sufficiently smaller than the minimum pattern dimension to be transferred using this apparatus. The imaging optical system is adjusted to be as follows. However, since it is impossible to reduce the error to zero, the distortion error has a unique value different for each exposure apparatus. Also, the strain generated by the wafer process has a certain tendency in the direction of expansion and contraction.
[0010]
Here, when the overlay error between two projection exposure apparatuses is estimated, even if the distortion error of each exposure apparatus is 50 [nm] or less, the overlay error between the two exposure apparatuses is an error. There is a possibility that it will be doubled to 100 [nm]. Further, the wafer distortion due to the wafer process also increases as the wafer size increases, and there is a possibility that an overlay error of several tens [nm] or more may occur. Therefore, it can be seen that the overlay error due to the distortion error has a very large value with respect to the above overlay accuracy.
[0011]
In order to suppress such an alignment error due to a distortion error between the projection exposure apparatuses, a method of using only a specific projection exposure apparatus for each lot has conventionally been used. As another method, a combination of projection exposure apparatuses is determined in advance such that an overlay error due to a distortion error falls within an allowable range, and a certain lot is processed using only the projection exposure apparatus in this combination. There is also a method.
[0012]
In addition, as a method of correcting the wafer distortion caused by the wafer process, the wafer distortion caused by the wafer process, specifically, the expansion and contraction of the chip array and the expansion and contraction of the chip size are measured in advance, or an exposure apparatus is used during the overlay exposure. There is a method in which distortion is measured, and these errors are corrected at the time of overlay exposure to transfer a pattern.
[0013]
[Problems to be solved by the invention]
In order to increase the overlay accuracy, it is desirable to minimize the distortion error of the imaging optical system and the wafer distortion due to the wafer process. However, it is impossible to make them zero due to manufacturing errors and the like. Normally, the imaging optical system is adjusted so that the distortion error over the entire exposure field falls within a certain allowable value range. The allowable value range at this time is smaller than the minimum pattern dimension to be transferred using this imaging optical system or the allowable overlay error in the solid-state element manufacturing process, for example, 100 nm or less, or 50 nm or less. Is required to be a very small value.
[0014]
The above-described distortion error has a unique value for each projection exposure apparatus. For this reason, the overlay error in the exposure chip between the plurality of projection exposure apparatuses may be deteriorated by the difference between the distortion errors between the apparatuses.
[0015]
For example, it is assumed that one exposure apparatus having a distortion error at a certain position in the exposure chip is 30 [nm] toward the center of the exposure chip and 50 [nm] is opposite to the center of the exposure chip in another exposure apparatus. . Regarding the overlay error between the two exposure apparatuses, even if the overlay error at another position in the exposure chip is 0 [nm], an error occurs at this position at 80 [nm]. Thus, it can be seen that the distortion error may be a major factor in the degradation of the overlay accuracy. Therefore, in order to improve the overlay accuracy, it is important to reduce the difference in distortion error between apparatuses.
[0016]
However, it is generally difficult to arbitrarily adjust only the distortion error of the imaging optical system. Therefore, in the processing of a certain lot, a method using only a specific exposure apparatus, or a combination of the exposure apparatuses in which the overlay error due to the difference of the distortion error is smaller, is determined. There is a method using only the exposure apparatus in the combination.
[0017]
By using these methods, it is possible to further reduce the overlay error. However, it is conceivable that the number of exposure apparatuses in the combination is insufficient or there is no appropriate combination in consideration of the actual apparatus use situation. In such a case, there has been a problem that a delay occurs in a device manufacturing process or a necessary overlay accuracy cannot be obtained. Also, since the projection exposure equipment to be used is determined for each lot, if the exposure work is stopped due to a problem with the exposure equipment, or if multiple lots have to be processed simultaneously depending on the manufacturing process, lot processing For example, there is a problem that the time required for manufacturing the element increases when the delay is caused, and the manufacturing cost increases as a result. Further, for example, when a projection exposure apparatus and an electron beam lithography apparatus are used in combination, there is a problem that the overlay accuracy is deteriorated due to a distortion error of the projection exposure apparatus.
[0018]
Further, regarding the wafer distortion, the expansion and contraction of the chip array can be corrected using different correction values in the X and Y directions by controlling the movement amount of the wafer stage. Since only the magnification error of the entire chip can be corrected, there is also a problem that correction cannot be performed when a non-linear wafer distortion occurs, for example, depending on the pattern to be superimposed.
[0019]
An object of the present invention is to provide a technique capable of suppressing deterioration of overlay accuracy due to distortion error and transferring a pattern with high overlay accuracy.
[0020]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0021]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0022]
The above problem is caused by distortion of an imaging optical system used in a mask pattern transfer method for transferring a mask pattern onto a substrate by projecting and exposing a mask pattern formed on a mask onto the substrate through an imaging optical system. A mask manufacturing method including a step of measuring an error, and a step of manufacturing a mask in which a mask pattern position is adjusted so as to correct the distortion error obtained by the measurement, and further obtaining a distortion error measurement result as a method of correcting the distortion. Is solved by a mask manufacturing method in which a mask pattern position is corrected using a value obtained by interpolating using, for example, a spline function using a value obtained by interpolating.
[0023]
[Action]
As described above, the distortion or distortion error of the substrate onto which the pattern is transferred can be a major factor in degrading the overlay accuracy. Therefore, it is important to reduce the influence of these errors in order to improve the accuracy. To suppress the shift of the transfer pattern position due to the distortion error, the mask pattern position may be corrected in advance so that the shift of the transfer pattern position is reduced. In addition, the amount of non-linear distortion of the substrate on which the pattern is to be superimposed and transferred is measured in advance, or immediately before the overlay exposure, or the amount of distortion of the substrate is predicted by calculation, and the mask pattern position is determined based on these results. What is necessary is just to correct further. As a result, it is possible to reduce the amount of misalignment between the transfer pattern position on the substrate and the mask pattern projection optical image, and as a result, the overlay error can be further reduced.
[0024]
An example of a process for manufacturing a mask with a corrected mask pattern position will be described with reference to FIG. First, step 1 for measuring a distortion error in an exposure chip of an exposure apparatus to be processed is performed. As a method for measuring the distortion error, various known methods can be used.
[0025]
For example, a substrate coated with a photosensitive resin is placed on a precise substrate stage having a position measuring means such as a laser interferometer, and a measurement reference pattern image projected at the center of an exposure field corresponding to the optical axis of the imaging optical system. Is exposed to a number of measurement positions on the substrate by driving the substrate stage in a stepping manner. Next, a large number of measurement reference pattern images are collectively exposed so as to be close to the measurement reference pattern at each measurement position in the exposure field, and after development processing, measurement is performed on each measurement position in the exposure field with respect to the measurement reference pattern position. There is a method of calculating the relative position of the reference pattern for use, and using the difference between the relative positions as a distortion error. Alternatively, a measuring method as described in JP-A-6-176999 can be used.
[0026]
Next, using the distortion error measurement value obtained by the above measurement, a step 2 of manufacturing a mask whose mask pattern position is corrected so as to compensate for the displacement of the transfer pattern position caused by the distortion error is performed. Here, it is impossible to measure the distortion error for every position in the exposure chip. Therefore, the value obtained from the peripheral distortion error measurement value may be used for correcting the mask pattern position at a portion other than the distortion error measurement point.
[0027]
For example, at a position between distortion error measurement points, the mask pattern position may be corrected so as to correct a value obtained by interpolating the measured value. There are various interpolation methods. For example, in the three-dimensional space, the x and y axes are made to coincide with the x and y axes on the substrate surface, and the z axis is considered as an x-direction error or a y-direction error of the distortion. A curved surface or a polyhedral surface passing through discrete points in a three-dimensional space, which is a value, may be obtained, and an error value z with respect to arbitrary x and y values may be obtained using this. As a method of expressing the curved surface or the polyhedral surface, for example, there is a method of expressing the surface by a polyhedral surface as shown in FIG. In the figure, reference numerals 21-1 to 21-9 denote distortion error measurement points, and reference numerals 22-1 to 22-9 three-dimensionally display the x component of the distortion error measurement value at each measurement point. The z-coordinate value of the point 24 on the polyhedron surface with respect to the position 23 may be used as an error value of this position, and the mask pattern position may be adjusted so as to correct this error.
[0028]
Here, the mask pattern to be subjected to position correction is determined by a method using an error value with respect to the center position or the position of the center of gravity of the mask pattern. As shown schematically in FIG. Is divided into a graphic 42 and a graphic 42-1 to 42-5 having a size of, and a method using an error value with respect to the center position 43, 43-1 to 43-5 or the position of the center of gravity of each graphic, an error obtained from a polyhedral surface There is a method in which an error value is displayed as a contour line using a value, and in a region divided by the contour line, an average value of error values serving as a boundary of the region is used as an error value of this region.
[0029]
Alternatively, for example, as shown schematically in FIG. 13, the z-axis direction is an error value with respect to the x and y coordinates, and the error value is three-dimensionally expressed using a spline curved surface using a spline function. There is also a method of correcting the error value by using the following method. In FIG. 13, reference numerals 21-1 to 21-9 denote distortion error measurement points, and reference numerals 22-1 to 22-9 three-dimensionally display the x component of the distortion error measurement value at each measurement point. The z-coordinate value of the point 25 on the curved surface with respect to the position 23 may be used as an error value of this position, and the mask pattern position may be adjusted so as to correct this error.
[0030]
In general, by interpolating measurement data using a cubic spline function, a distortion error measurement result at an arbitrary position in the exposure field plane can be represented with practically sufficient accuracy. In addition, since a curved surface or a polyhedral surface in which the measurement error of the distortion error is smoothed can be obtained by using the spline function, the error can be corrected more smoothly.
[0031]
Here, an example of a method of correcting a measurement result using a spline function will be briefly described. Hereinafter, a method of correcting the x component: Dx of the distortion error (Dx, Dy) will be described, but the same applies to the y component: Dy. The x component Dx (i, j) of the distortion error is represented by grid points (xi, yi) (i = 0,1,2, ..., I; j = 0,1,2, ...,) in the region within the exposure chip. , J). Further, it is assumed that the exposure chip area is defined by a = x0 ≦ x ≦ xI = b and c = y0 ≦ y ≦ yJ = d. At this time, an (m-1) -order spline function S (x, y) passing through the measured value is obtained. In practice, a measured value can be sufficiently interpolated and represented by a cubic spline function, so that a cubic spline function is determined here. The internal nodes in the x direction are
[0032]
(Equation 1)

[0033]
The internal node in the y direction is
[0034]
(Equation 2)

[0035]
And At this time, in the x direction,
[0036]
(Equation 3)

[0037]
In the y direction,
[0038]
(Equation 4)

[0039]
Suppose that The spline function S (x, y) can be represented using a set of basis functions. This basis function can be formed by a tensor product of one-dimensional basis functions. 2m additional nodes in the x direction to create the required basis functions
[0040]
(Equation 5)

[0041]
Are similarly added in the y direction by 2m additional nodes.
[0042]
(Equation 6)

[0043]
Are introduced respectively. Thus, the spline function S (x, y) becomes
[0044]
(Equation 7)

[0045]
Can be expressed as Here, Nmi (x) and Nmj (y) are
[0046]
(Equation 8)

[0047]
And a normalized m-th order ((m−1) th order) B-spline (or fundamental spline). The value of the B-spline can be calculated by the following recurrence formula.
[0048]
(Equation 9)

[0049]
(Equation 10)

[0050]
In order for the equation (7) to be an interpolation function of the given measured value,
[0051]
(Equation 11)

[0052]
It should just be. Equation (11) is a system of linear equations with Cij as an unknown, and has a unique solution under the conditions of Equations (3), (4) and (5). By solving (Equation 11), S (x, y) can be obtained.
[0053]
The calculation of the interpolation value Dxs at a certain position (Xs, Ys) may be performed as follows. First, a small region R in which (Xs, Ys) enters,
[0054]
(Equation 12)

[0055]
Find out. Then, from the locality of the B-spline,
[0056]
(Equation 13)

[0057]
As a result, the interpolation value Dxs = S (Xs, Ys) is obtained. The mask pattern position may be corrected using this value.
[0058]
Alternatively, regions may be classified for each certain error value change using the distortion error measurement result, and the correction amount may be determined for each region. For example, as schematically shown in FIG. 3, the mask pattern area is classified for each distortion error 10 [nm] centered on the error value 0 [nm], and the error is, for example, 15 [nm] to 25 [nm]. It is sufficient to correct the mask pattern position by -10 [nm] for the mask pattern in the region. In FIG. 3, as an example, a first region 61 having a distortion error of not less than -5 [nm] and less than +5 [nm] and a second region having an error of not less than +5 [nm] and less than +15 [nm] within a 20 [nm] square chip. 62, hereinafter, the third region 63 has an error of not less than +15 [nm] and less than +25 [nm], the fourth region 64 has an error of not less than +25 [nm] and less than +35 [nm], and the fifth region 65 has a difference of -15 [nm]. ] To less than -5 [nm], the sixth region 66 is a region having an error of -25 [nm] or more to -15 [nm], and the seventh region 67 is a region having an error of -35 [nm] to less than -25 [nm]. Represents. The error value in each area is 0 [nm] in the first area 61, the second area 62, the third area 63, the fourth area 64, the fifth area 65, the sixth area 66, In the region 67 of No. 7, +10 [nm], +20 [nm], +30 [nm], -10 [nm], -20 [nm], and -30 [nm] are used, respectively. The mask pattern position may be corrected using this value. This method may be performed for both the x and y components of the error.
[0059]
Further, as a simpler correction method, a first correction area 31 around the measurement point 33 is set as schematically shown in FIG. 4, and the correction value in this area is set at this measurement point. The mask pattern position may be corrected using the measured value to compensate for this. In this case, since the mask pattern position correction value may change discontinuously at the boundary between the first correction region 31 and the second correction region 32, the mask pattern after the mask pattern position correction has a discontinuous mask pattern. Might be. However, since the above-mentioned shift amount is usually several tens [nm] or less, which is a minute amount equal to or less than the resolution limit of a pattern writing apparatus such as an electron beam writing apparatus for writing a mask pattern during mask manufacturing, a continuous mask pattern is formed. It is possible.
[0060]
Incidentally, the reduced projection exposure method is a method of transferring a mask pattern on a substrate by reducing the pattern. At this time, the mask pattern reduction ratio is mainly 5: 1 at present, but 4: 1 or 2.5: 1 is also used. Since the dimension on the mask is the reciprocal multiple of the mask pattern reduction ratio, for example, when the reduction ratio is 5: 1, the dimension of the mask pattern for transferring the 0.4 [μm] pattern onto the substrate is 2.0 [ μm]. Similarly, in order to move the transfer pattern position on the wafer by 30 [nm], the mask pattern position may be moved by 150 [nm] on the mask. That is, it is possible to correct the mask pattern position with an accuracy that is an inverse multiple of the reduction ratio of the on-wafer dimension.
[0061]
Furthermore, if the pattern formed in advance on the substrate on which the mask pattern is superimposed and transferred has a pattern position distortion due to a wafer processing process such as a heat treatment process, the distortion amount is measured in advance, or the distortion amount is predicted by calculation. I do. The step 3 (FIG. 1) of further correcting the mask pattern position according to the pattern position distortion is performed using the obtained result.
[0062]
Step 4 (FIG. 1) of manufacturing a mask by correcting the mask pattern position as described above is performed. Further, by performing the step 5 (FIG. 1) of transferring the mask pattern using the manufactured mask in combination with the exposure apparatus, displacement of the transfer pattern position depending on the exposure apparatus and movement of the transfer pattern position due to wafer distortion are performed. Pattern transfer in which deviation has been corrected becomes possible. As a result, the overlay error can be kept small.
[0063]
It is preferable that a mask be manufactured for each exposure apparatus using the method described above and used for pattern transfer. However, it is not preferable in terms of cost to manufacture a mask for transferring the same pattern for each exposure apparatus. Therefore, when there is a combination of exposure apparatuses in which the difference between the distortion errors is sufficiently smaller than the overlay tolerance, it is possible to share one mask between these exposure apparatuses. For this purpose, as shown in FIG. 5, a step 51 for obtaining a combination of exposure apparatuses in which the difference between the distortion errors falls within an allowable range in advance, and an average value of the distortion errors of the exposure apparatuses obtained in the above step 51 are calculated. The process 52 for obtaining the mask and the process 53 for manufacturing a mask in which the mask pattern position is corrected using the average value of the distortion errors obtained in the process 52 may be performed. By performing the step 54 of transferring a pattern using the mask thus manufactured within the combination of the above-described exposure apparatuses, the overlay accuracy can be suppressed to an allowable value.
[0064]
In order to further improve the overlay accuracy, it is necessary to correct pattern distortion caused by wafer distortion caused by a wafer process such as heat treatment. If wafer distortion has occurred due to the wafer process, measure this distortion amount in advance, or predict the wafer distortion by calculation in advance, and correct the mask pattern position according to the distortion amount obtained at the time of mask manufacturing. Do it.
[0065]
By the way, as a lithography method put to practical use other than the optical lithography method, there is an electron beam direct writing method. In the case of the electron beam drawing method, a pattern is drawn or transferred by moving a substrate stage on which a substrate is mounted and deflecting an electron beam. In the case of overlay drawing on a base pattern, for example, position mark patterns for overlay drawing are arranged at four corners of the drawing chip, and these positions are detected to correct the drawing position to draw the pattern. Therefore, if the overlay pattern of the base is transferred by the projection exposure apparatus and the mark pattern positions in all four corners are displaced due to a distortion error, the drawing pattern position also causes an error due to the mark pattern position error. Would.
[0066]
It is possible to correct this error on the electron beam lithography apparatus side, but the error characteristics of each exposure apparatus and the correction value for each wafer lot must be input to the electron beam lithography apparatus. On the other hand, in the above method, the combination of the mask and the exposure apparatus may be determined, so that the process is simpler.
[0067]
【Example】
Hereinafter, examples of the present invention will be described.
[0068]
(Example 1)
The present embodiment describes a circuit pattern processing process of a 256 megabit DRAM (dynamic random access memory) class semiconductor large-scale integrated circuit having a minimum design dimension of 0.25 [μm] and a chip size of 20 [mm] × 20 [mm]. I do.
[0069]
In the present embodiment, pattern transfer was performed using a KrF excimer laser stepper (projection exposure apparatus) with NA = 0.55 [reduction ratio 5: 1, exposure wavelength 248 [nm]].
[0070]
FIG. 6 schematically shows a measurement result of a distortion error in a 20 [nm] square exposure chip of the first KrF excimer laser stepper used in this embodiment. In this example, distortion errors were measured at grid points of 5 rows and 5 columns (5 mm pitch) in a 20 [nm] square chip. In the figure, the distortion error measurement value at each lattice point position is schematically shown by the direction and length of the vector. FIG. 7 shows the distortion error measurement results at each lattice point position. The row and column numbers indicate the numbers obtained by counting each grid point position from the upper left of the chip. As a result of the measurement, in the two-dimensional xy coordinate system on the wafer surface, a distortion error of −10 [nm] in the x direction and +44 [nm] in the y direction at the position 21 (the position of the first row and the first column) in the exposure field. Measured.
[0071]
The mask pattern position was corrected using the distortion error measurement result. For example, the mask pattern position arranged at the position 21 ′ on the mask corresponding to the position 21 is shifted by +50 [nm] in the x direction and −220 [nm] in the y direction. At the position between the measurement points of the distortion error, the mask pattern position was corrected so as to correct the error value obtained by interpolating the distortion error measurement values of the adjacent measurement points using a spline function. The mask pattern positions were similarly corrected for other positions, and the first mask was manufactured.
[0072]
Using the mask manufactured as described above, the first circuit pattern was transferred onto a substrate that had been subjected to a predetermined process. After performing a predetermined circuit pattern processing step, the second circuit pattern was transferred using a second stepper.
[0073]
FIG. 8 schematically shows a measurement result of a distortion error in a 20 mm square exposure chip of the second KrF excimer laser stepper used in this embodiment. In this example, the distortion error was measured at grid points of 5 rows and 5 columns (5 [mm] pitch) in a 20 [mm] square chip. In the figure, the distortion error value at each grid point position is schematically shown by the direction and length of the vector.
[0074]
FIG. 9 shows a distortion error measurement result at each lattice point position. The row and column numbers indicate the numbers obtained by counting each grid point position from the upper left of the chip.
[0075]
As a result of the measurement, in the two-dimensional xy coordinate system on the wafer surface, a distortion error of −34 [nm] in the x direction and −22 [nm] in the y direction at the position 31 (the position of the third row and the first column) in the exposure field. Was measured.
[0076]
The mask pattern position was corrected using the above measurement results. For example, the mask pattern position arranged at the position 31 'on the mask corresponding to the position 31 is shifted by +170 [nm] in the x direction and -110 [nm] in the y direction. Further, other mask pattern positions were corrected in the same manner as the first mask, and the second mask was manufactured.
[0077]
The second circuit pattern was superimposed on the first circuit pattern and transferred using the mask manufactured as described above. As a result of inspecting the transferred pattern using a scanning electron microscope, the overlay error between the first circuit pattern and the second circuit pattern was within a desired overlay error allowable range of 100 [nm] or less. The second circuit pattern could be transferred with high accuracy.
[0078]
FIG. 16 schematically shows a cross-sectional structure of a part of the MOS transistor portion, which is a part of the large-scale integrated circuit manufactured in this embodiment. The first mask transferred in the present embodiment was used in the step of forming the element isolation pattern 71, and the second mask was used in the step of forming the gate wiring pattern 72.
[0079]
By performing pattern transfer as described above, pattern arrangement errors due to distortion errors can be suppressed. As a result, it is possible to reduce the overlay error. Therefore, the production process yield of the solid state device can be improved.
[0080]
Further, since overlay errors can be reduced, variations in device characteristics due to overlay deviation can be suppressed, so that the yield of the manufacturing process can be improved and a high-performance solid-state device can be manufactured.
[0081]
In FIG. 16, reference numeral 70 denotes a substrate, 73 denotes an insulating film, 74 denotes a source region, and 75 denotes a drain region.
[0082]
(Example 2)
This embodiment describes a circuit pattern processing step of a 256-Mbit DRAM (dynamic random access memory) class large-scale integrated circuit having a minimum design dimension of 0.25 [μm] and a chip size of 20 [mm] × 20 [mm]. .
[0083]
In the present embodiment, the same first circuit pattern as that of the first embodiment is formed by using a krF excimer laser stepper (projection exposure apparatus) with NA = 0.55 [reduction ratio 5: 1, exposure wavelength 248 [nm]]. The process was transferred onto the processed substrate.
[0084]
The distortion error in the 20 mm square exposure chip of the KrF excimer laser stepper used in this example was measured. In the present embodiment, a distortion error was measured at grid points of 5 rows and 5 columns (5 [mm] pitch) in a 20 [mm] square chip, as in the first embodiment.
[0085]
FIG. 10 shows the difference between the above measurement result and the distortion error measurement result of the KrF excimer laser stepper used in Example 1. From the measurement results, the difference of the distortion error between the stepper used in the present embodiment and the first stepper used in the first embodiment is within ± 30 [nm], and 3 minutes of the allowable overlay error 100 [nm]. Of 1 or less. Therefore, in the present embodiment, the first circuit pattern is transferred using the first mask manufactured in the first embodiment.
[0086]
As a result of inspecting the transferred pattern by using a scanning electron microscope, the overlay error between the first circuit pattern and the base pattern formed in the previous process is less than a desired overlay error allowable range of 100 [nm] or less. Thus, the first circuit pattern could be transferred with good overlay accuracy.
[0087]
(Example 3)
This embodiment describes a circuit pattern processing step of a 256-Mbit DRAM (dynamic random access memory) class large-scale integrated circuit having a minimum design dimension of 0.25 [μm] and a chip size of 20 [mm] × 20 [mm]. .
[0088]
In the present embodiment, in the same manner as in the first embodiment, the first circuit pattern transfer for use in a KrF excimer laser stepper (projection exposure apparatus) with NA = 0.55 [reduction ratio 5: 1, exposure wavelength 248 [nm]] Was manufactured. Using the manufactured mask and the stepper, the first circuit pattern was transferred onto a substrate that had been subjected to a predetermined process. After performing a predetermined circuit pattern processing step, the second circuit pattern was transferred using a second stepper.
[0089]
In the present embodiment, the second circuit pattern was transferred using the same second KrF excimer laser stepper as in the first embodiment. FIG. 9 shows a distortion error measurement result at each lattice point position. The row and column numbers indicate the numbers obtained by counting each grid point position from the upper left of the chip.
[0090]
As a result of the measurement, in the two-dimensional xy coordinate system on the wafer surface, a distortion error of −34 [nm] in the x direction and −22 [nm] in the y direction at the position 31 (the position of the third row and the first column) in the exposure field. Was measured.
[0091]
The mask pattern position was corrected using the above measurement results. For example, the mask pattern position arranged at the position 31 ′ on the mask corresponding to the position 31 is shifted by +170 [nm] in the x direction and −110 [nm] in the y direction. Further, other mask pattern positions were corrected in the same manner as the first mask, and the second mask was manufactured.
[0092]
The second circuit pattern was superimposed on the first circuit pattern and transferred using the mask manufactured as described above. Inspection of the transferred pattern by using a scanning electron microscope revealed that the substrate was distorted, causing an overlay error as shown in FIG. The horizontal axis in the figure indicates the position on the x-axis of the xy coordinate system with the chip center as the origin, and the vertical axis indicates the amount of misalignment, and shows the measurement result of one transfer chip on the substrate. The dotted line in the figure represents the average value of the measured values of the overlay displacement in the chip. In the chips other than those shown in the figure, the average value of the amount of misalignment varied from -70 [nm] to +43 [nm]. From the measurement results, it was found that an overlay deviation value of less than the desired overlay tolerance of ± 80 [nm] was not obtained, and as shown in FIG. nm], which is larger than the overlay deviation allowable range, so that the mask pattern position of the second mask is further corrected using the overlay error measurement result. That is, the mask pattern position corrected using the distortion error measurement result was further corrected so as to correct the overlay error shown in FIG. A second mask for transferring a second circuit pattern was manufactured again using the mask pattern data whose pattern position was corrected as described above.
[0093]
Using the mask manufactured as described above, the second circuit pattern was superimposed and transferred onto the first circuit pattern. As a result of inspecting the transferred pattern using a scanning electron microscope, the overlay error between the first circuit pattern and the second circuit pattern was within a desired overlay error allowable range ± 80 [nm] or less. The second circuit pattern could be transferred with alignment accuracy.
[0094]
By performing the pattern transfer as described above, it is possible to suppress a pattern arrangement error due to a distortion error and a substrate distortion. As a result, it is possible to reduce the overlay error. Therefore, the production process yield of the solid state device can be improved.
[0095]
Further, since overlay errors can be reduced, variations in device characteristics due to overlay deviation can be suppressed, so that the yield of the manufacturing process can be improved and a high-performance solid-state device can be manufactured.
[0096]
(Example 4)
This embodiment describes a circuit pattern processing step of a large-scale integrated circuit of a 64-megabit DRAM (dynamic random access memory) class having a minimum design dimension of 0.3 [μm] and a chip size of 20 [mm] × 20 [mm]. .
[0097]
In this embodiment, the first circuit pattern is formed on a substrate that has been subjected to a predetermined process by using an i-line stepper (projection exposure apparatus) with NA = 0.63 [reduction ratio 5: 1, exposure wavelength 365 [nm]]. Transferred to
[0098]
FIG. 11 shows a measurement result of a distortion error in a 20 mm square exposure chip of the i-line exposure apparatus used in this embodiment. In the present example, distortion errors were measured at grid points of 5 rows and 5 columns (5 [mm] pitch) in a 20 mm square chip.
[0099]
A mask was manufactured by correcting the mask pattern position using the above measurement results. The first circuit pattern was transferred using the manufactured mask.
[0100]
After processing the predetermined circuit pattern processing step, the second circuit pattern was transferred using an electron beam direct drawing apparatus. FIG. 12 schematically shows the arrangement positions of the position mark patterns used for the overlay drawing. Mark patterns 11 for overlay drawing were arranged at four corners of the chip 10. This mark pattern is formed simultaneously with the processing of the first circuit pattern.
[0101]
The second circuit pattern was drawn and transferred while correcting the pattern drawing position by detecting the position mark pattern. After the pattern transfer, when the overlay error between the first circuit pattern and the second circuit pattern was measured using a scanning electron microscope, it was found that the overlay error was larger than 100 [nm]. Did not. That is, the overlay error between the two patterns was 100 nm or less, which is the allowable overlay error range, and the desired overlay accuracy was achieved.
[0102]
By manufacturing a large-scale integrated circuit device as described above, a predetermined pattern can be processed with a desired overlay accuracy, so that the device can be manufactured with a high yield.
[0103]
(Example 5)
In this embodiment, the distortion error was measured in the same manner as in the first embodiment, and the distortion error in the x and y directions at an arbitrary position in the pattern transfer area was obtained from the measurement result by using a spline function using a spline curved surface. The value thus obtained was divided into regions for each error value of 10 [nm], and the mask pattern position was corrected so that each region was corrected for the amount of error. Note that the amount of change in the error value when dividing the region is not limited to 10 [nm]. However, considering the correction accuracy of the mask pattern position, it is necessary to set it at least equal to or less than the required overlay accuracy in the solid-state device manufacturing process. No.
[0104]
A method of correcting a mask pattern position in the present embodiment will be described with reference to FIG. FIG. 3 shows the x component of the distortion error value, but the y component can be similarly expressed. 3, a region 61 on the mask has a distortion error value of -5 [nm] or more and less than 5 [nm], and a region 62 has a distortion error value of 5 or more and less than 15 [nm], a region 63 or less. Numerals 64 denote regions of 15 to less than 25 [nm] and 25 to 35 [nm], respectively. Similarly, the region 65 represents a region from -15 to less than -5 [nm], the region 66 represents a region from -25 to less than -15 [nm], and the region 67 represents a region from -35 to less than -25 [nm]. In the exposure apparatus used in this example, the x component of the distortion error in the exposure area was less than ± 35 [nm].
[0105]
Therefore, when the mask pattern is drawn in the region 61 during the manufacture of the mask, the mask pattern position is not corrected for the x-direction component. In addition, when drawing in the area 62, the drawing position of −10 [nm] was corrected for the x-direction component. Similarly, for other regions, the mask pattern drawing position was corrected so as to correct the intermediate value of the distortion error range of each region. Note that the correction was similarly made for the y direction component.
[0106]
Using the mask manufactured as described above, the first circuit pattern was transferred onto a substrate that had been subjected to a predetermined process. After processing the predetermined circuit pattern processing step, the second circuit pattern was transferred using an electron beam direct drawing apparatus. The position of the position mark pattern used for the superimposed drawing is the position schematically shown in FIG. In addition, mark patterns 11 for overlay drawing are arranged at four corners of the chip 10. The mark pattern 11 is formed at the same time as the first circuit pattern processing.
[0107]
The second circuit pattern was drawn and transferred while correcting the pattern drawing position by detecting the position mark pattern. After the pattern transfer, when the overlay error between the first circuit pattern and the second circuit pattern was measured using a scanning electron microscope, it was found that the overlay error was larger than 100 [nm]. Did not. That is, the overlay error between the two patterns was 100 nm or less, which is the allowable overlay error range, and the desired overlay accuracy was achieved.
[0108]
By manufacturing a large-scale integrated circuit device as described above, a predetermined pattern can be processed with a desired overlay accuracy, so that the device can be manufactured with a high yield.
[0109]
(Example 6)
This embodiment describes a circuit pattern processing step of a 256-Mbit DRAM (dynamic random access memory) class large-scale integrated circuit having a minimum design dimension of 0.25 [μm] and a chip size of 20 [mm] × 20 [mm]. .
[0110]
In this embodiment, a substrate obtained by subjecting a first circuit pattern to a predetermined process using a KrF excimer laser stepper (projection exposure apparatus) with NA = 0.55 [reduction ratio 5: 1, exposure wavelength 248 [nm]] Transcribed above. After performing a predetermined circuit pattern processing step, the second circuit pattern was transferred using a second stepper.
[0111]
In the present embodiment, the second circuit pattern was transferred using the same second KrF excimer laser stepper as in the first embodiment. FIG. 9 shows a distortion error measurement result at each lattice point position. The row and column numbers indicate the numbers obtained by counting each grid point position from the upper left of the chip. As a result of the measurement, in the two-dimensional xy coordinate system on the wafer surface, for example, at the position 31 (the position of the 31st row and the 1st column) in the exposure field, the distortion is −34 [nm] in the x direction and −22 [nm] in the y direction. The error was measured.
[0112]
On the other hand, it has been found from preliminary studies that the position of the circuit pattern formed on the substrate is complicatedly distorted in the chip as shown in FIG. 17 due to the element manufacturing process. Here, the horizontal axis of the graph in FIG. 17 indicates the position on the y-axis when the two-dimensional xy coordinate system is taken in a direction parallel to each side of the chip with the center of the chip as the origin. The vertical axis indicates the amount of deviation of the circuit pattern position from the resist pattern position transferred for processing the circuit pattern in the element manufacturing process. The figure shows a case where a circuit pattern obtained by processing a material that causes wafer distortion is arranged in a 15 [mm] square area 82 in a 20 [mm] square chip 81.
[0113]
FIG. 18 shows a case where the center position of the region 82 is arranged so as to coincide with the center position of the chip 81, and the size of the region 82 is changed from 0 [mm] square to 20 [mm] square. It shows the expansion and contraction rate of the chip dimensions of the chip 81 (change rate of chip magnification). The horizontal axis in the drawing represents the size of the region 82. Here, the circuit pattern in the region 82 was the same as a line and space pattern that is periodic in the x direction. As shown in FIG. 18, it was also found that the difference in the expansion and contraction ratio of the chip 81 between the x direction and the y direction was about 0.5 [ppm] at maximum.
[0114]
In this embodiment, since the size of the region 82 is 15 [mm] square, a chip magnification error in the x direction is -0.6 [ppm] and a chip magnification error in the y direction is -0.9 [ppm]. The chip size of the mask pattern was corrected. Note that the expansion / contraction rate of -0.6 [ppm] corresponds to a contraction of about 11 [nm] with respect to the on-chip size of 18 [mm]. . Further, as shown in FIG. 17, since the pattern position changes within the chip, the circuit pattern position on the mask was corrected so as to correct this positional deviation. Further, mask pattern data was corrected in the same manner as in Example 1 so as to correct the above-described distortion error.
[0115]
A second mask for transferring a second circuit pattern was manufactured using the mask pattern data corrected as described above.
[0116]
The second circuit pattern was superimposed on the first circuit pattern and transferred using the manufactured mask. As a result of inspecting the transferred pattern using a scanning electron microscope, the overlay error between the first circuit pattern and the second circuit pattern was within a desired overlay error allowable range ± 80 [nm] or less. The second circuit pattern could be transferred with alignment accuracy.
[0117]
By performing the pattern transfer as described above, it is possible to suppress the pattern arrangement error due to the distortion error and the substrate distortion. As a result, it is possible to reduce the overlay error. Therefore, the production process yield of the solid state device can be improved.
[0118]
Furthermore, since overlay errors can be reduced, variations in device characteristics due to overlay errors can be suppressed, so that the yield of the manufacturing process can be improved and high-performance solid-state devices can be manufactured.
[0119]
FIG. 19 shows an example of the configuration of a stepper (projection exposure apparatus) used in the embodiment of the present invention.
[0120]
As shown in FIG. 19, light emitted from the light source 131 illuminates the mask 136 via the fly-eye lens 132, the condenser lens 133, the mirror 134, and the condenser lens 133. A pellicle 137 is provided on the mask 136 for preventing a pattern transfer failure due to foreign matter adhesion. The mask pattern drawn on the mask 136 is projected onto a wafer 139 as a sample substrate via a projection lens 138. The mask 136 is placed on the mask stage 148 controlled by the mask position control means 147, and the center of the mask 136 and the optical axis of the projection lens 138 are accurately aligned. The wafer 139 is vacuum-sucked on the sample stage 140. The sample stage 140 is mounted on a Z stage 141 movable in the optical axis direction of the projection lens 138, that is, in the Z direction (vertical direction), and further mounted on an XY stage 142. The Z stage 141 and the XY stage 142 are driven by the respective driving units 113 and 114 in accordance with a control command from the main control system 149, and can be moved to a desired exposure position. The position of the mirror 146 fixed to the Z stage 141 is accurately monitored by the laser length measuring device 145. In addition, the surface position of the wafer 139 is measured by a focus position detection unit included in a normal exposure apparatus. By driving the Z stage 141 according to the measurement result, the surface of the wafer 139 can always be made to coincide with the image plane of the projection lens 138.
[0121]
As described above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof. Of course.
[0122]
【The invention's effect】
The effects obtained by the typical inventions among the inventions disclosed in the present application will be briefly described as follows.
[0123]
As described above, according to the present invention, it is possible to transfer a pattern with high overlay accuracy while suppressing degradation of overlay accuracy due to distortion errors.
[Brief description of the drawings]
FIG. 1 is a process chart showing a mask manufacturing process according to the present invention.
FIG. 2 is a schematic diagram showing a mask pattern correction method according to the present invention.
FIG. 3 is a schematic diagram showing a mask pattern correction method according to the present invention.
FIG. 4 is a schematic view showing a mask pattern correction method according to the present invention.
FIG. 5 is a process chart showing a mask manufacturing process according to the present invention.
FIG. 6 is a schematic diagram illustrating a distortion error measurement result of a first stepper according to the first embodiment of the present invention.
FIG. 7 is a diagram illustrating a measurement result of a distortion error of a first stepper according to the first embodiment of the present invention.
FIG. 8 is a schematic diagram illustrating a measurement result of a distortion error of a second stepper according to the first embodiment.
FIG. 9 is a diagram illustrating a distortion error measurement result of a second stepper according to the first embodiment of the present invention.
FIG. 10 is a diagram illustrating a measurement result of a difference between distortion errors of two steppers according to the second embodiment of the present invention.
FIG. 11 is a diagram illustrating a measurement result of a distortion error of a stepper according to the third embodiment of the present invention.
FIG. 12 is a schematic diagram illustrating an arrangement of a position mark pattern according to a third embodiment of the present invention.
FIG. 13 is a schematic view showing a mask pattern correction method according to the present invention.
FIG. 14 is a schematic view showing a mask pattern correction method according to the present invention.
FIG. 15 is a diagram showing a measurement result of an overlay error measured in Example 3 of the present invention.
FIG. 16 is a schematic diagram showing a cross-sectional structure of a part of a MOS transistor section mounted on a large-scale integrated circuit.
FIG. 17 is a schematic diagram showing a pattern position shift amount of a circuit pattern formed on a substrate.
FIG. 18 is a schematic diagram showing a rate of change in expansion and contraction of a chip formed on a substrate in a two-dimensional direction.
FIG. 19 is a schematic configuration diagram showing an example of a configuration of a stepper used in the embodiment of the present invention.
[Explanation of symbols]
1. Step of measuring a distortion error, 2. Step of correcting a mask pattern position using the above result, 3. Step of correcting a mask pattern position according to pattern position distortion on a substrate, 4. Step of manufacturing a mask 5, a step of transferring a mask pattern;
10: chip, 11: position mark,
21-1,21-2,21-3,21-4,21-5,21-6,21-7,21-8,21-9,22-1,22-2,22-3,22- 4, 22-5, 22-6, 22-7, 22-8, 22-9 ... measured value, 23 ... pattern position, 24, 25 ... error value,
31: first correction area, 32: second correction area, 33: measurement point, 41: mask pattern,
42... Figures, 2-1, 42-2, 42-3, 42-4, 42-5... Figures, 43... Figure center positions, 43-1, 43-2, 43-3, 43-4, 43 -5: center position of the figure,
51: a step of obtaining a combination of exposure apparatuses, 52: a step of obtaining an average of distortion errors of the exposure apparatus group, 53: a step of manufacturing a mask with a corrected mask pattern position, 54: pattern transfer using the manufactured mask Process,
Reference numeral 60: chip, 61: first area, 62: second area, 63: third area, 64: fourth area, 65: fifth area, 66: sixth area, 67: seventh Area of the
70: substrate, 71: element isolation pattern, 72: gate wiring pattern, 73: insulating film, 74: source region, 75: drain region.

Claims (9)

Manufacturing of a mask used in a pattern transfer method of overlaying and transferring a mask pattern formed on a mask onto a pattern formed on the substrate by projecting and exposing the mask pattern on the substrate via an imaging optical system In the method,
So as to reduce the overlay error between the formed image and the imaging position of the mask pattern projected image projected onto the substrate via an optical system onto the substrate pattern, the exposure chip relative to the mask pattern position of the deviation of the mask pattern projected image imaging position, the path up position distortion of the exposure in the chip caused by wafer processing process pattern formed on the substrate, exposed and processed to be superimposed patterns on the substrate, it Adjusting the position of the mask pattern on the mask to be determined and corrected by measuring ,
The correction of the misalignment of the mask pattern projected image imaging position in the exposure chip relative to the mask pattern position, and Pa Tan displacement correction of exposure in a chip produced by the wafer processing process pattern formed on said substrate, said exposure chip Using a measurement result of a distortion at a lattice point position of a matrix assumed within the mask. Manufacturing of a mask used in a pattern transfer method of overlaying and transferring a mask pattern formed on a mask onto a pattern formed on the substrate by projecting and exposing the mask pattern on the substrate via an imaging optical system In the method,
So as to reduce the overlay error between the formed image and the imaging position of the mask pattern projected image projected onto the substrate via an optical system onto the substrate pattern, distortion of the imaging optical system exposing the imaging position distortion of the mask pattern projected image in the exposure chips caused by the error, the path up position distortions in the exposure chip caused by wafer processing process pattern formed on said substrate, to be superimposed patterns on the substrate Processing, adjusting the position of the mask pattern on the mask to determine and correct by measuring it ,
The correction of the imaging position distortion of the mask pattern projected image in the exposure chip caused by distortion error of the imaging optical system, and Pa Tan displacement correction of exposure in a chip produced by the wafer processing process pattern formed on the substrate Is a method for manufacturing a mask, wherein a measurement result of distortion at a lattice point position of a matrix assumed in the exposure chip is used. 3. The method of manufacturing a mask according to claim 1, wherein the mask pattern position is adjusted using a value obtained by interpolating a measurement result of a distortion error of the imaging optical system. . 4. The method according to claim 3, wherein a measurement result of the distortion error of the imaging optical system is interpolated using a spline function. In a method of manufacturing a solid-state device having a processing step including a heat treatment and a step of forming a pattern using a projection exposure apparatus,
The pattern position distortion in the exposure chip of the pattern formed on the substrate caused by the processing step including the heat treatment, the non-linear type obtained by exposing and processing the pattern to be overlapped on the substrate, and measuring the same. A step of preparing a mask whose pattern position has been corrected in advance in consideration of the amount of distortion , and the shift of the pattern imaging position in the exposure chip due to the imaging optical system of the projection exposure apparatus,
Correction of the amount of nonlinear distortion in the exposure chip of the pattern formed on the substrate resulting from the processing step including the heat treatment , and the projection exposure apparatus on the substrate that has undergone the processing step including the heat treatment. Transferring a pattern,
Correction of the shift of the pattern imaging position in the exposure chip due to the imaging optical system of the projection exposure apparatus is characterized by using the measurement result of the distortion at the lattice point position of the matrix assumed in the exposure chip. Manufacturing method of a solid state device. 6. The method according to claim 5, wherein the pattern of the mask is a gate wiring pattern. What is claimed is: 1. A method for manufacturing a solid-state device, comprising: forming a pattern using a first projection exposure apparatus and a second projection exposure apparatus;
Providing a first substrate;
A step of preparing a first mask whose pattern position has been corrected in advance by considering a shift of a pattern projection image forming position in an exposure chip due to an image forming optical system of the first projection exposure apparatus;
A first circuit pattern is formed on a second substrate using the first mask, a predetermined process is performed on the second substrate, and the first circuit pattern is caused by an imaging optical system of the second projection exposure apparatus. A second circuit pattern is formed on the second substrate on which the first circuit pattern is formed by using a second mask whose pattern position has been corrected in consideration of a shift in a pattern projection imaging position in an exposure chip in advance. Is formed, an overlay error between the first circuit pattern and the second circuit pattern is inspected to determine an amount of distortion in an exposure chip of the second substrate, and the distortion is further added to the second mask. Preparing a third mask manufactured by correcting the pattern position in consideration of the amount;
Transferring the first circuit pattern of the first mask to the first substrate using the first projection exposure apparatus;
Performing a predetermined process on the first substrate;
Transferring the second circuit pattern of the third mask to the first substrate by using the second projection exposure apparatus. The method according to claim 7, wherein the predetermined process is a heat treatment. 9. The method according to claim 7, wherein the first projection exposure apparatus is different from the second projection exposure apparatus.

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