JP3439387B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a trench element isolation region.

[0002]

2. Description of the Related Art In order to miniaturize and speed up a semiconductor device, it is necessary to narrow an element separation interval.
Conventionally, LOCO has been used as a method for forming the element isolation region.
Although the S method is generally used, it cannot sufficiently meet such a demand for miniaturization. Therefore, as an alternative method to the LOCOS method, recently, STI (Shallow Trench Isolation)
n) is receiving attention.

In the conventional STI, a thin pad oxide film and a nitride film are laminated on a semiconductor substrate such as a silicon substrate, and a resist mask having an opening for element isolation is formed by a photolithography method. Anisotropically etch the pad oxide film and the semiconductor substrate to form a groove (trench), remove the resist mask, deposit an insulating material on the entire surface, and use the nitride film as a stopper to perform chemical mechanical polishing (Chemical Mechanical Polishing). The trenches are filled with an insulating material by Polishing: CMP) to form element isolations.

[0006] When an insulator is embedded in the trench, the inner wall of the trench is generally thermally oxidized for the purpose of eliminating etching damage when the trench is formed.

In a semiconductor device using such trench element isolation, a transistor or the like is formed in contact with the trench element isolation region. At this time, if the shape of the trench edge is an acute angle, the electric field is concentrated at that portion. And the threshold characteristic of the transistor is deteriorated. That is, as shown in FIG. 5A, in the element region 52 partitioned by the trench element isolation, the gate electrode 51 is formed so as to extend over the trench element isolation region as well.
Subchannel 53 is formed adjacent to the edge of the trench,
Since the drain current characteristics with respect to the gate voltage of the main channel and the sub-channel are different from each other, as shown in FIG. 5B, the main channel having a normal threshold voltage and the relatively low parasitic parasitic on the edge of the active region are included. The sub-channel having the threshold voltage causes the threshold voltage of the transistor to change during operation, causing a current hump phenomenon in the threshold region of the sub-channel. Therefore, an increase in leak current of the transistor and deterioration of on / off characteristics are caused. Such a problem becomes more remarkable as the channel width of the device becomes narrower, that is, as the degree of integration increases.

Therefore, conventionally, a method of rounding the trench edge has been proposed in order to prevent the occurrence of hump in such STI. Usually, in order to round the trench edge, a method of performing the thermal oxidation inside the trench at a high temperature has been adopted.

However, as shown in FIG. 3, when a (111) silicon substrate 31 which is usually used as a semiconductor substrate is used, thermal oxidation at a high temperature (about 1100 ° C.) results in <111 at the corner of the trench bottom. The crystal plane 33 (facet) of the> plane appears, and dislocation occurs due to the stress of the thermal oxide film. This reaches the source / drain regions of the transistor that will be formed as a dislocation loop 32 in a later step, and there is a problem that the electrical characteristics deteriorate.

On the other hand, wet oxidation has a higher oxide film growth rate than dry oxidation, and when a thermal oxide film having a desired film thickness is obtained, thermal oxidation at a lower temperature is possible if the oxidation time is the same. Is. Facet is less likely to occur in the low temperature wet oxidation, but as shown in FIG. 4, the film thickness uniformity is slightly inferior to that in the dry oxidation, and the trench edge portion 41 cannot be sufficiently rounded. The above hump cannot be prevented.

By the way, JP-A-11-135608, JP-A-11-135609, and JP-A-11-13561.
In Japanese Unexamined Patent Application Publication No. 0-331, in order to prevent damage to the silicon substrate due to anisotropic etching at the time of forming a trench away from the element formation region, the semiconductor substrate exposed in the opening is isotropically etched and an anisotropic etching hard mask is used. A method has been proposed in which a silicon oxide film serving as a mask is projected in an eaves-like shape, and anisotropic etching is performed using this to form a trench. For example, taking Japanese Patent Laid-Open No. 11-135608 as an example, first, as shown in FIG.
A thin pad oxide film 2 is formed on a semiconductor substrate such as by a thermal oxidation method, and then a silicon nitride film 3 is formed by LPCV.
The desired thickness is formed by the D method or the like. Further, a silicon oxide film 4 is formed on the insulating film by the LPCVD method or the like by 1000-2.
Form to a thickness of about 000Å. Subsequently, a resist is applied, and a resist mask 5 is formed by an ordinary photolithography process so as to open a portion where element isolation is to be formed, and the oxide film 4 is dry-etched using this as a mask. After removing the resist mask, the nitride film 3 and the pad oxide film are sequentially dry-etched using the patterned oxide film 4 as a mask, and the exposed silicon substrate surface is shallowed (300-
1000Å) Dry etching is performed to form an opening 6 '(FIG. 6 (b)). Then, the exposed surface of the Si substrate 1 is thermally oxidized to form a thermal oxide film 11 of 100 to 200 Å (see FIG. 6).
(C)) The thermal oxide film 11 is removed to form the shallow groove 7'and the silicon nitride film and the silicon oxide film are overhanged in an eaves-like shape (FIG. 6 (d)). The surface of the Si substrate 1 exposed with the oxide film 4 as a mask is dry-etched to form a trench 8 of about 2000 to 4000 Å (FIG. 7A). After that, the inside of the trench is thermally oxidized by dry oxidation at 900 ° C. or higher or wet oxidation at 800 ° C. or higher to form a thermal oxide film 9 of 100 to 200 Å (FIG. 7 (b)), and the entire surface is thickened by the CVD method. The CVD oxide film 10 is deposited (FIG. 7C), and the CVD oxide film 10 is polished by the chemical mechanical polishing (CMP) method using the nitride film 3 as a stopper (FIG. 7D) to isolate trench elements. It is a method of forming.

However, in these prior arts, the above-mentioned problem of hump and facet is not mentioned.

[0011]

SUMMARY OF THE INVENTION An object of the present invention is to suppress the occurrence of dislocation loops due to the above facets as seen in high temperature dry oxidation to prevent the deterioration of electrical characteristics, and to reduce trenches in conventional wet oxidation. Provided is a method of manufacturing a semiconductor device having a trench forming step capable of preventing an increase in leak current and deterioration of on / off characteristics of a transistor due to STI hump due to an insufficiently rounded edge shape. is there.

[0012]

Means for Solving the Problems As a result of intensive studies to solve the above-mentioned problems, the present inventor has previously removed a portion corresponding to the edge of the trench by isotropic etching and then anisotropically etching the trench. It has been found that by forming it, the edge of the trench can be rounded even by subsequent wet thermal oxidation at low temperature, and facet generation can be prevented because of low temperature thermal oxidation.

That is, according to the present invention, a step of sequentially forming a pad oxide film and a silicon nitride film on a semiconductor substrate, a step of applying a resist on the silicon nitride film to form a pattern for forming a trench, and a formation Using the formed resist pattern as a mask, the silicon nitride film and the pad oxide film are sequentially etched to form an opening, the pad oxide film exposed in the opening is side-etched by wet etching, and further exposed to the bottom of the opening. Isotropically etching the surface of the semiconductor substrate to form a shallow groove on the surface of the semiconductor substrate, anisotropically etching the silicon substrate to form a deep groove, and thermally oxidizing the groove by low temperature wet oxidation. A step of forming a film, a step of depositing an insulator on the entire surface so as to fill the groove, and an insulator using the silicon nitride film as a stopper. A method of manufacturing a semiconductor device characterized by a step of flattening by MP polished.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, side etching is performed on a lowermost pad oxide film exposed on an opening surface of an insulator hard mask at the time of forming a trench, and a silicon substrate is isotropically etched by using this as a mask to make a shallow etch. Since the groove is formed, by adjusting the side etching amount of the pad oxide film, it is possible to easily adjust the entering amount of the silicon substrate under the hard mask due to isotropic etching.

Here, the distance (side etching amount) from the opening end face of the side etching applied to the pad oxide film is
If the amount is too small, the amount of shallow grooves formed by isotropic etching of the silicon substrate under the hard mask will be small. Of course, if the amount of etching by isotropic etching is increased, the amount of penetration can be secured, but the groove depth will be correspondingly increased. The side etching amount is 50 to 300Å, more preferably 50 to 200Å.

In the present invention, in the anisotropic etching for forming the hard mask, the pad oxide film may be completely removed to expose the silicon substrate, but the thin pad oxide film is not completely removed on the surface of the silicon substrate. Even in the state in which the oxide is left, it can be removed by wet etching during side etching of the pad oxide film.

Subsequently, a shallow groove is formed by isotropic etching of the silicon substrate. At this time, the isotropic etching is either dry etching such as plasma etching or wet etching using ammonia and hydrogen peroxide. The method is also good. The depth of the groove is 100-50.
It is 0Å, more preferably 100 to 300Å.

The anisotropic etching for forming the trench in the silicon substrate may be performed by using the resist mask at the time of forming the hard mask as a mask or by removing the resist mask and using the nitride film as a mask, but it is preferable. It is preferable that a silicon oxide film is further formed on the nitride film, and after the resist is removed, anisotropic etching is performed on the silicon substrate using the silicon oxide film as a mask. When a resist mask is used as a mask for anisotropic etching, isotropic etching performed before that is dry etching because the resist mask is peeled off by wet etching.

After forming the trench in this way,
A thermal oxide film is formed on the surface of the silicon substrate exposed in the trench by low temperature wet oxidation. As the wet oxidation method, conventionally known wet O ₂ oxidation or steam oxidation can be adopted. Wet oxidation temperature is 800
It is desirable to carry out in the temperature range of ˜1000 ° C., more preferably 800˜900 ° C. Here, the thermal oxide film is 1
The film is formed to a film thickness of about 00 to 500Å. For example, steam oxidation takes about 5 minutes at 900 ° C and 10-2 at 800 ° C.
It only has to be done for about 0 minutes.

Then, the CV is formed in the trench as in the conventional method.
An insulator such as a D oxide film is embedded, and CMP polishing is performed using the nitride film as a stopper to fill the trench with the insulator.

In the present invention, since the shallow groove is formed in the silicon substrate by isotropic etching, the trench edge can be rounded even by low temperature wet oxidation, and facet formation at the trench bottom can be prevented. Therefore, the dislocation loop does not occur.

[0022]

EXAMPLES The present invention will be specifically described below with reference to examples, but the present invention is not limited to these examples.

First Embodiment A first embodiment of the present invention will be described with reference to the drawings. 1 and 2 are process cross-sectional views of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

First, the Si substrate 1 is thermally oxidized in a H ₂ —O ₂ atmosphere at 900 ° C. to form a pad oxide film 2 having a thickness of about 200 Å, and silane and ammonia are used as source gases on the pad oxide film 2. LPC in the temperature range of 700-800 ℃
A nitride film (Si ₃ N ₄ ) film 3 is formed to a thickness of about 1500 Å by the VD method. Furthermore, using TEOS as a raw material, 650
A CVD silicon oxide film (SiO ₂ ) film 4 having a film thickness of about 500 Å is formed by LPCVD in the temperature range of up to 700 ° C. (FIG. 1A).

Subsequently, a resist is applied on the oxide film 4,
A predetermined pattern is formed by a photolithography process to form a resist mask 5, and the oxide film 4, the nitride film 3, and the pad oxide film 2 are anisotropically dry-etched using the resist mask 5 as a mask to form an opening 6 (FIG. 1
(B)).

After ashing with O ₂ plasma and removing the etching residue adhering to the resist mask 5 and the inner wall of the opening 6 with a resist stripping solution, the pad oxide film 2 with a hydrofluoric acid-based etching solution of about 100 liters is removed. Perform side etching. Then, a shallow groove 7 is formed by isotropic etching on the surface of the silicon substrate 1 exposed in the opening with an etching solution using ammonia and hydrogen peroxide (FIG. 1C). Here, the groove depth is 20
The depth should be about 0Å. Then, using the oxide film 4 as a mask, the Si substrate 1 exposed at the bottom of the shallow groove 7 is dry-etched to form a trench 8 (FIG. 1D). here,
As a trench depth, a 2500 Å trench was formed.

Subsequently, wet thermal oxidation was performed at 900 ° C. in an O ₂ atmosphere to form a thermal oxide film 9 of about 400 Å on the inner wall of the trench (FIG. 2A).

In order to bury the oxide film in the trench thus formed, first, as shown in FIG. 2B, the CVD oxide film 10 was formed on the entire surface by the HDPCVD method to a thickness of about 5500 Å. Then, using the nitride film 3 as a CMP stopper, the CVD oxide film 10 and the oxide film 4 were polished by the CMP method to obtain the structure shown in FIG. Further, the nitride film 3 was removed with hot phosphoric acid, and the pad oxide film 2 was removed with a hydrofluoric acid-based solution, so that trench element isolation as shown in FIG. 2D was formed.

[0029]

As described above, according to the present invention,
After the pad oxide film is side-etched and the silicon substrate is isotropically etched to form a shallow groove, a trench is formed by anisotropic etching, and the trench thus formed is thermally oxidized by wet oxidation. Since the thermal oxide film is formed by using it, generation of dislocation loops due to facets, which is observed in high temperature dry oxidation, can be suppressed, and deterioration of electrical characteristics can be prevented. It is possible to round the edge portion of the trench that could not be formed, and it is possible to prevent an increase in the leakage current of the transistor and deterioration of the on / off characteristics due to the hump of the STI.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a conceptual diagram illustrating a problem caused by dry oxidation, and FIG. 3B is a partially enlarged view of FIG.

FIG. 4 is a conceptual diagram illustrating a problem caused by wet oxidation.

FIG. 5A is a plan view schematically showing how a sub-channel is formed in the vicinity of the edge of the trench, and FIG. 5B is a graph explaining the occurrence of hump due to the formation of such a sub-channel. Is.

FIG. 6 is a cross-sectional view of a manufacturing process of a conventional semiconductor device.

FIG. 7 is a cross-sectional view of manufacturing steps of a conventional semiconductor device.

[Explanation of symbols]

1 Si substrate 2 Pad oxide film 3 Nitride film 4 oxide film 5 Resist mask 6 openings 7 shallow groove 8 trench 9 Thermal oxide film 10 CVD oxide film

Continuation of the front page (56) Reference JP 2000-340558 (JP, A) JP 60-128634 (JP, A) JP 58-9333 (JP, A) JP 11-135609 (JP, A) JP-A-11-8303 (JP, A) JP-A-1-107554 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/76-21/765

Claims (7)

(57) [Claims] 1. A step of sequentially forming a pad oxide film and a silicon nitride film on a semiconductor substrate, a step of applying a resist on the silicon nitride film to form a pattern for trench formation, and a formed resist pattern. As a mask
The silicon nitride film and the pad oxide film are sequentially etched,
In the step of forming an opening, the pad oxide film exposed in the opening is side-etched by wet etching in the range of 50 to 300Å, and the semiconductor substrate surface exposed at the bottom of the opening is isotropically etched to form a semiconductor substrate surface. A step of forming a shallow groove, a step of anisotropically etching a silicon substrate to form a deep groove, and subsequent to the above step, a thermal oxide film is formed in the groove by wet oxidation under a temperature condition of 800 ° C. or more and less than 1000 ° C. A method of manufacturing a semiconductor device, comprising: a step of forming, an step of depositing an insulator on the entire surface so as to fill the groove, and a step of planarizing the insulator by CMP polishing using the silicon nitride film as a stopper. . 2. The method of manufacturing a semiconductor device according to claim 1, wherein the isotropic etching of the semiconductor substrate is performed under dry conditions. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the isotropic etching of the semiconductor substrate is performed by wet etching using ammonia and hydrogen peroxide. 4. The method of manufacturing a semiconductor device according to claim 2, wherein anisotropic etching of the semiconductor substrate is performed using a resist pattern as a mask. 5. The anisotropic etching of the semiconductor substrate is performed using a silicon nitride film as a mask.
A method of manufacturing a semiconductor device according to item 1. 6. A silicon oxide film is further formed on the silicon nitride film to form an opening, and then anisotropic etching of the semiconductor substrate is performed using the silicon oxide film as a mask. 4. The method for manufacturing a semiconductor device according to item 3. 7. The method of manufacturing a semiconductor device according to claim 1, wherein side etching of the pad oxide film is performed using a hydrofluoric acid-based solution.