JP3413342B2 - Jitter measurement method and semiconductor test apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to measurement of jitter output from a device having an oscillation circuit or a device outputting a clock signal containing jitter by using a semiconductor test apparatus.

[0002]

2. Description of the Related Art Some recent devices include a PLL inside.
There is a device that has a built-in circuit and outputs a predetermined frequency signal in synchronization with a reference clock supplied from the outside. In testing such a device, it is necessary to set and control the setting conditions of the internal registers of the device, apply a high-purity reference clock, receive the output signal from the device, and measure the jitter amount. is there.

A prior art example will be described with reference to the jitter measurement configuration diagram of FIG. The device under test (DUT) is assumed to be a device with a built-in PLL circuit. The configuration of the jitter measuring apparatus includes a device internal condition setting control unit 70, a reference signal generator 80, and an output waveform observing apparatus 90 (for example, an oscilloscope).

The device internal condition setting control unit 70 uses the DU
A control signal for setting the setting condition of the T internal register or the like to a predetermined condition is supplied. The reference signal generator 80 is D
It is a reference clock source of high-purity desired frequency that does not affect the jitter measurement accuracy of the UT, and is supplied to the reference clock input terminal 11 of the DUT and the trigger input terminal of the output waveform observing device 90. The output waveform observing device 90 sweeps in synchronization with the reference clock signal 81 from the reference signal generator 80, receives an output signal from the output end 12 of the PLL oscillation frequency of the DUT, and observes this jitter width, Check if it is within the specifications of the device specifications.

As described above, a dedicated jitter measuring jig is prepared and the DU is set by the device internal condition setting control unit 70.
Although the test is performed by setting the T internal condition to a predetermined condition, the inspection time is long because the DUT internal condition is often changed and the measurement is performed a plurality of times. Particularly in mass-produced devices, various tests of general DC characteristics, AC characteristics, and functional characteristics of other built-in circuits are tested by a semiconductor test apparatus. For this reason, it is practically inconvenient in terms of test cost / measurement time to install a dedicated jig for jitter measurement separately and test separately.

[0006]

The problem to be solved by the present invention is to realize a measuring method and a jitter measuring apparatus for measuring the jitter of a frequency signal output from a device using a semiconductor test apparatus. .

[0007]

FIG. 1, FIG. 2, and FIG. 3 show a solution means according to the present invention. First, in order to solve the above problems, in the configuration of the present invention, the predetermined reference clock signal 21clk is supplied to the reference clock input terminal 1 of the DUT.
1 is provided with the test pattern generator 20 which receives the oscillation output signal 15 from the DUT output terminal 12 and moves the strobe signal STB1 sequentially from the front side to the rear side. A means for detecting the presence or absence (or the presence or absence of a path) and obtaining the Min position 201 of the jitter leading edge from this is provided.
In response to the oscillation output signal 15 from the output terminal 12, the strobe signal STB1 is sequentially moved from the rear side to the front side, and the presence or absence of a failure (or the presence or absence of a pass) by the fail counter 40 is detected at each strobe movement position. A means for obtaining the Max position 202 of the trailing edge is provided, and the difference between the obtained jitter positions is obtained as the jitter width. Accordingly, by using the strobe signal STB1 of the timing comparison unit 30 and the fail counter 40,
A semiconductor test apparatus for measuring the jitter of a device under test realizes the jitter measurement of a frequency signal output by the device under test.

FIG. 2 shows a solution according to the present invention. Secondly, in order to solve the above-mentioned problems, in the configuration of the present invention, the predetermined reference clock signal 21clk is supplied from the test pattern generator 20 to the reference clock input terminal 11 of the DUT, and the fail counter 40 does not detect the jitter. The position of the strobe signal STB1 is initialized to the position on the trailing edge side, the fail detection is performed by the fail counter 40 for a predetermined time Tmeas, and first, when the fail detection is not made, the strobe signal STB is detected in the direction to detect the jitter trailing edge.
When the timing position of 1 is moved and repeated, and the second fail is detected, the position of the strobe signal STB1 is obtained and stored as the Max position 202 of the trailing edge of the jitter.
Then, the position of the strobe signal STB1 is initialized to a position on the jitter leading edge side where the fail counter 40 detects all the failures (that is, a position where the pass does not occur even once), and the fail counter 40 performs the fail detection for a predetermined time Tmeas. First, if all the failures are detected (that is, if the path does not pass even once), the timing position of the strobe signal STB1 is moved in the direction to detect the jitter leading edge, and the operation is repeated. Secondly, all the failures are detected. If not performed (that is, at least one pass is detected), the position of the strobe signal STB1 is set to the Min position 201 of the jitter leading edge.
Then, the jitter measuring method is to obtain the difference between the Min position 201 at the jitter leading edge and the Max position 202 at the jitter trailing edge as the jitter width. As a result, the strobe signal STB of the timing comparison unit 30 included in the semiconductor test apparatus is
1 and the fail counter 40, for example PL
A jitter measuring method for a frequency signal output from a device under test is realized in measuring the jitter of a device under test including an L oscillation circuit.

As a method of measuring the jitter stabilization time until the jitter is stabilized, the jitter leading edge M
When the in position 201 and the Max position 202 of the trailing edge of the jitter are obtained and the predetermined reference clock signal 21clk is supplied from the test pattern generator 20 to the reference clock input terminal 11 of the DUT, the output is stopped for a predetermined period or is indefinite. After setting the reference clock signal 21clk, the original stable reference clock signal 21clk is supplied, the elapsed time by the built-in clock is measured from this point, and the Min of the jitter leading edge obtained in advance is determined.
The position of the strobe signal STB1 is set to a predetermined position where fail detection is not performed adjacent to the position 201 or the Max position 202 of the trailing edge of the jitter, and the count data of the fail counter 40 is read every unit micro time, and the count data does not change. There is a measuring method in which the elapsed time is obtained as the jitter stabilization time of the DUT. This realizes the measurement of the jitter stabilization time from the supply of the stable reference clock signal 21clk to the stabilization of the jitter.

FIG. 5 shows a solution according to the present invention. Thirdly, in order to solve the above problems, in the configuration of the present invention, the test pattern generator 2 that supplies the predetermined reference clock signal 21clk to the reference clock input terminal 11 of the DUT.
0, receives the oscillation output signal 15 from the DUT output terminal 12, and sequentially outputs one strobe signal S from the front side to the rear side.
A unit is provided which moves TB1 and detects the presence or absence of a fail by the fail counter 40 at each strobe moving position, and obtains the Min position 201 of the jitter leading edge from this.
In response to the oscillation output signal 15 from the T output terminal 12, the value of the expected value pattern 25exp is inverted, the other strobe signal STB2 is sequentially moved from the rear side to the front side, and the fail counter 40 fails at each strobe movement position. The presence or absence of the jitter is detected and the Max position 20 of the trailing edge of the jitter is detected.
There is a measuring method in which a means for obtaining 2 is provided and the difference between the obtained jitter positions is obtained as the jitter width. In this case, the jitter width measuring method uses both strobe signals STB1 and STB2.

In the above-mentioned jitter measurement, two comparator circuits 31 and 3 provided in the timing comparison section 30.
When the measurement method using only one of the two strobe signals STB1 is used, both strobe signals STB1
1 and the advantage that the jitter measurement error factor can be reduced as compared with the case of using STB2.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described in detail with reference to the drawings along with examples.

FIG. 1 is a block diagram of a main part relating to the measurement of jitter in the embodiment of the present invention, and FIG.
The detection operation by the fail counter in FIG. 3 will be described with reference to FIG.

The main structure of the present invention is as shown in FIG.
A test pattern generator 20, a timing comparison unit 30,
It includes a fail counter 40, a measurement program 50, and a control unit 60. All of these configurations are functional elements included in the semiconductor test apparatus. The counting operation of the fail counter 40 is a basic functional element of the semiconductor test device,
Expected value pattern 2 from the test pattern generator 20 for the signals latched by the comparator circuits 31 and 32.
It is counted when it is compared with 5exp and does not match, and when the CPE (comparator enable) signal is valid.
The expected value pattern 25exp and the CPE signal differ depending on the memory test device and the logic test device, and there is a configuration in which counting control is performed by, for example, a 3-bit code signal, but in any case, as an input functional element for controlling this fail counter. The same and the prior art.

According to the present invention, by checking the presence / absence of the count value of the fail counter 40 (that is, the presence / absence of a fail) while sequentially moving the strobe points, the jitter width is 2
This is a method of obtaining the jitter width by finding the boundary points at some points. In the present invention, only the strobe signal STB1 of one of the two comparator circuits 31 and 32 in the timing comparison unit 30 is used in order to make the jitter measurement more accurate. This is to remove a measurement error factor on the measurement side as much as possible in order to accurately measure a minute jitter width of several tens of picoseconds.

The jitter measuring operation will be described below with reference to the measurement flowchart of FIG. Needless to say, various setting conditions of the pin electronics circuit are set in advance so that the oscillation output signal 15 from the DUT output terminal 12 is supplied to the timing comparison unit 30 during the jitter measurement.

First, # 100 sets up the DUT in the jitter measurement state. That is, the DUT internal condition is set to a predetermined value, the other input pins of the DUT are set to a predetermined state, and the high-purity reference clock signal 21cl from the test pattern generator 20 is set.
k is supplied to the reference clock input terminal 11 of the DUT.
Furthermore, the expected value of the expected value pattern 25exp = “L” is set, and D
Predetermined elapsed time Twa at which the jitter stabilizes from the start of UT operation
After that, the fail counter 40 fails (Fa
il) The strobe signal STB1 is initialized at a position where it is not detected, that is, at the strobe point 200 shown in FIG. The reference clock signal 21clk supplied from the test pattern generator 20 to the DUT is a stable signal source with little jitter included in the semiconductor test apparatus. The position of the strobe point 200, which is the initial position, is obtained by first measuring the transition point of the oscillation output signal 15 of the DUT using the device test function of the semiconductor test apparatus and using this position information. Secondly, there is a method of using the measurement methods of # 101 to # 103 described below to coarsely move the strobe points to obtain the position information.

In the operation steps # 101 to # 103,
The Max position 202 of the trailing edge of the jitter is calculated. # 101 is
Fail counting is performed for a predetermined time Tmeas. That is, a predetermined clock time is waited at the designated strobe point 200, and the fail counter 40 performs fail counting during this period. As a result, the level of the oscillation output signal 15 of the DUT is "
When it becomes "H", fail counting is performed and fail detection is performed. Here, the predetermined time Tmeas is a clock time capable of detecting randomly generated jitter, for example, 1000 to 1000 clock time. This time is extremely short, The presence / absence of fail is detected at high speed.

# 102 is a decision branch. That is, the content of the fail counter 40 is read, and if the count value is zero, the process proceeds to # 103, and if there is, the process proceeds to # 104. That is, above # 1
As shown in FIG. 3A by 03, when the strobe point 200 is sequentially moved to the front, fail is detected eventually, and the process proceeds to # 104. # 103 is the next strobe point 2
To move to the 00 position, for example, unit time = 20 picoseconds time is moved in the front direction. Then, again at # 101, the fail count measurement is performed in the same manner. # 104 is shown in FIG.
As shown in (a), this position is stored as the Max position 202 of the trailing edge of the jitter.

In # 105, the expected value of the expected value pattern 25exp remains the same as "L", and the strobe signal ST
The strobe point 200 of B1 is moved to the position shown in FIG. 3 (b) so that the fail counter 40 is all failed. After that, the process proceeds to # 106.

In the operation steps # 106 to # 109,
The Min position 201 at the leading edge of the jitter is calculated. # 106 is
The CPE signal is enabled for a predetermined known number of times, and the fail counter 40 counts the failures during this period. When this count value matches the total fail count value, all are detected as fail, and when it is different from the total fail count value, at least one pass is detected.
This operation is repeated a predetermined number of times. If the result of this test is that all failures have not occurred even once, it means that at least one pass has been detected. # 107 is a decision branch. That is, in response to the test result of # 106, the process proceeds to # 108 in the case of all failures, and proceeds to # 109 if the pass is detected even once. That is, as shown in FIG. 3B, the strobe point 200 is sequentially moved backward, and if a pass is detected even once, the process proceeds to # 109. # 109
As shown in FIG. 3B, this position is the Min position 201 of the jitter leading edge.

Finally, at # 110, the jitter width of the DUT to be obtained 205 is obtained as 205 = Max position−Min position.
This is obtained as the DUT jitter width. Needless to say, the measurement program 50 is described and created so that the above-mentioned measurement is performed. Further, in the above measurement flow, # 105 to # 109 may be measured first.

According to the measuring method of the present invention, only one comparator circuit 31 in the timing comparing section 30 is used, the strobe point 200 is sequentially moved, and the presence / absence of a fail is detected. Since it is possible to measure the leading edge and the trailing edge, there is a great advantage that accurate jitter measurement can be realized. Further, there is a great advantage that various tests of the DUT including the jitter measurement items can be performed only by the semiconductor test equipment.

In the description of the above embodiment, the case where the oscillation output signal 15 from the DUT is a rectangular wave has been described, but even in the case of a sine wave, a desired comparison voltage is applied to the comparator in the timing comparison unit 30. VOL (eg 0.00V
It is obvious that the same operation can be performed because the setting can be given and converted into a digital signal.

In the above description of the embodiment, the case where the frequency of the oscillation output signal 15 from the DUT is the same as that of the applied reference clock signal 21clk has been described, but it is assumed that the output frequency of the DUT is different. Even if there is a correlation with the reference clock signal 21clk in phase synchronization, it suffices to create and execute a test program so as to enable the CPE signal only in a predetermined clock cycle, which is easy for a semiconductor test apparatus. That is. For example, when the oscillation output signal 15 is 1/10 of the reference clock signal 21clk, the reference clock signal 21clk may enable the CPE signal every 10 clock cycles. Therefore, it can be similarly implemented even when the output frequency is different.

In the above description of the embodiment, the measurement is performed after the predetermined elapsed time Twait when the jitter of the oscillation output signal 15 of the DUT stabilizes. However, until the jitter stabilizes using the above method. The jitter stabilization time of can be measured. That is, the Min position 2 of the jitter leading edge is measured by the above-described measurement method.
01 and the Max position 202 of the trailing edge of the jitter are obtained, and a predetermined reference clock signal 21cl is output from the test pattern generator 20.
When k is supplied to the reference clock input terminal 11 of the DUT, the reference clock signal 21clk in a random state (or another clock frequency or clock stop) is temporarily set for a predetermined period, and then the original stable reference clock signal 2
1clk is supplied, the elapsed time by the built-in clock is measured from this point, and the Min position 2 of the leading edge of the jitter is calculated in advance.
01 or a desired position where a fail is not detected adjacent to the Max position 202 of the trailing edge of the jitter (desired jitter standard position)
The position of the strobe signal STB1 is set to, and the count data of the fail counter 40 is read every unit minute time,
There is a method of obtaining the elapsed time when the count data does not change as the stable time of the DUT, and this jitter stable time measuring method may be additionally provided. This makes it possible to measure and realize the jitter stabilization time from the supply of the stable reference clock signal 21clk to the stabilization of the jitter. For example, in the case of a PLL oscillation circuit, the effect that the elapsed time until the phase lock is measured can be obtained.

In the description of the above-mentioned embodiment, the case where the presence or absence of jitter is detected by performing the fail count during the predetermined time Tmeas, which is a relatively short time, has been described. In order to obtain the jitter width, the worst jitter width may be obtained by performing the fail count during a predetermined time Tmeas for a long time.

In the above description of the embodiment, the measurement example in which the DUT conditions other than the jitter measurement are not changed has been described. However, this may occur when other peripheral circuits of the DUT internal circuit are changed as desired. A desired test pattern can be applied to the DUT from the test pattern generator 20 in parallel with the measurement of the dynamic jitter at the same time. Therefore, the same method as described above can be used for the measurement. That is clear. In this case, the actual DU
It is possible to obtain the advantage that it is possible to realize the jitter measurement due to the interference influence on the adjacent circuit inside the DUT under the operating condition close to the operating state of T.

In the description of the above-mentioned embodiment, the specific example of the jitter measurement of the DUT having the built-in PLL oscillation circuit is explained. However, if desired, an output signal having a phase synchronization correlation with the reference clock signal 21clk may be output. The jitter can be measured in the same manner in other output devices.

In the description of the above embodiment, in order to reduce the error factor at the time of measuring the jitter, the measurement method using only one strobe signal STB1 of the two comparator circuits 31 and 32 in the timing comparison unit 30. However, if desired, as shown in the measurement flowchart of FIG. 5B, both strobe signals ST may be used.
B1 and STB2 are used, and the expected value of the expected value pattern 25exp is inverted at # 105 corresponding to this, and # 106-
The test and determination in # 108 may be performed in the same manner as in # 101 to # 103, and the presence or absence of a fail may be detected to obtain the Min position 201 at the leading edge of the jitter. In this case, a factor of skew error between both strobe signals STB1 and STB2 is taken into consideration, but it is practical.

[0031]

The present invention has the following effects based on the above description. According to the above-described configuration of the present invention, the strobe point 200 is sequentially moved to detect the presence or absence of jitter, and by using this, the leading edge and the trailing edge of the jitter are respectively measured, so that the target jitter width can be obtained. . Further, various tests of the DUT including the jitter measurement items can be carried out only by using the semiconductor test apparatus, and the test cost can be reduced, and the economical effect is great.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a main part relating to jitter measurement according to the present invention.

FIG. 2 is a measurement flowchart of the present invention.

FIG. 3 is an operation explanatory diagram of a fail counter according to the present invention.

FIG. 4 is an example of a conventional jitter measurement configuration.

FIG. 5 is another measurement flowchart of the present invention.

[Explanation of symbols]

20 test pattern generator 30 Timing comparison unit 31, 32 Comparator circuit 40 fail counter 50 measurement programs 60 control 70 Device internal condition setting controller 80 Reference signal generator 90 Output waveform observation device DUT device under test

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-3-200081 (JP, A) JP-A-3-131778 (JP, A) JP-A-4-198773 (JP, A) JP-A-62-1 133360 (JP, A) JP-B-57-21144 (JP, B2) (58) Fields investigated (Int.Cl. ⁷ , DB name) G01R 31/319 G01R 29/02

Claims (4)

(57) [Claims] 1. A device under test (DU) using a strobe signal of a timing comparison section and a fail counter.
In a semiconductor test device for measuring the jitter of T), a test pattern generator for supplying a predetermined reference clock signal to a reference clock input end of the DUT and an output signal from the DUT output end are received, and the test pattern generator is sequentially rearward from the front side. The strobe signal is moved to, the presence or absence of a fail or the presence or absence of a pass by the fail counter is detected at each strobe moving position, and means for obtaining the Min position of the jitter leading edge from this, and an output signal from the DUT output terminal are received, The strobe signal is sequentially moved from the rear side to the front side, the presence / absence of a fail or the presence / absence of a pass is detected by a fail counter at each strobe movement position, and the Max position of the jitter trailing edge is obtained from the means. A semiconductor tester characterized by obtaining the difference between both jitter positions as the jitter width. 2. In a strobe signal of a timing comparison unit included in a semiconductor test apparatus and a jitter measurement of a device under test using a fail counter, a predetermined reference clock signal is output from the test pattern generator as D.
The strobe signal is supplied to the reference clock input terminal of the UT, the position of the strobe signal is initialized to the position on the trailing edge of the jitter where the fail counter does not detect fail, and the fail counter detects the fail for a predetermined time. If not, the timing position of the strobe signal is moved in the direction of detecting the jitter trailing edge and repeated. If the second fail is detected, the position of the strobe signal is obtained and stored as the Max position of the jitter trailing edge. , The fail counter detects all the failures, the position of the strobe signal is initialized to the position on the leading edge side of the jitter, the fail detection is performed by the fail counter for a predetermined time, and first, when all the failures are detected, the jitter is detected before the jitter. The timing position of the strobe signal is moved in the direction to detect the edge, and the strobe signal is repeatedly executed. If all the failures are not detected, the position of the strobe signal is obtained as the Min position of the jitter leading edge, and the difference between the Min position of the jitter leading edge and the Max position of the jitter trailing edge is obtained as the jitter width. Jitter measurement method. 3. In the jitter measurement of a device under test using a strobe signal of a timing comparison unit included in a semiconductor test apparatus and a fail counter, the Min position of the jitter leading edge and the jitter trailing edge are measured by the measuring method according to claim 2. The Max position is obtained, and a predetermined reference clock signal is output from the test pattern generator by D
When supplying to the reference clock input terminal of the UT, stop the output for a predetermined period or make an indefinite reference clock signal, then supply the original stable reference clock signal, and measure the elapsed time from the internal clock from this point, The position of the strobe signal is set to a predetermined position where fail detection is not performed adjacent to the Min position of the jitter leading edge or the Max position of the jitter trailing edge, which has been obtained in advance, and the count data of the fail counter is read out every unit minute time, A jitter measuring method, characterized in that an elapsed time when the count data does not change is obtained as a jitter stabilization time of the DUT. 4. A semiconductor test apparatus for measuring the jitter of a device under test using both strobe signals of a timing comparison section and a fail counter, and supplies a predetermined reference clock signal to a reference clock input terminal of a DUT. In response to the test pattern generator and the output signal from the DUT output terminal, one strobe signal is sequentially moved from the front side to the rear side, and the presence or absence of a fail is detected by the fail counter at each strobe moving position. A means for obtaining the Min position of the edge and an output signal from the DUT output terminal, and sequentially move the other strobe signal from the rear side to the front side, and detect the presence or absence of the fail by the fail counter at each strobe moving position. A means for obtaining the Max position of the trailing edge of the jitter, and The semiconductor testing apparatus and obtaining a partial as jitter width.