JP3412927B2 - Frame synchronization circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronizing circuit for fixed length frames.

[0002]

2. Description of the Related Art Conventionally, between transmitting and receiving devices (for example, between LSIs).
As a configuration method for establishing frame synchronization in the above, as shown in FIG. 10, each transmitting / receiving device 1101, 1102 is transmitted from a system different from the transmitting side device 1101 (for example, a clock generating device).
The frame synchronization signals FCLK1 and FCLK2 are respectively distributed to the three signal lines 11 between the transmission / reception LSIs.
03 to 1105 are wired to have substantially equal length, and each signal line 1103
~ 1105 is used to transmit data, a frame synchronization signal, and a bit clock, or as shown in FIG. 11, data lines 1123 between transmission / reception devices 1121 and 1122 are wired to have substantially equal lengths for transmission. Side device 110
Frame synchronization signals FCLK1 and FC from systems other than 1
There has been a configuration method of establishing frame synchronization by LK2.

On the other hand, without using the frame synchronization signal, a predetermined frame synchronization pattern is embedded in each frame,
There has been a method for frame synchronization while constantly searching for a synchronization pattern in the frame structure. For example, there is a synchronous digital hierarchy (SDH).

According to the first configuration method, it is only the paired data, the frame synchronization signal, and the bit clock that need to be equalized in the substrate. No wiring is required. However,
Due to the increase in the circuit scale, the number of wires between the transmitting and receiving devices has increased, which has been a factor of increasing the difficulty of board design. Further, when the transmission / reception device is an LSI, it has been a factor of increasing the number of pins.

Further, if the second configuration method is adopted, the number of wires to be wired between the transmitters and receivers can be reduced, but it is necessary to make the data wire lengths between all the transmitters and receivers equal, which results in a high transmission speed. This has been a factor that increases the difficulty of board design. In order to establish frame synchronization only from the frame synchronization signal distributed from another system, the delay until the data is transmitted to each receiving device is predicted in advance and the frame synchronization signal is distributed to each receiving device. There was a problem that it had to be.

Further, in the third method, since the receiving side apparatus always searches for the synchronization pattern, the transmitting side apparatus has a scramble transmission function in order to prevent false synchronization pull-in due to a synchronization pattern that happens to occur in the data. The side device requires a backward protection function, which causes a problem that the device configuration becomes complicated.

[0007]

As described above, the conventional frame synchronization system has a problem that the number of wires, the number of pins, and the difficulty of design between the transmitter and the receiver increase as the circuit scale increases. there were. Further, the method of detecting the frame synchronization pattern in the transmission data has a problem of false synchronization pull-in.

The present invention has been made in consideration of the above circumstances. A frame synchronization circuit capable of reducing the number of wirings and pins, avoiding false synchronization pull-in, and increasing the margin of equal-length wirings is provided. The purpose is to provide.

[0009]

SUMMARY OF THE INVENTION The present invention is a frame synchronization circuit for performing frame synchronization in a receiving side device, which is data for taking in transmission data having a predetermined frame length sent from a transmitting side device. A first frame based on an input unit, the transmission data taken in by the data input unit, and a first bit clock transmitted from the transmission side device together with the transmission data or extracted from the transmission data. Based on a frame synchronization signal detecting means for detecting a synchronization signal and a second frame synchronization signal and a second bit clock signal distributed and input from a device of a system different from the transmission side device, Frame synchronization determination period setting means for setting a frame synchronization determination period of a short predetermined length, and setting by the frame synchronization determination period setting means Within the frame synchronization determination period,
It is determined whether the first frame synchronization signal detected by the frame synchronization signal detection means is valid, and when it is determined that the first frame synchronization signal is valid, the enable indicating the output of data of a predetermined bit length from the data input means And a frame synchronization determining means for generating a signal. Further, the present invention is a frame synchronization circuit for performing frame synchronization in a receiving side device, wherein transmission data composed of a fixed length frame sent from a transmitting side device together with a first bit clock is transmitted to the first side. And a frame synchronization signal detection means for detecting a frame synchronization bit pattern included in the transmission data captured by the data input means and outputting a first frame synchronization signal. , A frame synchronization determination of a predetermined part of the transmitted fixed-length frame based on a second frame synchronization signal and a second bit clock signal distributed and input from a device different from the transmission side device. Frame synchronization determination period setting means for outputting a determination period signal indicating a period, and output from the frame synchronization signal detection means Whether the frame synchronization bit pattern detected by the frame synchronization signal detecting means is valid based on the first frame synchronization signal and the determination period signal output from the frame synchronization determination period setting means. It is characterized by further comprising frame synchronization determination means for generating an enable signal indicating an output of data of a predetermined bit length from the data input means when it is determined to be valid. Further, the present invention is a frame synchronization circuit for performing frame synchronization in the receiving side device, which is constituted by a plurality of storage elements connected in cascade and has been sent from the transmitting side device together with the first bit clock. Data input means for fetching transmission data composed of a fixed length frame in accordance with the first bit clock and outputting it in a predetermined bit length unit, and a predetermined consecutive bit length of the transmission data fetched by the data input means. Frame synchronization signal detecting means for inputting the data, comparing this data with a preset frame synchronization bit pattern of the predetermined bit length, and outputting a first frame synchronization signal when these match, A second device distributed and input from a device of a different system from the device on the transmission side.
Based on the frame synchronization signal and the second bit clock signal, the period in which the frame synchronization signal detecting unit detects the frame synchronization bit pattern is within a predetermined part of the transmitted fixed length frame. And a frame synchronization determination period setting means for outputting a determination period signal that is active during this period, and the frame synchronization determination period signal output from the frame synchronization determination period setting means while the determination period signal is active. It is reset when the first frame synchronization signal is input from the signal detection means, and the predetermined bit from the data input means is reset every time the bit length of the fixed length frame is counted according to the first bit clock. Frame synchronization determining means for generating an enable signal indicating the output of long data. The features.

Further, the frame synchronization circuit according to the present invention is
A data input unit that takes in transmission data composed of a fixed-length frame sent from the outside together with a bit clock according to the bit clock, and a frame synchronization bit pattern included in the transmission data taken in by the data input unit. Frame synchronization signal detection means for detecting and outputting a predetermined synchronization signal, and a predetermined portion in the transmitted fixed-length frame based on a frame synchronization signal input separately from the transmission data, for a frame synchronization determination period. Based on the determination period signal output from the frame synchronization determination period setting unit that outputs a determination period signal indicating as, the synchronization signal output from the frame synchronization signal detection unit and the frame synchronization determination period setting unit, The frame synchronization bit pattern detected by the frame synchronization signal detecting means. Wherein the chromatography emissions has and a frame synchronization determining means for determining if valid.

Further, the frame synchronization circuit according to the present invention is
A data input unit configured by a plurality of storage elements connected in cascade, taking in transmission data consisting of a fixed length frame sent from outside with a bit clock according to the bit clock, and outputting the data in a predetermined bit length unit; Data of a continuous predetermined bit length in the transmission data fetched by the data input means is input, and this data is compared with a preset frame synchronization bit pattern of the predetermined bit length, and these are coincident with each other. Frame sync signal detection means for outputting a predetermined sync signal in the case,
Based on a frame synchronization signal input separately from the transmission data, a period during which the frame synchronization signal detecting unit detects the frame synchronization bit pattern is within a predetermined period within the transmitted fixed-length frame. A frame synchronization determination period setting means that outputs a determination period signal that is set and is active during this period; and the frame synchronization signal while the determination period signal output from the frame synchronization determination period setting means is active. An enable signal which is reset when the synchronization signal is input from the detection means, and which outputs the data of the predetermined bit length from the data input means every time the bit length of the fixed length frame is counted according to the bit clock. And a frame synchronization determining means for generating a signal.

Further, preferably, the data input means extracts a bit clock from the transmission data sent from the outside, instead of inputting the bit clock from the outside.

Further, preferably, the data input means is composed of a plurality of storage elements connected in series to receive the transmission data, and a bit clock wired in equal length to the transmission data or the transmission data. It operates by the bit clock extracted from.

Further, preferably, the frame synchronization signal detecting means determines that a frame synchronization signal is detected when a frame synchronization bit pattern given to a specific position in the fixed length frame is detected. Is characterized by.

Further, preferably, the frame synchronization signal detecting means is an external device for changing a frame synchronization bit pattern provided at a specific position in the fixed length frame after a circuit design or a board design. A memory element is used so that the bit pattern can be set from the control processor.

Preferably, the frame synchronization signal detecting means detects a rising edge of the frame clock and detects frame synchronization when a frame clock is run in parallel with the transmission data from the transmitting side device. It is characterized by making a judgment.

Further, preferably, the frame synchronization determination period setting means limits frame synchronization determination time within one frame based on the frame clock and the bit clock distributed from the different series. It is characterized by having a function of generating a determination period setting signal.

Preferably, the frame synchronization determination period setting means is capable of changing the phase of the frame synchronization determination period setting signal after designing the circuit and the board.

Further, preferably, when there are a plurality of transmitting side devices, the frame synchronization determination period setting means has as many receiving side devices as there are transmitting side devices.

Further, preferably, the frame synchronization determination means performs frame synchronization determination based on the output from the frame synchronization signal detection means and the output from the frame synchronization determination period setting means, and from the determination result, the receiving side device It is characterized in that an enable signal for taking in the fixed length data is generated by a bit clock.

Further, preferably, the frame synchronization determination means is composed of a counter which operates with a bit clock of the receiving side device and a decoder which generates the enable signal, and the output of the frame synchronization signal detection means and the output of the frame synchronization signal detection means. It is characterized in that when both of the outputs of the frame synchronization determination period setting means are activated, the reset signal of the counter is used.

[0022]

In the present invention, first, the frame synchronization signal detecting means detects the frame synchronization signal based on the transmission data taken in by the data input means. On the other hand, the frame synchronization determination period setting means sets the frame synchronization determination in a period shorter than the frame length of the transmission data based on the frame synchronization signal distributed from a system different from the transmission data.

The frame synchronization determination means is effective when the frame synchronization signal detection means succeeds in detecting the frame synchronization signal during the frame synchronization determination period set by the frame synchronization determination period setting means. To determine.

As described above, according to the present invention, the frame synchronization determination period setting means is provided and the synchronization detection period is appropriately set to prevent erroneous synchronization pull-in due to the same bit pattern as the frame synchronization bit pattern that happens to appear in the data. Therefore, accurate frame synchronization detection can be performed by a simple method. For example, there is a shift in the wiring length of the transmission data line between the transmitting and receiving devices, and therefore, frame synchronization within the range (skew) from the phase at which the head of the frame arrives from the frame synchronization signal distributed to each LSI in the board from another system. Accurate synchronization detection can be performed by comparing with the pattern.

Further, according to the present invention, since the number of types of wiring required between the transmitter and the receiver is small, even if the circuit scale increases,
It is possible to avoid an increase in the number of wires and the number of pins of the LSI between the transmitting and receiving devices.

Further, since it is sufficient that the synchronization can be established within the synchronization detection period set by the frame synchronization determination period setting means, it is possible to perform the synchronization between the transmitting / receiving devices, for example, each LSI on the same substrate.
The wiring length of the transmission data line during this period can be kept within a certain range, and the margin of the equal length wiring can be increased.

[0027]

Embodiments will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a schematic block diagram showing a frame synchronization circuit according to the first embodiment of the present invention. A timing chart of main signals in this embodiment is shown in FIG. Further, it is assumed that the frame sync signal indicates the beginning of the frame at the rising edge.

The frame synchronization circuit of this embodiment is built in a receiving side device (eg LSI), and operates by a bit clock BCLk in transmitted from a transmitting side device (eg LSI) (not shown). 10
0, the frame synchronization signal detection unit 200, the frame synchronization determination unit 300, and the bit clock BCLk Mai distributed from a system different from the transmission side device (for example, a clock generation device).
The frame synchronization determination period setting unit 400 operates at n.

As shown in FIG. 8, the data input section 100 takes in the data Data in transmitted from the transmitting side device in accordance with the bit clock BCLk in, and takes n bits which is the frame synchronization pattern length from the taken in data Data in. Minute parallel data Sync Pat is output while shifting by 1 bit at a time, and output data D
ata in to N (eg 1 or 8, 16, 32, 6
4 bits, etc.) are sequentially output as data Data Main for bits.

The data input section 100 is, for example, as shown in FIG.
The storage elements (for example, flip-flop circuits) 101 are connected in series as described above. The n bits sent to the frame synchronization signal detection unit 200 match the predetermined frame synchronization pattern length. The bit width N of Data Main sent to the main body of the receiving side device such as an LSI is determined only by its internal processing. However, it is a divisor of the bit length of the data Data in. A position where data to be sent to the frame synchronization detection unit 200 is extracted in the shift register constituted by the storage element 101;
The relationship with the position output as ata Main is the number of bits (predetermined) between the frame synchronization pattern and the data that actually needs to be fetched (see FIG. 2B) and the frame synchronization determination unit 300 described later. Decoder 30 in
3 depends on how many count values generate the enable signal. For example, when the Stuff bit is 0 bit and the decoder in the frame synchronization signal determination unit 300 generates an enable signal with a count value of 1, it becomes as shown in FIG.

The bit clock BCLk in may be extracted from the data Data in in addition to the case where the bit clock BCLk in runs in parallel with the data line from the transmission side device. The frame synchronization signal detection unit 200 outputs the parallel data Sync Pat from the data input unit 100 to the bit clock BCLk i of the transmission side device.
Matching pulse SYNC is acquired only when the n-bit data matches the frame synchronization pattern.
Is generated and sent to the frame synchronization determination unit 300.

FIG. 3 shows an example of the internal structure of the frame synchronization signal detecting section 200. When the frame synchronization pattern is previously determined to be “00000001” at the time of circuit design and the like, and the 8-bit pattern from the data input unit 100 matches the frame synchronization pattern, FIG.
Then, the SYNC signal is activated and sent to the frame synchronization determination unit 300.

FIG. 4 shows an example of the structure in which the frame synchronization pattern can be changed after the circuit design or the board design, and is for comparing with the data from the storage element 201 and the data input unit 100 for the frame synchronization pattern length. It is composed of gate elements 202 and 203. The storage element 201 for the frame synchronization pattern length can be set to an arbitrary value by the external control processor.
Only when the value from 1 and the value from the data input unit 100 match, the match signal SYNC is activated and sent to the frame synchronization determination unit 300.

FIG. 5 shows the frame synchronization determination period setting section 40.
An example of the internal configuration of 0 is shown. Further, FIG. 6 shows the relationship between the output signal GWND shown in FIG. 8 and one frame period.
The frame cycle determination period setting section 400 includes a 1-frame cycle counter section 402, a decoder section 403 which receives the output signal of the 1-frame cycle counter section 402 as an input, and a reset pulse generation for generating a reset signal to the 1-frame cycle counter section 402. The frame period signal F which is composed of the circuit 401 and is distributed from a system different from that of the transmitting side device.
It operates by CLK Main and bit clock BCLK Main.

The 1-frame cycle counter section 402 can count the bit clock BCLK Main from 0 to (bit length within 1 frame-1), and outputs the count value. When the output of the reset pulse generation circuit 401 becomes active, it is determined that the frame is at the head, the counter value is reset, and counting is repeated. In addition,
When one frame is transmitted in parallel between the transmitting and receiving devices, the one-frame cycle counter unit 402 may be capable of count calculation up to (bit length of one frame / parallel width).

The decoder section 403 generates a GWND signal as shown in FIG. 8 in a certain period within one frame of the data Data in from the transmission side device. That is, the output of the 1-frame cycle counter unit 402 is the decoder unit 403.
Asserts a GWND signal when it matches a preset first count value (C1 in FIG. 6), and then the output matches a preset second count value (C2 in FIG. 6) Then, the GWND signal is deasserted.

When there are a plurality of transmitting side devices, the skew of the data Data in from each transmitting side device is GWND.
It only needs to fit within the signal width.
Therefore, when they are mounted on one board or one housing, board design and the like become easy. Further, as one configuration example in which there are a plurality of transmitting side devices and the skew of each transmission data is relatively large, a plurality of frame synchronization determination period setting units 400 may be provided corresponding to each transmitting side device. Further, after the board is designed or the case is assembled, the period for activating the GWND signal by flowing the cell for frame synchronization may be set when the system is started up.

The reset pulse generation circuit 401 detects the rising edge of the frame cycle signal FCLK Main distributed from another system and sends a reset signal to the 1-frame cycle counter section 402 at the rising edge. By allowing the phases of the frame cycle signal FCLK Main and the bit clock BCLK Main to be changed after the board design or the housing design, it is possible to deal with the case where the data delays between the respective transmitters / receivers deviate in the same direction.

FIG. 7 shows an example of the internal configuration of the frame synchronization determination section 300. The frame synchronization determination unit 300
1-frame cycle counter section 302, and decoder section 3 using the output signal of the 1-frame cycle counter section 302 as an input
03, a reset pulse generation circuit 301 for generating a reset signal for the 1-frame cycle counter 302.

The 1-frame cycle counter section 302 receives the bit clock BCLk in transmitted from the transmitting side device,
Counting from 0 to (bit length within one frame-1) is possible, and the count value is used as its output. When the output of the reset pulse generation circuit 301 becomes active, it is determined that the frame is at the head, the counter value is reset, and counting is repeated.

The decoder section 303 generates an enable signal Enable for instructing the data Data Main from the data input section 100 as shown in FIG. 8 in one frame cycle based on the output value of the one frame cycle counter section 302. That is, the enable signal Enable is asserted when the output of the 1-frame period counter unit 302 matches the first count value set in advance in the decoder unit 303, and then the output is set to the second count value set in advance. The operation of deasserting the enable signal Enable when the numerical values match is repeated. Note that the 1-frame cycle counter unit 302 may be configured by a counter for the internal incorporation width instead of the above configuration. For example, when incorporating with a 16-bit width, a 4-bit counter may be provided and the decoder unit 303 may generate the enable signal Enable when the value is a predetermined value from 0 to 15.

The enable signal Enable depends on the output format of the data Data Main from the data input unit 100. For example, when it is desired to output the data from the data input unit 100 in a bit-serial manner, the enable signal Enable is set for each bit. When it is desired to generate and output as 8-bit parallel data, the enable signal Enable is generated every 8 bits. Note that if the data format in one frame is determined, an operation of not capturing a part of data in one frame is also possible.

The reset pulse generating circuit 301 has a one-frame period counter section 30 only when both the SYNC signal from the frame period signal detecting section 200 and the GWND signal from the frame synchronization determination period setting section 400 are active.
Send a reset signal to 2. By taking the logical sum of the above two signals, it is possible to prevent erroneous synchronization due to the same pattern as the frame synchronization bit pattern that happens to occur in the data Data in.

As described above, according to the present embodiment, by properly setting the synchronization determination period, it is possible to prevent erroneous synchronization pull-in caused by the same bit pattern as the frame synchronization bit pattern that appears in the data by accident, and to transmit / receive data. Since the number of types of wiring required between the devices is small, even if the circuit scale increases, it is possible to avoid an increase in the number of wirings between the transmission / reception devices and the number of pins of the LSI. Since it is only necessary to establish synchronization within the synchronization detection period that is set, the wiring length of the transmission data line between the transmitter and receiver can be kept within a certain amount, and the margin for equal length wiring should be increased. You can

(Embodiment 2) FIG. 9 is a schematic block diagram of a frame synchronization circuit according to a second embodiment of the present invention.

The frame synchronizing circuit of the present embodiment operates by the data input section 10 which operates by the bit clock BCLk in transmitted from a transmitting side device (eg LSI) not shown.
0 ′, a frame head position detection unit 500, a frame synchronization determination unit 300, and a frame synchronization determination period setting unit 400 that operates with a bit clock BCLk Main distributed from a system different from the transmission side device.

The data input section 100 'has the same structure as the data input section 100 of the first embodiment except that it has n bits of parallel data Sy.
The configuration corresponding to the function for outputting nc Pat is omitted. The frame synchronization determination unit 300 and the frame synchronization determination period setting unit 400 are the same as those in the first embodiment.

In the first embodiment, the SYNC signal is generated by the frame sync signal detection unit 200 upon detection of coincidence between the parallel data Sync Pat fetched from the data input unit 100 and a predetermined frame sync pattern. On the other hand, in the present embodiment, the frame synchronization signal FCLKin is given from the transmission side device to the reception side device by using the signal line wired to the data line with substantially equal length, and the frame head position detection unit 500 shown in FIG. At the rising edge of the frame synchronization signal FCLK in, the bit clock BCLK in
According to the above, it is sent to the frame synchronization judging section 300 as a coincidence signal SYNC.

Even with this configuration, frame synchronization can be established. Further, the present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention.

[0050]

As described above, according to the present invention, by providing the frame synchronization determination period setting means and appropriately setting the synchronization detection period, erroneous synchronization pull-in by the same bit pattern as the frame synchronization bit pattern that happens to occur in the data is obtained. It is possible to prevent the above, and it is possible to perform accurate frame synchronization detection by a simple method.

Further, according to the present invention, since the number of types of wiring required between the transmitter and the receiver is small, even if the circuit scale increases,
It is possible to avoid an increase in the number of wires and the number of pins of the LSI between the transmitting and receiving devices.

Further, since it suffices that the synchronization can be established within the synchronization detection period set by the frame synchronization determination period setting means, it is possible to perform transmission / reception devices, for example, each LSI on the same substrate.
The wiring length of the transmission data line during this period can be kept within a certain range, and the margin of the equal length wiring can be increased.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a frame synchronization circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of an internal configuration of a data input unit.

FIG. 3 is a diagram showing an example of an internal configuration of a frame synchronization signal detection unit.

FIG. 4 is a diagram showing another example of the internal configuration of the frame synchronization signal detection unit.

FIG. 5 is a diagram showing an example of an internal configuration of a frame synchronization determination period setting unit.

FIG. 6 is a diagram showing an example of a window signal GWND.

FIG. 7 is a diagram showing an example of an internal configuration of a frame synchronization determination unit.

FIG. 8 is a timing chart of main signals of the first embodiment.

FIG. 9 is a diagram showing a schematic configuration of a frame synchronization circuit according to a second embodiment of the present invention.

FIG. 10 is a diagram showing a first configuration of a conventional example.

FIG. 11 is a diagram showing a second configuration of a conventional example.

[Explanation of symbols]

100 ... Data input section, 101 ... Storage element, 200 ... Frame synchronization signal detection section, 201 ... Storage element, 202, 2
03 ... Gate element, 300 ... Frame synchronization determination unit, 30
DESCRIPTION OF SYMBOLS 1 ... Reset pulse generation circuit, 302 ... 1-frame period counter section, 303 ... Decoder section, 400 ... Frame synchronization determination period setting section, 401 ... Reset pulse generation circuit,
402 ... 1-frame cycle counter section, 403 ... Decoder section, 500 ... Frame start position detection section

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-38026 (JP, A) JP-A-4-185129 (JP, A) JP-A 64-4135 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H04L 7/08 H04J 3/06

Claims (3)

(57) [Claims] 1. For performing frame synchronization in a receiving device
A frame synchronization circuit, the data input means for taking in transmission data having a predetermined frame length sent from the transmitting side device, the transmission data taken in by the data input means ,
And sent from the transmission side device together with the transmission data
The first bit clock that came or was extracted from the transmitted data.
A first frame the frame synchronization signal detecting means for detecting a synchronizing signal based on the click, a second frame synchronization signal and the second bit clock signal wherein the transmitting-side apparatus that has been input is distributed from the device of another system
Based on the item, and the frame synchronization determination period setting means for setting a full <br/> frame synchronization determination period of the frame length shorter than a predetermined length, a frame synchronization determination period set by the frame synchronization determination period setting means It is determined whether the first frame synchronization signal detected by the frame synchronization signal detection means is valid, and if it is determined that the first frame synchronization signal is valid , the data
Data output of a predetermined bit length from the input means
A frame synchronization circuit comprising: a frame synchronization determination means for generating an enable signal . 2. For performing frame synchronization in a receiving device
A frame synchronization circuit, a transmission data composed of the first fixed-length frame transmitted with the bit clock from the sending device, a data input means for loading in accordance with the first bi <br/> Ttokurokku, the data input the detected frame synchronization bit pattern included in said transmission data fetched by means
Frame synchronization signal detecting means for outputting a frame synchronization signal, a second frame synchronization signal and the second bit clock signal, wherein the transmitting device is distributed input from a device of another system
According to a predetermined number in the transmitted fixed length frame,
A frame synchronization determination period setting means for outputting a determination period signal indicating a first portion as a frame synchronization determination period, the frame output from the synchronization signal detection means the first
Of the frame synchronization signal and the determination period signal output from the frame synchronization determination period setting means, it is determined whether the frame synchronization bit pattern detected by the frame synchronization signal detection means is valid, Size
If the specified bit from the data input means is
A frame synchronization circuit, comprising: a frame synchronization determination means for generating an enable signal indicating the output of the data having a frame length . 3. For performing frame synchronization in a receiving device
A frame synchronization circuit is constituted by a cascaded plurality of storage elements, the transmission side
The transmission data composed of the first fixed-length frame transmitted with the bit clock from the device, takes in accordance with the first bit clock, a data input means for outputting a predetermined bit length unit, taken at the data input means The continuous data of the predetermined bit length in the transmitted transmission data is input, this data is compared with the preset frame synchronization bit pattern of the predetermined bit length, and if they match, the first
Frame synchronization signal detecting means for outputting a frame synchronization signal, and a second frame synchronization signal and a second bit clock signal distributed and input from a device of a different system from the transmission side device.
The period during which the frame synchronization bit pattern is detected by the frame synchronization signal detection means,
A frame synchronization determination period setting means for setting within a predetermined part of the transmitted fixed length frame and outputting a determination period signal active during this period, and an output from the frame synchronization determination period setting means. It is reset when the first frame synchronization signal is input from the frame synchronization signal detection means while the determination period signal is active, and is reset by the bit length of the fixed length frame according to the first bit clock. Frame synchronization determining means for generating an enable signal indicating the output of the data of the predetermined bit length from the data input means each time the frame synchronizing circuit is counted.