JP3409049B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a semiconductor memory device including memory cells having a main / sub bit line structure and reducing variations in threshold value when writing data.

[0002]

2. Description of the Related Art In a nonvolatile semiconductor memory such as a flash memory having a floating gate transistor as a memory cell, there is one called a main / sub bit line structure as one of the methods for forming a memory cell array. This structure is a kind of NOR type array in which cells are connected in parallel. N
The OR type array is such that the drains and sources of a plurality of memory cells are connected in parallel to a set of bit lines and ground wirings, and different word lines are connected to the control gates of the plurality of memory cells. is there. As one method of manufacturing this structure on a semiconductor substrate, there is a method of forming contact holes and connecting the bit lines, metal wirings serving as ground wirings, and the impurity diffusion layers forming the drains and sources of the memory cells. As another method, there is a method of forming a bit line and a ground line by diffusion layer wiring continuous from the drain and source of the memory cell. The former has a problem that the cell array area becomes large because each memory cell has a contact. Further, in the latter case, there is a problem that the load due to the resistance and parasitic capacitance of the bit line and the ground wiring becomes high, which adversely affects the operation speed.

As a solution to such problems,
A main / sub bit line structure has been proposed. This main / sub bit line structure reduces the cell array area by connecting a group of a certain number of memory cells with diffusion layer wiring (sub bit line), while the metal of each group of the one group of memory cells is reduced. It is connected to the wiring (main bit line) to prevent the increase of square load. A memory array having such a main / sub bit line structure is disclosed in Japanese Patent Laid-Open No. 181298/1994. An example of such a main / sub bit line structure is shown in the circuit diagram of FIG. 5 and the layout diagram of FIG. In this configuration, as shown in FIG. 5, 16 memory cells m301 to m316 are grouped into a sub-bit line S formed by a diffusion layer.
B3 and a sub ground line SG3 are connected in parallel, transfer gates TG and TB are arranged on both sides thereof, and the main bit line MB3 made of metal wiring and the ground line GND are connected through the transfer gates. In addition, the memory cells m301 to m3
16 control gates have word lines W301 to W3
16 are connected. Furthermore, the transfer gate TG,
Select signal lines S1 and S2 are connected to TB.

In FIG. 6, reference numeral 1 is a diffusion layer, and 201 and 21.
5, 216 are floating gates of the memory cells, 30
1, 315, 316 are word lines (W301, W315, W316) that also serve as control gates of the memory cells,
Further, 41 is a selection signal line (S31) that also serves as the gate of the transfer gate TG, and 42 is the transfer gate TB.
, A selection signal line (S32) also serving as a gate, a contact 51 to the main ground wiring, and a contact 52 to the main bit line. As shown in the figure, since there is no contact between m301 to m316, the size can be reduced. Further, since the metal wiring has a lower resistance than that of the diffusion layer wiring, the load is reduced as compared with the case where the whole of the diffusion layer wiring is used, so that the operation speed is less affected.

[0005]

By the way, a method called channel hot electron (CHE) method is often used in the case of a NOR type array as a method of burying data in a flash memory. In this method, a large current is caused to flow between the drain and source of the memory cell, and hot electrons generated there are injected into the floating gate. The voltage applied to the drain and the control gate at this time is selected to be a certain value in consideration of the threshold value of the memory cell after writing and the writing time. In this case, in the flash memory that stores binary data, the threshold value after writing has only to become a certain value or more, and the width of the variation has not been considered so much. However, in recent years, attention has been paid to a multi-valued memory technology for storing data of three or more values in one memory cell. In such a multi-valued memory, it is necessary to reduce the variation in the threshold value, but it is difficult to control the variation in the threshold value when writing by the CHE method with the conventional main / sub bit line structure. Is occurring.

This is partly due to variations in the voltage applied to each cell during writing, in addition to variations in the characteristics of the memory cell transistors. The diffusion layer forming the sub bit line usually has a resistance of several tens to several hundreds Ω / □. In FIG. 5, SG3 and SB3 are resistances between memory cell transistors, Rj = RG3X = RB3X (X = 1 to 1).
Have 5). When the write current is i, a potential difference of ΔVx = RG3X · i = RB3X · i is generated in each transistor. As a result, the source potential of the memory cell m316 rises by 15 · ΔVx as compared with m301. The potential difference between the respective electrodes with respect to the source is important for the operation of the transistor. However, in this conventional structure, all word line voltages Vw at the time of writing were constant, so that the actual m31
The gate-source potential difference of 6 is VGS16 = VGS1-1
It becomes 5 · ΔVx. Therefore, compared to the gate-source potential difference VGSl of m301 in which the source does not float,
There is a voltage drop of 15 · ΔVx. On the other hand, the drain-source voltage of the m316 is 15 on the source side.
・ ΔVx floats up, but in m301, the voltage on the drain side drops by 15 · ΔVx, so the voltage is the same. In other memory cells, the voltage rises on the source side and drops on the drain side, and the voltage is the same as m301 and m316.

As a result, the voltage between the drain and the source is the same from m301 to m316, and the voltage between the gate and the source is different by ΔVx. The write characteristics in such a state are shown in FIG. Even with the same drain-source voltage, the writing speed becomes slower as the gate-source voltage becomes lower. Therefore, the threshold value has a variation of dvt at a constant writing time tl, and the writing time has a variation of dt at a certain threshold value.

An object of the present invention is to provide a non-volatile semiconductor memory device having a good controllability, which is suitable for a multi-valued memory by reducing a threshold variation at the time of writing to a memory cell.

[0009]

Means for Solving the Problems The present invention, respectively spreading
Bit line and ground line composed of layers and formed in parallel
And is connected in parallel between the bit line and the ground line.
Had a plurality of nonvolatile semiconductor memory cells, and the <br/> Each Memoruseru is connected different word lines, respectively,
In a memory device in which a required voltage is applied to the word line to write data to the memory cell,
The voltage applied to the word line of each memory cell at the time of writing data is generated by the parasitic resistance of the ground line.
As the voltage rises, the gate
Different voltages are set so that the potential difference between the sources becomes constant . That is, the memory cell includes the bit line and
The bit line and the ground line are arranged at regular intervals along the extension direction of the ground line, the bit line and the ground line have the same parasitic resistance R1 between adjacent memory cells, and the voltage applied to the word line is the data write level. When the current flowing through the bit line is i1 at times, ΔV1 (= R
The relationship is set to have a potential difference of 1 · i1).

Further, the present invention comprises a diffusion layer.
The bit line and the ground line formed in parallel with the
A plurality of lines connected in parallel between the output line and the ground line.
A non-volatile semiconductor memory cell, and which is connected is different from the word line respectively to each Memoruseru, in a memory device for writing data to said word line to said memory cell is required voltage is applied, the memory cell They are divided into groups for each of the plurality of memory cells along the extension direction of the bit line and the ground line, writing data
The same voltage is applied to the word lines of the memory cells in each group at the same time, and to the ground line between the groups.
In response to the voltage rise caused by the parasitic resistance in
Gate-source in corresponding memory cell of group
Different voltages are set so that the inter-potential difference becomes constant . That is, the memory cell is connected to the bit line and the ground.
The bit lines and the ground lines are arranged at regular intervals along the extension direction of the line, and the bit line and the ground line have an equal parasitic between adjacent memory cells.
The resistor R1 has a voltage applied to the word line from the bit line through a memory cell when writing data.
The current flowing through the ground line and i2 Te, for each group
When the number of memory cells is n, the relationship is set to have a potential difference of ΔV2 (= n · R1 · i2 ) between adjacent groups.

Here, the bit line is configured as a sub bit line of a memory device having a main / sub bit line structure.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention, and the circuit configuration is the same main / sub bit line structure as the conventional configuration of FIG. That is, 1 as one group
Six memory cells m101 to m116 are connected in parallel by a sub-bit line SB1 and a sub-ground line SG1 formed of a diffusion layer, transfer gates TG and TB are arranged on both sides of the sub-bit line SB1, and transfer gates TG and TB are arranged. Connect to the line MB1 and the ground line GND. Here, the memory cells m101 to m116 are arranged at equal intervals in the extending direction of the sub bit line SB1 and the sub ground line SG1. The word lines W101 to W116 are connected to the control gates of the memory cells m101 to m116. Further, select signal lines S1 and S2 are connected to the transfer gates TG1 and TB1. Further, the layout configuration is also the same as the configuration shown in FIG. 6, and thus detailed description will be omitted.

On the other hand, in contrast to the main / sub bit line structure, in this embodiment, all the word line voltages in the sub bit line group applied at the time of writing are different. The relationship is that each word line voltage Vw applied to n memory cells of the first, second, ..., Nth (n is an integer of 2 or more)
(J) [j = 1 to n: the same applies hereinafter] has a relationship of Vw (j) = Vw (j−1) + ΔV1 which has a difference of a constant voltage ΔV1 with respect to the reference first memory cell. Has been set to a voltage. In the case of this embodiment, the resistances RB101 to RB between the memory cells in the diffusion layers of the sub-bint line SB1 and the sub-ground line SG1 between the adjacent word lines are based on the voltage Vwl0l of the word line W10l.
115 and resistance values R1 of RG101 to RG115,
It is set so as to have a difference ΔV1 = i1 · R1 for the floating of the source due to the current i1 at the time of writing.

By selecting the word line voltage in this way, the drain-source voltage is the same from m101 to m116 and the gate-source voltage is different by ΔV1 depending on the resistance of the diffusion layer forming the sub-bit line SB1. Even if there is a state, there is a difference in the gate voltage by ΔV1 correspondingly, and as a result,
The potential difference between the gate and the source becomes equal in all cells. As a result, as shown in FIG. 2, the write characteristic reduces the variation dvt in the threshold value, reduces the variation in the write time dt, and improves the controllability.

FIG. 3 is a circuit diagram of the second embodiment of the present invention, and the basic circuit configuration and layout are the same as those of the first embodiment. This embodiment is different from the first embodiment in that the word line is divided into two or more groups and the word voltage is set for each group. That is, in FIG. 3, m201 to m216 are memory cells, W201 to W216 are word lines, TB and TG are transfer gates, S1 and S2 are selection signal lines, MB2 is a main bit line, SB2 is a sub bit line, and GND is ground. Wiring, S
G2 is a sub ground line. Then, the word line is divided into two groups of word line groups WG21 and WG22 of memory cells m201 to m208 and m209 to m216, and different voltages are applied to the word line groups WG21 and WG22 of each group. Potential difference Δ between these word line groups
V2 is the resistance RB201 to RB21 between the memory cells in each diffusion layer of the sub bit line SB2 and the sub ground line SG2.
5, each resistance value of RG201 to RG215 is R1, the resistance R2 between groups is R for eight memory cells.
Since 2 = 8 · R1, resistances RG201 to RG20
Considering the potential difference up to 8, when the current i2 during writing is set, ΔV2 = 8 · i2 · R1 = i2 · R2 is set.

According to this structure, the potential difference due to the diffusion layer resistance occurs in each group, but m201 and m20
9, m208 and m216 have the same gate-source potential difference. As a result, the write characteristics for the memory cells are as shown in FIG. 4, and the variation dvt in the threshold value and the variation in the write time dt are substantially within the variation range of the memory cells m201 to m208. The controllability is improved as compared with the conventional configuration shown in FIG. In addition, unlike the first embodiment, 16 types of word line voltages are not required in this embodiment, and only two types of word line voltages are required. It has a feature that variation can be reduced.

Here, in each of the above-described embodiments, an example in which one memory cell group is composed of 16 memory cells has been shown, but the number is not limited to this. Further, even when the word lines are grouped, it is possible to divide the word lines into groups like the second embodiment.
The number is not limited to one group, and can be set to any number according to the circuit scale for voltage adjustment.

[0018]

As described above, according to the present invention, a plurality of memory cells are connected in parallel between the bit line and the ground line.
Different word lines to each memory cell.
Data is applied to the memory cell by applying the required voltage.
In a non-volatile semiconductor memory device that writes
Ground line rather than uniformly each word line voltage during the writing
There is an effect that the variation in the threshold value of the memory cell after writing can be reduced by making the resistance different depending on the parasitic resistance . That is, the voltage of each word line of the memory cells arranged along the bit line and the ground line is changed to the parasitic resistance of the ground line.
By setting different voltages corresponding to the voltage increase caused by the resistance, the potential difference between the gate and the source in each memory cell can be made equal, and the variation in the threshold value in the memory cell can be reduced. In addition, the memory cells arranged along the bit line and the ground line are divided into groups, and the word line voltage of each group is increased by the parasitic resistance of the ground line.
By correspondingly setting different voltages, it is possible to equalize the gate-source potential difference of the corresponding memory cells in each group, and it is possible to reduce the variation in the threshold value of the memory cells between the groups.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a write characteristic diagram of the memory cell according to the first embodiment.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a write characteristic diagram of a memory cell according to the second embodiment.

FIG. 5 is a circuit diagram of an example of a conventional nonvolatile semiconductor memory device.

FIG. 6 is a layout diagram of the memory device of FIG.

FIG. 7 is a write characteristic diagram of a memory cell of the memory device of FIG.

[Explanation of symbols]

m101 to m116 memory cells W101 to W116 word lines MB1 Main bit line SB1 Sub bit line GND main ground wire SG1 Sub ground wire RG101 to RG115 Diffusion layer resistance RB101 to RB115 Diffusion layer resistance m201 to m216 memory cells W201 to W216 word lines MB2 Main bit line SB2 Sub bit line SG2 Sub ground wire RG201 to RG215 Diffusion layer resistance RB201 to RB215 Diffusion layer resistance WG21, WG22 Word line group TG, TB transfer gate

Claims (7)

(57) [Claims] 1. Each of the diffusion layers is formed in parallel.
Formed bit line and ground line, and the bit line and the connection
Multiple non-volatile semiconductors connected in parallel with the ground line
A memory cell, and wherein in each Memoruseru respectively
A different word line is connected, in a memory device for writing data to the memory cells required voltage is applied to the word line, the voltage applied the when writing data to a word line of each memory cell, the ground
Corresponding to the voltage rise caused by the parasitic resistance of the line,
The gate-source potential difference in the memory cell becomes constant
As described above, the nonvolatile semiconductor memory device is set to different voltages. Wherein said memory cell is constituted by a MOS transistor having a floating gate and a control gate, is the word line to the control gate before the SL memory cell is connected, the voltage applied to the word line, the
The non-volatile semiconductor memory device according to claim 1, wherein the gate-source potential difference in each memory cell is set to a constant voltage corresponding to a rise in the source potential of each memory cell caused by a parasitic resistance in the ground line . 3. The memory cell is connected to the bit line and the contact.
The bit line and the ground line are arranged at regular intervals along the extending direction of the ground line, the bit line and the ground line have the same parasitic resistance R1 between adjacent memory cells, and the voltage applied to the word line is
Via the memory cell from the bit line when writing data
3. The non-volatile semiconductor memory device according to claim 2, wherein a relation of ΔV1 (= R1 · i1) is established between adjacent memory cells when the current flowing through the ground line is i1. 4. Each of the diffusion layers is formed in parallel.
Formed bit line and ground line, and the bit line and the connection
Multiple non-volatile semiconductors connected in parallel with the ground line
A memory cell, and wherein in each Memoruseru respectively
In a memory device in which different word lines are connected and a required voltage is applied to the word lines to write data to the memory cells, the memory cells include a plurality of memories along an extension direction of the bit lines and ground lines. The cells are divided into groups, the same voltage is applied to the word lines of the memory cells in each group when writing data , and the parasitic resistance in the ground line between each group.
Correspondence of each group corresponding to the voltage rise caused by
The gate-source potential difference in the memory cell is constant
The non-volatile semiconductor memory device is set to different voltages so that Wherein said memory cell is constituted by a MOS transistor having a floating gate and a control gate, is the word line to the control gate before the SL memory cell is connected, the voltage applied to the word line, the
5. The non-volatile according to claim 4, wherein the gate-source potential difference in the corresponding memory cells of each group is set to a constant voltage corresponding to a rise in the source potential of each memory cell caused by the parasitic resistance in the ground line . Semiconductor memory device. 6. The memory cell includes the bit line and ground.
The bit lines and the ground lines are arranged at regular intervals along the line extension direction, and the bit line and the ground line have an equal parasitic between adjacent memory cells.
The resistor R1 has a voltage applied to the word line from the bit line through a memory cell when writing data.
The current flowing through the ground line and i2 Te, for each group
6. The nonvolatile semiconductor memory device according to claim 5, wherein the relationship is set to have a potential difference of ΔV2 (= n · R1 · i2 ) between adjacent groups, where n is the number of memory cells . 7. The non-volatile semiconductor memory device according to claim 1, wherein the bit line is configured as a sub bit line of a memory device having a main / sub bit line structure.