JP3406485B2 - CDMA communication device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention has recently attracted attention due to its high frequency utilization efficiency, confidentiality, adaptability to variable data rates for multimedia communication, etc.
(Code Division Multiple A
access (code division multiple access) system, that is, in the transmitting device, after the data modulation, this modulated signal is further spread-modulated with the spreading code and transmitted, and in the receiving device, despreading is performed with the same spreading code as the transmitting side. After that, the present invention relates to a CDMA communication device to which a method of performing data demodulation processing and the like is applied.

[0002]

2. Description of the Related Art FIG. 8 shows an example of a channel structure of a CDMA system corresponding to a variable data rate of a signal used in a conventional CDMA communication device disclosed in Japanese Patent Laid-Open No. 7-312783. However, in the CDMA system, since communication channels on the same frequency are separated by using different spreading codes, interference from other channels becomes a major factor that determines the transmission quality of the system. Therefore, in a silent period during a voice call or in variable data rate communication,
The transmission rate of the transmission information is lower than the transmission capacity of the channel,
In an empty section where there is no information, it is operated so as to stop transmission and suppress interference on other channels.

Therefore, the information signal to be transmitted is divided into a group of frames and further divided into slots, which are the basic unit of data transmission on the physical channel, before being transmitted. In FIG. It shows the case of being divided into slots. Further, when the data rate of the transmitted information signal fluctuates, the amount of data in the frame is appropriately changed according to the amount of fluctuation.

FIG. 8A shows a state in which data is inserted in all one frame when the channel capacity and the data rate of the information signal are the same, that is, when the information signal rate is 100% of the channel capacity. Is shown. (B) shows the case where the information signal rate is 50% of the channel capacity, (c)
Is a case of 25%. In these cases, there is an empty section of data indicated by a blank in the slot to be transmitted, and transmission is stopped in the empty section.

(D) shows the contents of the slot, and OH (overhead) is data used for control and error correction. For example, demodulation pilot symbols, transmission power control data, and rate information. , CRC (C
For example, it is a cylic redundancy check (error detection) code. DATA is an information signal to be transmitted, and EMPTY is an empty section.

FIG. 9 is a block diagram of a transmitter in a conventional CDMA communication apparatus. In the figure, reference numeral 1 denotes convolutional coding and interleaving for information error correction on an information signal S1 to be transmitted. Convolutional coding / interleaving circuit 2 is a frame generation circuit for generating a frame signal by adding a control signal S2 to the output signal of convolutional coding / interleaving circuit 1.

Reference numeral 3 denotes a slot mapping circuit for performing mapping for allocating data to each slot of the frame signal output from the frame generation circuit 2, and reference numeral 4 denotes data mapped by the slot mapping circuit 3, for example, BPS.
K (Binary Phase Shift Keyi
ng) and the like, and outputs the modulated data to the spread modulation circuit 5. The data modulation circuit 5 performs spread modulation on the data modulated by the data modulation circuit 4 with a spread code, and 6 indicates the spread modulation circuit 5. An RF / IF unit that transmits spread-modulated data at a predetermined radio frequency via an antenna.

FIG. 10 is a block configuration diagram of a receiving device in a conventional CDMA communication device. In the figure, 9 receives a signal sent from the transmitting device shown in FIG. 9 at a predetermined frequency via an antenna. RF / IF section, 10 is R
A quadrature detection circuit that quadrature-detects the signal received by the F / IF unit 9 and further converts it into a baseband signal. Reference numeral 11 denotes a signal that has been converted into a baseband signal by the quadrature detection circuit 10 using a matched filter or a sliding correlator. It is a despreading circuit that despreads using the same spreading code as that on the transmitting side and restores a data-modulated signal.

Reference numeral 12 is a demodulation / rake combination circuit for demodulating the respective propagation paths (signals) despread by the despreading circuit 11 and RAKE combination, which will be supplementarily described later, to remove data modulation, and 13 is a demodulation.・ Rake synthesis circuit 1
The output signal of No. 2 is used to measure the SIR, which is the ratio of the desired wave signal power to the interference and thermal noise signal power, as described on page 58 of IEICE Technical Report RCS96-74, for example. It is a SIR measurement circuit.

Reference numeral 14 separates a part corresponding to the control signal S2 added on the transmission side from the output signal of the demodulation / rake combination circuit 12, outputs it as a signal S3, and deinterleaves the information signal part. A frame demultiplexing circuit for outputting to the decoding circuit 15, a deinterleaved Viterbi decoding circuit 15 for performing Viterbi decoding after releasing interleaving performed on the transmission side and outputting a received information signal S4, and 16 for deinterleaved Viterbi decoding Determine the received data rate using the output signal of the circuit 15,
It is a rate determination circuit that outputs the determination result as a signal S5.

However, the method of rate determination performed by the rate determination circuit 16 is, for example, the Institute of Electronics, Information and Communication Engineers Technical Report RCS9.
As described on pages 55 to 60 of 5-166, when the rate information is included in the received data, the rate information is extracted and judged, and the rate information is not transmitted and there is only a CRC code. CRC for all rates if
The code is generated by the same calculation formula as the transmitting side, and the generated C
The RC code and the CRC code extracted from the received data are compared with each other, and the data rate when the two match is determined as the rate of the received signal.

FIG. 11 shows a block diagram of a conventional rate determination circuit 16 using the above method when the rate information is included in the received data. In FIG. 11, 20
Is a rate information extraction circuit that extracts the rate information portion of the received data signal S6 decoded by the deinterleaved Viterbi decoding circuit 15 and outputs this as rate information S5a.
21 is the received data signal S according to the rate information S5a
6 is a CRC extraction circuit for extracting a CRC code from 6.

Reference numeral 22 is a CRC generating circuit for generating a CRC code from the received data signal S6 according to the rate information S5a by the same formula as that of the transmitting side, and 23 is a CRC extracting circuit 21.
And the CRC generation circuit 22 output the CRC codes, and outputs the comparison result as the CRC information S5b.

The demodulation / rake combination circuit 12 described above.
The rake combination performed by will be described. In general, the received signal of mobile communication is a composite wave of multiple paths delayed by reflection and diffraction in addition to the directly received path. Demodulation, weighting according to the reliability of the received signal of each path, and then combining.

Next, the operation will be described. In the transmitter shown in FIG. 9, the information signal S1 to be transmitted is input to the convolutional coding / interleaving circuit 1, where the convolutional coding and interleaving are performed and then input to the frame generation circuit 2. The frame generation circuit 2 adds the control signal S2 to generate a frame signal, and the slot mapping circuit 3 distributes the data to each slot.

The signal mapped to the slot is subjected to, for example, BPSK modulation in the data modulation circuit 4, the spread code is spread-modulated in the spread modulation circuit 5, and the received signal shown in FIG. Sent to the device.

In the receiving apparatus, the signal received via the RF / IF unit 9 is converted to a baseband signal by being subjected to quadrature detection by the quadrature detection circuit 10, and then transmitted to the transmission side by the despreading circuit 11. It is despread using the same spreading code and is returned to the data-modulated signal. Next demodulation
In the rake combining circuit 12, demodulation and rake combining of the despread propagation paths are performed, and the signal whose data modulation has been released by this is output to the SIR measurement circuit 13 and the frame separation circuit 14.

The SIR measuring circuit 13 measures the SIR, which is the ratio of the desired wave signal power to the interference and thermal noise signal power, from the signal from which the data modulation has been released. In this measurement, for example, in the channel configuration corresponding to the variable data rate shown in FIG. 8, the positions of the signal-bearing part and the positions of the vacant intervals without the signal are uncertain at this stage, so the SIR measurement circuit 13 performs the measurement. For the period during the slot to be performed, only the OH portion or the like where data is transmitted regardless of the rate is used.

Next, in the frame separation circuit 14, demodulation /
From the output signal of the rake combining circuit 12, a part corresponding to the control signal S2 added on the transmitting side is separated, and this is output as a signal S3, and the information signal part is input to the deinterleave / Viterbi decoding circuit 15. The deinterleave / Viterbi decoding circuit 15 outputs the received information signal S4 by performing Viterbi decoding after deinterleaving the interleave performed on the transmission side.

The rate judging circuit 16 judges the received data rate using the signal from the deinterleave / Viterbi decoding circuit 15, and outputs the judgment result as a signal S5.
If the rate information is included in the received data, the rate information is extracted and judged, and the rate information is not transmitted.
If there is only an RC code, CRC codes of all rates are generated by the same calculation formula as the transmission side, compared with the CRC code extracted from the received data, and the data rate when both match is taken as the rate of the received signal. judge.

Here, when the rate information is included in the received data, the rate determination circuit 16 having the configuration shown in FIG.
At, the received data signal S6 decoded by the deinterleave / Viterbi decoding circuit 15 is input.

The rate information extraction circuit 20 extracts the rate information portion from the signal S6 and outputs it as rate information S5a. The CRC extraction circuit 21 extracts the CRC code from the received data signal S6 according to the rate information, and C
The RC generation circuit 22 generates a CRC code from the received data signal S6 according to the rate information by the same calculation formula as that of the transmission side. The two CRC outputs are input to the comparison circuit 23, and the comparison result is output as the CRC information S5b.

[0023]

Since the conventional CDMA communication apparatus is configured as described above, in a system in which variable rate transmission is performed, the receiving apparatus of the CDMA communication apparatus receives all frame data, Rate determination circuit 1
Since the rate is not known until the transmission rate of the received signal is determined in 6, the position of the vacant section of the received signal is not known,
Each part must be operated even in the section where the operation of the demodulation part can be stopped because there is no signal originally, and there is a problem that only SOH measurement can use only OH etc. where data is transmitted regardless of the rate. there were.

Further, the rate determination circuit 16 also has a problem that the reliability is lowered when the received rate information has an error. The present invention has been made to solve the above problems, and determines the data rate of a transmission signal before receiving all frame data, and stops the operation of the demodulation unit in the data empty section to reduce power consumption. It is an object of the present invention to obtain a CDMA communication apparatus including a receiving apparatus that improves the reliability of SIR estimation by performing a measurement period of SIR measurement in a section corresponding to a data rate.

Further, according to the present invention, the data vacant zone detection information is used for the rate judgment, so that the rate judgment can be performed even if the transmission data does not include the rate information, and the reliability of the rate judgment is improved. It is an object of the present invention to obtain a CDMA communication device including a receiving device.

[0026]

[0027]

[0028]

[0029]

In a CDMA communication apparatus according to the invention described in claim 1, the receiving apparatus is provided with an empty section detecting means.
In the section other than the empty section detected in
Measures SIR, which is the ratio of interference and thermal noise signal power
It is equipped with SIR measuring means.

In the CDMA communication apparatus according to the invention as defined in claim 2, the receiving device is provided with a free space detected by the free space detecting means.
The reception information, which is the transmission rate of the received information, is detected from the detected position of the section.
It is equipped with rate judgment means for judging the information rate.
It

The CDMA communication apparatus according to the invention of claim 3 sets the received information rate judged by the rate judging means.
Therefore, the error detection code is extracted and generated to perform error detection.
It is equipped with a function for sending out.

According to a fourth aspect of the present invention, there is provided a CDMA communication device, wherein a free space detection position detected by the free space detection means.
A rate information generator for generating a first received information rate
And the second received information rate from the demodulated received data
Rate information extracting means for extracting the first and second receptions
Compare information rates and judge rate information based on the comparison result
It is provided with a comparison and determination means for performing.

The CDMA communication device according to the invention of claim 5 is erroneous according to each of the first and second received information rates.
Error detection code extraction and generation
It is equipped with Noh.

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below. Embodiment 1. FIG. 1 shows a C according to the first embodiment of the present invention.
FIG. 10 is a block configuration diagram of a receiving device in the DMA communication device. In the figure, 9 indicates an RF signal for receiving a signal transmitted from the transmitting device shown in FIG. 9 described in the conventional example at a predetermined frequency via an antenna. IF section, 10 is RF / I
A quadrature detection circuit that quadrature-detects the signal received by the F unit 9 and further converts the signal into a baseband signal. Reference numeral 11 represents the signal converted into the baseband signal by the quadrature detection circuit 10 by a matched filter or a sliding correlator. This is a despreading circuit that despreads using the same spreading code as the transmitting side and thereby restores the data-modulated signal.

Reference numeral 12 is a demodulation / rake combination circuit (demodulation means) for solving data modulation by demodulating and rake combining each propagation path (signal) despread by the despreading circuit 11, and 13 is a demodulation / rake combination circuit. It is an SIR measuring circuit (SIR measuring means) which measures SIR which is a ratio of desired wave signal power to interference and thermal noise signal power using 12 output signals.

Reference numeral 14 separates a part corresponding to the control signal S2 added on the transmission side from the output signal of the demodulation / rake combination circuit 12, outputs it as a signal S3, and deinterleaves the information signal part. A frame demultiplexing circuit for outputting to the decoding circuit 15 and a deinterleave / Viterbi decoding circuit for outputting a received information signal S4 by performing Viterbi decoding after deinterleaving the interleave performed on the transmitting side.

Numeral 25 detects an empty section in which signal transmission is stopped from the data S7 after rake combination inputted from the demodulation / rake combination circuit 12, and according to the detection result, the demodulation / rake combination circuit 12, The operation of the SIR measurement circuit 13 or the like in the empty section is stopped, and the SIR measurement period of the SIR measurement circuit 13 is controlled to reach the position before the detected empty section. Information S8 is sent to the rate determination circuit (rate determination means) 1
6 is an empty section detection circuit (empty section detection means) for outputting to 6. Reference numeral 16 determines the received data rate and checks the CRC code by using the output signal of the deinterleave / Viterbi decoding circuit 15 and the free space detection position information S8.
The rate determining circuit outputs the result as a signal S5.

Next, the operation will be described. For example, it is assumed that the transmission signal of the transmitter shown in FIG. 9 is received by the receiver shown in FIG. The signal received via the RF / IF unit 9 of the receiving device is converted to a baseband signal by being quadrature detected by the quadrature detection circuit 10, and then the same spreading code as that on the transmission side is applied by the despreading circuit 11. Despreading is used to restore the data modulated signal.

Next, in the demodulation / rake combination circuit 12, the despread propagation paths are demodulated and rake combined, and the signal whose data modulation is released by this is S
It is output to the IR measurement circuit 13, the vacant section detection circuit 25, and the frame separation circuit 14.

The frame separation circuit 14 separates the part corresponding to the control signal S2 added on the transmission side from the output signal of the demodulation / rake combination circuit 12 and outputs it as the signal S3, and at the same time, outputs the information signal part. It is input to the deinterleave / Viterbi decoding circuit 15. The deinterleave / Viterbi decoding circuit 15 outputs the received information signal S4 by performing Viterbi decoding after deinterleaving the interleave performed on the transmission side.

The vacant section detection circuit 25 is supplied with the data S7 after the rake combination from the demodulation / rake combination circuit 12, and detects the vacant section in which signal transmission is stopped from this input. According to the detection result, the empty section detection circuit 25 stops the operation of the demodulation / rake combination circuit 12, the SIR measurement circuit 13 and the like in the empty section, thereby reducing the power consumption.

The vacant section detection circuit 25 controls the SIR measuring circuit 13 so that the SIR measurement period is up to the position before the detected vacant section, whereby the SIR measurement period is adjusted.
Increase the accuracy of information. Further, the vacant section detection position information S
8 is output to the rate determination circuit 16. Rate determination circuit 1
6 uses the output signal of the deinterleave / Viterbi decoding circuit 15 and the vacant section detection position information S8 to determine the reception data rate and check the CRC code, and outputs the result as a signal S5.

As described above, according to the first embodiment, the demodulation operation is stopped until transmission is performed again from the empty section detection position according to the empty section detection position information S8, and the power consumption of the receiving apparatus is reduced. Further, there is an effect that the measurement period of the SIR measurement circuit 13 is controlled according to the above-mentioned empty section detection position to improve the SIR estimation accuracy.

That is, the characteristics of the receiving apparatus are improved by detecting the empty section in which the transmission is stopped by using the despread received signal and controlling the operation of the receiving apparatus according to the detection result of the empty section. The effect that can be obtained is obtained.

Embodiment 2. 2 is a block configuration diagram of an idle section detection circuit in a receiver of a CDMA communication apparatus according to Embodiment 2 of the present invention. In FIG.
Is a power measurement circuit (power measurement circuit) that obtains a power value by squaring each of the I component S7a and the Q component S7b of the demodulated / rake combined symbol data S7 output from the demodulation / rake combination circuit 12 and adding them. Means), 29 is an I & D circuit that performs integration (or averaging) of the power value output from the power measurement circuit 28 for a certain period, outputs the power value data Pt obtained by this, and then dumps and repeats the integration operation again. is there.

Reference numeral 30 is a delay circuit for delaying the power value data Pt output from the I & D circuit 29 by one data and outputting the delayed power value data Pt-1. Reference numeral 31 is the power value data Pt.
Is compared with the delay power value data Pt−1, and the comparison result (comparison means) that outputs the comparison result to the vacant section determination circuit (judgment means) 32 is a delay as the comparison result output from the comparison circuit 31. If the data Pt that has not been processed is smaller than the delayed data Pt-1 by the specified threshold Psh,
It is an empty section determination circuit that determines the position of the data Pt as the start position of the data empty section.

Next, the operation will be described. Here, FIG.
9 is a flowchart showing a processing flow of a free space detection circuit in the receiving device of the CDMA communication device according to the second embodiment.

First, in step ST1, the power measurement circuit 28 squares each of the I component S7a and the Q component S7b of the symbol data S7 output from the demodulation / rake combination circuit 12, and then adds them to obtain a power value. , I
Output to the & D circuit 29.

Next, the I & D circuit 29 executes the step ST2.
In step S3, integration (or averaging) is performed on the power value for a certain period, and in step ST3, it is determined whether or not integration of a predetermined number of samples is completed. This judgment result is N
If it is O, the process returns to step ST1 and the same processing as described above is performed. If YES, the process proceeds to step ST4, where the I & D circuit 29 outputs the power value data Pt obtained by the integration processing up to step ST3 to the delay circuit 30 and then dumps it to repeat the above-described integration operation again.

Next, in step ST5, the comparison circuit 31 outputs the power value data P output from the I & D circuit 29.
t and the data Pt- delayed by one data in the delay circuit 30
1 is compared, and the comparison result is output to the empty section determination circuit 32.

Next, in step ST6, the vacant section determination circuit 32 uses the comparison result output from the comparison circuit 31 to calculate the undelayed data Pt from the delayed data Pt-1 to the prescribed threshold value Psh. To determine whether or not it is small. If the determination result is NO, not small, the process returns to step ST1. If YES, step ST7
Then, the position of the data Pt is determined as the start position of the data empty section.

This is a diagram showing the power measurement level and the vacant section detection position of the vacant section detection circuit of FIG. 4, and the vacant section detection circuit 2 in the OH and DATA section in one slot.
The power value calculated in 5 shows a certain value or more, but the power level decreases from the empty section (EMPTY) where data transmission is stopped, and the position where this difference exceeds the measurement threshold Psh is the empty section. Is detected as the start position of. Then, in step ST8, from the detection time to the start time of the next slot, it is considered that the transmission is stopped, and the demodulation operation is stopped by the empty section detection position information S8 indicating the section.

As described above, according to the second embodiment, the vacant section detection circuit 25 measures the power level of the received signal from the power measurement circuit 28 and sequentially compares the measured values,
By determining the position of the vacant section from the comparison result, it is possible to obtain an effect that the data vacant section can be accurately determined.

Embodiment 3. FIG. 5 is a block configuration diagram of a rate determination circuit in a receiver of a CDMA communication apparatus according to Embodiment 3 of the present invention. In the figure, reference numeral 33 designates empty section detection position information output from the empty section detection circuit 25 in slot units. It is a rate information generation circuit (rate information generation means) that outputs rate information S5a according to S8.

Reference numeral 21 is a CRC extracting circuit for extracting a CRC code from the received data signal S6 according to the rate information S5a, and 22 is a CRC for generating a CRC code from the received data signal S6 according to the rate information S5a using the same formula as the transmitting side. A generation circuit, 23 is a CRC code extraction circuit 21 and C
Both CRCs output from the RC code generation circuit 22 are compared, and the comparison result is output as CRC code information S5b. For example, when both match, the matched data rate is set as the rate of the received signal, and Are output as CRC code information S5b.

Next, the operation will be described. The vacant section detection circuit 25 inputs the vacant section detection position information S8 to the rate information generation circuit 33. Since the start position of the empty section is uniquely determined by the data rate, the rate information generation circuit 33 determines the rate information S based on the detected empty section start position.
5a is generated.

Since the free space detection position information S8 is input to the rate information generation circuit 33 in slot units,
The rate information S5a may be determined by one of the signals S8 for one frame, or the average value of the signals S8 for one frame may be used to improve accuracy.

The CRC code extraction circuit 21 uses the rate information S
The CRC code is extracted from the received data signal S6 according to 5a, and the CRC code generation circuit 22 generates a CRC code from the received data signal S6 according to the rate information S5a using the same formula as that of the transmission side. Two CRC outputs are comparison circuit 2
3 and the comparison result of both is output as CRC information S5b. With the above operation, the data rate can be determined even if the transmission data does not include the rate information.

As described above, according to the third embodiment, the rate of the received information is judged from the empty section detection position by the empty section detection position information S8, and the rate judgment function can be easily performed without transmitting the rate information. Can be realized,
Further, the effect that the error detection code is extracted and generated from the received information rate judged by the rate judgment circuit 16 and the error can be accurately detected is obtained.

Fourth Embodiment FIG. 6 is a block diagram showing another configuration of the rate determination circuit in the receiving device of the CDMA communication device according to the fourth embodiment of the present invention. In the figure, reference numeral 33 indicates a vacancy output from the vacant section detection circuit 25 in slot units. A rate information generation circuit that outputs the first rate information S5a1 according to the section detection position information S8, and 20 extracts the rate information portion of the reception data signal S6 decoded by the deinterleaved Viterbi decoding circuit 15 and outputs it as the second
It is a rate information extraction circuit (rate information extraction means) that outputs as rate information S5a2.

Reference numeral 35 compares the first rate information S5a1 with the second rate information S5a2 to obtain the first and second rate information S5.
When 5a1 and S5a2 match, the matched value is output to the re-determination circuit 36 as rate information, and
One of the two sets of CRC extraction circuit 21 and CRC generation circuit 22 is controlled to operate, and if they do not match, the first and second rate information S5a1 and S5a2 are output to the re-determination circuit 36 as rate information. With 2 sets of CR
It is a comparison / judgment circuit (comparison judgment means) for controlling the C extraction circuit 21 and the CRC generation circuit 22 to operate.

When the rate information at the time of coincidence is input from the comparison / determination circuit 35, 36 outputs the rate information as it is as rate information S5a, and the comparison / determination circuit 35 outputs the first and second rate information. S5a1 and S5a
When 2 is input, according to the control of the comparison circuit 23,
The redetermination circuit outputs either the first or second rate information S5a1 or S5a2 as the rate information S5a, or outputs the information indicating the rate information determination failure as the rate information S5a.

Next, the operation will be described. Here, FIG.
9 is a flow chart showing the flow of processing of the rate determination circuit in the fourth embodiment.

First, in step ST1, the rate information generating circuit 33 and the rate information extracting circuit 20 individually output the first and second rate information S5a1 and S5a2, respectively.
Is calculated, and in step ST2, the calculated first and second rate information S5a1 and S5a2 are compared.
The decision circuit 35 makes a comparison.

As a result of this comparison, the first and second rate information S
If 5a1 and S5a2 match, step ST3
In the above, the comparison / determination circuit 35 determines the rate information to the value, and the re-determination circuit 36 outputs the matched rate information as it is as the rate information S5a.

Further, in step ST4, a set of the CRC extraction circuit 21 and the CRC generation circuit 22 is operated under the control of the comparison / determination circuit 35.
The CRC extraction circuit 21 extracts the CRC code from the received data signal S6 according to the rate information, and the CRC generation circuit 22 receives the received data signal S6 according to the rate information.
Then, a CRC code is generated by the same calculation formula as that of the transmitting side, and both CRC codes are output to the comparison circuit 23. Then, in step ST5, both CRC codes are compared by the comparison circuit 23, and the comparison result is the CRC information S5.
It is output as b.

On the other hand, in step ST2, when the first and second rate information S5a1 and S5a2 do not match, the comparison / determination circuit 35 controls the two sets of the CRC extraction circuit 21 and the CRC generation circuit 22 to operate. .

As a result, in step ST6,
According to the first rate information S5a1, one set of the CRC extraction circuit 21 and the CRC generation circuit 22 receives the received data signal S6.
CRC code is extracted and generated from the C code of the other set according to the second rate information S5a2 in step ST7.
The RC extraction circuit 21 and the CRC generation circuit 22 extract and generate a CRC code from the received data signal S6, and the CRC code is output to the comparison circuit 23.

Next, in step ST8, the comparison circuit 23 compares the CRC codes extracted and generated according to the first rate information S5a1. If the comparison result is a match in step ST9, in step ST10, The CRC codes extracted and generated according to the second rate information S5a2 are compared, and the comparison result is obtained in step ST.
It is assumed that there is a disagreement in 11.

This case is a case where the CRC codes extracted and generated according to the first rate information S5a1 match, and the CRC codes extracted and generated according to the second rate information S5a2 do not match. In this case, In step ST12, the comparison result of the CRC code extracted and generated according to the first rate information S5a1 is output as the CRC information S5b, and the first rate information is output as more reliable information under the control of the comparison circuit 23. S5a1 is output from the redetermination circuit 36 as rate information S5a.

On the other hand, in step ST11, it is assumed that the comparison results in step ST10 match. In this case, the CRC code extracted and generated according to the first and second rate information S5a1 and S5a2 also matches, and in this case, in step ST13, the information indicating the rate information determination failure is output from the comparison circuit 23. Rate information S
5b and, under the control of the comparison circuit 23, the information indicating the rate information determination failure is output as 5b.
Is output as rate information S5a.

In step ST9, if the comparison results in step ST8 do not match, step ST14
In, it is assumed that the CRC codes extracted and generated according to the second rate information S5a2 are compared, and the comparison result is a match in step ST15.

In this case, the CRC codes extracted and generated according to the first rate information S5a1 do not match, and the CRC codes extracted and generated according to the second rate information S5a2 match. In this case, In step ST16, the comparison result of the CRC code extracted and generated according to the second rate information S5a2 is output as the CRC information S5b, and the second rate information is output as more reliable information under the control of the comparison circuit 23. The redetermination circuit 36 outputs S5a2 as rate information S5a.

On the other hand, in step ST15, it is assumed that the comparison results in step ST14 do not match. In this case, the first and second rate information S5a1 and S5a2 are
In this case, the comparison circuit 23 outputs the information indicating the rate information determination failure as the rate information S5b and the control of the comparison circuit 23 at the same time. In response to this, information indicating that the rate information determination has failed is output from the re-determination circuit 36 as rate information S5a.

As described above, according to the fourth embodiment, the first reception information rate (first rate information S5a1) from the empty section detection position by the empty section detection position information S8.
Is generated, the second reception information rate (second rate information S5a2) is extracted from the demodulated reception data signal S6, and the rate is determined by comparing the first and second reception information rates. The accuracy of rate determination can be improved, and the error detection code (CRC code) is extracted and generated according to each of the first and second reception information rates, and the error detection is performed. The effect that the accuracy of determination can be improved is obtained.

In the above-described first to fourth embodiments, the CDMA communication device using the channel having the frame and slot configuration has been described, but the receiving device of the CDMA communication device according to the present invention has no data. The present invention can be applied to all CDMA communication devices that stop transmission in an empty section.

Further, the data used in the vacant section detection circuit 25 may be demodulation data of the maximum path before rake combination, for example, instead of the data after rake combination. The determination method of the empty section detection circuit 25 shown in FIG.
It is not necessary that there is a difference equal to or greater than the threshold value Psh between Pt-1 and Pt-1 and that the condition where each power value data is below a certain level is determined as a data empty section.

[0078]

[0079]

[0080]

[0081]

Effects of the Invention According to the first aspect of the invention, the receiving device
Section other than the empty section detected by the empty section detection means
And the ratio of the desired signal power to the interference and thermal noise signal power
It was configured with SIR measuring means for measuring a certain SIR.
Therefore, there is an effect of improving the SIR estimation accuracy.

According to the invention described in claim 2, the receiving device
, The detection position of the vacant section detected by the vacant section detecting means
Determine the reception information rate, which is the transmission rate of the reception information
Since it is equipped with a rate determination means for
The effect of easily realizing the rate judgment function without sending
There is a fruit.

According to the third aspect of the invention, the rate judgment is made.
Means, error detection from the received signal according to the received information rate
Equipped with a function to detect errors by extracting and generating codes
Since it is configured in such a way, there is an effect that error detection is accurately performed.

According to the invention described in claim 4, rate determination
Detecting the vacant section detected by the vacant section detecting means
A rate information source for generating a first received information rate from the position
And a second reception information record from the demodulated reception data.
Rate information extracting means for extracting the
The received information rates are compared, and if they match, the matching value is received.
It is configured with a comparison / determination means for setting the signal information rate.
Thus, there is an effect of increasing the accuracy of rate determination.

According to the invention described in claim 5, rate determination
Means for each of the first and second received information rates
The error detection code is extracted and generated from the received information and
Error detection judgment because it is configured with a function to detect
Has the effect of increasing the accuracy of.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a receiving device in a CDMA communication device according to a first embodiment of the present invention.

FIG. 2 is a block configuration diagram of an empty section detection circuit in a receiving device of a CDMA communication device according to a second embodiment of the present invention.

FIG. 3 is a flowchart showing a processing flow of a free space detection circuit in the receiving device of the CDMA communication device according to the second embodiment.

FIG. 4 is a diagram showing a power measurement level and a vacant section detection position of a vacant section detection circuit in the receiving device of the CDMA communication apparatus according to the second embodiment of the present invention.

FIG. 5 is a block configuration diagram of a rate determination circuit in a receiving device of a CDMA communication device according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing another configuration of the rate determination circuit in the receiving device of the CDMA communication device according to the fourth embodiment of the present invention.

FIG. 7 is a flowchart showing a processing flow of a rate determination circuit in the receiving device of the CDMA communication device according to the fourth embodiment.

FIG. 8 is a diagram showing an example of a channel configuration of a CDMA system corresponding to a variable data rate of a conventional CDMA communication device.

FIG. 9 is a block configuration diagram of a transmission device in a conventional CDMA communication device.

FIG. 10 is a block diagram of a receiving device in a conventional CDMA communication device.

11 is a block diagram of a rate determination circuit in the receiving device of the CDMA communication device shown in FIG.

[Explanation of symbols]

12 demodulation / rake combination circuit (demodulation means), 13 SI
R measurement circuit (SIR measurement means), 16 rate determination circuit (rate determination means), 20 rate information extraction circuit (rate information extraction means), 25 empty section detection circuit (empty section detection means), 28 power measurement circuit (power measurement) Means), 3
DESCRIPTION OF SYMBOLS 1 1 comparison circuit (comparison means), 32 vacant section determination circuit (determination means), 33 rate information generation circuit (rate information generation means), 35 comparison / determination circuit (comparison determination means).

─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-6-120888 (JP, A) JP-A-9-84138 (JP, A) JP-A-5-252139 (JP, A) JP-A-8- 204654 (JP, A) JP-A-9-130338 (JP, A) JP-A-6-97868 (JP, A) International Publication 96/026582 (WO, A1) (58) Fields investigated (Int.Cl. ⁷⁾ , DB name) H04J 13/00-13/06 H04B 1/69-1/713 H04B 7/24 H04B 7/26

Claims (5)

(57) [Claims] 1. A transmission device that applies a CDMA system and generates a data frame including an empty section with no information when the transmission rate of transmission information is lower than the transmission capacity of a channel, and stops transmission in the empty section. , A receiving device that performs data processing after despreading the received information with the same spreading code as this transmitting device, and a reception device that is provided in this receiving device and that uses the despread received signal to indicate the stop of transmission In the CDMA communication apparatus, which is provided with an empty section detecting unit for detecting an empty section used for controlling the data processing operation, the receiving apparatus is provided with an empty section detecting unit.
Signal power, interference and thermal noise
Controls the measurement period for measuring SIR which is the ratio of signal power
A CDMA communication device comprising SIR measuring means . 2. A transmission device that applies a CDMA system and generates a data frame including an empty section with no information when the transmission rate of transmission information is lower than the transmission capacity of a channel, and stops transmission in the empty section. , A receiving device that performs data processing after despreading the received information with the same spreading code as this transmitting device, and a reception device that is provided in this receiving device and that uses the despread received signal to indicate the stop of transmission In the CDMA communication device having a free space detecting means for detecting a free space used for controlling the data processing operation, the free space detecting means detects the free space in the receiving device.
From the detected position of the vacant section, the reception rate that is the transmission rate of the received information
A CDMA communication device comprising rate determining means for determining a signal information rate . 3. Error detection in a transmitted data frame.
In a system that includes a code, the rate determination means determines
The error detection code is extracted according to the specified reception information rate.
3. The CDMA communication device according to claim 2, further comprising means for performing error detection by outputting and generating . 4. A transmission layer in a data frame to be transmitted.
In a system that includes traffic information
From the empty section detection position detected in
Rate information generating means for generating the
Rate information extraction for extracting the second received information rate from the data
Comparing the output means with the first and second received information rates
Then, the comparison determination means for performing rate information determination based on the comparison result
CDMA communication apparatus according to claim 2, further comprising a. 5. In a system in which an error detection code is included in a transmitted data frame, the first and second receivers are provided.
Extraction of error detection code according to each of the signal information rate and
5. The CDMA communication device according to claim 4, further comprising means for performing generation and error detection .