JP3493860B2 - Vertical field-effect transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical field effect transistor (Field) for passing a current in a direction vertical to a substrate.
d Effect Transistor), in particular, CMOS that is compatible with high speed, miniaturization, and low power consumption
(Complementary Metal Oxid
The present invention relates to a vertical field effect transistor having an element structure that can be formed into an eSemiconductor, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, an FET having a silicon-germanium (SixGe1-x) heterostructure has been researched from the viewpoint that carrier mobility can be improved and the device speed can be increased. Among them, attention is focused on a vertical structure MOSFET aiming at accurate control of the channel length and suppression of the short channel effect, and one example thereof is disclosed in JP-A-6-224435 and JP-A-5-267678. The structure and method of manufacture are described.

[0003]

However, in the method disclosed in the above-mentioned patent, an oxide is directly grown as a gate insulating film on the surface of SixGe1-x. In such a method, Ge is formed between the oxide and SixGe1-x.
Is known to precipitate and greatly increase the interface state density of the oxide / SixGe1-x interface (for example,
GLPatton et al. Material Research Society Procee
ding., vol.295 p.102 (1987)). Due to the increase in the interface state density, the effective carrier mobility is significantly reduced, so that there is a problem that desired characteristics cannot be obtained.

SUMMARY OF THE INVENTION An object of the present invention is to provide a Si / SixGe1-x heterostructure vertical field effect transistor having a reduced interface state density and a higher speed, and a method of manufacturing the same.

[0005]

In order to solve the above-mentioned object, the invention of claim 1 has a structure in which a silicon layer is interposed between a channel layer made of a SixGe1-x alloy and a gate insulating film. A source layer or a drain layer, which is formed on a silicon substrate and to which an impurity of the first conductivity type is added, which reduces the interface state density and realizes high-speed operation of the device. And a second impurity layer which is formed on the first impurity layer and serves as a channel layer to which an impurity of the second conductivity type is added, and the second impurity layer. A third impurity layer that is formed on the first impurity layer and serves as a drain layer or a source layer to which an impurity of the first conductivity type is added, and a silicon layer and a gate insulating film on the side surface of the second impurity layer. A gate electrode formed, the second The impurity layer is formed of an alloy of silicon and germanium epitaxially grown on the first impurity layer.

According to the second aspect of the present invention, the parasitic resistance is reduced and the speed of the device is increased. Specifically, the element is formed on a silicon substrate, and Is formed on the first alloy layer of cobalt and silicon, which becomes the source layer or the drain layer epitaxially grown, and the first alloy layer of cobalt and silicon, and is doped with impurities of the first conductivity type. A first impurity layer, a second impurity layer serving as a channel layer to which an impurity of the second conductivity type is added, and the second impurity layer are formed on the second impurity layer. Third added
Second impurity layer and a second alloy layer of cobalt and silicon, which is formed on the third impurity layer and serves as a drain layer or a source layer, and a silicon layer on a side surface of the second impurity layer. And a gate electrode formed through a gate insulating film, wherein the second impurity layer is an alloy of silicon and germanium epitaxially grown with respect to the first impurity layer.

The invention of claim 3 is the structure of claim 1 or 2.
A second conductive layer under the region where the first impurity layer is formed.
Equipped with a second conductivity type well layer to which a conductivity type impurity is added
Is added.

According to the invention of claim 4, the interface state density is reduced.
It is a complementary field effect transistor designed for high speed.
Is formed on the silicon substrate and is of the first conductivity type.
The first layer becomes a source layer or a drain layer to which a pure substance is added.
An impurity layer and a first impurity layer formed on the first impurity layer.
Becomes a channel layer to which a second conductivity type impurity is added.
A second impurity layer and formed on the second impurity layer
And a drain layer to which an impurity of the first conductivity type is added or
A third impurity layer serving as a source layer and the second impurity layer
Was formed on the side surface of the silicon via a silicon layer and a gate insulating film.
The first gate electrode and the first gate electrode on the silicon substrate.
Impurity of the second conductivity type is formed on the side of the first impurity layer.
A fourth layer which becomes a source layer or a drain layer to which a substance is added.
The pure layer and the fourth impurity layer are formed on the fourth impurity layer.
The fifth layer which becomes a channel layer to which an impurity of one conductivity type is added
Formed on the impurity layer and the fifth impurity layer,
Drain layer or source doped with second conductivity type impurities
Side surface of the fifth impurity layer and a sixth impurity layer to be a layer
The second layer formed on the silicon via the silicon layer and the gate insulating film.
A gate electrode, and the second impurity layer is formed on the first impurity layer.
The fifth impurity layer is the same as the impurity layer.
Epitaxial growth was performed on each of the four impurity layers.
And an alloy of silicon and germanium
To do.

The invention of claim 5 is a complementary type field effect transistor.
In the transistor, the parasitic resistance is reduced and the device speed is increased.
Of silicon substrate, specifically, silicon substrate
Formed on the silicon substrate, and with respect to the silicon substrate
Becomes an epitaxially grown source or drain layer
A first alloy layer of cobalt and silicon;
It is formed on the alloy layer of Baltic and silicon.
A first impurity layer to which conductivity type impurities are added, and a second conductive layer.
Second impurity that becomes a channel layer doped with electric type impurities
And a first impurity layer formed on the second impurity layer.
A third impurity layer to which conductivity type impurities are added;
The drain layer or the saw formed on the impurity layer of FIG.
The second alloy layer of cobalt and silicon to form a sputter layer, and
A silicon layer and a gate insulating film are formed on the side surface of the second impurity layer.
A first gate electrode formed through
Formed on the side of the first impurity layer in the plate
Saw epitaxially grown on the silicon substrate
Third cobalt and silicon, which will become a drain layer or a drain layer
Alloy layer, and the third alloy layer of cobalt and silicon
Is formed on top of and has impurities of the second conductivity type added
The fourth impurity layer and the impurity doped with the first conductivity type
Fifth impurity layer to be a channel layer and the fifth impurity layer
Is formed on top of and has impurities of the second conductivity type added
A sixth impurity layer and formed on the sixth impurity layer
And the fourth cobalt that becomes the drain layer or the source layer
The surface of the alloy layer with silicon and the side surface of the fifth impurity layer are shielded.
The second gate formed via the silicon layer and the gate insulating film
A second impurity layer, and the second impurity layer is
And the fifth impurity layer is the fourth impurity layer.
For the impurity layers, the epitaxially grown
It is composed of an alloy of recon and germanium
It is a thing.

The invention of claim 6 is based on the structure of claim 4.
A second conductivity type layer is formed under the region where the first impurity layer is formed.
When the well layer of the second conductivity type to which pure material is added is provided,
A first conductive layer under the region where the fourth impurity layer is formed.
Equipped with a well layer of the first conductivity type to which a conductivity type impurity is added
Is added.

The invention of claim 7 is the same as the structure of claim 5,
The region where the first silicon-cobalt alloy layer is formed
Of the second conductivity type in which impurities of the second conductivity type are added below the region
A well layer, and the third silicon and cobalt
Impurity of the first conductivity type under the region where the alloy layer with
A well layer of the first conductivity type to which a substance is added
The configuration is added.

According to the invention of claim 8, the strain of the channel layer is reduced.
In order to reduce the number, the configuration according to any one of claims 1 to 7
For the second impurity layer made of an alloy of recon and germanium
The germanium atomic concentration is the first and third impurities.
Is less than a few percent in the vicinity of the
If the content is 30% or more in the central portion of the second impurity layer
The above-mentioned configuration is added.

According to a ninth aspect of the present invention, parasitic capacitance is reduced, and
Insulation instead of silicon substrate to speed up the child
Substrate on which a silicon layer is formed (Silicon
On Insulator: hereinafter referred to as SOI substrate)
, The vertical field effect according to 8 or Re noise claims 1
The configuration is such that a transistor is formed.

The invention of claim 10 is the surface of a transistor.
A layer leak is prevented, and specifically, claim 1
Or the silicon layer is
Almost the same impedance as the first, second and third impurity layers immediately below
It is a regulation that has a pure substance concentration.

The invention of claim 11 is the surface of a transistor.
A layer leak is prevented, and specifically, claim 1
0, the thickness of the silicon layer is 100 on.
It is defined as less than Gstrom.

According to the structure of the first aspect, since the gate insulating film is not directly formed on the SixGe1-x, the interface state density between the insulating film and the channel layer can be reduced.

According to the structure of claim 2, the source / drain layer can be made low in resistance, and the silicon layer or the channel layer can be directly formed on the source layer or the drain layer.
Since the e1-x layer can be epitaxially grown, a transistor having excellent characteristics can be formed. Further, as in the first aspect, since the gate insulating film is not directly formed on SixGe1-x, the interface state density between the insulating film and the channel layer can be reduced.

With the structure of claim 4 , the same as in claim 1
Structure that does not form a gate insulating film directly on SixGe1-x
Therefore, the interface state density between the insulating film and the channel layer is low.
Can be reduced.

According to the structure of claim 5 , as in claim 2,
The resistance of the source / drain layer can be reduced, and the source / drain layer
Is the silicon layer or channel layer directly on the drain layer
To grow epitaxially a SixGe1-x layer
Therefore, a transistor with favorable characteristics can be formed. Also, the contract
Form gate insulating film directly on SixGe1-x as in Requirement 1.
Since the structure is not formed, the interface between the insulating film and the channel layer
The surface state density can be reduced.

According to the structure of claim 8 , the first and third problems
Relaxation of lattice mismatch at the interface between pure layer and SixGe1-x layer
Can reduce the off-leakage current between the source and drain.
It Also, in the effective channel section, the concentration of germanium is
Since the temperature is kept high, the high speed of the device can be maintained.

According to the structure of claim 9 , the source / drain
The parasitic capacitance of can be reduced, and the speed of the device can be increased.

According to the structure of claims 10 and 11 , the impurity activity is
Thermalization process, gate insulation film formation process or interlayer insulation film heat
By the high temperature heat treatment process such as the treatment process, the first, second and
And an impurity having a concentration similar to that of the third impurity layer
Since it diffuses into the con layer, a PN junction can be formed in the surface layer,
Leakage of the surface layer can be reduced. Also, the resistance of the channel layer
Can be reduced.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment of the Invention) FIG. 1 is a schematic view showing the structure of an N-channel vertical field effect transistor according to the first embodiment of the present invention. In FIG. 1, 1 is a silicon substrate, 2 is SixGe1
-x channel layer, 3 is an N + silicon layer, 4 is an extremely thin silicon layer, 5 is a gate oxide film, and 6 is a gate electrode.

According to the structure of the embodiment of the present invention, since the ultrathin silicon layer 4 is sandwiched just below the gate oxide film 5, the interface state density with the gate oxide film 5 is close to that of the bulk silicon MOSFET. Become.

[0025] Therefore, in the following differences in the structure in the form of implementation of the conventional structure and the present invention, A-A in FIG. 1 (a) '
A description will be given using a band diagram (FIG. 2) in the cross section.

In the conventional structure, the gate oxide film and SixG
Carrier capture levels are generated in the vicinity due to the precipitation of unoxidized Ge at the interface with e1-x. Carriers traveling in the channel directly under the gate oxide film are trapped in the carrier trapping level, resulting in a decrease in carrier mobility (FIG. 2).
(A) and (b)).

On the other hand, according to the structure of the embodiment of the present invention, since the ultrathin silicon layer is sandwiched between the gate oxide film and the SixGe1-x layer, the interface state density is significantly reduced. (FIGS. 2C and 2D).

In this case, since the ultra-thin silicon layer exhibits various plane orientations, the interface state density is several times higher than that of the bulk silicon MOSFET formed on the (100) plane. However, according to the structure of the embodiment of the present invention, since the channel region in which carriers travel is formed mainly at the Si / SixGe1-x interface, not directly under the gate oxide film, the gate oxide film / silicon layer interface is formed. Even if the level density is slightly increased, the degree of decrease in carrier mobility is small.

Especially when the gate voltage is low, the channel region is limited to the vicinity of the Si / SixGe1-x interface,
The effect of the interface state density is almost negligible. As a result, high speed operation is possible even at low voltage operation.

Further, by limiting the thickness of the side surface silicon layer to 100 angstroms or less, leakage of the surface layer can be prevented. An example thereof is shown in FIG.

In the case of N-channel transistor, Si / S
A channel is mainly formed on the Si side of the ixGe1-x interface, but at the same time, a surface channel is induced at the Si / SiO2 interface. As shown in FIG. 3A, when the thickness of the silicon layer is large, the electrons flowing out from the surface channel are drawn to the drain side, but pass through the high resistance layer during that time, so that noise is easily generated.

If the thickness of the silicon layer is 100 angstroms or less, impurities are diffused from each layer due to the impurity activation process and the like, and the silicon layer has almost the same impurity concentration as the layer immediately below. In that case,
As shown in (b), even if the surface channel is formed, the electrons are quickly drawn into the drain and do not become a noise component.

(Embodiment of the Second Invention) FIG. 4 is a schematic diagram showing the structure of a P-channel vertical field effect transistor having a low resistance source / drain layer in the embodiment of the second invention of the present invention. Is. In FIG. 4, 7 is an alloy layer of silicon and cobalt serving as a source region, 8 is a P + silicon layer, 2 is a SixGe1-x channel layer, 9 is an alloy layer of silicon and cobalt that is a drain region, and 4 is a pole. A thin silicon layer, 5 is a gate oxide film, and 6 is a gate electrode.

According to the structure of the embodiment of the present invention, since the alloy layer of silicon and cobalt is used, the resistance of the source / drain layer can be made low and the speed of the device can be increased. In particular, when the alloy of silicon and cobalt is CoSi2, the specific resistance can be minimized among the existing alloys of silicon and cobalt (the specific resistance of CoSi2 is 14 to 20 .mu..OMEGA.cm. , 70
~ 140 μΩ · cm).

The lattice constant of Si is 5.431 angstroms and the lattice constant of CoSi2 is 5.365 angstroms. Since the lattice mismatch is within 1.2%, epitaxial growth on silicon can be performed. Furthermore, a silicon film and SixGe are formed on CoSi2.
Because 1-x films can be grown epitaxially,
A transistor structure with few crystal defects can be easily formed.

Further, by reducing the source / drain resistance, when viewed as an electric circuit, the asymmetric structure originally possessed by the vertical field effect transistor can be relaxed, and it is possible to make it difficult to restrict the configuration of the logic circuit. Becomes

FIG. 5 shows a vertical field effect transistor formed on the SOI substrate 10 according to the embodiment of the present invention. With such a structure, the parasitic capacitance in the layer closer to the substrate in the source layer or the drain layer can be reduced, so that the electrically asymmetric structure can be further relaxed.

Next, FIG. 6 is an explanatory diagram relating to generation of a leak current in the channel direction in the vertical field effect transistor according to the present invention.

To increase carrier mobility, SixG
When the content of Ge in the e1-x alloy is increased, the lattice constant of Ge is about 4% larger than that of Si, so that the strain received by the alloy increases up to 4% depending on the mixed crystal ratio. When epitaxial growth is further performed on a large lattice mismatch, a large number of dislocations are generated due to interface strain, and a leak current flows through the dislocations. In order to solve such a problem, it is necessary to modulate the Ge concentration to reduce the amount of lattice mismatch at the interface with Si.

FIG. 7 is a Ge concentration distribution diagram in the channel layer of the vertical field effect transistor according to the present invention. In FIG. 7, (a) shows the case where the Ge concentration, which is a conventional problem, is uniformly high, and (b) to (d) show the case where the Ge concentration is changed stepwise as in the present invention. There is. As shown here, in a SixGe1-x alloy, Si
When the Ge concentration at the interface with and is set to several% or less, the amount of lattice mismatch becomes 0.4% or less, and the generation of dislocations at the interface is almost suppressed. In addition, by increasing the Ge concentration stepwise,
It is possible to secure a high mobility portion of the carrier and form a high performance field effect transistor.

(Embodiment of the Third Invention) FIG. 8 is an explanatory diagram of a manufacturing process of a complementary vertical field effect transistor according to an embodiment of the third invention of the present invention.

First, as shown in FIG. 8A, boron and arsenic are continuously ion-implanted on the silicon substrate 1 using the first resist pattern 11 as a mask, and then the resist pattern is removed.

Next, as shown in FIG. 8B, phosphorus and BF2 are successively ion-implanted by using the inverted pattern 12 of the first resist pattern as a mask, the resist is removed, and then heat treatment is performed to obtain N. Well layer 13, P well layer 1
4, P + silicon layer 15 and N + silicon layer 16 are formed respectively.

Next, after removing the natural oxide film on the surface of the substrate, the SixGe1-x layer 17 is subjected to P + as shown in FIG. 8 (c).
Heteroepitaxial growth is performed on the silicon layer 15 and the N + silicon layer 16. This process uses disilane (SiH
6) and monogermane (GeH4) are used as source gases by a chemical vapor deposition method to grow at a substrate temperature of 600 ° C or lower.

As shown in FIG. 8D, boron ions are implanted using the resist pattern as a mask, and then the resist pattern is removed. Further, phosphorus is ion-implanted using the inversion pattern as a mask to remove the resist pattern, and then heat treatment is performed at 700 ° C. so that the SixGe1-x layer 17 is formed.
To recover the crystal defects generated in the.

Next, as shown in FIG. 8 (e), 700 ° C.
A silicon film 18 is epitaxially grown on the SixGe1-x layer 17 at the following temperature.

As shown in FIG. 8F, arsenic is ion-implanted using the resist as a mask, and then the resist is removed. Further, BF2 is ion-implanted by using the inversion pattern as a mask, the resist is removed, and the P + silicon layer 15 is formed.
N + silicon layers 16 are formed respectively.

A silicon oxide film 19 is deposited on the entire surface of the substrate by atmospheric pressure chemical vapor deposition. Further, a resist is applied on the entire surface, and then exposed and developed to form a resist pattern. Subsequently, the silicon oxide film is etched mainly by dry etching using a fluorine-based gas, and then the resist pattern is ashed and removed.

Further, as shown in FIG. 8G, the P + silicon layer 15, the N + silicon layer 16 and the SixGe1-x layer 17 are continuously etched mainly by dry etching using a chlorine-based gas.

Next, as shown in FIG. 8H, after the second resist pattern 20 is formed, the P + silicon layer 1 is formed.
5. Etch the N + silicon layer 16 to obtain an island-shaped semiconductor.

After the second resist pattern 20 is ashed and removed by oxygen plasma, the sample is washed with a mixed solution of sulfuric acid and hydrogen peroxide. Then, the silicon oxide film is etched and removed with a hydrofluoric acid-based aqueous solution, and then washed with a mixed solution of ammonium hydroxide and hydrogen peroxide to remove the damaged layer on the island-shaped semiconductor surface. After removing the natural oxide film in a chemical vapor deposition apparatus having a chamber for removing the natural oxide film by HF vapor, the ultrathin silicon layer 4 is continuously epitaxially grown on the surface of the substrate including the island-shaped semiconductor. At this time, the substrate is grown at a temperature of 650 ° C. or lower. The ultrathin silicon layer 4 is thermally oxidized at a temperature of 750 ° C. or lower to form a gate oxide film 5. At this time, the thickness of the silicon layer is previously determined so that the thickness of the ultrathin silicon layer 4 after the gate oxide film is formed is 100 angstroms or less.

Subsequently, as shown in FIG. 8 (i), a polycrystalline silicon film is deposited by the low pressure vapor deposition method.

Next, using the first resist pattern 11 as a mask, arsenic is ion-implanted at a dose of ² to 8 × 10 ¹⁵ cm ^-2 , the resist pattern is removed, and then the inverted pattern 12 of the first resist pattern 12 is formed. Forming BF2
Ion implantation at a dose of 1 to 3 × 10 ¹⁵ cm ^-2 ,
Subsequently, the inverted pattern 12 is removed. The impurities implanted by the ions are activated by rapid thermal annealing at 900 ° C. for 60 seconds.

Next, as shown in FIG. 8 (j), after applying a resist, exposing and developing to form a resist pattern, the polycrystalline silicon film 21 is etched with a chlorine-based gas, and the gate electrode 6 is formed. To form.

Silicon oxide film 19, borate glass (B 2 O 3) and phosphate glass (P 2 O) were formed by atmospheric pressure chemical vapor deposition.
5) A silicon oxide film (BPSG film) 22 including and is continuously deposited, and heat treatment is performed at 750 ° C. or lower. BPS
The G film is polished by chemical mechanical polishing (CMP) to be flattened, and then a resist is applied, exposed and developed to form an opening pattern. Next, an opening is formed by dry etching mainly using a fluorocarbon gas.

After cleaning, as shown in FIG. 8 (k), titanium (Ti), titanium nitride (TiN), and tungsten (W) were used.
The film is sequentially formed to form the plug 23.

Next, the first aluminum wiring 24 is formed,
A silicon oxide film 25 is deposited by plasma chemical vapor deposition. After the silicon oxide film 25 is polished by CMP and flattened, a through hole 26 is formed, as shown in FIG.
As shown in (l), the second aluminum wiring 27 is continuously formed.
To form.

As shown in FIG. 8 (m), phosphorus glass (PSG) and silicon nitride film (SiN) films are continuously deposited by plasma chemical vapor deposition to form a passivation film 28, and then an electrode lead-out portion 29 is formed. To form.

SixGe1-x in the embodiment of the present invention
In the layer growth step, the amount of disilane introduced is kept constant,
By changing the introduction amount of monogermane, the Ge concentration distribution shown in FIG. 7 can be easily obtained.

As shown in the embodiment of the present invention, Si
By forming a silicon layer on the side surface of the xGe1-x layer and then forming a gate insulating film and a gate oxide film, it becomes possible to form a vertical field effect transistor in which the channel layer does not deteriorate.

(Embodiment of Fourth Aspect of the Invention) FIG. 9 is an explanatory diagram showing a manufacturing process of a complementary vertical field effect transistor according to an embodiment of the fourth aspect of the present invention.

First, as shown in FIG. 9A, boron is ion-implanted on the silicon substrate 1 using the first resist pattern 11 as a mask, and then the resist pattern is removed.

Next, as shown in FIG. 9B, phosphorus is ion-implanted using the inverted pattern 12 of the first resist pattern as a mask, the resist is removed, and then heat treatment is performed to form an N well layer 13, The P well layers 14 are formed respectively.

After removing the natural oxide film on the substrate surface, FIG.
As shown in (c), cobalt is deposited on the entire surface by sputtering, and rapid thermal annealing is performed once or twice, and then unreacted cobalt is removed to remove CoS.
The i2 layer 30 is formed.

Next, a silicon oxide film 19 is deposited on the entire surface by atmospheric pressure chemical vapor deposition, a resist pattern is formed, and the silicon oxide film 19 is removed by wet etching using this as a mask.

At this time, CoS is applied by wet etching.
The liquid concentration is adjusted or the CoSi2 layer is thickened so that the i2 layer is not lost.

As shown in FIG. 9D, exposed CoS
On the i2 layer 30, an N-silicon layer 31, a P-SixGe1-
The x layer 32 and the N-silicon layer 31 are selectively epitaxially grown. Especially when growing the P-SixGe1-x layer 32, disilane (SiH6), monogermane (GeH4)
Further, the chemical vapor deposition method using diborane (B2H6) as a source gas is performed to grow the substrate at a temperature of 600 ° C. or less.

After the silicon oxide film 19 is formed on the entire surface again, an inverted resist pattern is formed, and the silicon oxide film 19 is removed by wet etching using this as a mask until the CoSi 2 layer is exposed.

As shown in FIG. 9E, the exposed CoS
On the i2 layer 30, a P-silicon layer 33 and N-SixGe1-
The x layer 34 and the P-silicon layer 33 are continuously and selectively epitaxially grown. In particular, the growth of the N-SixGe1-x layer 34 is performed by a chemical vapor deposition method using disilane (SiH6), monogermane (GeH4) and phosphine (PH3) as source gases.

After removing the natural oxide film on the surface of the substrate, FIG.
As shown in (f), the silicon layer 18 is replaced with the P-silicon layer 3
3 and N-silicon layer 31 is epitaxially grown, and cobalt is deposited on the entire surface by sputtering.
After performing rapid thermal annealing twice or twice,
Unreacted cobalt is removed to form a CoSi2 layer 30.

At this time, all of the grown silicon layer is C
The thicknesses of the silicon layer and cobalt are predetermined so as to be consumed as the oSi2 layer.

A silicon oxide film 19 is deposited on the entire surface of the substrate by atmospheric pressure chemical vapor deposition. Further, a resist is applied on the entire surface, and then exposed and developed to form a resist pattern. Subsequently, the silicon oxide film is etched mainly by dry etching using a fluorine-based gas, and then the resist pattern is ashed and removed.

Further, as shown in FIG. 9 (g), CoSi2 is mainly formed by dry etching using a chlorine-based gas.
The layers, P-silicon layer, N-silicon layer, SixGe1-x layer are successively etched.

Next, as shown in FIG. 9H, after forming a resist pattern, the P + silicon layer, the N + silicon layer and the CoSi 2 layer are etched to obtain an island-shaped semiconductor. Then, the structure shown in FIG. 9I is obtained through the steps shown in FIGS. 8K to 8M.

As shown in the embodiment of the present invention, a CoSi2 layer is epitaxially grown on silicon, and a silicon layer and a SixGe1-x layer are further epitaxially grown on the CoSi2 layer, so that a source / drain layer having a low resistance is provided. A vertical field effect transistor can be formed.

Further, instead of the silicon substrate, as shown in FIG. 10, a vertical field effect transistor is formed on the SOI substrate 10 by a method similar to the method shown in the embodiment mode of the present invention. It is possible to realize a transistor which can reduce the capacitance and can operate at higher speed.

In the embodiment of the third invention, Si
Although the impurity doping into the xGe1-x layer and the silicon layer above it is performed by ion implantation, selective epitaxial growth in which impurities are introduced into the source gas may be used as described in the fifth embodiment of the invention.

Similarly, in the embodiment of the fourth invention, S
Impurity doping into the ixGe1-x layer and the silicon layer thereabove is performed by selective epitaxial growth in which impurities are introduced into the source gas, but ion implantation may be used as shown in the embodiment of the third invention. At this time, in order to suppress the generation of crystal defects as much as possible, the dose amount is 10 ¹³ cm.
^-2 or less is recommended.

Although the gate oxide film was formed by the thermal oxidation method in the third and fourth embodiments of the present invention,
Other methods may be used as long as the formation temperature does not exceed 800 ° C. For example, tetraethyl silicate (TEOS) may be used and formed at a temperature of about 700 ° C. by a reduced pressure vapor phase growth method. Further, as described above, the growth temperature is 80
As long as the temperature does not exceed 0 ° C., another insulating film such as a silicon nitride film may be used instead of the oxide film.

In the third and fourth embodiments of the present invention, the disilane and monogermane are used as raw materials for SixGe1.
-x layer was formed, but other source gases such as silane (Si
H4), dichlorosilane (SiH2Cl2) or higher order silane may be used.

Further, the structures and types of wirings and interlayer insulating films,
The forming method is not particularly limited.

[0082]

According to the vertical field effect transistor of the present invention, since the gate insulating film is not directly formed on the SixGe1-x layer, the interface state density between the insulating film and the channel layer can be reduced. A transistor having good characteristics can be realized.

[0083] Further, the source-drain layer can lower resistance, and the source layer or the drain layer, since the SixGei-x layer as a direct silicon layer or channel layer may epitaxial growth capable of ultrafast operation preparative Rungis <br/> It can be realized.

According to the vertical field effect transistor of the present invention, the lattice mismatch at the interface between the first and third impurity layers and the SixGe1-x layer can be relaxed, and the off-leak current between the source and the drain can be reduced. A transistor can be realized.
Further, since the germanium concentration is kept high in the effective channel portion, a transistor maintaining high speed can be realized.

According to the vertical field effect transistor of the present invention, the transistor is formed using the SOI substrate.
Therefore, the parasitic capacitance of the source / drain can be reduced, and the device speed can be increased.

According to the vertical field effect transistor of the present invention, since the impurities are sufficiently diffused from the source, channel, and drain layers to the silicon layer in contact with them, P is formed in the surface layer.
A transistor in which an N junction can be formed and leakage of the surface layer is reduced can be realized.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a structure of an N-type vertical field effect transistor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a band diagram of an N-type vertical field effect transistor according to the first embodiment of the present invention.

FIG. 3 shows Si / in the first embodiment of the present invention.
The figure which shows the effect of the thickness of the ultrathin silicon layer provided in the channel layer side wall of a SiGe heterostructure vertical field effect transistor.

FIG. 4 is a schematic diagram showing the structure of a P-type vertical field effect transistor using an alloy of silicon and cobalt for the source and drain layers in the second embodiment of the present invention.

FIG. 5: SOI in the second embodiment of the present invention
Structural cross-sectional view of a P-type vertical field effect transistor formed on a substrate

Diagram showing a channel direction of the leak current generation mechanism of a vertical field effect transistor capacitor of the present invention; FIG

FIG. 7 is a Ge concentration distribution diagram in the channel layer of the vertical field effect transistor of the present invention.

FIG. 8 is a sectional view of a manufacturing process of a complementary vertical field effect transistor according to the third embodiment of the present invention.

FIG. 9 is a sectional view of a manufacturing process of the complementary vertical field effect transistor according to the fourth embodiment of the present invention.

FIG. 10 is a sectional view of a complementary vertical field effect transistor according to an embodiment of the fourth aspect of the present invention.

[Explanation of symbols]

1 Silicon Substrate 2 SiGe Channel Layer 3 N + Silicon Layer 4 Ultrathin Silicon Layer 5 Gate Oxide Film 6 Gate Electrode 7 Alloy Layer of Silicon and Cobalt as Source Layer 8 P-type Silicon Layer 9 Silicon and Cobalt as Drain Layer Alloy layer 10 SOI substrate 11 First resist pattern 12 First resist pattern inversion pattern 13 N well layer 14 P well layer 15 P + silicon layer 16 N + silicon layer 17 SixGe1-x layer 18 Silicon layer 19 Silicon oxide film formed by atmospheric pressure chemical vapor deposition 20 Second resist pattern 21 Polycrystalline silicon film 22 BPSG film 23 Plug 24 First aluminum wiring 25 Silicon oxide film formed by plasma chemical vapor deposition 26 Through Hole 27 Second Aluminum Wiring 28 Passivation Film 29 Electrode Extraction Section 3 CoSi2 layer 31 N-silicon layer 32 P-SixGe1-x layer 33 P- silicon layer 34 N-SixGe1-x layer

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-267678 (JP, A) JP-A-6-224435 (JP, A) JP-A-61-144875 (JP, A) JP-A-2- 91976 (JP, A) JP-A-7-297406 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78 652

Claims (11)

(57) [Claims] 1. A first impurity layer formed on a silicon substrate and serving as a source layer or a drain layer to which an impurity of the first conductivity type is added, and a first impurity layer formed on the first impurity layer. A second impurity layer serving as a channel layer doped with a second conductivity type impurity; and a drain layer or a source layer formed on the second impurity layer and doped with a first conductivity type impurity. And a gate electrode formed on a side surface of the second impurity layer via a silicon layer and a gate insulating film, the second impurity layer being different from the first impurity layer. A vertical field effect transistor characterized by being an alloy of silicon and germanium epitaxially grown. 2. A first alloy layer of cobalt and silicon, which is formed on a silicon substrate and serves as a source layer or a drain layer epitaxially grown on the silicon substrate, and an alloy of the first cobalt and silicon. A first impurity layer formed on the layer and doped with an impurity of the first conductivity type; a second impurity layer serving as a channel layer doped with an impurity of the second conductivity type; A third impurity layer formed on the impurity layer and added with an impurity of the first conductivity type, and a second cobalt formed on the third impurity layer and serving as a drain layer or a source layer. An alloy layer of silicon and silicon, and a gate electrode formed on the side surface of the second impurity layer via a silicon layer and a gate insulating film, wherein the second impurity layer is different from the first impurity layer. Epitaxial growth Vertical field effect transistor, characterized in that the an alloy of silicon and germanium. 3. A process according to claim 1 or 2, characterized in that it e Bei a well layer of a second conductivity type impurity of the second conductivity type below the region where the first impurity layer is formed is added The vertical field effect transistor described. 4. A first conductor formed on a silicon substrate.
To be a source or drain layer doped with electrical impurities.
And a first impurity layer formed on the first impurity layer.
And a channel layer doped with impurities of the second conductivity type
And a second impurity layer to be formed on the second impurity layer.
Drain made of impurities of the first conductivity type
A third impurity layer to be a layer or a source layer, and the second impurity layer.
Formed on the side surface of the pure layer through the silicon layer and the gate insulating film
And a first gate electrode formed on the silicon substrate.
The second conductivity type is formed on the side of the first impurity layer.
The source or drain layer to which the impurities of
And a fourth impurity layer and formed on the fourth impurity layer.
It becomes a channel layer to which an impurity of the first conductivity type is added
A fifth impurity layer and formed on the fifth impurity layer
Or a drain layer doped with impurities of the second conductivity type or
A sixth impurity layer to be a source layer and the fifth impurity layer
Was formed on the side surface of the silicon via a silicon layer and a gate insulating film.
A second gate electrode, wherein the second impurity layer is
With respect to the first impurity layer, the fifth impurity layer is
Epitaxial to each of the fourth impurity layers
That it is an alloy of grown silicon and germanium
A characteristic vertical type field effect transistor. 5. Formed on a silicon substrate,
Epitaxially grown on the silicon substrate
First cobalt and silicon to be the source or drain layer
Alloy layer with the alloy and the first cobalt and silicon
It is formed on the gold layer and contains impurities of the first conductivity type.
The first impurity layer and the second conductivity type impurity are added.
A second impurity layer to be a channel layer, and the second impurity layer
Formed on the metal layer and doped with impurities of the first conductivity type.
And a third impurity layer formed on the third impurity layer.
The second koval which is a drain layer or a source layer.
Alloy layer of silicon and silicon, and side surface of the second impurity layer
On the first layer formed through the silicon layer and the gate insulating film
The gate electrode and the first insulating layer on the silicon substrate.
It is formed on the side of the pure material layer and
Source layer or drain layer that is epitaxially grown by
A third cobalt-silicon alloy layer,
It is formed on the alloy layer of cobalt and silicon.
A fourth impurity layer to which an impurity of two conductivity type is added;
A fifth impurity which becomes a channel layer to which conductivity type impurities are added is formed.
The pure layer and the fifth impurity layer are formed on the fifth impurity layer.
A sixth impurity layer to which an impurity of two conductivity type is added;
It is formed on the sixth impurity layer and is formed on the drain layer or the semiconductor layer.
A fourth alloy layer of cobalt and silicon to form a base layer,
A silicon layer and a gate insulating film are formed on the side surface of the fifth impurity layer.
A second gate electrode formed through
The second impurity layer is different from the first impurity layer in
The fifth impurity layer is different from the fourth impurity layer in that
The epitaxially grown silicon and germanium, respectively
Complementary vertical field effect transistor characterized by being an alloy of
Langista. 6. A region in which the first impurity layer is formed
A second conductivity type wafer having a second conductivity type impurity added below
And a fourth impurity layer is formed.
First conductivity type in which impurities of the first conductivity type are added below the region
5. The well layer of claim 4 is provided.
Vertical field effect transistor. 7. An alloy of the first silicon and cobalt
An impurity of the second conductivity type is added below the region where the layer is formed.
And a second conductive type well layer
Below the area where the alloy layer of silicon and cobalt is formed
First conductivity type well layer doped with first conductivity type impurities
6. The vertical electric field according to claim 5, further comprising:
Effect transistor. 8. In the second impurity layer made of an alloy of silicon and germanium, the atomic concentration of germanium is several percent or less in the vicinity of the first and third impurity layers, and the second impurity layer to be a channel layer. 8. The center portion is 30% or more, as claimed in claim 1.
The vertical field effect transistor according to any one of the above. 9. A vertical field effect transistor of any of claims 1 to 8 serial <br/> mounting characterized by using an SOI substrate instead of a silicon substrate. 10. The silicon layer is formed on the first layer immediately below the silicon layer.
It has almost the same impurity concentration as the first, second and third impurity layers.
The method according to any one of claims 1 to 9, characterized in that
Mounted vertical field effect transistor. 11. The method of claim 10, wherein the thickness of the silicon layer is equal to or less than 100 angstroms
Vertical field effect transistor.