JP3491606B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3491606B2 JP3491606B2 JP2000272436A JP2000272436A JP3491606B2 JP 3491606 B2 JP3491606 B2 JP 3491606B2 JP 2000272436 A JP2000272436 A JP 2000272436A JP 2000272436 A JP2000272436 A JP 2000272436A JP 3491606 B2 JP3491606 B2 JP 3491606B2
- Authority
- JP
- Japan
- Prior art keywords
- lsi chip
- substrate
- lsi
- semiconductor device
- ground
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、複数のＬＳＩをス
タックした（積み重ねた）半導体デバイスに関し、特に
パッケージ化に適した構造の半導体デバイス及びその製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of LSIs are stacked (stacked), and more particularly to a semiconductor device having a structure suitable for packaging and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】従来、ＬＳＩパッケージでは、パッケー
ジ内において複数のＬＳＩチップをスタック（積み重
ね）することが小型化するための重要な要素の一つとな
っている。この種のＬＳＩパッケージでは、図８に示す
ようにワイヤボンディング技術でスタックする手法が知
られている。図８に示すように、従来のＬＳＩパッケー
ジは、通常サブストレートと呼ばれる基板１００の上に
ＬＳＩ１０１、１０２をスタックし、各ＬＳＩと基板１
００との接続をワイヤボンディング１０５、１０６で行
い、さらに、封止樹脂１０３で封止したものである。基
板１００には半田ボール１０４が形成される。ＬＳＩ１
０１はＬＳＩ１０２に樹脂等により固定され、ＬＳＩ１
０２は、基板１００の接地（ＧＮＤ）配線パターンに導
電性樹脂を介して接続及び固着している。2. Description of the Related Art Conventionally, in an LSI package, stacking a plurality of LSI chips within the package has been one of the important factors for downsizing. In this type of LSI package, a method of stacking by a wire bonding technique is known as shown in FIG. As shown in FIG. 8, in a conventional LSI package, LSIs 101 and 102 are stacked on a substrate 100 usually called a substrate, and each LSI and the substrate 1 are stacked.
00 is connected by wire bonding 105 and 106, and is further sealed with a sealing resin 103. Solder balls 104 are formed on the substrate 100. LSI1
01 is fixed to the LSI 102 with resin or the like,
Reference numeral 02 is connected and fixed to the ground (GND) wiring pattern of the substrate 100 via a conductive resin.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、図８に
示すＬＳＩパッケージでは、ＬＳＩチップ１０１のシリ
コン基板をＧＮＤ接続できない欠点がある。However, the LSI package shown in FIG. 8 has a drawback that the silicon substrate of the LSI chip 101 cannot be GND-connected.
【０００４】例えばＬＳＩ１０１のＬＳＩ１０２へのマ
ウントに、通常のエポキシ樹脂の代わりに導電ペースト
を用いたとしても、それを基板１００のＧＮＤ電極に接
続する手段がワイヤボンディング１０５しかない。また
図８の場合には、ボンディングワイヤ長の制約から組み
合わせる二つのＬＳＩチップの寸法差に制約が発生して
いた。すなわち図８に示す様な従来のワイアボンディン
グ技術を用いたスタック型の半導体デバイスにおいて
は、基板上の上段のＬＳＩチップの外形寸法が、例えば
４ｍｍ以上、下側のＬＳＩチップより小さい場合には、
ボンディングワイア長が長すぎて製造歩留まりが悪化す
る。すなわちワイヤ長が長いために樹脂封止時の樹脂の
流動圧力によってワイアが流されて、ボンディングワイ
ア相互の電気的短絡などの不具合が発生する。For example, even if a conductive paste is used for mounting the LSI 101 on the LSI 102 instead of a normal epoxy resin, the wire bonding 105 is the only means for connecting it to the GND electrode of the substrate 100. Further, in the case of FIG. 8, there is a restriction on the dimensional difference between the two LSI chips to be combined due to the restriction of the bonding wire length. That is, in the stack type semiconductor device using the conventional wire bonding technique as shown in FIG. 8, when the outer dimension of the upper LSI chip on the substrate is, for example, 4 mm or more and smaller than the lower LSI chip,
The bonding wire length is too long and the manufacturing yield deteriorates. That is, since the wire length is long, the wires flow due to the flow pressure of the resin at the time of resin sealing, which causes a problem such as an electrical short circuit between the bonding wires.
【０００５】本発明の主な目的は、複数のＬＳＩチップ
を一つのパッケージに収納するスタックＣＳＰなどにお
いて、少なくとも二つのＬＳＩのＧＮＤ接続を可能とす
る半導体デバイスを提供することにある。また本発明の
他の目的は、ボンディングワイヤ長の制約から組み合わ
せる二つのＬＳＩチップの寸法差に制約が発生しない半
導体デバイスを提供することにある。A main object of the present invention is to provide a semiconductor device capable of GND connection of at least two LSIs in a stack CSP which accommodates a plurality of LSI chips in one package. Another object of the present invention is to provide a semiconductor device in which there is no restriction on the dimensional difference between two LSI chips to be combined due to the restriction on the bonding wire length.
【０００６】さらに本発明の目的は、上記目的を達成す
るための半導体デバイスの製造方法を提供することにあ
る。A further object of the present invention is to provide a method of manufacturing a semiconductor device for achieving the above object.
【０００７】[0007]
【課題を解決するための手段】上述した目的を達成する
ために、本発明による第１の半導体デバイスは、少なく
とも、第１及び第２のＬＳＩチップを含み、前記第１の
ＬＳＩチップは基板に設けられた貫通穴に挿入され、前
記第２のＬＳＩチップは前記第１のＬＳＩチップのグラ
ンド面側に搭載されてなるスタックタイプの半導体デバ
イスであって、前記第１及び第２のＬＳＩチップのグラ
ンド面同士が導電性樹脂を介して互いに直接接続される
ことによりＧＮＤ接続されることを特徴とする。[Means for Solving the Problems] To achieve the above-mentioned object.
Therefore, the first semiconductor device according to the present invention is less
In addition, the first and second LSI chips are included, and the first
The LSI chip is inserted into the through hole provided on the board,
The second LSI chip is a graph of the first LSI chip.
Stack type semiconductor device mounted on the band side
A chair, Ru is connected directly to one another the ground surfaces of the first and second LSI chip via the conductive resin
It is characterized by being connected to GND .
【０００８】 また、上述した目的を達成するために、
本発明による第２の半導体デバイスは、少なくとも、第
１及び第２のサブストレート層と、前記第１及び第２の
サブストレート層に挟まれて形成された内層パターンと
からなる多層サブストレートに、少なくとも第１及び第
２のＬＳＩチップが実装されてなるスタックタイプの半
導体デバイスであって、前記第１のＬＳＩチップは前記
多層サブストレートに設けられた貫通しない穴に挿入さ
れ、前記第２のＬＳＩチップは前記第２のサブストレー
ト層の前記内層パターンが形成されていない面に実装さ
れ、前記第１のＬＳＩチップのグランド面と前記内層パ
ターンのグランド電極とが接続されることによりＧＮＤ
接続されることを特徴とする。本発明によれば、従来の
サブストレート上に積み上げる方式の場合のスタック型
の半導体デバイスの制約であった二つのＬＳＩの大きさ
の差の課題を解決できる。In order to achieve the above-mentioned object,
A second semiconductor device according to the present invention comprises at least a second semiconductor device .
First and second substrate layers, and the first and second substrate layers
With the inner layer pattern sandwiched between the substrate layers
A multi-layer substrate comprising at least a first and a first
Stack type half with 2 LSI chips mounted
A conductor device, wherein the first LSI chip is
Inserted in a non-penetrating hole in the multilayer substrate
And the second LSI chip is the second subsystem
Mounted on the surface of the inner layer where the inner layer pattern is not formed.
The ground plane of the first LSI chip and the inner layer pattern.
GND by connecting to the ground electrode of the turn
It is characterized by being connected . According to the present invention, it is possible to solve the problem of the difference in size between two LSIs, which is a limitation of the stack type semiconductor device in the case of the conventional method of stacking on a substrate.
【０００９】 また、上述した目的を達成するために、
本発明による半導体デバイスの製造方法は、少なくと
も、第１のＬＳＩチップを基板に設けた貫通穴に挿入す
る第１の工程と、第２のＬＳＩチップを前記第１のＬＳ
Ｉチップのグランド面側に搭載する第２の工程と、前記
第１及び第２のＬＳＩチップのグランド面同士を導電性
樹脂を介して互いに直接接続することによりＧＮＤ接続
する第３の工程とを含む。Further , in order to achieve the above-mentioned object,
The manufacturing method of the semiconductor device according to the present invention is at least
Also insert the first LSI chip into the through hole provided on the substrate.
The first process and the second LSI chip to the first LS
GND connection by connecting directly to one another via a second step of mounting the ground plane side of the I chip, a conductive resin ground surfaces of the first and second LSI chip
And a third step of
【００１０】 また、上述した目的を達成するために、
本発明による半導体デバイスの別の製造方法は、少なく
とも、第１及び第２のサブストレート層と、前記第１及
び第２のサブストレート層に挟まれて形成された内層パ
ターンとからなる多層サブストレートを形成する第１の
工程と、第１のＬＳＩチップを前記多層サブストレート
に設けた貫通しない穴に挿入する第２の工程と、第２の
ＬＳＩチップを前記第２のサブストレート層の前記内層
パターンが形成されていない面に実装する第３の工程
と、第１のＬＳＩチップのグランド面と前記内層パター
ンのグランド電極とを接続することによりＧＮＤ接続す
る第４の工程とを含む。In order to achieve the above object,
Another method of manufacturing a semiconductor device according to the invention, less
And the first and second substrate layers and the first and second substrate layers.
And the inner layer pattern formed between the second substrate layer
First forming a multi-layer substrate consisting of turns
Process and the first LSI chip to the multilayer substrate
The second step of inserting into the non-penetrating hole provided in the
The LSI chip is the inner layer of the second substrate layer.
Third step of mounting on the surface on which no pattern is formed
And the ground surface of the first LSI chip and the inner layer pattern
GND connection by connecting the
And a fourth step .
【００１１】[0011]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して詳細に説明する。BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings.
【００１２】図１から図３は本発明の半導体デバイスの
実施の形態の製造方法を示す断面図であり、図３は本発
明の半導体デバイスの第１の実施の形態を示す断面図で
ある。、図３に示す本発明の第１の実施の形態は、スタ
ックＣＳＰ（ｃｈｉｐ ｓｉｚｅｐａｃｋａｇｅ）の半
導体デバイスである。1 to 3 are sectional views showing a manufacturing method of an embodiment of a semiconductor device of the present invention, and FIG. 3 is a sectional view showing a first embodiment of a semiconductor device of the present invention. The first embodiment of the present invention shown in FIG. 3 is a semiconductor device of a stack CSP (chip size package).
【００１３】最初、製造方法について説明する。図１に
示すように、ＣＳＰを構成する基板であるサブストレー
ト２の中央には、ＬＳＩ挿入用穴２Ａが形成されてい
る。その穴２Ａの中にＬＳＩチップ（以降単にＬＳＩと
称する）１が挿入された状態で、ＬＳＩ１の図示しない
電極がボンディングワイア（金線）３によりサブストレ
ート２の図示しない電極に接続する。この場合、ＬＳＩ
１及びサブストレート２は、搭載台４の上に搭載された
状態となっている。First, the manufacturing method will be described. As shown in FIG. 1, an LSI insertion hole 2A is formed in the center of a substrate 2 which is a substrate forming a CSP. With an LSI chip (hereinafter simply referred to as LSI) 1 inserted in the hole 2A, an electrode (not shown) of the LSI 1 is connected to an electrode (not shown) of the substrate 2 by a bonding wire (gold wire) 3. In this case, the LSI
The substrate 1 and the substrate 2 are mounted on the mounting table 4.
【００１４】この後、図２に示すようにメタルマスク７
とスキージ８によってエポキシ系樹脂からなる封止樹脂
６をＬＳＩ１の上から（ボンディングワイヤ側から）供
給し、封止樹脂６を１２０℃、３０分で固化する。これ
によりＬＳＩ１とボンディングワイヤ３とＬＳＩ挿入用
穴２Ａの周囲が、封止樹脂６により固定される。その
後、サブストレート２を反転し、ＬＳＩ１の裏面に相当
するシリコン基板面（グランド（ＧＮＤ）面）及びサブ
ストレート２のグランド（ＧＮＤ）電極面を上に向け
る。そして、図３に示すように、ＬＳＩ１よりサイズの
大きなＬＳＩチップ（以降単にＬＳＩと称する）９をそ
の裏面（グランド面）を下にして導電性樹脂１１を介し
てマウントし、導電性樹脂１１を固化した後、ＬＳＩ２
の電極（図示せず）をボンディングワイヤ１０にてサブ
ストレート２の電極（図示せず）に接続する。Thereafter, as shown in FIG. 2, the metal mask 7
Then, the squeegee 8 supplies the sealing resin 6 made of an epoxy resin from above the LSI 1 (from the bonding wire side), and the sealing resin 6 is solidified at 120 ° C. for 30 minutes. As a result, the periphery of the LSI 1, the bonding wire 3, and the LSI insertion hole 2A are fixed by the sealing resin 6. After that, the substrate 2 is turned over so that the silicon substrate surface (ground (GND) surface) corresponding to the back surface of the LSI 1 and the ground (GND) electrode surface of the substrate 2 face upward. Then, as shown in FIG. 3, an LSI chip (hereinafter simply referred to as an LSI) 9 having a size larger than that of the LSI 1 is mounted with a back surface (ground surface) thereof facing down via a conductive resin 11, and the conductive resin 11 is mounted. After solidification, LSI2
The electrode (not shown) is connected to the electrode (not shown) of the substrate 2 by the bonding wire 10.
【００１５】これにより、ＬＳＩ９のグランドとＬＳＩ
１及びサブストレート２のグランドが導電性樹脂１１を
介して互いに接続される。なお、導電性樹脂１１は、エ
ポキシ樹脂に銀のフィラーを混ぜたものであるが、これ
以外の導電性樹脂や樹脂以外の導電性ペーストであって
もよい。その後、封止樹脂１２によりＬＳＩ９をサブス
トレート２の上で封止し、さらにサブストレート２の半
田ボール実装面にハンダボール８を形成し、図３のスタ
ックＣＳＰが完成する。As a result, the ground of the LSI 9 and the LSI
1 and the ground of the substrate 2 are connected to each other via the conductive resin 11. The conductive resin 11 is a mixture of epoxy resin and silver filler, but may be conductive resin other than this or conductive paste other than resin. After that, the LSI 9 is sealed on the substrate 2 with the sealing resin 12, and the solder balls 8 are formed on the solder ball mounting surface of the substrate 2 to complete the stack CSP of FIG.
【００１６】本発明の第１の実施の形態によれば、ＬＳ
Ｉ１及び９のボンディングワイヤは、基板（サブストレ
ート２）の裏と表の面に実装され、接続距離が短くなる
ので、ＬＳＩ１、９両方のＬＳＩチップサイズには制限
されないスタックＣＳＰを得ることができる。たとえ
ば、ＬＳＩ１の寸法（縦、横サイズ）をＬＳＩ９の寸法
より４ｍｍ小さくしても、ワイヤボンディングに支障を
きたすことがない。According to the first embodiment of the present invention, the LS
The bonding wires I1 and 9 are mounted on the back and front surfaces of the substrate (substrate 2), and the connection distance is shortened, so that a stack CSP that is not limited to the LSI chip size of both LSI1 and 9 can be obtained. . For example, even if the dimensions (length and width) of the LSI 1 are made smaller than the dimensions of the LSI 9 by 4 mm, the wire bonding will not be hindered.
【００１７】また、ＬＳＩ９のマウント樹脂に導電性樹
脂を用いることによって、二つのＬＳＩチップ１及び９
のシリコン基板をサブストレート２に形成したＧＮＤ端
子に容易に接続することができる。Further, by using a conductive resin as a mount resin for the LSI 9, two LSI chips 1 and 9 can be used.
This silicon substrate can be easily connected to the GND terminal formed on the substrate 2.
【００１８】図４は本発明の第２の実施の形態を示す断
面図である。本第２の実施の形態では、２つのＬＳＩ１
Ａ、１Ｂがサブストレート２の２つのＬＳＩ挿入用穴に
配置され、ワイヤボンディングでサブストレート２に接
続されてからそれぞれ封止樹脂６Ａ、６Ｂによって封止
されたもので、それ以外の構造は、図３と同様である。FIG. 4 is a sectional view showing a second embodiment of the present invention. In the second embodiment, two LSIs 1
A and 1B are arranged in the two LSI insertion holes of the substrate 2 and connected to the substrate 2 by wire bonding, and then sealed by the sealing resins 6A and 6B, respectively. It is similar to FIG.
【００１９】このように、本発明では、基板（サブスト
レート）の穴の内部に複数のＬＳＩを配置して樹脂封止
した構造を提供することが容易にできるので、小型化に
大きく貢献する。しかも、本発明では、図４のように、
ＬＳＩ１Ａ、１Ｂのグランド面およびＬＳＩ９のグラン
ド面が互いに対向するので、導電性樹脂１１によって一
度に複数のＬＳＩ１Ａ、１ＢおよびＬＳＩ９のグランド
を取れる利点があり、製造工程の短縮にもつながる。図
５は本発明の第３の実施の形態を示す断面図である。本
第３の実施の形態では、図３に示す第１の実施の形態の
ＬＳＩ９の上に別なＬＳＩ９０を搭載して樹脂１２によ
って封止したものである。ＬＳＩ９０は、ＬＳＩ９より
サイズの小さいもので、サブストレート２の図示しない
電極にボンディングワイヤ９１で接続される。それ以外
の構造は、図３と同様である。As described above, according to the present invention, it is possible to easily provide a structure in which a plurality of LSIs are arranged inside the holes of the substrate (substrate) and resin-sealed, which greatly contributes to miniaturization. Moreover, in the present invention, as shown in FIG.
Since the ground surfaces of the LSIs 1A and 1B and the ground surface of the LSI 9 are opposed to each other, there is an advantage that the conductive resin 11 can ground the plurality of LSIs 1A, 1B, and LSI 9 at one time, which leads to a reduction in manufacturing process. FIG. 5 is a sectional view showing a third embodiment of the present invention. In the present third embodiment, another LSI 90 is mounted on the LSI 9 of the first embodiment shown in FIG. 3 and sealed with resin 12. The LSI 90 has a smaller size than the LSI 9, and is connected to an electrode (not shown) of the substrate 2 by a bonding wire 91. The other structure is the same as that of FIG.
【００２０】本発明では、図５に示すように、ＬＳＩ９
の上部に多層実装してもよい。ただし、ＬＳＩ９０とＬ
ＳＩ９とは、非導電性樹脂（たとえば、非導電性のエポ
キシ樹脂）１４によって接続され、絶縁される。In the present invention, as shown in FIG.
It may be mounted in multiple layers on top of. However, LSI90 and L
SI9 is connected and insulated by a non-conductive resin (for example, a non-conductive epoxy resin) 14.
【００２１】図６は本発明の半導体デバイスの第４の実
施の形態を示す断面図である。前述した第１の実施の形
態では、サブストレートにＬＳＩ挿入用穴を形成して一
つのＬＳＩをそこに配置したが、図６に示す第４の実施
の形態では、サブストレートに多層サブストレート２０
を用いて、その内層パターン２１のＧＮＤパターン部分
にＬＳＩ１をマウントしてＧＮＤ接続する。FIG. 6 is a sectional view showing a fourth embodiment of the semiconductor device of the present invention. In the above-described first embodiment, the LSI insertion hole is formed in the substrate and one LSI is arranged therein. However, in the fourth embodiment shown in FIG. 6, the multilayer substrate 20 is provided on the substrate.
Using, the LSI 1 is mounted on the GND pattern portion of the inner layer pattern 21 and GND connection is performed.
【００２２】この場合、ＬＳＩ１は、多層サブストレー
ト２０の第１のサブストレート層２０Ａに形成された挿
入用穴に挿入されるが、その下の第２のサブストレート
層２０Ｂには、ＬＳＩ１を挿入する穴が形成されていな
い。内層パターン２１は、銅箔などの導電パターンによ
り形成される。In this case, the LSI 1 is inserted into the insertion hole formed in the first substrate layer 20A of the multilayer substrate 20, but the LSI 1 is inserted into the second substrate layer 20B below the insertion hole. No holes are formed. The inner layer pattern 21 is formed of a conductive pattern such as copper foil.
【００２３】また、図６の第４の実施の形態の場合、図
３に示す第１の実施の形態で使用したＬＳＩ９は、導電
性樹脂１１により第２のサブストレート層２０Ｂのグラ
ンドパターンに実装され、ボンディングワイヤ１０によ
って接続される。この場合、第２のサブストレート層２
０Ｂのグランドパターンと内層パターン２１のグランド
部分とは、スルーホール２５によって接続される。最後
に、図示しない樹脂によってＬＳＩ９を図３のように封
止し、半田ボールをサブストレート２０Ａ側に形成して
ＣＳＰの半導体パッケージとなる。Further, in the case of the fourth embodiment of FIG. 6, the LSI 9 used in the first embodiment shown in FIG. 3 is mounted on the ground pattern of the second substrate layer 20B by the conductive resin 11. And are connected by the bonding wire 10. In this case, the second substrate layer 2
The ground pattern of 0B and the ground portion of the inner layer pattern 21 are connected by a through hole 25. Finally, the LSI 9 is sealed with a resin (not shown) as shown in FIG. 3, and solder balls are formed on the substrate 20A side to form a CSP semiconductor package.
【００２４】図７は本発明の半導体デバイスの第５の実
施の形態を示す断面図である。FIG. 7 is a sectional view showing the fifth embodiment of the semiconductor device of the present invention.
【００２５】図７の第５の実施の形態では、ＬＳＩ１を
封入する多層サブストレート３０の第１のサブストレー
ト層３０ＡのＬＳＩ挿入用穴の形状が、図６に示す第４
の実施の形態と異なり、段差を持たせている。また、Ｌ
ＳＩ１のワイアボンディングを第１のサブストレート層
３０Ａの内層（図の段差の部分）に行うことによって封
止樹脂６の膨らみを防止する。なお、ＬＳＩ９の封止と
半田バンプの形成によるパッケージ化は、前述した実施
例の通りです。本実施の形態の場合、多層サブストレー
ト３０および封止樹脂６の表面がフラットになるので、
ＬＳＩ９は、多層サブストレート３０のどちらの面にも
実装でき設計の自由度がある利点があります。In the fifth embodiment of FIG. 7, the shape of the LSI insertion hole of the first substrate layer 30A of the multilayer substrate 30 enclosing the LSI 1 is the fourth shown in FIG.
Unlike the above embodiment, a step is provided. Also, L
The swelling of the sealing resin 6 is prevented by performing the wire bonding of SI1 on the inner layer (the stepped portion in the figure) of the first substrate layer 30A. The packaging by encapsulating the LSI 9 and forming solder bumps is the same as in the above-mentioned embodiment. In the case of the present embodiment, since the surfaces of the multilayer substrate 30 and the sealing resin 6 are flat,
The LSI 9 has the advantage that it can be mounted on either side of the multi-layer substrate 30 and has the freedom of design.
【００２６】[0026]
【発明の効果】以上説明したように、本発明によれば、
少なくとも二つのＬＳＩのＧＮＤ接続を可能とし、ボン
ディングワイヤ長の制約から組み合わせる二つのＬＳＩ
チップの寸法差に制約が発生しない。As described above, according to the present invention,
Two LSIs that allow GND connection of at least two LSIs and are combined due to the limitation of bonding wire length
There are no restrictions on the chip size difference.
【図１】本発明の半導体デバイスの第１の実施の形態の
製造工程を示す断面図である。FIG. 1 is a cross-sectional view showing a manufacturing process of a first embodiment of a semiconductor device of the present invention.
【図２】本発明の半導体デバイスの第１の実施の形態に
おいて図１の次の製造工程を示す断面図である。FIG. 2 is a cross-sectional view showing the next manufacturing step of FIG. 1 in the first embodiment of the semiconductor device of the present invention.
【図３】本発明の半導体デバイスの第１の実施の形態を
示す断面図である。FIG. 3 is a cross-sectional view showing a first embodiment of a semiconductor device of the present invention.
【図４】本発明の半導体デバイスの第２の実施の形態を
示す断面図である。FIG. 4 is a sectional view showing a second embodiment of a semiconductor device of the present invention.
【図５】本発明の半導体デバイスの第３の実施の形態を
示す断面図である。FIG. 5 is a sectional view showing a third embodiment of the semiconductor device of the present invention.
【図６】本発明の半導体デバイスの第４の実施の形態を
示す断面図である。FIG. 6 is a sectional view showing a fourth embodiment of a semiconductor device of the present invention.
【図７】本発明の半導体デバイスの第５の実施の形態を
示す断面図である。FIG. 7 is a sectional view showing a fifth embodiment of a semiconductor device of the present invention.
【図８】従来の半導体パッケージを示す断面図である。FIG. 8 is a cross-sectional view showing a conventional semiconductor package.
１ ＬＳＩ ２ サブストレート（基板） ２Ａ ＬＳＩ挿入用穴 ３ ボンディングワイヤ ４ 搭載台 ６ 封止樹脂 ７ メタルマスク ８ スキージ ９ ＬＳＩ １０ ボンディングワイヤ １１ 導電性樹脂 １２ 封止樹脂 1 LSI 2 substrate (substrate) 2A LSI insertion hole 3 Bonding wire 4 mounting base 6 Sealing resin 7 metal mask 8 squeegee 9 LSI 10 Bonding wire 11 Conductive resin 12 Sealing resin
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平９−270435（ＪＰ，Ａ) 特開 平３−211763（ＪＰ，Ａ) 特開 平１−93196（ＪＰ，Ａ) 特開 平５−48001（ＪＰ，Ａ) 特開 平２−58356（ＪＰ，Ａ) 実開 昭61−102074（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 25/065 H01L 25/07 H01L 25/18 H01L 23/52 ─────────────────────────────────────────────────── --- Continuation of front page (56) References JP-A-9-270435 (JP, A) JP-A-3-211763 (JP, A) JP-A-1-93196 (JP, A) JP-A-5- 48001 (JP, A) JP-A-2-58356 (JP, A) Actually developed 61-102074 (JP, U) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 25/065 H01L 25 / 07 H01L 25/18 H01L 23/52
Claims (8)
記第１のＬＳＩチップは基板に設けられた貫通穴に挿入
され、前記第２のＬＳＩチップは前記第１のＬＳＩチッ
プのグランド面側に搭載されてなるスタックタイプの半
導体デバイスであって、前記第１及び第２のＬＳＩチッ
プのグランド面同士が導電性樹脂を介して互いに直接接
続されることによりＧＮＤ接続されることを特徴とする
半導体デバイス。1. A device including a first and a second LSI chip, comprising:
Insert the first LSI chip into the through hole provided on the board.
And the second LSI chip is connected to the first LSI chip.
Stack type half mounted on the ground side of the stack
A conductor device, a semiconductor device, characterized in that the ground surfaces of the first and second LSI chip is connected to GND by Rukoto directly contact <br/> connection with each other via the conductive resin.
１のＬＳＩチップが搭載された前記基板と同一基板上の
電極にワイヤボンディングされることにより接続される
ことを特徴とする請求項１に記載された半導体デバイ
ス。2. The electrode of the second LSI chip is the first
On the same substrate as the substrate on which the 1st LSI chip is mounted
The semiconductor device according to claim 1, wherein the semiconductor device is connected to the electrode by wire bonding .
前記第２のＬＳＩチップの外形寸法より４ｍｍ以上小さ
いことを特徴とする請求項１に記載された半導体デバイ
ス。3. The outer dimensions of the first LSI chip are:
4 mm or more smaller than the external dimensions of the second LSI chip
The semiconductor device according to claim 1 , wherein
記第１及び第２のサブストレート層に挟まれて形成され
た内層パターンとからなる多層サブストレートに、少な
くとも第１及び第２のＬＳＩチップが実装されてなるス
タックタイプの半導体デバイスであって、前記第１のＬ
ＳＩチップは前記多層サブストレートに設けられた貫通
しない穴に挿入され、前記第２のＬＳＩチップは前記第
２のサブストレート層の前記内層パターンが形成されて
いない面に実装され、前記第１のＬＳＩチップのグラン
ド面と前記内層パターンのグランド電極とが接続される
ことによりＧＮＤ接続されることを特徴とする半導体デ
バイス。4. A first and a second substrate layer, and
Formed by being sandwiched between the first and second substrate layers
A multi-layer substrate consisting of
At least a first and a second LSI chip mounted
A tack-type semiconductor device, wherein the first L
SI chip penetrates through the multi-layer substrate
Not inserted into the hole, and the second LSI chip is inserted into the first
The inner layer pattern of the two substrate layers is formed
It is mounted on the non-side and is the ground of the first LSI chip.
And the ground surface of the inner layer pattern is connected
A semiconductor device characterized by being GND-connected by doing so.
導電性樹脂を介して前記第２のサブストレート層のグラ
ンドパターンに接続され、前記第２のＬＳＩと前記第２
のサブストレート層のグランドパターンの接続面とが前
記第２のサブストレート層に設けられたスルーホールを
介して前記内層パターンにＧＮＤ接続されることを特徴
とする請求項４に記載された半導体デバイス。 5. The ground surface of the second LSI chip is
Through the conductive resin, the glass of the second substrate layer is
The second LSI and the second LSI.
The ground plane connection surface of the substrate layer
The through hole provided in the second substrate layer
It is characterized in that it is GND-connected to the inner layer pattern through
The semiconductor device according to claim 4.
穴に挿入する第１の工程と、第２のＬＳＩチップを前記
第１のＬＳＩチップのグランド面側に搭載する第２の工
程と、前記第１及び第２のＬＳＩチップのグランド面同
士を導電性樹脂を介して互いに直接接続することにより
ＧＮＤ接続する第３の工程とを含む半導体デバイスの製
造方法。6. A through hole provided with a first LSI chip on a substrate.
The first step of inserting into the hole and the second LSI chip
The second process to be mounted on the ground side of the first LSI chip
And extent, the ground plane the same of the first and second LSI chip
By connecting the engineers directly to each other via the conductive resin
And a third step of GND connection .
１のＬＳＩチップを搭載した前記基板と同一基板上の電
極にワイヤボンディングする第４の工程とを含む請求項
６に記載された半導体デバイスの製造方法。7. An electrode of the second LSI chip is connected to the first LSI chip.
The same circuit board as the one on which the 1st LSI chip is mounted.
A fourth step of wire bonding to the pole.
7. The method for manufacturing a semiconductor device described in 6 .
記第１及び第２のサブストレート層に挟まれて形成され
た内層パターンとからなる多層サブストレートを形成す
る第１の工程と、第１のＬＳＩチップを前記多層サブス
トレートに設けた貫通しない穴に挿入する第２の工程
と、第２のＬＳＩチップを前記第２のサブストレート層
の前記内層パターンが形成されていない面に実装する第
３の工程と、第１のＬＳＩチップのグランド面と前記内
層パターンのグランド電極とを接続することによりＧＮ
Ｄ接続する第４の工程とを含む半導体デバイスの製造方
法。 8. A first and second substrate layer, and
Formed by being sandwiched between the first and second substrate layers
A multi-layer substrate consisting of
And the first LSI chip and the first LSI chip
Second step of inserting into a non-penetrating hole provided in the slate
And a second LSI chip on the second substrate layer.
Mounted on the surface where the inner layer pattern is not formed
Step 3, and the ground plane of the first LSI chip and the above
GN by connecting to the ground electrode of the layer pattern
Manufacturing method of semiconductor device including fourth step of D connection
Law.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000272436A JP3491606B2 (en) | 2000-09-08 | 2000-09-08 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000272436A JP3491606B2 (en) | 2000-09-08 | 2000-09-08 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002083924A JP2002083924A (en) | 2002-03-22 |
| JP3491606B2 true JP3491606B2 (en) | 2004-01-26 |
Family
ID=18758547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000272436A Expired - Fee Related JP3491606B2 (en) | 2000-09-08 | 2000-09-08 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3491606B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4571320B2 (en) * | 2001-02-02 | 2010-10-27 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor chip package |
-
2000
- 2000-09-08 JP JP2000272436A patent/JP3491606B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2002083924A (en) | 2002-03-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7615859B2 (en) | Thin semiconductor package having stackable lead frame and method of manufacturing the same | |
| US7872343B1 (en) | Dual laminate package structure with embedded elements | |
| US7338837B2 (en) | Semiconductor packages for enhanced number of terminals, speed and power performance | |
| US6781240B2 (en) | Semiconductor package with semiconductor chips stacked therein and method of making the package | |
| US7230326B2 (en) | Semiconductor device and wire bonding chip size package therefor | |
| JP5135493B2 (en) | Integrated circuit package | |
| US20090278243A1 (en) | Stacked type chip package structure and method for fabricating the same | |
| US20070176269A1 (en) | Multi-chips module package and manufacturing method thereof | |
| JP2002170906A (en) | Semiconductor device and its manufacturing method | |
| US8361857B2 (en) | Semiconductor device having a simplified stack and method for manufacturing thereof | |
| KR100803643B1 (en) | A method of manufacturing an integrated circuit package | |
| US20040124516A1 (en) | Circuit device, circuit module, and method for manufacturing circuit device | |
| US7015591B2 (en) | Exposed pad module integrating a passive device therein | |
| US20060006504A1 (en) | Multilayer leadframe module with embedded passive component and method of fabricating the same | |
| US7479706B2 (en) | Chip package structure | |
| US6689637B2 (en) | Method of manufacturing a multi-chip semiconductor package | |
| JP3491606B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP4140012B2 (en) | Chip-shaped electronic component, manufacturing method thereof and mounting structure | |
| CN114826190B (en) | Acoustic surface filter packaging method, acoustic surface filter and communication equipment | |
| US11694904B2 (en) | Substrate structure, and fabrication and packaging methods thereof | |
| KR100762871B1 (en) | method for fabricating chip scale package | |
| KR20010073946A (en) | Semiconductor device and manufacturing method of the same with dimple type side pad | |
| KR100907730B1 (en) | Semiconductor package and manufacturing method thereof | |
| TW201738976A (en) | Chip package and chip packaging process | |
| KR20040045696A (en) | method for fabricating semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20031014 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071114 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081114 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081114 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091114 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091114 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101114 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111114 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111114 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121114 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121114 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131114 Year of fee payment: 10 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |