JP3454705B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device in which a memory cell having a floating gate is electrically rewritable.

[0002]

2. Description of the Related Art An electrically rewritable EEPROM
(Electrically Erasable Programmable Read Only Mem
ory), there is something called flash memory. The flash memory stores information by controlling the state of injecting charges into the floating gate and the state of erasing charges for each memory cell.

FIG. 2 shows a unit cell structure of a flash memory. (11) is, for example, a P-type semiconductor substrate, (1
2) and 13) are drain and source regions made of N-type diffusion layers, (14) is an oxide film, (15) is a floating gate made of polycide, (16) is an oxide film, and (17) is a polycide. Is a control gate, (18) is an interlayer insulating film, and (19) is a bit line. The bit line (19) is connected to the drain region (12). The structure mentioned here is a split gate type in which a part of the control gate (17) is above the floating gate (15) and the remaining part is directly on the oxide film (14) to control the channel. There is. In particular, a projection is provided at the end of the floating gate (15) from which electrons are extracted to the control gate (17) during erasing. In addition, the drain region (1
2) and the source region (13) are formed by ion implantation and thermal diffusion using the floating gate (15) and the control gate (17) as a mask. In particular, the source region (13) has a large implantation amount. Therefore, the thermal diffusion region extends below the floating gate (15) and a capacitive coupling is formed between the thermal diffusion region and the floating gate (15).

FIG. 3 shows a cell array of a flash memory. In the central part of the figure, the word line (21) and the source line (23) run in parallel, and the bit line (22) runs crossing this. At the intersection of the word line (21) and the source line (23) and the bit line (22), one memory cell transistor (20) shown in FIG.
Are formed. The word line (21) is connected to all the control gates (17) in the same row. The bit line (22) is connected to all drain regions (12) in the same column, and the source line (23) is connected to all source regions (13) in the same row. The source line (23) is further connected to the power supply line (26). The source line (23) is formed by extending the source region (13) shown in FIG. 2 in the direction perpendicular to the plane of the drawing. On the left side of the figure, a row decoder (2
7) and is connected to each word line (21). In the upper part of the figure, there is a column decoder (28) for selecting the column position.
Control the ON / OFF of the column selection transistor (24) connected to the data line (25) and each bit line (22). The power supply line (26) is connected to the first write control circuit (3
1), the first write control circuit (31) is supplied with the voltage of the booster circuit (32). The data line (25) is controlled by the second write control circuit (33).

When writing with this configuration, first,
The high voltage generated by the booster circuit (32) is applied from the first write control circuit (31) to the power supply line (26), and 15 V is applied to the source region (13) via the source line (23). To do. At the same time, the data line (25) is grounded by the second write control circuit (33). In this state, for example,
When writing to the memory cell (20) at the upper left position (1, 1), the first word line (2
1) is selected, a 2V voltage is applied to the control gate (17), the first column selection transistor (24) is turned on by the column decoder (28), and the drain region (12) is grounded. Then, a high voltage is applied to the floating gate (15) for capacitive coupling with the source region (13), and as a result, the memory cell transistor (20) is turned on. As a result, the electrons supplied to the drain region (12) are accelerated, pass through the oxide film (14) as hot electrons, and are injected into the floating gate (15). Thus, the memory cell transistor (20) in which electrons are injected into the floating gate (15) has a high threshold value.

When reading a written cell,
First, the first write control circuit (31) causes the power supply line (2
6) is grounded and the source region (13) is grounded via the source line (23). At the same time, a low voltage is applied to the data line (25) by the second write control circuit (33). In this state, the memory cell (2
When reading 0), the row decoder (27) selects the first word line (21), applies 2V to the control gate (17), and the column decoder (28) selects the first column. The transistor (24) is turned on and the drain region (1
1V is applied to 3). In the memory cell transistor (20), electrons are injected into the floating gate (15) to raise the threshold value, so that the memory cell transistor (20) still does not turn on and no current flows. As a result, the voltage of the bit line (22) does not change, and the bit line (2
The 0) voltage and the reference voltage are compared and "1" is read.

On the other hand, if writing is not performed in the memory cell transistor (20) at the (1,1) position,
The memory cell transistor (20) is turned on by the voltage applied to the control gate (17), and a current flows between the source and drain. As a result, the voltage of 1 V applied to the bit line (22) changes, so that the changed bit line (22) voltage is compared with the reference voltage in the sense circuit, and "0" is read.

When erasing is performed, the first write control circuit (3
1) and the second write control circuit (33) from the power supply line (2
6) and the data line (25) are grounded, and all the column selection transistors (24) are turned on by the column decoder (28), so that the drain region (12)
And the source region (13) to ground. In this state, further select all rows by the row decoder (27),
A high voltage of 14V is applied to the control gate (17). Then, the electric field is concentrated on the protrusion formed on the floating gate (15), and electrons are extracted to the control gate (17) by the tunnel effect.

[0009]

The split gate type flash memory shown in FIG. 2 has a problem that the occupied area of a memory cell becomes larger than that of a stack gate type in which a control gate and a floating gate are vertically stacked. . Therefore, as shown in FIG. 2, by adopting a cell array in which the positions of the drain (12) and the source region (13) are reversed in the row direction between adjacent rows, a structure in which the occupied area is made as small as possible is adopted. Has been done. However, in such a cell array, the following new problems are caused.

If there is a mask shift in the manufacturing process, the planar positional relationship between the drain region (12) and the source region (13), the floating gate (15), and the control gate (17) may shift. Therefore, the on-current value may fluctuate due to a change in channel length, a change in the amount of electrons injected into the floating gate (15), or the like. As a result,
In the written cell, "1" should be read because the ON current does not flow, but the ON current value becomes large and "0" is read.

Such a problem depends on the mask displacement.
Although it is possible to solve the problem by a method such as fine adjustment of the reference voltage at the time of writing, in the cell array structure of FIG. 3, it is necessary to increase or decrease the reference voltage between the odd-numbered row and the even-numbered row. There is a difference. Therefore, the circuit configuration becomes too complicated in order to solve the problem of mask shift by adjusting the reference voltage.

[0012]

The present invention has been made to solve this problem, and a plurality of memory cell transistors for storing write information by injecting charges into an electrically insulated floating gate are arranged in a matrix. In the non-volatile semiconductor memory device, the source and drain of the memory cell transistor are arranged in such a manner that the positional relationship between the source and the drain of the memory cell transistor is reversed between the odd row and the even row. A first correction cell transistor having the same source / drain positional relationship as the transistor, a second correction cell transistor having the same source / drain positional relationship as the memory cell transistors in the odd rows, and a charge in the floating gate The row position information of the memory cell transistor selected to inject Alternatively, a correction circuit that selects a second correction cell transistor and generates a correction voltage according to the selected correction cell transistor, and voltage control that controls a read selection voltage for the memory cell transistor according to the correction voltage This is a configuration including a circuit.

As a result, even if the characteristics of the memory cells are different between the even-numbered row and the odd-numbered row, the reading is performed by the selection voltage corresponding thereto, so that the characteristic variation is absorbed and disappears at the time of reading. In addition, a plurality of memory cell transistors that store write information by injecting charges into an electrically insulated floating gate are arranged in a matrix, and the memory cell transistors have a positional relationship between a source and a drain thereof. A non-volatile semiconductor memory device in which odd-numbered rows and even-numbered rows are arranged in reverse to each other, a first correction cell transistor and an odd number having the same source / drain positional relationship as the memory cell transistors in the even-numbered row. The second correction cell transistor having the same source / drain positional relationship as the memory cell transistor of the row, and the first or the second depending on the row position information of the memory cell transistor selected to inject charges into the floating gate. The second correction cell transistor is selected, and the selected correction cell transistor is selected. A correction circuit for generating a correction voltage according to the Le transistor, a configuration in which a voltage control circuit for controlling the write select voltage to the memory cell transistor in response to the correction voltage.

As a result, even if the characteristics of the memory cells are different between the even-numbered row and the odd-numbered row, the writing is performed by the selection voltage corresponding thereto, so that the variations in the reading characteristics are absorbed and disappear during the writing.

[0015]

1 is an equivalent circuit diagram of a correction circuit according to an embodiment of the present invention. Voltage stabilizing transistor (1), resistors (2) (3), selector (4), first
And second correction cell transistors (5) and (6). The first correction cell transistor (5) has the same source / drain direction as the even row of the memory cell transistor (20) shown in FIG. 2, and the second correction cell transistor (6) has an odd row. It has the same source / drain orientation as.

First, as the first embodiment, when the written information is read, the read selection control voltage Vr for applying the read selection voltage to the word line (21) is the voltage stabilization transistor (1). Applied to the gate. As a result, a predetermined current flows from the voltage source VDD to the resistors (2) and (3) and is supplied to the output terminal of the selector (4). The selector (4) receives the same row position data as the row decoder (27), in particular, the data of the least significant bit that determines whether it is an odd row or an even row as an even / odd data signal O / E. The selection switching of the input terminal is controlled. However,
The even / odd data signal O / E is output via the exclusive OR gate (7). This exclusive OR gate (7) has an even / odd data signal O /
In addition to being supplied with E, the read / write switching signal R / W is also supplied to the other input terminal, and the even / odd data signal O / E is inverted / non-inverted depending on whether it is reading or writing. Inversion is controlled. The control gate (17) and the source region (13) of the first correction cell transistor (5) are connected to one of the two input ends of the selector (4), and the second input is connected to the other input end. Correction cell transistor (6)
The control gate (17) and the source region (13) are connected to each other. The drain regions (12) of the first and second correction cell transistors (5) and (6) are connected to the ground source VSS. Partial voltage V between resistors (2) and (3)
R is supplied to each output transistor (171) in the row decoder (27). The divided voltage VR is applied to each word line (21) as a read selection voltage via the output transistor (171) turned on by the selection circuit (170) in the row decoder (27). The first and second correction cell transistors (5) and (6) are formed on the same substrate at the same time as the memory cell transistor (20).

For example, the plane positional relationship between the floating gate (15) and the control gate (17) may be displaced due to a mask shift in the manufacturing process. Figure 2
In the above, it is assumed that the floating gate (15) and the control gate (17) are shifted to the left and right, and are changed so that even rows are separated from each other and odd rows are moved closer to each other. Since the drain region (12) and the source region (13) are formed by using the floating gate (15) and the control gate (17) as a mask, the channel length becomes long for even rows and short for odd rows. Become. As a result, the on-resistance increases and the on-current decreases in the even rows, and the on-resistance decreases and the on-current increases in the odd rows.

In the present invention, when reading is performed, the first correction cell transistor (5) is selected when reading an even numbered row and controlled by the even / odd data signal O / E, and when reading an odd numbered row, the first correction cell transistor (5) is selected. The correction cell transistor (6) of No. 2 is selected. Partial voltage VR between resistors (2) and (3)
Is determined by the ratio between the resistance value of the resistors (2) and (3) and the ON resistance value of the first or second correction transistor (5) (6). Since the ON resistances of the first and second correction transistors (5) and (6) are different, the partial voltage VR can be adjusted depending on which is selected. Since the first correction transistor (5) has the same structure as the memory cell transistors (20) in even rows, the on-resistance value is large. As a result, the partial pressure VR becomes relatively high when reading an even-numbered row. Therefore, the read selection voltage applied to each word line (21) in the even-numbered row becomes relatively high and the memory cell transistor (20).
The resistance of the channel formed in the lower part is reduced, and the increase in the on-resistance due to the position shift is offset and disappeared. Further, when reading an odd-numbered row, since the second correction cell transistor (6) having a small ON resistance is selected, conversely, the divided voltage VR becomes relatively low and the read applied to the word line (21). The selection voltage becomes low. Therefore, the channel resistance of the memory cell transistor (20) increases, and the decrease in the on-resistance due to the positional shift is offset and disappears.

As described above, according to the present invention, the first and second correction cell transistors (5) (6), which are the same as those in the even-numbered row and the odd-numbered row, are selected depending on whether the even-numbered row or the odd-numbered row is read. ) The word line (21)
This is a configuration for controlling the read selection voltage applied to. For this reason, even if the characteristics of each memory cell transistor (20) change due to misalignment in the manufacturing process, the change can be absorbed and erased at the time of reading, thus preventing malfunction.

Next, a second embodiment of the present invention will be described. This embodiment relates to the case of writing. The write selection control voltage Vw for applying the write selection voltage to the word line (21) is the voltage stabilizing transistor (1).
Read / write switching signal R /
W Inverted with respect to the first embodiment. As a result, a current flows through the resistors (2) and (3) and the selector (4) to the first correction cell transistor (5) or the second correction cell transistor (6). In the present embodiment, the output signal from the exclusive OR gate (7) is a signal obtained by inverting the even / odd data signal O / E as compared with the case of the first embodiment. Therefore, the second correction cell transistor (6) is selected when writing to the even-numbered row, and the first correction cell transistor (5) is selected when writing to the odd-numbered row. Since the on-resistance value of the second correction transistor (6) is small, the voltage division VR is relatively low when writing to even-numbered rows, and the write selection voltage applied to the word line (21) is also low. As a result, the energy of hot electrons is small, the amount of electrons injected into the floating gate (15) is reduced, the threshold rise of the memory cell transistor (20) is suppressed to a small level, and the on-resistance is also reduced. Therefore, the increase in the on-resistance due to the positional deviation is offset and disappears. When writing to odd rows, the first correction cell transistor (5) is selected. Therefore, contrary to the even-numbered row, the partial voltage VR is relatively high and the write selection voltage is also high, so that the amount of electrons injected into the floating gate (15) is increased, and the memory cell transistor (20) is increased. ON resistance increases. Therefore, the decrease in the on-resistance due to the positional deviation is offset and disappears.

As described above, according to the present invention, the second and first correction cell transistors (6) (6) The configuration is such that the write selection voltage is controlled by the characteristic variation of 5). Therefore, even if the characteristics of each memory cell transistor (20) change due to a positional shift in the manufacturing process, the change is absorbed and disappears at the time of writing, so that malfunction can be prevented.

[0022]

As described above, according to the present invention,
Since fluctuations in characteristics that occur during the manufacturing process of the nonvolatile semiconductor memory can be automatically absorbed and erased in the operation stage, malfunctions can be prevented and the yield can be improved.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a correction circuit of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a cell structure of a nonvolatile semiconductor memory device.

FIG. 3 is an equivalent circuit diagram showing a cell array of a nonvolatile semiconductor memory device.

[Explanation of symbols]

1 Voltage stabilizing transistor A few resistors 4 selector 5,6 Correction cell transistor 12 drain region 13 Source area 15 floating gate 17 Control gate 21 word lines 19,22 bit line 23 Source line 24-column selection transistor 25 data lines 26 power line 27 Row Decoder 28 column decoder 171 output transistor

─────────────────────────────────────────────────── Continued Front Page (56) References JP 10-269789 (JP, A) JP 8-203291 (JP, A) JP 11-260072 (JP, A) US Patent 5335198 (US , A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 16/00-16/34

Claims (6)

(57) [Claims] 1. A plurality of memory cell transistors for storing write information by injecting charges into an electrically insulated floating gate are arranged in a matrix.
The memory cell transistor, the positional relationship between the source and drain, in the nonvolatile semiconductor memory device in which are arranged reversed to one another between the odd and even rows, the same source de and the memory cell transistors of the even rows
The same source drain as the first correction cell transistor having the positional relationship of the rain floating gate control gate and the memory cell transistor in the odd row
A second correction cell transistor having a positional relationship of in-floating gate and control gate ,
The first or second correction cell transistor is selected according to the row position information of the memory cell transistor selected to inject charges into the floating gate, and a correction voltage is generated according to the selected correction cell transistor. And a voltage control circuit that controls a selection voltage supplied to the control gate of the memory cell transistor according to the correction voltage. 2. The correction circuit selects either the first correction cell transistor or the second correction cell transistor depending on whether the read or write operation is performed and whether the row position information indicates an even row or an odd row. 2. The method according to claim 1, wherein
A nonvolatile semiconductor memory device according to claim 1. 3. A plurality of memory cell transistors that store write information by injecting charges into an electrically insulated floating gate are arranged in a matrix.
The memory cell transistor, the positional relationship between the source and drain, in the nonvolatile semiconductor memory device in which are arranged reversed to one another between the odd and even rows, the same source de and the memory cell transistors of the even rows
The same source drain as the first correction cell transistor having the positional relationship of the rain floating gate control gate and the memory cell transistor in the odd row
A second correction cell transistor having a positional relationship of in-floating gate and control gate ,
The first or second correction cell transistor is selected according to the row position information of the memory cell transistor selected to inject charges into the floating gate, and a correction voltage is generated according to the selected correction cell transistor. And a voltage control circuit for controlling a read selection voltage supplied to the control gate of the memory cell transistor according to the correction voltage. 4. The correction circuit selects the first correction cell transistor when the row position information indicates an even row, and selects the second correction cell transistor when the row position information indicates an odd row. The non-volatile semiconductor memory device according to claim 3, wherein 5. A plurality of memory cell transistors that store write information by injecting charges into an electrically insulated floating gate are arranged in a matrix.
The memory cell transistor, the positional relationship between the source and drain, in the nonvolatile semiconductor memory device in which are arranged reversed to one another between the odd and even rows, the same source de and the memory cell transistors of the even rows
The same source drain as the first correction cell transistor having the positional relationship of the rain floating gate control gate and the memory cell transistor in the odd row
A second correction cell transistor having a positional relationship of in-floating gate and control gate ,
The first or second correction cell transistor is selected according to the row position information of the memory cell transistor selected to inject charges into the floating gate, and a correction voltage is generated according to the selected correction cell transistor. And a voltage control circuit for controlling a write selection voltage supplied to the control gate of the memory cell transistor according to the correction voltage. 6. The correction circuit selects the second correction cell transistor when the row position information indicates an even row, and selects the first correction cell transistor when the row position information indicates an odd row. The non-volatile semiconductor memory device according to claim 5, wherein: