JP3447372B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to an ESD (electrostatic breakdown) in an ultra thin film SOI structure.
The present invention can be applied to an improved technology of a protection element, and particularly, when a CMOS having an ultra-thin film SOI structure is configured, by reducing the peak voltage of ESD noise, the E of the ESD protection circuit can be reduced.
The present invention relates to a semiconductor device capable of improving SD withstand voltage to improve the performance of an ESD protection circuit and relaxing an internal electric field of a MOSFET used in the ESD protection circuit to suppress deterioration of the ESD protection circuit itself.

[0002]

2. Description of the Related Art FIG. 6 is a sectional view showing the structure of a conventional semiconductor device. The illustrated example is a case where it is applied to a CMOS inverter having an ultra-thin film SOI structure. In FIG. 6, 100
Reference numeral 1 denotes a substrate made of Si or the like, 1002 denotes a buried insulating film such as SiO ₂ having a film thickness of about 0.4 μm formed on the substrate 1001, 1003 denotes a buried insulating film formed on the buried insulating film 1002, and elements and the like are formed. It is a Si film to be formed and is 10
Reference numeral 04 is a field insulating film such as SiO ₂ having a film thickness of about 250 μm, which becomes an element isolation region formed in the Si film 1003.

Next, 1005 and 1006 are n ⁺ type source / drain diffusion layers formed on the Si film 1003, respectively.
A p ⁺ type source / drain diffusion layer 1007 is an S formed on the Si film 1003 between the source / drain diffusion layers 1005 and 1006 facing each other.
Reference numeral 1008 denotes a gate insulating film such as iO ₂ , and poly-S having a film thickness of about 400 μm formed on the gate insulating film 1007.
It is a gate electrode such as i.

Reference numeral 1009 denotes an n ⁺ type source / drain diffusion layer 1005 and ap ⁺ type source / drain diffusion layer 10.
06 and the gate electrode 1008 are exposed in the opening 1
PSG, BPS having a film thickness of about 500 μm having 010
An interlayer insulating film made of G, SiO ₂ , Si ₃ N _4, etc., 101
1 is the source / drain diffusion layer 100 in the opening 1010.
5, 1006 and a wiring layer of Al, TiN, W or the like formed so as to be in contact with the gate electrode 1008.

In this conventional semiconductor device having an ultra-thin film SOI structure, N-channel / P-channel MOSFETs forming a CMOS have insulating films 1002 and 10 formed on the bottom surface and the periphery thereof.
04, 1009, the element is completely separated. This conventional semiconductor device, as shown in FIG.
ESD entering from the outside through the input / output pad 1021
A CMOS buffer type ESD protection circuit 1022 is used to protect the internal circuit from noise.

This CMOS buffer type ESD protection circuit 1
Reference numeral 022 has been used normally in bulk CMOS, and this CMOS buffer type ESD protection circuit 1
Regarding No. 022, Japanese Patent Application Laid-Open No. 54-30783 (Japanese Patent Publication No. 61-3111, Registration No. 133496).
4). The configuration of the CMOS buffer type ESD protection circuit 1022 is such that the signal line 1023 from the input / output pad 1021 is connected to the drain diffusion layer of the N-channel MOSFET 1024 and the N-channel MOSFET 1 is connected.
The gate and source of 024 are connected to the Vss line 1025, the signal line 1023 from the input / output pad 1021 is connected to the drain diffusion layer of the P-channel MOSFET 1026 at the same time, and the gate and source of the P-channel MOSFET 1026 are connected to the Vdd line 1027. .

According to the ESD protection circuit 1022, in the voltage range between the Vdd line 1027 and the Vss line 1025 in the normal operation, both the N-channel MOSFET 1024 and the P-channel MOSFET 1026 are turned off and no current flows. it can. However, ES
When spike noise of several 100V such as D noise enters the CMOS buffer type ESD protection circuit 1022 from the outside, the CMOS buffer type ESD protection circuit 10 is used.
22 through the N-channel MOSFET 1024 and the P-channel MOSFET 1026 forming the noise charge Vs
It can escape to the s line 1025 or the Vdd line 1027.

For example, when positive ESD noise is applied to the CMOS buffer type ESD protection circuit 1022, P
By turning on the channel MOSFET 1026 side, noise can be released to the Vdd line 1027, and when negative ESD noise is applied, by turning on the N channel MOSFET 1024 side, Vss
Noise can escape to line 1025.

[0009]

However, in the conventional semiconductor device as described above, when the chip is assembled, etc.
The SD noise is not necessarily applied to the N channel M
This is not after the Vss line 1025 terminal on the OSFET 1024 side and the Vdd line 1027 terminal on the P-channel MOSFET 1026 side are grounded. The same applies when the IC is assembled as a component.

For example, P-channel MOSFET 1026
ESD is positive when is not connected to Vdd line 1027
When noise is applied, the P-channel MOSFET 10
Since 26 is floating, N-channel MOSF
A current cannot flow until a voltage at which the source / drain of the ET1024 punches through. Further, even when the N-channel MOSFET 1024 is not connected to the Vss line 1025, the negative E-channel noise will be E until the P-channel MOSFET 1026 punches through.
SD charge cannot escape. Therefore, CMOS
There is a problem that the ESD withstand voltage of the buffer type ESD protection circuit 1022 itself is lowered, and it is difficult to sufficiently exhibit the performance as an element of the ESD protection circuit 1022.

Incidentally, such a problem does not occur in the bulk CMOS. Because, as shown in FIG. 8, the n-type and p-type wells 10 formed in the bulk Si substrate 1001.
This is because the N-channel / P-channel MOSFET is formed on 31. Assuming a P-channel MOSFET
Is floating and even if positive ESD noise is applied, the n ⁺ -type source /
The junction between the drain diffusion layer 1005 and the p-type well 1031 is reverse-biased, and the depletion layer capacitance (C1) generated in the well 1031 can absorb the charge. Alternatively,
The depletion layer capacitance (C2) generated at the junction formed between the n-type well 1031 and the n-type substrate 1001 of the P-channel MOSFET can also absorb the charge. Usually, the well capacitance is sufficiently large so that there is no problem in absorbing charges due to ESD noise. Furthermore, P channel M
Vdd line 102 through well contact of OSFET
It is also possible for 7 to absorb the charge. As described above, in the bulk CMOS, the ESD charge can be released through the well 1031 by various paths.

On the other hand, in the CMOS buffer type ESD protection circuit 1022 having the ultra-thin film SOI structure, since no well is formed, it is expected to have an effect on the Vss / Vdd path via the well parasitic capacitance and the well contact like the above-mentioned bulk. Can not do it. Furthermore, in the ultra-thin SOI structure,
In particular, since a self-latch-up current due to a parasitic bipolar effect flows in the N-channel MOSFET 1024, an overcurrent is likely to occur under some conditions, which may cause deterioration of the CMOS buffer type ESD protection circuit 1022 itself. It was

Since the mobility of holes is smaller than the mobility of electrons, the CMOS buffer type ESD protection circuit 10
ESD through 22 P-channel MOSFETs 1026
When the charge is released, the charge may not be able to be released sufficiently in a short time when the ESD noise is applied (it is expected to be several tens ns). Therefore, the ESD withstand voltage is higher than the floating state on the P-channel MOSFET 1026 side on the N-channel MOSFET 1024 side. Floating tended to be lower.

Therefore, according to the present invention, the C of the ultrathin film SOI structure is used.
When configuring a MOS, by reducing the peak voltage of ESD noise, the ESD withstand voltage of the ESD protection circuit can be improved and the performance of the ESD protection circuit can be improved, and at the same time, the inside of the MOSFET used in the ESD protection circuit can be improved. An object of the present invention is to provide a semiconductor device capable of relaxing an electric field and suppressing deterioration of the ESD protection circuit itself.

[0015]

The invention according to claim 1 is
An internal circuit formed on an insulating layer and surrounded by an insulating layer, the internal circuit being connected to an input / output terminal, and a CMOS buffer type for protecting the internal circuit from noise penetrating through the input / output terminal SOI with ESD protection circuit
In a semiconductor device having a structure, an npn diode and a p-type diode having an SOI structure are formed so that their conductivity types are opposite to each other.
a np diode, and one of the electrodes of one electrode and the pnp diode of the npn diode is connected to the input output terminals, said input output terminal, said npn diode, the pnp diode, said CMOS buffer type ESD protection The circuit and the internal circuit are connected in this order.

According to a second aspect of the invention, in the first aspect of the invention, the other electrode of the npn diode and the pnp diode are connected.
At least one of the other electrodes of the ion is the reference
It is characterized in that it is connected to a voltage line or a power supply voltage line .

The invention according to claim 3 is the same as in claim 1.
The other electrode of the npn diode and the pnp diode.
One of the other electrodes of the battery is connected to the reference voltage line.
And the other one is connected to the power supply voltage line .

According to a fourth aspect of the present invention, there is provided a semiconductor region formed on the insulating layer and surrounded by the insulating layer, and has an internal circuit connected to the input / output terminal. An SOI structure semiconductor device provided with a CMOS buffer type ESD protection circuit for protecting the internal circuit from intruding noise, comprising an SOI structure npn diode or pnp diode formed so that their conductivity types are opposite to each other. , One electrode of the diode is connected to the input / output terminal, and the input / output terminal, the npn diode or the p
An np diode, the CMOS buffer type ESD protection circuit, and the internal circuit are connected in this order.

The invention according to claim 5 is the same as in claim 4.
The other electrode of the diode
It is characterized by being connected to a pressure wire .

[0020]

In the present invention, as shown in FIGS. 1 to 3 of the embodiment described later, the junctions on the side surfaces of the source / drain diffusion layers 5 and 6 of the MOSFETs 21 and 22 are used as diodes, and the conductivity types are opposite to each other. By forming the pn junctions connected in series as described above, the npn diode 27 and the pnp are formed.
The diode 28 is formed, and one of the diffusion layers 5 and 6 of the diodes 27 and 28 is connected to the input / output pad 23 and the internal circuit 41.
Configured to connect to.

Therefore, even when neither the N-channel MOSFET 21 nor the P-channel MOSFET 22 is turned on, the charge due to the ESD noise can be absorbed by the capacitances of the diodes 27 and 28 formed by the source / drain diffusion layers 5 and 6. Besides, N-channel MOSFET
Even in the operation state in which 21 or the P-channel MOSFET 22 is turned on, the ESD noise waveform can be blunted by the source / drain diffusion layers 5 and 6 capacitance of the diodes 27 and 28, and the peak voltage can be reduced. The ESD resistance of can be increased.

Moreover, since the peak voltage of the ESD noise can be reduced, the internal electric field of the MOSFET used in the CMOS buffer type ESD protection circuit 31 can be relaxed, and the deterioration of the CMOS buffer type ESD protection circuit 31 itself can be prevented. Can be prevented. Also, P channel M
Since the hole carrier mobility of the OSFET 22 can be reduced, the source / drain diffusion layers 5 and 6 of the diodes 27 and 28 can absorb the charges even when the escape speed of the ESD charges is slow. , The internal circuit 41 can be protected. Further, since the source / drain diffusion layers 5 and 6 of the diodes 27 and 28 can be formed without changing the normal CMOS process, no special process can be added.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a sectional view showing the structure of a semiconductor device according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram showing the circuit configuration of the semiconductor device shown in FIG. 1, and FIG. 3 is a structure of the semiconductor device shown in FIG. It is a top view shown. The illustrated example is a C having an ultra-thin SOI structure.
This is a case where it is applied to a MOS inverter. In FIGS. 1 to 3, 1 is a substrate made of Si or the like, 2 is a buried insulating film made of SiO ₂ or the like having a film thickness of about 0.4 μm formed on the substrate 1, and 3 is formed on the buried insulating film 2. And 4 is a field insulating film such as SiO ₂ having a film thickness of about 250 μm which is an element isolation region formed in the Si film 3.

Next, 5 and 6 are n ⁺ type source / drain diffusion layers and p ⁺ type source / drain layers formed on the Si film 1003, respectively.
Reference numeral 7 is a drain diffusion layer, and 7 is a Si film 3 between the source / drain diffusion layers 5 and the source / drain diffusion layers 6 facing each other.
A gate insulating film made of SiO ₂ or the like is formed on the upper surface, and a gate electrode 8 made of poly Si or the like having a thickness of about 400 μm is formed on the gate insulating film 7. Reference numeral 9 denotes an interlayer insulating film such as PSG having a film thickness of about 500 μm and having an opening 10 exposing the n ⁺ type source / drain diffusion layer, the p ⁺ type source / drain diffusion layer and the gate electrode 8, respectively.
Is the source / drain diffusion layer 5 in the opening 10,
The wiring layer is made of Al or the like so as to be in contact with the drain diffusion layer 6 and the gate electrode 8.

In this embodiment, an N-channel MOSFET 21 and a P-channel MOSFET 22 which form a CMOS.
However, as in the conventional case, the bottom surface and the periphery are completely separated by the insulating films 2, 4 and 9. Then, as shown in FIG. 2, in order to protect the internal circuit 41 from the ESD noise entering from the outside through the input / output pad 23, C
A MOS buffer type ESD protection circuit 31 is formed.

This CMOS buffer type ESD protection circuit 3
In the configuration of No. 1, the signal line 24 from the input / output pad 23 is connected to the drain diffusion layer of the N-channel MOSFET 21 and the gate and source of the N-channel MOSFET 21 are connected to the Vss line 25 at the same time as in the conventional configuration.
The signal line 24 from 3 is connected to the drain diffusion layer of the P-channel MOSFET 22 and
The gate and source of 22 are connected to the Vdd line 26.

In this embodiment, the MOSFETs 21 and 2 are further added.
By using the process of forming 2
The npn diode 27 and the pnp diode 28 are formed by forming the source / drain diffusion layers 5 and 6 of 21 and 22. One of the source / drain diffusion layers 5 and 6 of the diodes 27 and 28 is connected to the input / output pad 23.
Is connected to the internal circuit 41, the other is connected to the Vss line 25 in the npn diode 27, and the other is connected to the pnp diode 28.
Connect to Vdd line 26.

Such PN junction diodes 27, 28
Are arranged only on the N-channel MOSFET 21 side, on the P-channel MOSFET 22 side only, or on both sides of the N-channel MOSFET 21 and the P-channel MOSFET 22 as required. In the present embodiment, when noise is applied according to the positive or negative of the ESD noise, one of the junctions of the diodes 27 and 28 is biased in the forward direction and the other junction is biased in the reverse direction. A depletion layer spreads in the channel portion of the junction biased in the reverse direction, and the depletion layer capacitance absorbs the ESD charge.

At this time, the Vss line 25 and the Vdd line 26 are pulled out by the MOSFE of the CMOS buffer circuit.
It may be configured to be shared with the source / drain diffusion layers of T21 and T22, or may be provided separately. Further, since the gate electrodes 8 of the diodes 27 and 28 form the PN junction diodes 17 and 18, they may be left floating without being connected to the wiring layer 11. The so-called gate electrode 8 is used as a mask for ion implantation. The gate length of the gate electrode 8 serving as the mask may be longer than the gate length used for the MOSFET of the CMOS buffer type ESD circuit 31.

Thus, in this embodiment, the MOSFET is
The npn diode 27 and the pnp diode 28 are formed by using the junctions on the side surfaces of the source / drain diffusion layers 5 and 6 of 21, 22 as diodes to form pn junctions connected in series so that their conductivity types are opposite to each other. And the diffusion layer 5 on one side of the diodes 27 and 28 is formed.
6 is connected to the input / output pad 23 and the internal circuit 41.

Therefore, even when neither the N-channel MOSFET 21 nor the P-channel MOSFET 22 is turned on, the charges due to the ESD noise can be absorbed in the source / drain diffusion layers 5 and 6 of the diodes 27 and 28. In the operating state in which the N-channel MOSFET 21 or the P-channel MOSFET 22 is turned on, the ESD noise waveform is blunted by the capacitance of the source / drain diffusion layers 5 and 6 of the diodes 27 and 28,
Since the peak voltage can be reduced, the internal circuit 4
The ESD resistance of No. 1 can be increased.

Moreover, since the peak voltage of the ESD noise can be reduced, the internal electric field of the MOSFET used in the CMOS buffer type ESD protection circuit 31 can be relaxed, and the deterioration of the CMOS buffer type ESD protection circuit 31 itself can be prevented. Can be prevented. Also, P channel M
Since the hole carrier mobility of the OSFET 22 can be reduced, the source / drain diffusion layers 5 and 6 of the diodes 27 and 28 can absorb the charges even when the escape speed of the ESD charges is slow. , The internal circuit 41 can be protected.

Further, since the source / drain diffusion layers 5 and 6 of the diodes 27 and 28 can be formed without changing the normal CMOS process, no special process need be added. . In the above embodiment, the p or n type Si film 3 is formed below the gate electrode 8 serving as a mask for the diodes 27 and 28, and the p or n type S film is sandwiched on both sides of the gate electrode 8.
The n or p type diffusion layers 5 and 6 are formed so as to be adjacent to the i film 3, and one of the diffusion layers 5 and 6 is connected to the terminal 23 for inputting and outputting to and from the outside and the internal circuit 41. , 6 is connected to the Vss or Vdd wirings 25 and 26, the protection circuit has been described. However, in the present invention, as shown in FIG. 4, a diode 27 that functions as a gate electrode in a transistor is used. , A p- or n-type Si film 3 is formed below the gate electrode 8 serving as a mask for 28 parts,
The n or p type diffusion layers 5 and 6 are formed on both sides of the gate electrode 8 so as to be adjacent to the p or n type Si film 3, and one of the diffusion layers 5 and 6 is used for input / output with the outside. It is also possible to connect the terminal 23 and the internal circuit 41 and mount a protection circuit formed by floating the other side of the diffusion layers 5 and 6.

In this case, the same effect as that of the above-described embodiment can be obtained, and in addition, the two sources / the gate electrodes 8 are sandwiched in between.
One of the drain diffusion layers 5 and 6 is connected to the input / output pad 23, while the other is left floating (open).
The depletion layer capacitance of one of the drain diffusion layers 5 and 6 can be connected in series with the buried insulating layer capacitance to store charges. Further, in the present invention, as shown in FIG. 5, both of the two source / drain diffusion layers 5, 6 are provided with the input / output pad 2.
It may be configured by connecting to 3 and the same effect as in the above embodiment can be obtained in this case as well, and the ESD noise is P
It can be stored in the series capacitance of the N-junction capacitance and the buried insulating film capacitance.

[0035]

According to the present invention, C having an ultra-thin film SOI structure is used.
When configuring a MOS, by reducing the peak voltage of ESD noise, the ESD withstand voltage of the ESD protection circuit can be improved and the performance of the ESD protection circuit can be improved, and at the same time, the inside of the MOSFET used in the ESD protection circuit can be improved. There is an effect that the electric field can be relaxed and the deterioration of the ESD protection circuit itself can be suppressed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram showing a circuit configuration of the semiconductor device shown in FIG.

FIG. 3 is a plan view showing the structure of the semiconductor device shown in FIG.

FIG. 4 is a sectional view showing a structure of a semiconductor device applicable to the present invention.

FIG. 5 is a sectional view showing a structure of a semiconductor device applicable to the present invention.

FIG. 6 is a sectional view showing the structure of a conventional semiconductor device.

FIG. 7 is a circuit diagram showing a configuration of a conventional CMOS buffer type ESD protection circuit.

FIG. 8 is a cross-sectional view showing the structure of a conventional semiconductor device.

[Explanation of symbols]

1 substrate 2 Embedded insulating film 3 Si film 4 field insulation film 5,6 Source / drain diffusion layer 7 Gate insulation film 8 gate electrode 9 Interlayer insulation film 10 openings 11 wiring layer 21 N-channel MOSFET 22 P-channel MOSFET 23 Input / output pad 24 signal lines 25 Vss wire 26 Vdd line 27 npn diode 28 pnp diode 31 CMOS buffer type ESD protection circuit 41 Internal circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 27/092 (56) References JP-A-2-97066 (JP, A) JP-A-4-259259 (JP, A) Kaihei 4-297018 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 21/822 H01L 21/8238 H01L 27/04 H01L 27/092

Claims (5)

(57) [Claims] 1. An internal circuit formed on an insulating layer and surrounded by an insulating layer, the internal circuit being connected to an input / output terminal, and the internal circuit being protected from noise entering through the input / output terminal. CMOS to protect
An SOI structure semiconductor device including a buffer type ESD protection circuit includes an SOI structure npn diode and a pnp diode formed so that their conductivity types are opposite to each other, and one electrode of the npn diode and the and one electrode of the pnp diode is connected to the input output terminals, and wherein said input output terminal, said npn diode, the pnp diode, said CMOS buffer type ESD protection circuit, that are connected in this order of the internal circuit Semiconductor device. 2. The other electrode of the npn diode and the pn
The semiconductor device according to claim 1, wherein at least one of the other electrode of the p diode is connected to the reference voltage line or the power supply voltage line. 3. The other electrode of the npn diode and the pn
The semiconductor device according to claim 1, wherein one of the other electrode of the p diode is connected to the reference voltage line, and the other one is connected to the power supply voltage line. 4. An internal circuit formed on an insulating layer and surrounded by an insulating layer, having an internal circuit connected to an input / output terminal, wherein the internal portion is protected from noise entering through the input / output terminal. CM to protect the circuit
An SOI structure semiconductor device having an OS buffer type ESD protection circuit is provided with an SOI structure npn diode or pnp diode formed so that their conductivity types are opposite to each other.
One of the electrodes of the diode is connected to the input / output terminal, and the input / output terminal, the npn diode or the pnp diode, the CMOS buffer type ESD protection circuit, and the internal circuit are sequentially connected. Semiconductor device. 5. The semiconductor device according to claim 4, wherein the other electrode of the diode is connected to a reference voltage line or a power supply voltage line.