JP3337012B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a vertical field effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor device having a vertical field-effect transistor, it is important to reduce Ron, capacitance and gate resistance. For this reason, a trench-type cell structure is usually employed, and the cell size has been reduced along with the progress of photolithography technology, thereby realizing low Ron and low capacity. The reduction in gate resistance has been realized by increasing the amount of impurities doped into the gate polysilicon and increasing the arrangement and number of gate fingers.

A conventional semiconductor device having a vertical field effect transistor will be described with reference to FIG. A conventional semiconductor device includes a semiconductor substrate 101, an epitaxial layer 102 formed on the semiconductor substrate 101, a base diffusion layer 103 formed on the epitaxial layer 102, and a base diffusion layer 103. A trench 104 formed in the epitaxial layer 102, a gate insulating oxide film 105 formed on the surface of the trench 104, and a gate formed on the surface of the gate insulating oxide film 105 inside the trench 104. Polysilicon layer 10
6, a source diffusion layer 107 formed on the base diffusion layer 103 on both sides of the gate polysilicon layer 106, and an interlayer insulating film formed on the source diffusion layer 107 and the gate polysilicon layer 106. 10
8 and a source electrode metal film 109 formed on the interlayer insulating film 108.

[0004]

However, in the conventional semiconductor device, a trench 104 is formed with reference to the upper surface of the base diffusion layer 103, and the gate insulating oxide film 10 is formed.
5 is formed and the gate polysilicon layer 106 is filled, so that the upper surface of the gate polysilicon layer 106 is lower than the upper surface of the base diffusion layer 103 during the entire surface plasma etching (etch back) of the gate polysilicon layer 106. I will. Therefore, the source diffusion layer 107 has a thickness of 0.4 to 0.6 μm.
m, and the base diffusion layer 103 is also formed to about 1.0 to 1.5 μm. Depending on the depth of the base diffusion layer 103, the trench 104 having an optimum depth
Is 1.2 to 1.7 μm, and there is a problem that the parasitic capacitance cannot be reduced. The reduction in Ron due to cell shrinkage has been reduced by photolithography technology alone, and the shrinkage rate has been low, and it has become impossible to achieve sufficient effects. There is a limit to the reduction of the gate resistance with a material such as polysilicon, which cannot be said to be sufficient.

It is an object of the present invention to reduce the capacity and
An object of the present invention is to provide a semiconductor device capable of reducing Ron and a method for manufacturing the same. Another object of the present invention is to provide a semiconductor device capable of reducing gate resistance and a method for manufacturing the same.

[0006]

In order to solve the above-mentioned problems, the invention according to claim 1 comprises a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, and an epitaxial layer formed on the semiconductor substrate. A base diffusion layer formed, a trench groove formed in the base diffusion layer and the epitaxial layer, a gate insulating oxide film formed on a surface of the trench groove, and a gate insulating oxide film in the trench groove. A gate polysilicon layer formed on the surface of the film and having an upper part projecting above the base diffusion layer; a source diffusion layer formed on the base diffusion layer on both sides of the gate polysilicon layer; A sidewall oxide film formed on both sides of the gate polysilicon layer above the layer, and a polysilicon film formed on the gate polysilicon layer. And de layer, and having a silicide layer is continuously formed on the upper and the base diffusion layer of a part of the source diffusion layer.

According to a second aspect of the present invention, there is provided a semiconductor substrate preparing step, a step of forming an epitaxial layer on the semiconductor substrate, a step of forming a trench in the epitaxial layer, and a step of forming a gate on the surface of the trench. Forming an insulating oxide film, forming a gate polysilicon layer on the surface of the gate insulating oxide film inside the trench, and forming the upper surface of the epitaxial layer such that the upper surface is located below the upper surface of the gate polysilicon layer. Forming a source diffusion layer on the base diffusion layer on both sides of the gate polysilicon layer, and forming a sidewall oxide film on both sides of the gate polysilicon layer on the source diffusion layer. Forming a polycide layer on the gate polysilicon layer; and forming a polycide layer on a portion of the source diffusion layer and a base diffusion layer. Characterized by a step of forming a continuous silicide layer.

[0008]

Next, embodiments of the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, a semiconductor device according to a first embodiment of the present invention includes an N-type semiconductor substrate 1 and an N-type semiconductor substrate 1 formed on the semiconductor substrate 1.
-Type epitaxial layer 2, a P-type base diffusion layer 3 formed on the epitaxial layer 2, a trench 4 formed in the base diffusion layer 3 and the epitaxial layer 2, and a trench 4 And a gate polysilicon layer 6 formed on the surface of the gate insulating oxide film 5 inside the trench 4 and having an upper part protruding above the base diffusion layer 3. A source diffusion layer 7 formed on the base diffusion layer 3 on both sides of the gate polysilicon layer 6 and a sidewall oxide film 8 formed on both sides of the gate polysilicon layer 6 on the source diffusion layer 7 A polycide layer 9 formed on the gate polysilicon layer 6 and a silicide layer formed on a part of the source diffusion layer 7 and on the base diffusion layer 3 Has a 0 and.

The silicide layer 10 is formed by self-alignment with the sidewall oxide film 8. The semiconductor device further includes a polycide layer 9 and a sidewall oxide film 8.
And an interlayer insulating film 11 formed on a part of the silicide layer 10 and a source electrode metal film 12 formed on the interlayer insulating film 11.

Next, a method for manufacturing a semiconductor device will be described in detail with reference to FIGS. First, as shown in FIG. 2, a P-doped 0.3 μm on an N-type semiconductor substrate 1 of 1-6 / 1000 Ω · cm doped with As.
An N-type epitaxial layer 2 having a thickness of about 0.4 Ω · cm is formed so as to have a thickness of about 6 μm. A mask material 1 of about 4000 to 6000 angstroms on the epitaxial layer 2
3 is formed by thermal oxidation and LPCVD, and is patterned by photolithography. Next, the mask material 13 and the epitaxial layer 2 are etched by plasma etching to form a trench groove 4 having a depth of 0.6 to 0.8 μm.

Next, the gate insulating oxide film 5 is thermally
It is formed to a thickness of 0 to 700 angstroms. next,
LPC is applied to the surface of the gate insulating oxide film 5 inside the trench 4.
The gate polysilicon layer 6 is formed to a thickness of 5000 to 10 by the VD method.
It is formed to a thickness of 000 angstroms. Next, the gate polysilicon layer 6 is etched back by a plasma etch method.

Next, as shown in FIG. 3, the mask material 13 is etched by wet etching or the like, and boron ions are implanted and pushed into the entire surface to form a junction depth of 0.5 to 0.6.
A P-type base diffusion layer 3 of μm is formed. Next, As ions are selectively implanted and pushed into the base diffusion layer 3 by photolithography, so that the junction depth is 0.1 to 0.1.
An N-type source diffusion layer 7 of 2 μm is formed.

Next, as shown in FIG. 3, the base diffusion layer 3
And an oxide film is deposited on the source diffusion layer 7 by the CVD method, and plasma etching (etch back) is performed on the entire surface.
A sidewall oxide film 8 is formed. Next, T
i, etc., and a polycide layer 9 and a silicide layer 10 are formed by annealing.
Of excess Ti on the surface is removed by wet etching.

Next, as shown in FIG. 1, an interlayer insulating film 11 is deposited by a CVD method, and is patterned by photolithography to form a source contact window. Next, TiN / Ti is formed as a barrier metal by sputtering, and after annealing, the source electrode metal film 12 is formed by AlSiCu sputtering.

In the first embodiment of the present invention, since the salicide process is employed, the number of photolithography steps is not increased, and even if there is no advanced photolithography technology, it can be easily performed. Can be produced by an inexpensive process. Although the first embodiment of the present invention relates to an N-channel semiconductor device, the present invention can be applied to a P-channel semiconductor device.

In the first embodiment of the present invention, since the upper portion of the gate polysilicon layer 6 protrudes above the upper surface of the base diffusion layer 3, the source diffusion layer 7 is set to 0.1 to
It can be formed with a very shallow bonding layer of 0.2 μm. For this reason, the base diffusion layer 3 having the concentration profile in the vertical direction can be formed with a very shallow junction layer of 0.5 to 0.6 μm, and has an optimum depth depending on the depth of the base diffusion layer 3. The depth of the trench 4 is also 0.6 to 0.8 μm.
And can be very shallow. The parasitic capacitance of the trench type vertical field effect transistor is substantially determined by the width and depth of the trench 4.
By reducing the depth of the trench 4, the parasitic capacitance can be significantly reduced.

Next, the polycide layer 9 formed on the gate polysilicon has a resistance of about 1/10 of a normal gate polysilicon resistance sufficiently diffused by phosphorus.
The gate resistance of the trench type vertical field effect transistor can be greatly reduced. Since the silicide layer 10 formed on the base diffusion layer 3 can form the distance between the gate polysilicon layer 6 and the source contact by the width of the sidewall oxide film 8 without using the photolithography technique,
The cell size can be reduced. By reducing the cell size, the cell density per unit area can be improved, and the channel resistance can be reduced. Further, in the first embodiment of the present invention, the number of times of photolithography is not increased and advanced technology is not required, and the device can be manufactured at low cost.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings. As shown in FIG. 5, a semiconductor device according to a second embodiment of the present invention includes an N-type semiconductor substrate 1, an N-type epitaxial layer 2 formed on the semiconductor substrate 1, P-type base diffusion layer 3 formed on epitaxial layer 2, trench 4 formed in base diffusion layer 3 and epitaxial layer 2, and a gate formed in the surface of trench 4 An insulating oxide film 5; a gate polysilicon layer 6 formed on the surface of the gate insulating oxide film 5 inside the trench 4 and having an upper part protruding above the base diffusion layer 3; A source diffusion layer 7 formed on the base diffusion layer 5 and a gate polysilicon layer 6
And a WSi layer 15 formed inside the groove 14.

The semiconductor device further includes an interlayer insulating film 11 formed on the source diffusion layer 7, the gate polysilicon layer 6, and the WSi layer 15, and a source electrode metal formed on the interlayer insulating film 11. And a film 12.

Next, a method of manufacturing the semiconductor device shown in FIG. 5 will be described in detail with reference to FIGS. First, as shown in FIG.
An N-type epitaxial layer 2 of 0.3 to 0.4 Ω · cm doped with P is formed on an N-type semiconductor substrate 1 having a thickness of about 6 μm. A mask material 13 of about 4000 to 6000 angstroms is formed on the epitaxial layer 2 by thermal oxidation and LPCVD, and is patterned by photolithography. Next, the mask material 13 and the epitaxial layer 2 are etched by plasma etching to form a trench groove 4 having a depth of 0.6 to 0.8 μm.

Next, the gate insulating oxide film 5 is thermally oxidized to 30
It is formed to a thickness of 0 to 700 angstroms. next,
LPC is applied to the surface of the gate insulating oxide film 5 inside the trench 4.
The gate polysilicon layer 6 is formed to a thickness of 5000 to 10 by VD method.
It is formed to a thickness of 000 angstroms. Next, the gate polysilicon layer 6 is etched back by a plasma etch method.

Next, as shown in FIG. 7, the mask material 13 is etched by wet etching or the like, and boron ions are implanted and pushed into the entire surface to form a junction depth of 0.5 to 0.6.
A P-type base diffusion layer 3 of μm is formed. Next, As ions are selectively implanted and pushed into the base diffusion layer 3 by photolithography, so that the junction depth is 0.1 to 0.1.
An N-type source diffusion layer 7 of 2 μm is formed.

Next, as shown in FIG. 8, a groove 14 is formed in the gate polysilicon layer 6 by photolithography. Next, WSi is formed inside the groove 14 by LPCVD.
To form a WSi layer 15 inside the trench 14 of the gate polysilicon layer 6 by plasma etching (etch back).

Next, as shown in FIG.
Is deposited by a CVD method and patterned by photolithography to form a source contact window. Next, TiN / Ti is formed as a barrier metal by sputtering, and after annealing, the source electrode metal film 12 is formed by AlSiCu sputtering.

Although the second embodiment of the present invention relates to an N-channel type semiconductor device, the present invention can be applied to a P-channel type semiconductor device. In the second embodiment of the present invention, since the WSi layer 15 is embedded in the gate polysilicon layer 6, the gate resistance can be further reduced.

[0026]

According to the present invention, the capacitance can be reduced and Ron can be reduced. Further, according to the present invention, the gate resistance can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view for explaining a step of manufacturing the semiconductor device of FIG.

FIG. 3 is a schematic cross-sectional view for explaining another process for manufacturing the semiconductor device of FIG. 1;

FIG. 4 is a schematic cross-sectional view for explaining another process for manufacturing the semiconductor device of FIG. 1;

FIG. 5 is a schematic sectional view showing a semiconductor device as a second embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view for explaining a step of manufacturing the semiconductor device in FIG. 5;

FIG. 7 is a schematic cross-sectional view for explaining another process for manufacturing the semiconductor device of FIG. 5;

FIG. 8 is a schematic cross-sectional view for explaining another process for manufacturing the semiconductor device of FIG. 5;

FIG. 9 is a schematic sectional view showing a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Epitaxial layer 3 Base diffusion layer 4 Trench groove 5 Gate insulating oxide film 6 Gate polysilicon layer 7 Source diffusion layer 8 Side wall oxide film 9 Polycide layer 10 Silicide layer 11 Interlayer insulating film 12 Source electrode metal film 13 Mask material 14 groove 15 WSi layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (2)

(57) [Claims] A semiconductor substrate; an epitaxial layer formed on the semiconductor substrate; a base diffusion layer formed on the epitaxial layer; and a base diffusion layer formed on the base diffusion layer and the epitaxial layer. A trench groove, a gate insulating oxide film formed on the surface of the trench groove, and a gate insulating oxide film formed on the surface of the gate insulating oxide film inside the trench groove, and an upper portion protruding above the base diffusion layer. A gate polysilicon layer, a source diffusion layer formed on the base diffusion layer on both sides of the gate polysilicon layer, and a side formed on both sides of the gate polysilicon layer on the source diffusion layer A wall oxide film, a polycide layer formed on the gate polysilicon layer, and a portion of the source diffusion layer. And a silicide layer continuously formed on the base diffusion layer. A step of preparing a semiconductor substrate; a step of forming an epitaxial layer on the semiconductor substrate; a step of forming a trench in the epitaxial layer; and forming a gate insulating oxide film on a surface of the trench. Forming a gate polysilicon layer on a surface of the gate insulating oxide film inside the trench groove; and forming a gate polysilicon layer on the epitaxial layer such that an upper surface is located below an upper surface of the gate polysilicon layer. Forming a source diffusion layer on top of the base diffusion layer on both sides of the gate polysilicon layer; and forming a source diffusion layer on both sides of the gate polysilicon layer above the source diffusion layer. Forming a wall oxide film; forming a polycide layer on the gate polysilicon layer; Forming a continuous silicide layer on a part of the diffused layer and on the base diffusion layer.