JP3332114B2 - High breakdown voltage field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage field effect transistor (MOSFET).

[0002]

2. Description of the Related Art In recent years, an integrated circuit (IC) formed by integrating a large number of transistors, resistors and the like so as to achieve an electric circuit and integrating them on one chip has been frequently used in important parts of computers and communication equipment. ing. Such an IC
Among them, a device including a high breakdown voltage element is called a power IC. Among power ICs, those in which a drive circuit and a control circuit are integrated include display drive devices and vehicle-mounted ICs.
Can be used for many applications. This kind of power IC
The MOSFET used for the output stage of (1) is required to have a high drain withstand voltage and a low on-resistance.

In a high-breakdown-voltage MOSFET, the impurity concentration of the offset layer in the drain region must be reduced in order to make the element have a high withstand voltage. However, if the concentration of the offset layer is set to be lower than the concentration of the channel region, impurities implanted in the channel region will diffuse to regions other than the gate at the time of subsequent thermal diffusion, which may hinder MOS operation. Become. For this reason, in the conventional high breakdown voltage MOSFET, a combination of an offset layer having a low impurity concentration and a channel region having a high impurity concentration cannot be obtained. That is, there is a problem that it is difficult to obtain an element having a high withstand voltage and a desired threshold voltage.
In addition, the conventional high breakdown voltage MOSFET requires a different process from the low breakdown voltage control circuit and the logic circuit in the same IC.

[0004]

As described above, the conventional high breakdown voltage MOSFET has a low degree of freedom in setting the threshold voltage, and has a different process from the low breakdown voltage control circuit and the logic circuit in the same IC. There is a problem that needs to be created.

The present invention has been made in view of the above circumstances, and has as its object to have a high withstand voltage, a desired threshold voltage, and to be manufactured by the same process as a logic circuit or the like. It is an object of the present invention to provide a high-breakdown-voltage MOSFET capable of performing the following.

[0006]

A high withstand voltage field effect transistor that achieves the above object has a holding layer made of an insulator, an active layer made of a semiconductor of a second conductivity type formed on the holding layer, A source layer and a drain layer of low resistance and a first conductivity type formed on the surface of the active layer, a source electrode and a drain electrode connected to the source layer and the drain layer, respectively, and the source layer and the drain layer; A first conductivity type first and second offset layer formed on the surface of the active layer so as to be connected and not reach the holding layer; and formed on the surface of the active layer between the first and second offset layers. A channel region, a gate electrode formed on the channel region via a gate insulating film, and a lower portion positioned under the gate insulating film so as not to contact the first and second offset layers. Is formed on the surface of the active layer, the impurity concentration comprises a base layer of high second conductivity type than the impurity concentration of said first and second offset layer.

Preferably, the first and second offset layers are formed by diffusion, the diffusion depth into the active layer is 1-2 μm, and the dose of impurities is 2-3 × 10 ¹² cm ^−2.
It is. The semiconductor device may further include a low-resistance second conductivity type layer formed in the active layer so as to be connected to the source layer and reach the holding layer. Further, the holding layer includes an insulator layer formed on a surface of the semiconductor substrate.

[0008]

According to the present invention, insulation isolation, breakdown voltage and on-resistance can be simultaneously improved by employing an SOI substrate and optimizing an offset layer. For example, even if the high breakdown voltage MOSFET is used for high-side switching, a high drain breakdown voltage can be achieved without increasing the on-resistance. In addition, since the base layer is formed independently by ion implantation, the impurity concentration of the offset layer is reduced in order to provide a high withstand voltage to the element, while the impurity concentration in the channel region is adjusted to a desired threshold voltage. Can be ion-implanted. Since the base layer can be formed by an ion implantation step required when forming a CMOSFET,
This high breakdown voltage MOSFET can be created simultaneously with a logic circuit or the like in the same IC.

[0009]

Embodiments will be described below with reference to the drawings. FIG. 1 shows a high breakdown voltage MOSFET according to an embodiment of the present invention.
FIG. In the figure, reference numeral 21 denotes a semiconductor substrate, on which a high-resistance p-type active layer 23 is provided via an insulating layer 22 serving as a holding layer. The substrate 21 having the insulating layer 22 and the active layer 23 is formed, for example, by bonding two silicon substrates and polishing one of them. On the surface of the p-type active layer 23, first and second n-type offset layers 27a and 27b are selectively formed. The n-type offset layer is formed, for example, by implanting ions serving as donors under the condition of a dose of 2 to 3 × 10 ¹² cm ⁻² and then performing shallow diffusion by heat treatment.

On the surfaces of the n-type offset layers 27a and 27b, an n ⁺ -type source layer 25 and an n ⁺ -type drain layer 26 are selectively formed. A low resistance p ⁺ -type layer 24 for preventing punch through is selectively formed in the p-type active layer 23 adjacent to the n-type offset layer 27a. A source electrode 28 is provided on the p ⁺ -type layer 24 and the n ⁺ -type source layer 25. N ⁺ type drain layer 26
A drain electrode 29 is provided thereon.

A gate electrode 30 is provided between the n-type offset layers 27a and 27b via a gate oxide film 31 having a thickness of about 15 nm. This gate electrode 30
Has a field plate extending over the oxide film 32 formed by LOCOS (localized 0xidation of silicon). This field plate works to weaken the electric field at the drain end of the gate.

The p between the n-type offset layers 27a and 27b
On the surface of type active layer 23, ap ⁺ type base layer 33 for controlling threshold voltage Vth is formed. The p ⁺ -type base layer 33 has a higher impurity concentration than the p-type active layer 23, and has a higher impurity concentration than the offset layers 27a and 27b.

The p ⁺ type base layer 33 is formed by using a mask.
It is formed by implanting boron ions into the center of the opening of oxide film 32. At this time, the p ⁺ type base layer 33
The position is set so as not to contact the offset layers 27a and 27b. Since the p ⁺ -type base layer 33 can be formed by an ion implantation step required when forming a CMOSFET, a process is performed in comparison with a case where a channel region is formed by double diffusion as described below as a comparative example. Becomes simple.

The outline of the manufacturing process of the MOSFET shown in FIG. 1 will be described below. First, a p-type layer 24 for preventing punch-through is formed on an SOI substrate having a high-resistance p-type or n-type active layer 23. Next, a silicon nitride film is formed in a portion to be a gate. And the offset layer 27
a and 27b are formed by using this nitride film as a mask and forming a layer 2 under the condition of a dose of 2-3 × 10 ¹² cm ^−2.
3 is selectively ion-implanted. Next, LOCOS processing is performed until the thickness of the oxide film 32 becomes about 800 nm. At this time, the offset layers 27a and 27b are diffused to a depth of about 1 to 1.5 μm.

Next, a resist is applied using a mask while leaving the center of the opening of the oxide film 32, and a dose of boron for controlling the threshold value Vth is 1 × 10 ¹³ to 1 × 10 ¹⁴ cm.
Ion implantation is performed under the condition of ^-2 . Next, the gate oxide film
Oxidize to a thickness of 5 nm;
Deposit 0. Next, the n ⁺ source layer 25 and the n ⁺ drain layer 26 are diffused and formed in a self-aligned manner by using the source side end of the gate as an edge and the opening of the LOCOS oxide film 32. Next, source and drain electrodes 28 and 29 are formed.

FIG. 2 shows the distribution of the impurity concentration on the surface of the device thus manufactured. In this embodiment, the withstand voltage is 60 V, the on-resistance is 100 mΩ-mm ² , and the Vth is 0.8.
The characteristics of V were obtained.

FIG. 3 is a sectional view showing a high breakdown voltage MOSFET for comparison with the embodiment shown in FIG. FIG. 4 shows FIG.
4 shows the distribution of the impurity concentration on the surface of the illustrated device. 3, parts corresponding to those in the embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

In this element, the threshold voltage Vth of the element is controlled by the p ⁺ type base layer 33 of the embodiment shown in FIG.
This is performed by the p-type base layer 36. This element is a so-called D
It has a MOS structure, and the p-type base layer 36 and the n-type source layer 25 are formed in a self-aligned manner by double diffusion using the gate electrode as a mask.

In the device of this comparative example, it is necessary to produce the low-voltage control circuit and the logic circuit in the same IC by different processes, so that the manufacturing cost of the device is high. Also,
In order to make the element have a high breakdown voltage, the impurity concentration of the n-type offset layer must be reduced. However, if the concentration of the offset layer is set to be lower than the concentration of the channel region, impurities implanted in the channel region will diffuse to regions other than the gate at the time of subsequent thermal diffusion, which may hinder MOS operation. Become. Therefore, a combination of an offset layer having a low impurity concentration and a channel region having a high impurity concentration cannot be obtained.

On the other hand, in the embodiment shown in FIG. 1, the channel region, that is, the p ⁺ type base layer 33 is independently formed by ion implantation of boron. Therefore, while the impurity concentration of the offset layer is reduced in order to give the element a high withstand voltage, the impurity can be ion-implanted into the channel region in accordance with the desired threshold voltage Vth.

The p ⁺ type base layer 33 is formed of a CMOSF
Since the ET can be formed by an ion implantation step required for forming the ET, the present high breakdown voltage element can be formed simultaneously with the low breakdown voltage control circuit and the logic circuit in the same IC.

In the MOSFET shown in FIG. 1, the diffusion depth and dose of the offset layers 27a and 27b,
The impurity concentration of the mold active layer 23 is selected based on the data shown in FIGS. 5 to FIG.
Represents the diffusion depth of the offset layer, and L represents the lateral length of the offset layer.

FIG. 5 is a characteristic diagram showing the relationship between the dose to the offset layer and the breakdown voltage when the diffusion depth is used as a parameter. It can be seen from FIG. 5 that when the dose amount is 3 × 10 ¹² cm ⁻² or more, the breakdown voltage sharply decreases regardless of the diffusion depth.
When the diffusion depth is 1 μm or less, the peak of the breakdown voltage is low,
The area of the optimal dose is also narrow. Therefore, in order to obtain a required breakdown voltage, at least 1 μm, more preferably 1.mu.m.
A diffusion depth of 5 μm or more is desirable. If the dose is in the range of ² to 3 × 10 ¹² cm ⁻² , a sufficient withstand voltage can be obtained.

FIG. 6 is a characteristic diagram showing the relationship between the diffusion depth of the offset layer and the ON resistance when the dose is set to 2.7 × 10 ¹² cm ⁻² . According to FIG. 6, the diffusion depth is 1.5-2.
It can be seen that the on-resistance decreases as the depth increases to μm, but increases when the depth increases.

To summarize the above results, if the diffusion depth of the n-type offset layers 27a and 27b is 1-2 μm and the dose is 2-3 × 10 ¹² cm ⁻² , the on-resistance and withstand voltage will be improved. Can be compatible.

FIG. 7 is a characteristic diagram showing the relationship between the dose to the offset layer and the breakdown voltage when the concentration of the p-type substrate (p-type active layer 23) is used as a parameter. As the dose is increased, the breakdown voltage rapidly decreases when the dose exceeds approximately 2 × 10 ¹² cm ⁻² . As the concentration of the p-type substrate is increased, the dose at which the breakdown voltage is reduced can be increased, and the on-resistance can be reduced. However, since the breakdown voltage decreases when the concentration of the p-type substrate is more than 1 × 10 ¹⁶ cm ^-3, the concentration of the p-type substrate is 1 × 10 ¹⁶
Around cm ^-3 is good.

According to the condition setting, a high drain withstand voltage can be obtained without increasing the on-resistance even when used for high-side switching by employing an SOI substrate and optimizing the n-type offset layers 27a and 27b. A achievable high breakdown voltage MOSFET is obtained.

[0028]

As described in detail above, according to the present invention, a high withstand voltage MO having a high withstand voltage and a desired threshold voltage, and which can be manufactured by the same process as a logic circuit or the like.
It becomes possible to provide an SFET. Further, by using the SOI substrate and optimizing the offset layer, the insulation separation, the withstand voltage, and the on-resistance can be simultaneously improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a high breakdown voltage MOSFET according to an embodiment of the present invention.

FIG. 2 is a view showing a distribution of impurity concentration on the surface of the MOSFET shown in FIG. 1;

FIG. 3 is a cross-sectional view showing a high breakdown voltage MOSFET as a comparative example.

FIG. 4 is a view showing a distribution of an impurity concentration on the surface of the MOSFET shown in FIG. 3;

FIG. 5 is a characteristic diagram showing a relationship between a dose amount to an offset layer and a withstand voltage.

FIG. 6 is a characteristic diagram showing a relationship between a diffusion depth of an offset layer and on-resistance.

FIG. 7 is a characteristic diagram showing the relationship between the dose to the offset layer and the breakdown voltage when the concentration of the p-type substrate (active layer) is used as a parameter.

[Explanation of symbols]

21 ... semiconductor substrate 22: insulating layer (retention layer) 23 ... p ^- -type active layer 24 ... p ⁺ -type layer 25 ... n ⁺ -type source layer 26 ... n ⁺ -type drain layer 27a, 27b ... n-type offset layer 28 ... Source Electrode 29 ... Drain electrode 30 ... Gate electrode 31 ... Gate oxide film 33 ... P ⁺ type base layer

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (4)

(57) [Claims] 1. A holding layer made of an insulator, an active layer made of a semiconductor of a second conductivity type formed on the holding layer, and a low-resistance and first conductivity type formed on the surface of the active layer. And a source electrode and a drain electrode respectively connected to the source layer and the drain layer; and a surface of the active layer connected to the source layer and the drain layer and not reaching the holding layer. A first conductivity type first and second offset layer formed, a channel region formed on the surface of the active layer between the first and second offset layers, and a gate insulating film on the channel region. A gate electrode formed on the surface of the active layer under the gate insulating film so as not to contact the first and second offset layers; and an impurity concentration of the first and second offset layers. A high-breakdown-voltage field-effect transistor, comprising: 2. The method according to claim 1, wherein said first and second offset layers are formed by diffusion, and have a diffusion depth of 1 to 2 μm into said active layer.
2. The transistor according to claim 1, wherein the dose of the impurity is 2 to 3 × 10 ¹² cm ⁻² . 3. A low-resistance second layer connected to the source layer and formed in the active layer so as to reach the holding layer.
The transistor according to claim 1, further comprising a conductive type layer. 4. The transistor according to claim 1, wherein said holding layer comprises an insulator layer formed on a surface of a semiconductor substrate.