JP3326648B2 - Digital video / audio signal recording / reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video / audio signal recording / reproducing apparatus for encoding and recording / reproducing video and audio signals.

[0002]

2. Description of the Related Art At present, the diversification of functions and services in television broadcasting has been widely promoted. For example, in North America, as a data service using a line 21 in a vertical blanking period, a conventional Clos is used.
ed Caption (hereinafter referred to as CC) and TE
In addition to XT, a third service, EDS (Ext
Ended Data Service) has been proposed. The data service contents of this EDS are mainly 1)
Information on the start time and contents of the currently transmitted program, 2) Information on the start time and contents of the program to be transmitted, 3) Information on the broadcasting station, 4) Time information, 5) Weather information, etc. It is.

[0003] The signal format of this EDS will be described. As shown in FIG.
16-bit data (Character 1 and Ch) defined for EDS using the same signal format as
arcar2) is transmitted using line 21 of field2.

The line 21 of field 1 is used only for the CC main language and TEXT, and the line 21 of field 2 is used for CC sub-language. The EDS signal is sent during the period of the line 21 of the field 2 that does not come. This will be described with reference to FIG. 35. L1, L2, L3,..., L12 shown in FIG. It shows the start bits of S1 to S3, and the parts of Character1 and Character2 each consisting of character components b0 to b6 and a parity component P1. Then, as shown in this figure, the EDS data is CAPTION or TEX.
T is transmitted in a form interpolated on a line to which T is not sent.

[0005] While CC and TEXT are only characters, EDS defines data in a packet format. In the example shown in FIG.
6 and L9-L12 for a total of 8 lines of data, one E
A packet of DS data is configured. EDS
Character sent to the first line of the packet
er1 is composed of a “START” code (see L3 in this figure).
C or Character1 of the first line when resuming after being interrupted by TEXT is "Con
"tween" code (see L9 in this figure). Then, these "Start" codes and "C
The “ontinue” code is called a control character, and its specific value is obtained by converting EDS data to Capti.
01h to 0F so that it can be distinguished from on or TEXT data
h (h represents hexadecimal notation) is used.

[0006] Character2 following these control characters is composed of a "Type" code, and the specific data content of the packet is defined by the type character and the control character. As a specific example, for example, when “Start” is 01h and “Type” is 05h (or “Continue” is 02h and “Type”
e ”is 05h), the evaluation of the contents of the program as packet data (Program Rating
g) is sent. This Program Rating
(Hereinafter, referred to as PR) is a packet representing the Ch
The data components b0 of each of arcar1 and arc2
b6 is defined as in [1] of FIG. The specific content of the evaluation is r of Character1.
2, r1 and r0 are defined according to [2] in the figure, and particularly, information indicating whether or not the program content is appropriate for a young person. In addition, c of Character1
2, c1 and c0 indicate information such as violent expression, linguistic expression, and nude expression. In the last line of the packet, as shown in FIG. 35, a control character "End" code for recognizing that the packet is the last part and whether or not the packet data is complete are checked. "Checksum" code is sent.

[0007]

SUMMARY OF THE INVENTION As described above, the P.I. R. By transmitting the information together with the television signal, if the transmitted television program is inappropriate for viewing by a young person, the receiving side transmits the P.P. R. It is desirable to execute a measure for automatically prohibiting viewing based on the information, that is, a child lock. Then, it is required that such a child lock be configured to be able to be executed naturally in a television signal recording / reproducing apparatus.
In a device that records and reproduces an image signal and an audio signal in a digital recording format, for example, in a digital VTR, when recording an image signal to reduce the amount of data to be recorded, usually only data in the effective scanning area is used. The data is recorded, and data during the horizontal blanking period and the vertical blanking period is not recorded.

Therefore, in such a digital recording / reproducing apparatus, the P.P. signal transmitted during the vertical blanking period is used. R. Information cannot be recorded. R. Child lock cannot be performed based on information. The invention of the present application is intended to solve such a problem. R. The recording and reproduction of information is made possible so that child lock can be executed at the time of reproduction.

[0009]

SUMMARY OF THE INVENTION The present invention relates to a digital video / audio signal recording / reproducing apparatus which encodes a video signal and a voice signal constituting a television signal and performs recording / reproduction on a recording medium. An image data recording circuit that records an encoded output in an image data recording area of a recording medium; an audio data recording circuit that records an encoded output of an audio signal in an audio data recording area of a recording medium; and vertical blanking of a television signal An accompanying data recording circuit for recording the accompanying data inserted in the period in the accompanying data recording area of the recording medium, and a control code based on the program evaluation code inserted in the vertical blanking period in the television signal. A control code recording circuit for recording in a data recording area, and processing of image data or audio data reproduced from a recording medium , And a blocking circuit for blocking based on the control codes reproduced from the associated data recording area.

In this case, a component in the program evaluation code can be directly used as the control code. Furthermore, it comprises key code input means and blocking circuit control means, and
Preferably, when the value of the key code input by the key code input means matches a predetermined code value, the operation of the inhibition circuit is forcibly stopped by the inhibition circuit control means. It is practical that the predetermined code value is stored in the digital video / audio signal recording / reproducing apparatus, or is recorded in an associated data recording area of a recording medium.

[0011]

The program evaluation information inserted during the vertical blanking period in the television signal is recorded as additional data in the additional data recording area of the recording medium. During reproduction, child lock is automatically executed based on the program evaluation information reproduced from the associated data recording area. The child lock state can be forcibly released by inputting a predetermined key code.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS R. A description will be given of a television receiver configured to execute a child lock in accordance with information. R. A digital VTR configured to execute a child lock in response to information will be described.

1. P. R. FIG. 37 shows an outline of a circuit configuration of such a receiver. The operation of the circuit shown in FIG.
Are output to the Y signal processing circuit 201 and the color signal processing circuit 202, and the outputs from these processing circuits are further combined by the matrix circuit 223 to extract the primary color signals R, G, and B. On the other hand, in order to extract digital CC data or EDS data superimposed on the line 21 during video detection output, the television receiving circuit 20
0 is supplied to a data separation circuit 205 via a waveform equalization circuit 204, and the separated digital data of the line 21 is stored in a memory 2 for error correction and data storage.
06.

The data stored in the memory 206 is CC
CPU 210 for data and EDS data processing is mainly processed. That is, first, it is determined whether the data stored in the memory 206 is CC data or EDS data (the first line of the EDS data has a unique control character “Start” as described above).
Alternatively, since “Continue” is sent, and a unique control code is also sent to the first line of the CC data, the discrimination of both data is easily performed.) The specified character signal is read from the character generator 209 on the basis of the character caption and supplied to the CC display control circuit 211, and the desired caption is superimposed on the screen.

If the transmitted data is EDS data, the "Start (or Continue)"
ue) code and the "Type" code to determine the contents of the transmitted data and perform various data services. (In this circuit diagram, only the EDS processing circuit related to the child lock described above is used.) Is shown). In this receiver, the above-described P.S. R. The “r2 r1 r0” code included in the information (hereinafter referred to as RATIN
When the value of (G code) is included in a range set by the user in advance, a child lock is automatically performed to prevent normal viewing, and a key code registered in the receiver in advance by the user. When the same key code is input by the user, the child lock state is released.

Next, a specific flow of the child lock control executed by the CPU 210 will be described with reference to FIG. In this flow, when the main switch of the receiver is turned on, the CPU 210 resets the switch switching signal output from the child lock control circuit 212 and provides the switch switching signal on each of the R, G, B signal paths and the audio signal path. After connecting the respective movable terminals of SW21 to SW24 to the a side, the data of the line 21 of the second field is changed to the PDS of EDS. R. It is determined whether the data is data (step S
T120, step ST121). Step ST121
If the determination result is NO, the process returns to step ST120, and this loop is repeated, so that ordinary R, G, B
Output and audio output are retrieved.

On the other hand, if the decision result in step ST121 is Y
In the case of ES, R. It is checked whether the value of the RATING code in the data is less than a preset value "TH" or is greater than or equal to the value "TH" (step ST1).
22, step ST124). Here, the value “TH” is
This is a value that the user inputs in advance to the receiver as a threshold value for setting the value range of the rating code for executing the child lock.
Can be set to any value from “010” to “110” in the table shown in FIG. When the value of the RATING code is between "001" and "TH", the first display control signal is supplied from the child lock control circuit 212 to the child lock display control circuit 214, whereby the message "Junior Signal is required from the display control circuit, and the message is displayed on the screen (step ST123).

The value of the rating code is within the child lock range set by the user, ie, "TH".
If the value is equal to or less than "110", it is checked whether or not the user has input a key code for releasing the child lock (step ST125). If the key code has not been input, the switch switching output from the child lock control circuit 212 is performed. Set signal and set SW21-SW24 to b
Switch to the terminal side and display the blue-back signal generation circuit 2 on the screen
A blue-back screen based on the blue-back signal from 15 is displayed, and the audio signal is cut off. Also, at this time, the second display control signal is supplied from the child lock control circuit 212 to the child lock display control circuit 214, and the message "Child lock program. Please input the key code when watching." Is output, and this message is displayed on the screen.

If a key code has been entered in the check in step ST125, it is checked whether or not the input code matches the registered code. If the input code matches, the process returns to step ST120 to return to normal image display and sound emission. Run sound. If they do not match, the switches SW21 to SW24 are connected to the terminal b, and a third display control signal is supplied from the child lock control circuit 212 to the child lock display control circuit 214, and the message "key code input error" is output from the display control circuit. Please input the correct key code. "And display this message on the screen.

2. P. R. Corresponding Digital VTR Next, the child lock control according to the present invention employs a helical scan type image compression recording system for consumer digital VTR.
Embodiments applied to a TR (hereinafter, referred to as a digital VTR) will be sequentially described according to the following items.

2-1. Outline of digital VTR 1) Recording format of digital VTR (1) ITI area (2) AUDIO area (3) VIDEO area (4) SUBCODE area (5) Structure of ID part (6) MIC (7) Recording of accompanying data 2 ) Recording circuit of digital VTR 3) Reproduction circuit of digital VTR 2-2. P. R. Control based on information 1) First embodiment 2) Second embodiment

2-1. Overview of Digital VTR First, an overview of a digital VTR constituting this embodiment will be described in the order of recording format, recording circuit, and reproducing circuit.

1) Recording Format of Digital VTR FIG. 39 shows a recording format of one track on a tape of the digital VTR. In this figure, margins are provided at both ends of the track. Inside the recording start end, there is an IT
There are provided an I area, an AUDIO area for recording an audio signal, a VIDEO area for recording an image signal, and a SUBCODE area for recording secondary data. An inter-block gap (IBG) is provided between the areas to secure the area.

Next, the details of the signals recorded in each of the above areas will be described. (1) ITI Area As shown in the enlarged portion of FIG. 39, the ITI area has a 1400-bit preamble and an 1830-bit SSA (Start-Sync Block Are).
a), 90-bit TIA (Track Information)
ation Area) and a 280-bit postamble.

Here, the preamble has a function such as a run-in of the PLL at the time of reproduction, and the postamble has a role to gain a margin. And SSA and TIA are
Each block data has a predetermined SY in the first 10 bits of the block data.
An NC pattern (ITI-SYNC) is recorded.

In the 20-bit portion following the SYNC pattern, SYNC block numbers (0 to 60) are mainly recorded in SSA, and 3 bits of APT information (APT2 to APTO) are mainly used in TIA. An SP / LP flag for identifying a recording mode and a PF flag indicating a reference frame of the servo system are recorded. In addition,
APT is ID data that defines the data structure on the track. In the digital VTR of this embodiment, the value “000” is used.
Take.

As can be understood from the above description, since a large number of block data having a short code length of 30 bits are recorded in a fixed position on the magnetic tape in the ITI area, for example, the 61st data of the SSA from the reproduced data is obtained. SYN
By using the position where the C pattern is detected as a reference for defining the after-recording position on the track, the position to be rewritten at the time of after-recording can be defined with high accuracy, and good after-recording can be performed. Note that the digital V
The TR is designed so that it can be easily developed into various digital signal recording / reproducing devices outside as described later, but it is necessary to rewrite data in a specific area in any digital signal recording / reproducing device. Therefore, the ITI area on the track entrance side is always provided.

(2) AUDIO area As shown in the enlarged part of FIG. 39, the audio area has a preamble and a postamble before and after it, and the preamble is a run-up for pulling in the PLL,
And a pre-SYNC for pre-detection of an audio SYNC block. Also, the postamble is a post S for confirming the end of the audio area.
It is composed of a YNC and a guard area for protecting the audio area at the time of video data dubbing.

Here, the pre-SYNC and post-SYNC
Each of the SYNC blocks is configured as shown in (1) and (2) of FIG. 40. The pre-SYNC is composed of two SYNC blocks, and the post SYNC is composed of one SYNC block. The SP / LP identification byte is recorded in the sixth byte of the pre-SYNC. This is FF
h indicates SP, OOh indicates LP, and when the SP / LP flag recorded in the above-mentioned ITI area cannot be read, the value of the SP / LP identification byte of the pre-SYNC is adopted (h is expressed in hexadecimal notation). That there is).

The audio data recorded in the area between the amble areas as described above is generated as follows. First, an audio signal for one track to be recorded is subjected to A / D conversion and shuffling, then framing is performed, and further parity is added. A format in which parity is added by performing this framing is shown in FIG.
(1). In this figure, 5-byte audio accompanying data (this is called AAUX data) is added to the beginning of 72-byte audio data to form 77-byte data per block, and these are vertically stacked in 9 blocks for framing. Then, an 8-bit horizontal parity C1 and a vertical parity C2 corresponding to five blocks are added thereto.

The data to which the parity is added is read out in units of each block, and 3 bits are added to the head of each block.
A byte ID is added, and a 2-byte SYNC signal is inserted in the recording modulation circuit.
Is formed into a signal of 1 SYNC block having a data length of 90 bytes as shown in FIG. Then, this signal is recorded on the tape.

(3) VIDEO Area The video area has the same preamble and postamble as the audio area as shown in the enlarged part of FIG. However, it differs from that of the audio area in that the guard area is formed longer. Video data sandwiched between these amble areas is generated as follows.

First, video signals to be recorded are represented by Y, RY,
After being separated into BY component signals, AD conversion is performed, and data of an effective scanning area for one frame is extracted from the AD conversion output. When the video signal is a 525/60 system, the extracted data for one frame is Y
The AD conversion output (DY) of the signal is output in the horizontal direction 72.
It is composed of 0 samples and 480 lines in the vertical direction.
AD conversion output (DR) of the RY signal and A of the BY signal
The D conversion output (DB) is 18
It consists of 0 samples and 480 lines in the vertical direction.

The extracted data is divided into blocks of 8 samples in the horizontal direction and 8 lines in the vertical direction as shown in FIG. However, in the case of the color difference signal, since the block at the right end in (2) of FIG. 42 has only four samples in the horizontal direction, two blocks vertically adjacent to each other are combined into one block. By the above blocking processing, a total of 81 in DY, DR, and DB per frame
00 blocks are formed. This horizontal direction 8
Sample, block composed of 8 vertical lines is D
It is called a CT block.

Next, these blocked data are shuffled according to a predetermined shuffling pattern, and then subjected to DCT transform in units of DCT blocks, followed by quantization and variable length coding. Here, the quantization step is set for every 30 DCT blocks, and the value of this quantization step is set so that the total amount of output data obtained by quantizing the 30 DCT blocks and performing variable length coding is equal to or less than a predetermined value. You. That is, the video data is transferred to the DCT block 30.
Fixed length for each piece. The data for 30 DCT blocks is called a buffering unit.

The data fixed in length as described above is subjected to framing together with video accompanying data (hereinafter referred to as VAUX data) for each data of one track, and thereafter, an error correction code is added. FIG. 43 shows a format in which the framing is performed and the error correction code is added.

In this figure, BUF0 to BUF26 each represent one buffering unit. Then, one buffering unit corresponds to (1) in FIG.
Has a structure divided into five blocks in the vertical direction, and each block has a data amount of 77 bytes.
An area Q for storing parameters related to quantization is provided in the first byte of each block.

Video data is stored in an area of 76 bytes following the quantized data. As shown in FIG. 43, VAUX data α and β corresponding to two blocks in the buffering unit are arranged above the 27 buffering units arranged in the vertical direction. At the lower part, VAUX data γ corresponding to one block is arranged, and a horizontal parity C1 of 8 bytes and a vertical parity C2 corresponding to 11 blocks are added to these framed data. Is done.

The signal to which the parity has been added in this manner is read out in units of blocks, a 3-byte ID signal is added to the head of each block, and a 2-byte SYNC signal is inserted in the recording modulation circuit. You. This allows
For the video data block, a signal of a 1 SYNC block having a data amount of 90 bytes as shown in (2) of FIG. 44 is formed, and for the block of VAUX data, 1 SYNC as shown in (3) of FIG. A block signal is formed. The signal for each 1 SYNC block is sequentially recorded on the tape.

In the framing format described above, since 27 buffering units representing video data for one track have data for 810 DCT blocks, data for one frame (8100 DCT blocks) is It is recorded in ten tracks separately.

(4) SUBCODE area The SUBCODE area is provided mainly for recording information for high-speed search. Of the data recorded on the tape, only the data in this area is rewritten by post-recording. Is possible. For example, as will be described later, a still image search flag recorded in the ID portion of this area can be post-recorded, or a desired optional pack can be dubbed in this area. For reference, an enlarged view of the SUBCODE area is shown in FIG. As shown in this figure, this area includes 12 SYNC blocks having a data length of 12 bytes, and a preamble and a postamble are provided before and after it. However, a pre-SYNC and a post-SYNC are not provided unlike the audio area and the video area. And, in each of the 12 SYNC blocks,
A data section for recording 5-byte accompanying data (AUX data) is provided. As a parity for protecting the 5-byte associated data, only a 2-byte horizontal parity C1 is used, and a vertical parity is not used.

The AUDIO area described above,
Each SYNC block forming the VIDEO area and the SUBCODE area is 24/25 in the recording modulation.
The conversion (recording modulation method in which a recording control code is added with a tracking control pilot frequency component by converting data of every 24 bits of the recording signal into 25 bits) is performed. Is shown in FIG.
The number of bits is as shown in FIG.

(5) Structure of ID section As is clear from the configuration of each SYNC block shown in FIGS. 40, 41, 44 and 45, A
UDIO area, VIDEO area, and SUBOCO
Each of the SYNC blocks recorded in the DE area has ID0, ID1, and I after a 2-byte SYNC signal.
3 consisting of DP (parity protecting ID0 and ID1)
It has a common structure in that a byte ID portion is provided. The data structure of ID0 and ID1 in the ID area is determined in the audio area and the video area as shown in FIG.

That is, SYNC numbers (0 to 168) in the track from the pre-SYNC in the audio area to the post-SYNC in the video area are stored in ID1 in a binary number. The track number in one frame is stored in the lower 4 bits of ID0. The track numbers are numbered at a rate of one per two tracks, and the distinction between the two tracks can be determined by the azimuth angle of the head.

The upper 4 bits of ID0 include AAU
SYNC of X + audio data and video data
In the block, as shown in FIG.
The bit sequence number is stored. On the other hand, in the pre-SYNC block, post-SYNC block and parity C2 SYNC block of the audio area, a 3-bit ID that defines the data structure of the audio area is used.
The data AP1 is stored, and the pre-S
In the YNC block, the post-SYNC block, and the SYNC block of the parity C2, 3-bit ID data AP2 that defines the data structure of the video area is stored (see (2) in this figure). Note that these values of AP1 and AP2 are “0” in the digital VTR of this embodiment.
00 ".

The above sequence number is "000
Twelve different numbers from "0" to "1011" are recorded for each frame. By looking at this sequence number, it can be determined whether or not the data obtained at the time of variable speed reproduction is in the same frame. On the other hand, SUBCOD
The structure of the ID part of the SYNC block in the E area is defined as shown in FIG.

This figure shows the structure of each ID part of SYNC block numbers 0 to 11 for one track of the SUBCODE area, and the FR flag is provided in the most significant bit of ID0. This flag indicates whether the frame is the first five tracks of the frame, and takes a value of "0" in the first five tracks and "1" in the second five tracks. The next three bits include S in the SYNC blocks whose SYNC block numbers are “0” and “6”.
The ID data AP3 that defines the data structure of the UBCODE area is recorded, and the SYNC block number “1” is recorded.
In the SYNC block of "1", ID data APT defining the data structure on the track is recorded, and in the other SYNC blocks, the TAG code is recorded. The value of AP3 is the digital V of this embodiment.
In TR, "000" is taken.

The TAG code is composed of three types of ID signals for search, as shown in an enlarged view in FIG.
That is, it is composed of a conventional INDEX ID for INDEX search, a SKIP ID for cutting unnecessary scenes such as commercials, and a PP ID (Photo / Picture ID) for still image search. The absolute number of the track (the continuous track number from the beginning of the tape) is recorded using the lower 4 bits of ID0 and the upper 4 bits of ID1. An arbitrary position on the tape can be specified by using the absolute track number, and the absolute track number has a role as a position specifying signal. As shown in this figure, one absolute track number is recorded using a total of 24 bits for three SYNC blocks. The SYNC block number of the SUBCODE area is recorded in the lower 4 bits of ID1.

(6) MIC In the digital VTR of this embodiment, as described above, the accompanying data is recorded in each area defined on the tape, but the tape is stored outside the area. A circuit board provided with a memory IC is mounted on a cassette,
Associated data is also recorded in this memory IC. When this cassette is mounted on the digital VTR, the accompanying data written in the memory IC is read out to assist the operation and operation of the digital VTR (Japanese Patent Application No. 4-165444, See Japanese Patent Application No. 4-287875). In the present application, this memory IC is referred to as MIC (Memory In Cassette), and its data structure will be described later in detail.

(7) Recording of Associated Data As described above, in the digital VTR of this embodiment, the AAUX area of the audio area on the tape and the VA of the video area
The AUX data recording area of the UX area and the SUBCODE area is used, and in addition, the recording area of the MIC mounted on the tape cassette is used. Each of these areas is constituted by a pack having a fixed length of 5 bytes.

FIG. 48 shows the basic structure of this pack. In this figure, the first byte (PC0) is item data (also called a pack header) indicating the contents of data stored in a pack. Then, a format of the succeeding 4 bytes (PC1 to 4) is determined corresponding to the item data, and predetermined data is stored according to the format.

The item data is divided into upper and lower 4 bits, and the upper 4 bits are called a large item and the lower 4 bits are called a small item. The large item of the upper 4 bits is, for example, data indicating the purpose of the subsequent data, and the pack is used to pack the control “0000” and the title “000” as shown in the table of FIG.
1 ", chapter" 0010 ", part" 0011 ",
Program "0100", audio auxiliary data (AAUX)
“0101”, image auxiliary data (VAUX) “011”
0, camera "0111", line "1000", and soft mode "1111".

Each group of packs expanded by the large items in this way is further expanded into 16 types of packs by further small items (which represent, for example, the specific contents of subsequent data). Using these items, up to 256 types of packs can be defined. Note that “RESERVED” entered in the table of FIG. 49 indicates an undefined portion left for addition. Therefore, by defining new item data (header) using an undefined item data code, new data can be arbitrarily recorded in the future. Further, since the contents of the data stored in the pack can be grasped by reading the header, the position on the tape where the pack is recorded can be set arbitrarily. Next, the structure of each recording area of the above-described accompanying data and a specific example of a pack recorded therein will be described.

A) AAUX area In the AAUX area, 1SY shown in (2) of FIG.
5 bytes AA in NC block format
One pack is constituted by the UX area. Therefore, AA
The UX area is composed of nine packs per track. In the digital VTR of the 525/60 system, one frame of data is recorded on ten tracks, so the AAUX area for one frame is represented as shown in FIG.

In this figure, one section represents one pack. Then, the numbers 50 to 55 written in the sections
Is a hexadecimal representation of the item codes of the packs in that section, and these six types of packs are called main packs. The area where these main packs are recorded is called an AAUX main area. That is, the same pack data is stored in this main area as shown in FIG.
It is recorded repeatedly 10 times per frame. These main packs mainly store important and essential data related to the recording and reproduction of audio signals. By performing the above-mentioned repetitive recording, data can be recorded even if tape scratches or channel clogs occur. Has a higher reproducibility.

The specific structures of these six types of main packs are shown in [1] and [2] in FIG. 1 and (1) to (1) in FIG.
This will be described using (4). The pack of the item code 50h shown in [1] of FIG. 1 is AAUX SOURCE.
It is called a pack and is used to record accompanying data related to audio. That is, as shown in the figure, a flag (LF) indicating whether the audio sample frequency is locked to the video signal, the number of audio samples per frame (AF SIZE), and the number of audio channels (C
H), information on the mode of each audio channel such as stereo / monaural (PA and AUDIO MODE), information on the television system (50/60 and STYP)
E), presence or absence of emphasis (EF), time constant of emphasis (TC), sample frequency (SMP), and quantization information (QUA) are recorded.

Item code 5 shown in [2] of FIG.
1h pack is AAUX SOURCE CONTROL
It is called an L-pack, and as shown in the figure, SCMS data (the upper bits indicate the presence or absence of a copyright and the lower bits indicate whether or not the original tape), copy source data (an analog signal source or a digital signal source) , Copy generation data, an SS code indicating whether the signal to be recorded is scrambled or to be child-locked (when the value of this code is “00”, the signal is a scrambled signal. When "10", it indicates that the signal should be child-locked.
“01” is undefined, and “11” means no information. ), A flag (RS) indicating whether a frame is a recording start frame, a flag (RE) indicating whether a frame is a recording last frame, and recording mode data (REC MODE) such as original recording / after-recording recording / insert recording. ),
A flag (DRF) indicating the tape running direction, playback speed data, and a genre category of the recorded content are recorded.

The AAUX REC shown in FIG.
In the DATE pack, data such as the recording date for audio recording is recorded, and AA shown in (2) of FIG.
In the UXREC TIME pack, data of the recording time of ** hour ** minute ** second ** frame is recorded in SMPTE time code display. AAU shown in (3) of FIG.
The X REC TIME BINARY GROUP pack records SMPTE time code binary group data.

The AAUX CLO shown in FIG.
The SED CAPTION pack contains EDS (Extended Da) related to the language and type of the main sound and the second sound.
taService) data is stored. The area other than the main area where the main pack described above is recorded is called an AAUX optional area, and an arbitrary pack can be selected from a variety of packs and a maximum of 30 packs can be recorded per frame. In the optional area, a common option area in which a common option is recorded is provided first. In the case of a soft tape, a maker optional area is provided after this common option area, in which contents unique to each soft tape maker are recorded. However, there is a case where only one or both exist, or both do not exist because they are optional.

Then, in the common optional area,
For example, text data is recorded. On the other hand, in the maker optional area, first, the soft mode “111” is set.
A MAKER CODE pack (see (5) in FIG. 2) having a large item of “1” and a small item of “0000” is provided, followed by contents unique to each manufacturer. Therefore, if the MAKER CODE pack is determined, it is determined that the content before the MAKER CODE pack is the common content, and thereafter, the content is unique to each manufacturer.

As a special example of a pack, a pack with an item code of all 1s is a pack with no information (NO I
NFORMATION pack), and when there is no information to be recorded in the optional area, this NO INFORMATION pack is recorded. The mechanism of the main area, optional area, common option, and maker's option described above is common to all AAUX, VAUX, SUBCODE, and MIC associated data recording areas.

B) VAUX area For the VAUX area, the VAU area in one track
The X area is composed of three SYNC blocks α, β, and γ as shown in FIG.
As shown in the figure, 15 pieces per 1 SYNC block, 1
There are 45 trucks. The area of 2 bytes immediately before the horizontal parity C1 in one SYNC block is:
Used as a preliminary recording area.

For the VAUX area for one frame,
FIG. 4 shows the pack configuration. In this figure, packs to which item codes 60 to 65 in hexadecimal are attached are VAUs constituting a VAUX main area.
An X main pack, and the other packs constitute a VAUX optional area.

The specific structure of the VAUX main pack will be described. The pack of the item code 60h shown in [1] of FIG. 5 is called a VAUX SOURCE pack, and is used for recording the accompanying data related to the image. That is, as shown in this figure, the channel number of the recording signal source, a flag (B / W) indicating whether the recording signal is a monochrome signal, and a code (CF) indicating color framing.
L), a flag (E) indicating whether the CFL is valid
N), a code (SOURCE CODE) indicating whether the recording signal source is a camera / line / cable / tuner / soft tape, etc., data (50/60 and STYPE) related to a television signal system, UV
Data related to identification of broadcasting / satellite broadcasting (TUNER
(CATEGORY) is recorded.

The VAUX SOURCE CONTROL of the item code 61h shown in [2] of FIG.
AAUX SOURCE CONTROL
SCMS data, copy source data similar to the pack,
Copy generation data, SS data, a flag (RS) indicating whether the frame is a recording start frame, and recording mode data (REC such as original recording / after-recording / insert recording)
MODE) is recorded, and further, data (BCSYS and DISP) relating to the aspect ratio and the like, a flag (FF) relating to whether or not to output only the signal of one of the odd / even fields twice, and a field (FF) A flag (FS) regarding whether to output a field 1 signal or a field 2 signal during the period 1, a flag (FC) regarding whether or not image data of a frame is different from image data of a previous frame, interlacing , A flag (ST) regarding whether or not the recorded image is a still image, a flag (SC) indicating whether or not the recorded image is recorded in the still camera mode, And the genre of the recorded content is recorded.

When the item codes are 62h, 63h,
And 64h packs are VAUX REC D
ATE pack, VAUX REC TIME pack, and VAUX REC TIME BINARY GRO
It is called an UP pack, has the same data structure as the packs shown in (1) to (3) of FIG. 2 (only the item code is different from these packs), and records the image signal recording date. , And SMPTE time code. In the CLOSED CAPTION pack of the item code 65h shown in [3] of FIG. 5, closed caption information transmitted during the vertical retrace period of the television signal is recorded.

C) AUX data recording area in SUBCODE area The AUX data recording area in the SUBCODE area has SYNC block numbers 0 to 11 as shown in FIG.
5 bytes are present in each SYNC block, and each pack constitutes one pack. That is, 1 for 1 track
Two packs are recorded, of which packs with SYNC block numbers 3 to 5 and 9 to 11 constitute a main area, and the other packs constitute optional areas.

In this SUBCODE area, 1
Frame data is repeatedly recorded in a format as shown in FIG. In this figure, uppercase alphabets represent packs in the main area, and packs used for high-speed search, such as packs storing time codes and packs storing recording dates, are recorded. The lower case alphabet represents a pack of the optional area, and is repeatedly recorded in the position as shown in this figure.

FIG. 6 shows a recording pattern in the case of the 525/60 system. For reference, FIG. 7 shows a recording pattern of SUBCODE data for one frame in the case of the 625/50 system. As shown in this figure, 6
In the case of the 25/50 system, one frame is composed of 12 tracks, but the SUBCODE in one track is 12 SYNCs as in the case of the 525/60 system.
It is composed of blocks, and differs only in the number of tracks. However, the number of tracks used per second is equal to 300 tracks.

The SD (STANDARD) described above
In the DENSITY method, one frame is composed of 10 tracks or 12 tracks, but HD (HIGH)
In the case of the (DENSITY) system, recording is performed in 20 tracks per frame in the 1125/60 system and in 24 tracks in 1 frame in the 1250/50 system.

It should be noted that the main area in each recording area described above has a feature that a pack storing auxiliary information on basic data items common to all tapes is recorded. On the other hand, a soft tape maker or a user can freely write arbitrary accompanying data in the optional area.
Such additional information includes, for example, various character information, teletext signal data, television signal data of an arbitrary line within a vertical blanking period or an effective scanning period, data of computer graphics, and the like. is there.

D) MIC Recording Area FIG. 8 shows the data structure of the MIC recording area. This recording area is also divided into a main area and an optional area, and all are described in a pack structure except for the first byte and an unused area (FFh is recorded).

At the head address 0 of the MIC main area, ID data A that defines the data structure of the MIC is stored.
PM3 bit and BCID (Basic Cassette)
eID) 4 bits are recorded. Here, the value of APM is “000” in the digital VTR of the present embodiment. BCID is a basic cassette ID, and MI
The contents are the same as those of the ID board for ID recognition (tape thickness, tape type, tape grade) for a cassette without C. The ID board allows the MIC reading terminal to perform the same function as the conventional 8 mm VTR recognition hole, thereby eliminating the need to make a hole in the cassette half as in the conventional case.

After address 1, CASSETE
ID pack, TAPE LENGTH pack, TIT
Three main packs of the LE END pack are recorded. To explain the structure of these main packs,
The CASSETE ID pack shown in [1] of FIG. 9 includes a flag ME indicating whether data recorded on the MIC corresponds to data recorded on the tape of the cassette, and a type of the memory (MIC). , Information on the size of the memory, and information on the tape thickness (PC4) are recorded.

The TAPE LEN shown in [2] of FIG.
In the GTH pack, the entire length of the magnetic tape body excluding the leader tape in the video tape is recorded as 23-bit data converted into the number of tracks.

The TITLE EN shown in [3] of FIG.
In the D pack, the absolute track number of the last recording position on the tape is recorded. This final recording position means the position closest to the tape end in the area on the tape where recording has been performed, and after this position is an unrecorded area. When there is a blank portion (blank) in the middle of the tape, a discontinuous portion occurs in the absolute track number recorded on each track on the tape. This flag indicates whether there is such a discontinuous portion at a position before the absolute track number recorded in the pack.

The flag SL indicates whether the recording mode at the last recording position is the SP mode or the LP mode. When the recording operation is restarted from the last recording position, the start of the servo system is started. It is convenient to speed up. The flag RE is a flag indicating whether there is any recorded content that must not be deleted on the tape. The length (remaining amount) of the unrecorded portion of the tape can be immediately obtained from the absolute track number stored in the TITLE END pack and the value of the absolute track number stored in the TAPE LENGTH pack.

The above-mentioned last recording position information provides a convenient usability for stopping the reproducing operation started after rewinding the tape in the camcorder and then returning to the original last recording position or timer reservation. I do. The main area explained above is 1 from addresses 0 to 15.
The optional area is a variable area located after the address 16 while the fixed area is 6 bytes. The data recorded in the optional area of the MIC is configured in units of events.

Here, an event usually means one data group composed of a plurality of packs, and the pack located at the head thereof is called an event header. The pack that becomes this event header is predetermined to a specific pack according to the content of each event,
One event cannot contain a pack defined as another event header. That is, one event is formed from the event header to the next event header.

The overall control of the digital VTR is performed by a mode processing microcomputer as described later. For example, in the case of performing control based on the above-mentioned event, this microcomputer is controlled by a user's instruction or the like. The content of each event in the MIC is decoded in response thereto, and operations such as display and control are executed based on a command or the like from the user according to the decoding result. Specific examples of such an event include various events such as a ZONE event, a VAUX event, and an AAUX event, which will be described later.

As described above, various events are recorded in the optional area. Here, when a specific event that has been recorded is deleted, the remaining events are recorded after the address 16. FFh is written in all the data areas that become unnecessary after the stuffing operation and become unused areas. At the time of reading MIC data, the next pack header appears every 5 bytes or every variable length byte (text data) depending on the contents of the pack header. Pack without information (NO INFO pack)
The control microcomputer can detect that there is no information after that.

As can be seen from the above description, in the digital VTR of the present embodiment, the structure of the accompanying data is a pack structure common to each area as described above. Software can be shared and processing is simplified. Further, since the timing at the time of recording / reproducing becomes constant, there is no need to provide an extra memory such as a RAM for time adjustment, and the software can be easily developed even when a new model is developed. be able to.

Further, by adopting the pack structure, even if an error occurs during reproduction, for example, the next pack can be easily taken out. Therefore, a large amount of data is not destroyed due to propagation of an error.

2) Recording Circuit of Digital VTR In the digital VTR of this embodiment, recording is performed on the tape and the MIC according to the recording format described above.
The configuration and operation of the recording circuit of the TR will be described. FIG. 10 shows the configuration of such a recording circuit.

In this figure, an input analog composite video signal is converted by a Y / C separation circuit 41 into Y and R signals.
−Y and RY component signals, and A /
It is supplied to the D converter 42. The analog composite video signal is supplied to a sync separation circuit 44, and the separated sync signal is supplied to a clock generator 45.
The clock generator 45 generates a clock signal for the A / D converter 42 and the blocking / shuffling circuit 43.

The component signal input to the A / D converter 42 is a 525/60 system, and the Y signal is 1
3.5 MHz, the color difference signal has a sampling frequency of 13.5 / 4 MHz, and for a 625/50 system, Y
The signal is 13.5 MHz and the color difference signal is 13.5 / 2 MHz
A / D conversion is performed at the sampling frequency of. Then, only the data DY, DR, and DB in the effective scanning period among these A / D conversion outputs are supplied to the blocking / shuffling circuit 43.

This blocking / shuffling circuit 43
, The valid data DY, DR, DB
The sample is subjected to a blocking process in which eight lines in the vertical direction constitute one block, and further four DY blocks,
After shuffling is performed to increase the compression efficiency of image data and disperse errors at the time of reproduction in units of a total of six blocks, one for each of the DR and DB blocks,
It is supplied to the compression encoding unit.

The compression encoding unit applies D data to the input block data of 8 samples in the horizontal direction and 8 lines in the vertical direction.
A compression circuit 46 for performing CT (Discrete Cosine Transform), an estimator 48 for estimating whether or not the result has been compressed to a predetermined data amount, and finally a quantization step is determined based on the determination result, and the variable length coding And a quantizer 47 for performing data compression using. The output of the quantizer 47 is framed by the framing circuit 49 into the format described in FIG.

The mode processing microcomputer 67 in FIG.
Is a microcomputer having a man-machine interface with a human, and operates in synchronization with the frequency of the vertical synchronization of the television signal. The signal processing microcomputer 55 operates on a side closer to the machine, and has a rotation speed of the drum of 9%.
It operates in synchronization with 000 rpm and 150 Hz.

Then, VAUX, AAUX, SUBCO
The pack data for each area of the DE is basically generated by the mode processing microcomputer, and the absolute track number stored in the TITLE END pack or the like is generated by the signal processing microcomputer 55, and is later inserted into a predetermined position. Is executed. The time code data stored in the SUBCODE is also generated by the signal processing microcomputer 55.

These results can be obtained from the interface VAUX IC 5 which is provided between the microcomputer and the hardware.
6. IC57 for SUBCODE and IC58 for AAUX
Given to. The VAUX IC 56 combines the output of the framing circuit 49 with the combiner 50 at an appropriate timing. Further, the SUBCODE IC 57 includes AP3, S
SID, which is the ID of UBCODE, and SUBCODE
Is generated.

On the other hand, the input audio signal is converted by the A / D converter 51 into a digital audio signal. In addition, at the time of A / D conversion of a video signal and an audio signal, although not shown in this figure, it is necessary to provide an LPF corresponding to the sampling frequency in a preceding stage of the sampling circuit. The A / D-converted audio data undergoes data distribution processing by a shuffling circuit 52, and is then framed by the framing circuit 53 into the format described in FIG. At this time AA
The UX IC 58 generates the AAUX pack data, measures the timing, and packs them in a predetermined location in the audio SYNC block by the synthesizing circuit 54.

Next, generation and recording of VAUX pack data will be described. FIG. 11 shows the overall flow. First, the mode processing microcomputer 67 generates pack data to be stored in the VAUX. The data is converted into serial data by the P / S conversion circuit 118 and sent to the signal processing microcomputer 55 according to the communication protocol between the microcomputers. Here, the data is returned to parallel data by the S / P conversion circuit 119 and the switch 12
2 is stored in the buffer memory 123. From the transmitted pack data, the header part at the beginning of every 5 bytes is extracted by the pack header detection circuit 120, and it is checked whether the pack requires an absolute track number. If necessary, the switch 122 is switched to store the 23-bit data from the absolute track number generation circuit 121 in 8-bit units. The storage area is the PC of the pack to be stored as described in the individual pack structure.
1, PC2 and PC3 are fixed positions.

Here, the circuit 119 is a serial I / O in the microcomputer, the circuits 120, 121 and 122 are constituted by microcomputer programs, and the circuit 123 is a RAM in the microcomputer. As described above, the processing of the pack structure uses a microcomputer which is advantageous in cost because the processing time of the microcomputer is sufficient even if the processing is not performed by hardware. The data stored in the buffer memory 123 in this way is VA
Write-side timing controller 12 of UX IC 56
According to the instruction from 5, the data is sequentially read. At this time, the switch 124 is switched for the first six packs for the main area and for the subsequent 390 packs for the optional area.

The FIFO 126 for the main area is 30 bytes, and the FIFO 127 for the optional area is 1950.
It has a capacity of bytes (525/60 systems) or 2340 bytes (625/50 systems). VAUX
Is the SYN in the track as shown in [1] of FIG.
C numbers 19, 20, and 156 are stored. When the track numbers in the frame are 1, 3, 5, 7, and 9, the main area is + azimuth in the first half of the SYNC number 19, and when the track numbers in the frame are 0, 2, 4, 6, and 8, −
There is a main area in the latter half of SYNC number 156 in azimuth. This is drawn together in one video frame,
This is [2] in FIG. Thus, the timing signal nM
When AIN = “L”, the main area is set. Such a signal is generated by the read-side timing controller 129, the switch 128 is switched, and its output is
Pass to 0.

Here, when nMAIN = "L", the data of the main area FIFO 126 is repeated 10 times (525/60 system) or 12 times (625/60 system).
50 systems). nMAIN =
If "H", the optional area FIFO 127 is read. It reads only once per video frame.
FIG. 13 shows a VAUX pack data generation unit in the mode processing microcomputer. First, the circuit is roughly divided into a main area and an optional area. Circuit 131
Is a main area data collection and generation circuit. Data shown in the figure is received from a digital bus or tuner, and a data group 139 is generated internally.
This is assembled into the bit byte structure of the main pack, a pack header is added by the switch 132, and input to the P / S conversion circuit 118 via the switch 136.

The optional area data collection and generation circuit 133 receives, for example, TELETEXT data and a program title from a tuner, and generates pack data storing these. Which optional area is to be recorded is determined individually by the VTR set. The pack header is set by the circuit 134 and added by the switch 135, and the P / S conversion circuit 1 is connected via the switch 136.
Input to 38. These timings are performed by the timing adjustment circuit 137. Again, as mentioned earlier, circuit 1
Reference numeral 18 denotes a serial I / O in the microcomputer, and the circuits 131 to 137 are configured by a microcomputer program.

FIG. 14 shows an AAUX pack data generation unit in the mode processing microcomputer. A in this circuit
The generation of the AUX pack data is performed by the same operation as in the case of the VAUX pack data described above, and a detailed description thereof will be omitted.

Returning to the description of FIG. 10, the generator 59 in FIG. 10 uses an AV (Audio / Video)
o) Each ID part, pre-SYNC and post-SYNC are generated. Here, AP1 and AP2 are also generated and a predetermined ID
Fit into the department. The output of the generator 59 and ADATA (AU
DIO DATA), VDATA (VIDEO DAT)
A), SID, and SDATA are switched by the first switching circuit SW1 while observing the timing.

Then, a predetermined parity is added to the output of the first switching circuit SW1 in the parity generation circuit 60, and the randomization circuit 61 and the 24/25 conversion circuit 62
Supplied to Here, the randomizing circuit 61 converts input data into random numbers in order to eliminate DC components of the data. Also, 2
The 4/25 conversion circuit 62 performs a process of adding one bit to every 24 bits of data to give a pilot signal component and a precoding process (partial response class IV) suitable for digital recording.

The data thus obtained is supplied to the synthesizer 63, where the A / V SYNC and the SUBCODE
The audio, video and SUBCODE SYNC patterns generated by the SYNC generator 64 are synthesized.
The output of the synthesizer 63 is supplied to the second switching circuit SW2. The ITI data output from the ITI generator 65 and the amble pattern output from the amble pattern generator 66 are also supplied to the second switching circuit SW2.

The ATI, SP / LP, and PF data are supplied from the mode processing microcomputer 67 to the ITI generator 65. The ITI generator 65 fits these data into a predetermined position of the TIA to generate a second switching circuit SW2.
Supply to Therefore, by switching the switching circuit SW2 at a predetermined timing, the amble pattern and the ITI data are added to the output of the synthesizer 63. The output of the second switching circuit SW2 is amplified by a recording amplifier (not shown), and is amplified by a magnetic head (not shown).
Is recorded on a magnetic tape (not shown).

The mode processing microcomputer 67 has a digital VT
The mode management of the entire R is performed. The third switching circuit SW3 connected to the microcomputer is an external switch of the VTR main body, and is capable of instructing various operation modes of the digital VTR and inputting various data necessary for generating pack data. It is a configured switch group. The set contents and input data of the switch group are detected by the mode processing microcomputer 67, and given to the signal processing microcomputer 55, the MIC microcomputer 69, and the mechanism control microcomputer (not shown) by communication between the microcomputers. In addition,
The MIC microcomputer 69 is a MIC processing microcomputer.
Here, pack data and APM in the MIC are generated, and M
This is supplied to the MIC 68 in a cassette with MIC (not shown) via an IC contact (not shown).

Next, generation of pack data in the MIC microcomputer will be described with reference to FIG. In this figure, serial data input from the mode processing microcomputer 67 is converted into parallel data in the S / P conversion circuit 9 and processed inside the microcomputer. In the main area shown in FIG.
APM, the ME flag in the CASSETTE ID pack, and the TITLE END pack (TA
The data in the PE LENGTH pack is written by the tape maker). Among them, the RE flag and M
The E flag is generated inside the MIC microcomputer, and the other data is received from the mode processing microcomputer 67. Note that the absolute track number, the SL flag, and the BF flag are generated by the signal processing microcomputer and received via the mode processing microcomputer.

The data thus obtained is assembled according to the operation of the MIC, and written into the MIC 68. The switch 12 is for supplying the pack header when writing the TITLE END pack, and is switched upward only at this time. Various items are recorded in the optional area of the MIC. For example, text data such as a program title is sent from the mode processing microcomputer 67. These are assembled and written by the MIC microcomputer as needed.

The data assembled by the MIC microcomputer is converted to the IIC bus format, which is the MIC communication protocol, by the circuit 8 and then transmitted to the MIC. The circuits other than the circuits 8 and 9 in the figure are microcomputer programs.
Actually, the data of the circuits 1 and 3 are stored in the RAM inside the microcomputer. The above-described series of recording operations in the recording circuit of FIG.
This is performed by a cooperative operation between the mechanical control microcomputer or the signal processing microcomputer 55 and the IC in charge of each part.

3) Reproduction Circuit of Digital VTR Next, the reproduction circuit of the digital VTR in this embodiment will be described with reference to FIGS. In these figures, a weak signal reproduced from a magnetic tape (not shown) by a magnetic head (not shown) is amplified by a head amplifier (not shown), and is equalized.
Added to The equalizer circuit 71 performs reverse processing of emphasis processing (for example, partial response class IV) performed for improving electromagnetic conversion characteristics between a magnetic tape and a magnetic head during recording.

The clock CK is extracted from the output of the equalizer circuit 71 by the clock extracting circuit 72. This clock CK is supplied to the A / D converter 73, and the output of the equalizer circuit 71 is digitized. The 1-bit data thus obtained is written into the FIFO 74 using the clock CK. The clock CK is a temporally unstable signal including a jitter component of the rotating head drum. However, since the data itself before the A / D conversion also contains a jitter component, there is no problem in sampling itself.

However, when extracting image data or the like from this point, since the data cannot be extracted unless the data is temporally stable, the time axis is adjusted using the FIFO 74. That is, writing is performed with an unstable clock, while reading is performed with a stable clock SCK from a self-excited oscillator 91 using a crystal oscillator or the like shown in FIG. FI
The depth of the FO 74 is set to have a margin so as not to read out faster than the input speed of the input data.

The output of each stage of the FIFO 74 is applied to a SYNC pattern detection circuit 75. Here, the SYNC pattern of each area is switched by the fifth switching circuit SW5 and given by the timing circuit 79. The SYNC pattern detection circuit 75 has a flywheel configuration, and once a SYNC pattern is detected, the same SYNC pattern is re-entered after a predetermined SYNC block length.
See if a YNC pattern comes. That is, for example, 3
A majority rule that is considered true if it is correct more than twice prevents erroneous detection. The depth of the FIFO 74 needs several minutes.

When the SYNC pattern is detected in this way, the shift amount is determined as to which part is extracted from the output of each stage of the FIFO 74 to extract one SYNC block. SW4 is closed and necessary bits are taken into the SYNC block determination latch 77. With this, the captured SY
The NC number is extracted by the SYNC number extraction circuit 78 and supplied to the timing circuit 79. This read S
Since the position on the track where the head is scanning can be known from the YNC number, the fifth switching circuit SW5 and the sixth switching circuit SW6 are switched accordingly.

The sixth switching circuit SW 6 is switched to the lower side when the head scans the ITI area. The sixth switching circuit SW 6 removes the ITISYNC pattern by the subtracter 80 and adds the same to the ITI decoder 81. Since the ITI area is coded and recorded, the APT, SP / LP, and PF data can be extracted by decoding it. These data are supplied to the mode processing microcomputer 82 to which the seventh switching circuit SW7 for setting the SP / LP mode is connected. Mode processing microcomputer 8
Reference numeral 2 designates an operation mode and the like of the entire digital VTR.
In cooperation with 0, system control of the entire set is performed.

An MIC microcomputer 83 for managing APM and the like is connected to the mode processing microcomputer 82. MIC
The information from the MIC 84 in the cassette with cassette (not shown) is transmitted via the MIC contact switch (not shown) to this MI.
It is given to the C microcomputer 83 and performs MIC processing while sharing the role with the mode processing microcomputer 82. Depending on the set, the MIC microcomputer 83 may be omitted, and the mode processing microcomputer 82 may perform MIC processing.

When the head is scanning the audio area, the video area, or the SUBCODE area, the sixth switching circuit SW6 is switched to the upper side. After the SYNC pattern of each area is extracted by the subtractor 86, the SYNC pattern is passed through a 24/25 inverse conversion circuit 87, further applied to an inverse random number generation circuit 88, and returned to the original data string.
The data thus extracted is added to the error correction circuit 89.

The error correction circuit 89 detects and corrects error data by using the parity added on the recording side.
Output with flags. Each data is switched and output by the eighth switching circuit SW8. AV
The ID, pre-SYNC, and post-SYNC extraction circuits 90
A / V area, SYNC number, track number stored in pre-SYNC and post-SYNC, and pre-S
The SP / LP signals stored in the YNC are extracted. These are given to the timing circuit 79 and used for generating various timings. In the extraction circuit 90, AP1 and AP2 are also extracted and supplied to the mode processing microcomputer 82 for checking. AP
When 1, AP2 = 000, the operation is normal, but when the value is other than that, a warning operation such as a warning process is performed.

For the SP / LP, the mode processing microcomputer 82 performs a comparative study with that obtained from the ITI.
In the ITI area, three times SP /
LP information is written, and a majority vote is taken alone to improve reliability. The pre-SYNC has 2 SYNCs each for audio and video, and SP / LP information is written in four places in total. Here, too, a majority vote is taken to improve reliability. If the two do not finally match, the one in the ITI area is preferentially adopted.

VDATA output from the eighth switching circuit SW8 is separated into video data and video accompanying data by the ninth switching circuit SW9 shown in FIG. Then, the video data is supplied to the deframing circuit 94 together with the error flag. The deframing circuit 94 performs the inverse conversion of the framing on the recording side, and grasps the nature of the data packed therein. Therefore, when there is an error that cannot be removed from certain data, the propagation error processing is performed here because it is understood how the error affects other data. As a result, the ERROR flag becomes a VERROR flag including a new propagation error. Even if the data has an error and is not important for image reproduction, the deframing circuit 94 also performs a process for modifying the image data to remove the error flag.

The video data is returned to the data before compression through the inverse quantization circuit 95 and the inverse compression circuit 96. Next, the data is returned to the original image space arrangement by the deshuffling / deblocking circuit 97. Only when the data is returned to the real image space, the image can be repaired based on the VERROR flag. That is, for example, a process is performed in which the image data of one frame before is always stored in the memory, and the image block in which the error occurred is substituted with the previous image data.

After the deshuffling, DY, DR,
Data is divided into three systems of DB and handled. The D / A converters 101 to 103 return the analog components to Y, RY, and BY. The clock at this time uses the output of the oscillation circuit 91 and the output obtained by dividing the output by the frequency divider 92. That Y _{is, 13.5MH Z, R-Y,} B-Y 6.7
Is a 5MH _Z or 3.375MH _Z.

The three signal components thus obtained are represented by Y /
C is synthesized in the C synthesizing circuit 104, and
In 5, the composite video signal is synthesized with the composite synchronization signal from the synchronization signal generation circuit 93, and output from the terminal 106 as a composite video signal. Eighth switching circuit SW8
ADATA output from is the 10th shown in FIG.
Is divided into audio data and audio accompanying data by the switching circuit SW10. Then, the audio data is supplied to the deframing circuit 107 together with the ERROR flag.

The deframing circuit 107 performs the inverse conversion of the framing on the recording side, and grasps the nature of the data packed therein. Therefore, when there is an error that cannot be removed from certain data, the propagation error processing is performed here because it is understood how the error affects other data. For example, at the time of 16-bit sampling, since one data is in units of 8 bits, one E
The RROR flag indicates that the AERR containing the new propagation error
It becomes an OR flag.

The audio data is returned to the original time axis by the next deshuffling circuit 108. At this time, the audio data is repaired based on the AERROR flag. That is, processing such as a previous value hold, which substitutes the sound immediately before the error, is performed. The error period is too long,
If the repair is not effective, the sound itself will be stopped by taking measures such as muting.

After such treatment, the D / A converter 1
The value is returned to the analog value by 09, and is output from the analog audio output terminal 110 while taking timing such as lip sync with the image data. Now, each data of VAUX and AAUX separated by the ninth switching circuit SW9 and the tenth switching circuit SW10 is
IC98 for VAUX and IC111 for AAUX respectively
Performs preprocessing such as majority processing while referring to the error flag.

The ID data SID and the pack data SDATA of the SUBCODE area output from the eighth switching circuit SW8 are stored in the SUBCODE IC11.
2, and also performs preprocessing such as majority processing while referring to the error flag. The data on which these pre-processes have been performed are then provided to the signal processing microcomputer 100 to perform a final reading operation. Errors that could not be removed in the pre-processing are respectively VAUXE
The signals are given to the signal processing microcomputer 100 as R, SUBER, and AAUXER.

Here, the SUBCODE IC 112 is the AP
3, and the APT are extracted and passed to the mode processing microcomputer 82 via the signal processing microcomputer 100 for checking. The mode processing microcomputer 82 receives A from the ITI.
A based on PT and APT from SUBCODE
The value of PT is determined, and when the value is not “000”, an operation such as a warning process is performed. When AP3 = 000, normal operation is performed. When the value is other than that, a warning operation such as a warning process is performed.

Here, supplementing the error processing of the pack data, each area has a main area and an optional area. In the case of the 525/60 system, the same data is written ten times in the main area. Therefore, even if some of them have errors, the ERROR flag there is no longer an error because they can be supplementarily reproduced with other data. However, SUBCODE
For optional areas other than, the data is written once, so the error remains VAUXER, AAUXER
Will remain as. The signal processing microcomputer 100 further performs a propagation error process, a data repair process, and the like, by analogy with the context of each data pack. The result of the determination is given to the mode processing microcomputer 82, and is used as a material for determining the behavior of the entire set.

Next, a circuit for reproducing the pack data in the VAUX IC 98 and the signal processing microcomputer 100 will be described by taking VAUX as an example. Here, a description will be given of a configuration example using a simple processing method in which an error is not written to a memory in the case of an error, instead of a majority decision process as preprocessing. FIG.
8 shows a circuit example of the VAUX IC 98. First, the VAUX pack data coming from the switching circuit SW9 is written into the nMAIN =
By switching the switch 141 at the timing of “L”, the data is distributed to the memory 145 for the main area and the FIFO 148 for the optional area.

The pack data in the main area is read by the pack header detection circuit 143 and the switch 144 is switched. Then, data is written to the main area memory only when the error is not found. This memory has a 9-bit configuration, and the shaded portions in the figure are bits for storing error flags. As an initial setting of the main area memory, all the contents are set to all 1 (= no information) for each video frame. And if it is ERROR, do nothing, ERROR
If it is not R, the data is written and 0 is written in the error flag. Since the same pack has been written 10 or 12 times per frame in the main area, an error flag of 1 at the end of one video frame is finally recognized as an error.

Since the optional area is basically written once, the ERROR flag is written as it is to the optional area FIFO 148 together with the data. These are sent to the signal processing microcomputer 100 via the switches 146 and 147 which are switched by the read-side timing controller 149. The signal processing microcomputer 100 analyzes the received pack data and the error flag.
The processing operation in the signal processing microcomputer 100 will be described with reference to FIG. In this figure, pack data (VAUXDT) sent from the VAUX IC 98 is sorted by the pack header identification circuit 150 and stored in the memory 151. This does not particularly distinguish between the main area and the optional area.

For packs in the main area, VAU
As in the case of the IC 98 for X, when the error flag “1” is set in VAUXER, the writing process is not performed. Thus, repair can be performed with a value at least one video frame before. Since the content of the main area is considered to have a very strong correlation with the value one video frame before, there is no particular problem if this processing is substituted.

On the other hand, in the case of a pack in the optional area, since it is considered that there is no correlation with the value one video frame before, an error propagation process is performed for each pack.
This method is basically performed by changing the “package without information” in which all data are FFh if there is an error in the 5-byte fixed-length pack data. . For example, in the case of a “Teletext” pack in which Teletext data is stored,
Due to the relationship that the packs continue, even if there is an error in the pack header between them, it can be easily replaced with a Telext pack header. Even if there is an error in the data portion, if there is no error in the pack header, the pack is not changed to the "pack without information".
This will restore the Teletext data,
Since it is left to the parity check of the ext decoder, the data is kept as it is even if an error is found.

That is, in the digital VTR of this embodiment, although not shown in the reproduction circuit of FIG. 17, the data amount is large like text data, Teletext data, etc. The characteristic pack data is passed from the signal processing microcomputer 100 to a dedicated data processing circuit, thereby performing more efficient error correction and reducing the load on the mode processing microcomputer 82.

An error flag does not already exist in the data prepared by the processing in the signal processing microcomputer 100 as described above. These are converted into serial data by the P / S conversion circuit 152 and sent to the mode processing microcomputer 82 according to the communication protocol between the microcomputers. Where S / P
The data is converted back to parallel data by the conversion circuit 153, and the packed data decomposition analysis is performed.

Here, the circuits 150 and 155 and the switch 154 are constituted by a microcomputer program, the memory 151 is a memory inside the microcomputer, and the circuits 152 and 153 are serial I / Os inside the microcomputer. In the disassembly and analysis of the pack data in the mode processing microcomputer 82, the pack data is analyzed based on the determined pack header, and various control information and display information obtained as an analysis result are transmitted to respective control circuits, display circuits, and the like. Supply to The switching control circuit 3 shown in FIG.
01, the blue-back signal generation circuit 302, and the character display control circuit 303 R. This is for executing child lock control based on information, and details of the operation will be described later.

The outline of the digital VTR according to the present embodiment has been mainly described for the case of the 525/60 system. However, the digital VTR according to the present embodiment is not limited to this system and employs another SD (Standard Density) system. 625/50 system and HD (High De
1125/60 system and 1
It is immediately applicable to 250/50 systems.

2-2. P. R. Control Based on Information Next, in the digital VTR described above, the P.V.
R. An operation when recording and reproducing a television signal into which information is inserted will be described.

In the present digital VTR, the P.P. signal is recorded on the 21st line of the second field of the television signal to be recorded. R. When the information has been inserted, the P.P. information is inserted using the CLOSED CAPTION pack shown in [3] of FIG. R. Since the information is automatically recorded in the VAUX main area, the original closed caption signal and EDS signal are restored to the VTR reproduction system based on the reproduced data in the closed caption pack. By providing a circuit and inserting the restored signal into the 21st line of the reproduced signal, the original television signal can be accurately extracted. Then, the extracted television signal is transmitted to the P.S. R. If the signal is input to a compatible receiver, the P.P. R. The child lock is automatically executed according to the information.

1) First Embodiment In this digital VTR, CLOSED
By using the CAPTION pack, the original E
Television signals with DS signals can be recovered, but besides such a method, VAUX SORC
E CONTROL PACK AND AAUX SOURCE
Utilizing the SS code stored in the CONTROL pack, the P.P.
R. It is also possible to execute a child lock according to the information. An embodiment in this case will be described below.

The present digital VTR is compatible with the P. R. In order to enable child lock according to the information, P.P. R. If this information is included, this P.P. R. Each SOURC based on the information
The configuration is such that the value of the SS code stored in the E CONTROL pack is determined. The determination of the value of the SS code is specifically performed in the mode processing microcomputer that generates the pack, and the determination flow is shown in FIG. That is, as shown in this figure, the above-mentioned P.P.
R. An EDS signal representing information exists and the P.S.
R. Only when the value of the rating code in the information is between “111” and “TH”, the SS code “10” indicating that the child should be locked is generated.

Here, the value "TH" is set to the value of RATING for executing child lock, as in the case of the above-mentioned receiver.
This is a value that the user has previously input to the digital VTR as a threshold value for setting the range of the code value, and “01” in the table shown in [2] of FIG.
Any value from “0” to “110” can be set. This allows the user to automatically execute child lock when recording / reproducing a program given an evaluation value equal to or more than a predetermined value with this digital VTR. For example, if the value of “TH” is “10”
If the digital VTR is set as “0”, “r”
2, r1, r0 ”is in the range of“ 110 ”to“ 100 ”. R. In the recording of a television signal having information, the value of the SS code in each of the above packs is "1".
0, indicating that the child should be locked (in this embodiment, the value of “TH” is “00”).
If "1" is set, it is possible to prevent young people from viewing even a general program.)

The child lock operation based on the SS code is mainly performed by the mode processing microcomputer 82, the switching control circuit 301, the switches SW11 to SW14, and the generation of the blue-back signal in the reproducing circuit shown in FIGS. Circuit 302, character display control circuit 30
3, and is executed by the addition circuit 305. That is, the mode processing microcomputer 82 performs the VAUX SOU included in the pack data group supplied from the signal processing microcomputer 100.
RCE CONTROL PACK AND AAUX SOURC
When the SS code of the E CONTROL pack is decoded and the value is in the range of “110” to “TH”,
The above-mentioned SW11 to SW14 are controlled by the switching control circuit 301.
Is switched, the child lock is executed, and a predetermined display is performed on the reproduction screen by the character display control circuit 303.

The child lock state can be released by the user by inputting the same key code as the key code registered in the digital VTR in advance, as in the case of the above-mentioned receiver. In this case, And the control circuit 30
The control of 1 and 303 is performed by the mode processing microcomputer.

The operation flow of the mode processing microcomputer relating to the execution and release of the above child lock is shown in FIG.
This will be described below. In this figure, when the user turns on the reproduction button, first, in step ST1, SW11 to SW14 in FIG. 17 are connected to the terminal a side, and a reproduction image signal and a reproduction audio signal are output. next,
In step ST2, SOURCE CONTROL
The value of the SS code in the pack is checked. If this value is not "10", steps ST1 and ST2
Is repeated, and the operation of outputting the reproduced image signal and the reproduced audio signal is continued.

If the value of the SS code is "10", it is checked whether or not a key has been registered in the digital VTR. If the key has been registered, the user sets a key code for releasing the child lock. It is checked whether the input has been made (step ST5). When a key code is not input, SW11 to SW14 are connected to the terminal b and a blue-back signal from the blue-back signal generation circuit 302 is output from the VTR to display a blue-back screen and to output a reproduced audio signal. The output is cut off, and a character signal indicating the message "Child lock program. To view, enter a key code."
3, which is superimposed on the output signal and displayed on the screen (step ST6), and then returns to step ST2. As a result, the child lock is executed until the key code is input or the playback position on the tape moves to the non-child lock portion.

If the key code is input and the result of determination in step ST5 is YES, it is checked whether or not the input key code matches the registered key code, and if so, the flow returns to step ST1. Step ST1,
Repeat the loop consisting of 2, 3, 5, and 7
The display of the reproduced image and the reproduction of the sound are executed by holding the SW 14 on the terminal a side. If the input key code does not match the registered key code, SW11 to SW14 are connected to the terminal b to display the blue-back screen and cut off the reproduced audio signal, and furthermore, the message "Key code input is incorrect. A character signal representing "Please enter a key code" is generated from the character display control circuit 303, this message is displayed on the screen, and the process returns to step ST2.

If the key is not registered in the judgment of step ST3, when the SW11 to SW14 are connected to the terminal b and a blue screen is displayed, the reproduced audio signal is cut off.
Further, a character signal representing the message "Child lock program. The key has not been registered. Please register the key." Is generated from the character display control circuit 303, this message is displayed on the screen, and the process returns to step ST2. According to the above flow, in the reproduction operation of the child lock portion where the value of the SS code is “10”, the key is registered and the reproduced image is displayed on the screen only when a correct key code is input. And the sound is reproduced. When the playback position on the tape shifts to the non-child lock portion during the child lock operation, the determination result in step ST2 becomes NO, and the process returns to step ST1, where the display of the playback image and the playback of the sound are performed. .

In the flow described above, no key has been registered in the child lock portion on the tape, or if the key code has not been entered, the blue back until the tape playback position moves to the non-child lock portion. An operation of displaying a screen and shutting off a voice is performed. Alternatively, when a child lock operation is started, when a key is not registered or a key code is not input within a predetermined time, a tape may be used. May be fast-forwarded to the non-child lock portion to restart the reproduction operation.
The operation flow in this case will be described with reference to FIG.

In this figure, if the key is not registered in the check in step ST69, the same operation as step ST4 in FIG. 21 is performed in step ST70, and the time until the key is registered is measured. Then, it is checked whether or not the timer (1) is turned on (step ST71). If it is not turned on, the timer (1) is turned on, and it is checked whether or not the timer operation of this timer has expired (step S).
T73). If the timing operation has not expired, step ST
Return to 68. Here, the time counted by the timer (1) is set to 3 minutes, and if the user does not register the key within 3 minutes, the steps ST68, 69, 70, and 7 are performed for 3 minutes.
After repeating the loop consisting of 1, 73, step ST
Then, the flow goes to 74 to reset the timer (1).

Next, the tape is fast-forwarded to the non-child lock portion while performing the blue back display (step S).
Execution of a loop consisting of T75 and step ST76).
When the non-child lock portion is reached by the fast-forward operation, the tape is rewound at a low speed to the child lock portion while performing a blue-back display (execution of a loop including steps ST77 and ST78). When the child lock portion is reached, the tape is advanced by one track to move to the head position of the non-child lock portion, and the process returns to step ST67 to resume image reproduction and audio reproduction.

If the key has been registered in the judgment of step ST69, after resetting the timer (1), the operations of step ST82 or steps ST87 and ST88 are executed similarly to the flow of FIG. . Thereafter, it is checked whether the timer (2) for measuring the time until a correct key code is input is turned on, and the same operation as that of the timer (1) is performed in steps ST84 and ST85. It returns to step ST68. The time counted by the timer (2) is also set to 3 minutes. If a correct key code is not input within this time, the timer is reset and the process proceeds to step ST75, where the tape is fast-forwarded to the non-child lock portion. .

In the reproduction of a soft tape, by setting the value of the SS code stored in the AAUX SOURCE CONTROL pack and the VAUX SOURCE CONTROL pack in the portion where the child lock is to be executed on the tape to "10", A similar child lock operation can be performed.

2) Second Embodiment In the digital VTR described above, the P.V. R. The SS code is generated based on the information, and this code is stored in each of the SOURCE CONTROL packs.
The above-mentioned RATING in the RCE CONTROL pack
A configuration in which the code is recorded as it is may be adopted. In the above-described digital VTR, key information for releasing the child lock is configured to be registered in advance in the digital VTR, but the key information is configured to be recorded on a tape. When the user inputs a key code for releasing the child lock, it is determined whether or not the input key code matches the key recorded on the tape to determine whether to release the child lock. It may be configured as follows.
Next, the digital VT when such a configuration is adopted
R will be described.

AAUX in such a digital VTR
SOURCE CONTROL PACK AND VAUX
FIG. 23 shows the structure of the SOURCE CONTROL pack. In this figure, a 3-bit RATI in a pack
The P.S. of the EDS signal included in the recording signal as the NG code. R. The RATING code in the information is recorded as it is. Note that the recording signal has a R. When there is no information, “111” indicating no information is stored.

As a method for recording keys on a tape, a key pack shown in [4] of FIG. 9 is used. By using this key pack, a user can record a key code expressed by a hexadecimal number or a decimal number of up to eight digits set arbitrarily in an optional area on a tape. In this digital VTR, an EDS signal including a RATING code is inserted into a recording signal input to the digital VTR, and the value of the RATING code is from "010" to "010".
When it is within the range of "110", a key pack storing a key code previously input to the digital VTR by the user is automatically generated by the mode processing microcomputer and programmed to be recorded in the optional area. .

Next, the digital V thus constructed is
The child lock operation at the time of reproducing the TR will be described with reference to FIG. 24 (note that the basic configuration of the circuit block of the recording / reproducing system of the digital VTR in this case is shown in FIG.
5, and FIGS. 16 and 17), and will be described with reference to these figures. In the flow shown in FIG. 24, step S in the flow shown in FIG.
Steps ST91 to ST93 are provided instead of T2. Here, step ST91 and step ST91
"TH" in 93 is a threshold value indicating the range of the RATING code to be child-locked similarly to "TH" in FIG. 20, and is set in advance to the digital VTR by the user. Then, the RATING in each of the reproduced SOURCE CONTROL packs
If the code value is affirmative in the judgment of step ST91, then in the next step ST92, the message "Character's attention is needed when a young person watches this program" from character display control circuit 303 in FIG. Required. "
This message is superimposed on the playback screen.

If the RATING code value in the reproduced pack is within the child lock range set by the user, the decision result in the step ST93 is YES, and in the next step ST94, it is checked whether or not the key pack is reproduced. You. This step ST94
Is provided mainly in consideration of the case of reproducing a soft tape. In a tape recording operation by a normal user, the RA included in the recording signal as described above is used.
When the value of the TING code is in the range of "010" to "110", the key pack is automatically recorded on the tape, so that in a normal tape reproducing operation, the determination result in step ST94 is YES. Becomes Then, in the next step ST96, it is checked whether or not the user has input a key code for releasing the child lock. The flow after this step is the same as in the case of FIG.

In the case of a soft tape, there are two types of tapes: a key pack recorded in advance on a tape by a soft tape maker, and a key pack recorded by a user. For the former tape, the result of determination in step ST94 is YE
At S, the child lock can be released by the user inputting a key code notified in advance by the soft tape maker. For the latter tape, the first judgment result in step ST94 is N
The result is O, and a message stating "This tape is child locked. Please record the key code on the tape when watching" is displayed on the screen in step ST95. Thereby, the user rewinds the tape, records the key code freely set by himself in the SUBCODE area of the tape by post-strike using the key pack, starts the tape reproducing operation again, and releases the child lock. Execute the key code input operation.

[0158]

As described above, according to the present invention, a control code based on a program evaluation code inserted during a vertical blanking period in a television signal, for example, a P.A. R. Information is recorded as additional data in the additional data recording area of the recording medium, and a child lock can be automatically performed based on the additional data during reproduction. The child lock state can be forcibly released by inputting a key code.

In the digital VTR of this embodiment, as described above, the P.V. R. In recording and reproducing a broadcast signal having information, R. The child lock can be automatically executed based on the information. In addition to this, for example, a user can independently perform a child lock only on a desired tape portion on a tape recorded using a camcorder. It also has a configuration. Hereinafter, this configuration will be described.

The above-mentioned user-specific child lock is executed by recording an event for the child lock on the MIC of the cassette tape. When child lock is performed on both the image and the sound in a predetermined range on the tape, an event for realizing the child lock is performed as shown in (1) of FIG.
When a child lock is performed only on audio using a ZONE event including an AG pack, a ZONE END pack, and a key pack, the AAUX START pack and the AAUX EN as shown in (2) of FIG.
When the child lock is performed only on the image using the AAUX event including the D pack and the key pack, as shown in (3) of FIG.
A VAUX event consisting of a T pack, a VAUX END pack, and a key pack is used.

Next, these events will be described. (1) ZONE event In this event, TA which is an event header
TA stored in the G pack (see [1] in FIG. 27)
When the value of the G ID is “0100”, a ZONE PLAY is designated by this event.
The absolute track number stored in the pack indicates the start of the zone on the tape to which this event applies,
Also, ZONE END pack (see [2] in FIG. 27)
Indicates the end position of the zone. The TAG CONT code stored in the ZONE END pack indicates an operation to be performed in this zone, and is defined as follows.

That is, the upper two bits of the TAG CONT code are codes specifying the number of times of execution of the operation mode defined by the lower six bits, and the value is “0”.
When "1", the operation mode defined by the lower 6 bits is executed only once, and when "10", the operation mode defined by the lower 6 bits is repeated twice. When the value is "11", the operation mode defined by the lower 6 bits is repeated endlessly until some command is input.

Next, the operation mode defined by the lower 6 bits will be described. Of the lower 6 bits, the upper 3 bits are a code for designating the operation mode when the tape is running in the forward direction. Is defined. 000 = No Operation 001 = Play 010 = Slow 011 = Cue 100 = FF 101 = Strobe 100 to 111 = Reserved The lower three bits are a code for designating an operation mode when the tape is running in the reverse direction. Is defined as 000 = No Operation 001 = Reverse Play 010 = Reverse Slow 011 = Review 100 = Rewind 101 = Reverse Strobe 100-111 = Reserved

When this ZONE event is used as a child lock event, the TAG
The value of the CONT code is set to "01001000" which specifies one reproduction operation in the forward direction. The mode processing microcomputer is programmed so as to recognize that the execution of the child lock is instructed in the zone designated by this event, because the key pack is further added to the ZONE END pack. You.

(2) AAUX event The AAUX event used for the child lock is, as shown in FIG. 26 (2), the AAU of FIG. 27 [3].
The X START pack is used as an event header, and an AAUX END pack and a key pack shown in [4] of FIG. 27 are added to the event header. Here, AAUX STAR
The absolute track number stored in the T pack indicates the start position of the zone to which this event is applied with respect to audio, and the absolute track number stored in the AAUX END pack indicates the end position of the zone. Then, the mode processing microcomputer is programmed so as to recognize that the execution of the child lock is instructed for the voice in the zone specified by the event, when the event includes the key pack.

(3) VAUX Event The VAUX event used for the child lock is, as shown in (3) of FIG. 26, the VAU event of [1] in FIG.
The X START pack is used as an event header, and a VAUX END pack and a key pack shown in [2] of FIG. 28 are added to the event header. By using this event, it is possible to specify the execution of the child lock on the image with the same definition as in the case of the AAUX event.

A specific procedure for actually executing the child lock by using the above-described event is performed as follows. First, the user inputs an event recording command for executing the child lock to the mode processing microcomputer, and then specifies the start position and the end position of the range on the tape where the child lock is to be executed while watching the tape playback screen. Here, the mode processing microcomputer determines whether the child lock execution target from the user is both the image and the sound, only the sound, or only the image, and determines the type of the event. The absolute track numbers of the playback tracks at the start position and the end position are read and stored in the event header pack and subsequent packs, and a key pack storing a key code previously input by the user is generated. Is recorded in an optional area of the MIC via the MIC microcomputer.

When the tape is reproduced, the mode processing microcomputer executes the child lock according to the flow shown in FIG. 29 based on the event stored in the MIC of the tape cassette. This flow will be described. In this figure, a flow including steps ST13 to ST19 represents a flow relating to a child lock operation using a ZONE event, and a flow including steps ST20 to ST26 relates to a child lock operation using a VAUX event. Represents a flow,
The flow composed of steps ST27 to ST33 represents a flow relating to the child lock operation using the AAUX event.

First, the flow relating to the ZONE event will be described. When a key pack exists in this event (step ST14), the currently reproduced track is set in the child lock range specified by the ZONE event. Is determined (step ST15). If the determination result is YES, it is checked whether a key code for releasing the child lock is input by the user (step ST16). If not entered, step ST
At 17, a blue screen display, voice cutoff, and key input instruction to the user are performed, and the process returns to step ST15. When the key code is input, it is checked whether or not the key code matches the key stored in the key pack. If the key code matches, the process returns to step ST12 to display the reproduced image and reproduce the sound. If they do not match, in step ST19, a blue back display, voice cutoff, and a key re-input to the user are instructed, and then step ST1 is performed.
Return to 5.

The same operation is performed in the flow relating to the VAUX event and the AAUX event. However, unlike the case of the ZONE event, the steps ST24 and S24 are performed according to whether the child lock is performed only on the image or the sound only.
The only difference is the switching control operation of SW11 to SW14 in T26, step ST31 and step ST33. If each event exists in the MIC but does not include a key pack, the process proceeds to step ST1.
A loop consisting of 2, 13, 14, 20, 21, 27, 28 is repeatedly executed to display a reproduced image and reproduce sound.

In the child lock operation based on these events, the start position at which the child lock is executed can be known in advance from the event data in the MIC. When the user approaches, the user may be notified in advance that the child lock position has been approached, and a warning may be displayed to execute the key code input. Next, an embodiment in which such a warning display is performed will be described. FIGS. 30 to 32 show the operation flow of this embodiment. In the flow shown in FIG. 29, a flow composed of steps ST15 to ST19, a flow composed of steps ST22 to ST26, and a flow composed of steps ST29 to ST29 are shown. Instead of the flow of step ST33, a flow of steps ST35 to ST56 shown in FIG.
32, and the flow of step ST15 shown in FIG.
The above object is achieved by executing the flow including Step 3 to Step ST174.

Here, the flow shown in FIG. 30 will be described first. If it is confirmed in step ST14 that the key pack exists in the event, the child lock start position (CL start) in which the current playback position on the tape is stored in the event header is determined in steps ST35 and ST36. It is checked whether the position is within 90 seconds from (track number) and before the start position (note that the difference of 27000 between the track numbers is 90 seconds in terms of time). Then, when it is confirmed that the key code is within the range, it is checked whether a key code has already been input by the user (step ST44). When no key code has been input, the message "soon" is displayed in the character display control circuit 303 in FIG. Child lock part.
Please enter the key code. Is generated and displayed on the screen (step ST45).
Next, the 3-minute timer is set to step ST46 and step S46.
After turning on according to the flow of T47, the process returns to step ST12 of FIG.

When the playback position on the tape reaches the child lock start position, it is checked through step ST36 and step ST37 whether or not a key code has been entered in step ST38. If so, it is checked in step ST39 whether the key code is correct. If the key code is incorrect, a blue screen display and voice cutoff are performed in step ST40 to instruct the user to re-enter the key code. At this point the 3 minute timer is set to O
If it is not N, after turning it on, the loop consisting of steps ST39 to ST43 is repeated until the timer expires or a correct key code is input.

If the correct key code has not been input before the timer expires, the timer is reset (step ST52), and the tape is rapidly advanced until the child lock period has passed (steps ST53 and ST54). Then, after rewinding at a low speed to the end position of the child lock period (steps ST55 and ST56), the process returns to step ST12 in FIG. 29 to execute the image display and the sound reproduction. When the determination result in step ST38 is NO, the timer is counted after the blue back display, the voice cutoff, and the key input instruction to the user are performed. If the key input is not performed before the time expires, the process proceeds to steps ST52 to ST52. Step ST5
Execute 6 to fast-forward to the non-child lock portion.
31 and 32, the same operation as described above is performed. However, based on the difference in the child lock target, steps ST143 and ST
139, the switching control operation of SW11 to SW14 in step ST161 and step ST171 is different only.

As described above, the digital V for recording the key pack
In the TR, the configuration in which the user independently executes the child lock on the recorded tape has been described. However, as described in FIG. 21, the key code is configured to be recorded in the storage device of the digital VTR main body. In a digital VTR, it is possible to independently perform child lock on a recorded tape.
However, in this case, instead of the above key pack, VAU
X SOURCE CONTROL pack, or
AAUX SOURCE CONTROL Pack
ZONE event, AAUX event, VAUX in C
It is configured to be recorded in addition to the event. And
When the value of the SS code in each SOURCE CONTROL pack added to these events is "10", the mode processing microcomputer determines that the event is related to a child lock, and executes the reproduction process. For reference, the configuration of each event in this case is shown in FIG.
Shown in Of course, it is also possible to employ a SOURCE CONTROL pack that records a RATING code. In this case, the value of the RATING code may be set and recorded in the range of “110” to “TH”.

While the various embodiments have been described above,
Various other configuration changes are possible. For example, when a child lock is to be independently performed on a recorded tape, and when this tape is a tape of a cassette on which no MIC is mounted, the SUBCODE area of the tape on which the child lock is to be performed is added to the SS. After recording is performed with the SOURCE CONTROL pack having a code value of “10” as an optional pack, and the mode processing microcomputer performs SOURCE playback from the VAUX main area or the AAUX main area.
By programming so as to preferentially use the SOURCE CONTROL pack reproduced from the SUBCODE area over the CONTROL pack,
It is possible to execute a desired child lock. Also in this case, it is of course possible to employ a CONTROL CONTROL pack that records a RATING code.

Further, the control state of the screen when the child lock is executed is not limited to the blue screen as described above, and an external color may be displayed. And may take various methods. As one example, for example, the image may be scrambled. As a specific method, the descramble circuit provided in the reproduction system of the digital VTR may not be operated. The audio signal may be scrambled instead of blocking the signal path. Further, at the time of child lock, the tape running may be stopped immediately or the state may be switched to a pause state.

[0178]

According to the present invention, the P.D. R. Information is recorded on the tape as accompanying data, and a child lock can be automatically performed based on the accompanying data during reproduction. The child lock state can be forcibly released by inputting a key code.

[Brief description of the drawings]

FIG. 1. AAUX SOURCE pack and AAUX
It is a figure explaining the structure of a SOURCE CONTROL pack.

FIG. 2 AAUX REC DATE pack, AAUX
REC TIME pack, AAUX REC TIM
E BINARY GROUP PACK, AAUX CL
OSED CAPTION pack and MAKE C
It is a figure explaining the structure of an ODE pack.

FIG. 3 is a diagram illustrating the structure of a VAUX area for one track.

FIG. 4 is a diagram illustrating a pack structure of a VAUX area for one frame.

FIG. 5: VAUX SOURCE pack, VAUX S
OUR CONTROL PACK AND CLOSED
It is a figure explaining the structure of a CAPTION pack.

FIG. 6 is a diagram illustrating multiplex writing of pack data in a SUBCODE area in a digital VTR of a 525/60 system.

FIG. 7 is a diagram illustrating multiplex writing of pack data in a SUBCODE area in a digital VTR of a 625/50 system.

FIG. 8 is a diagram illustrating a memory map of an MIC.

FIG. 9: CASSETTE ID pack, TAPE L
ENGTH pack, TITLEEND pack, and KE
It is a figure explaining the structure of a Y pack.

FIG. 10 is a diagram showing a recording circuit of a digital VTR.

FIG. 11 is a diagram illustrating generation of pack data in a recording circuit of a digital VTR.

FIG. 12 is a diagram illustrating a main area on a recording track.

FIG. 13 is a diagram illustrating generation of VAUX pack data in the mode processing microcomputer.

FIG. 14 is a diagram illustrating generation of AAUX pack data in the mode processing microcomputer.

FIG. 15 is a diagram illustrating generation of pack data in an MIC microcomputer.

FIG. 16 is a diagram showing a configuration of a part of a reproduction circuit of the digital VTR.

FIG. 17 is a diagram showing a configuration of another part of the reproduction circuit of the digital VTR.

FIG. 18 is a diagram for explaining processing of reproduced pack data in a VAUX IC.

FIG. 19 is a diagram for explaining processing of reproduced pack data in the signal processing microcomputer.

FIG. 20 is a diagram illustrating generation of an SS code in the mode processing microcomputer.

FIG. 21 is a diagram showing an operation flow of an embodiment in which child lock control is performed using an SS code in a digital VTR.

FIG. 22 is a diagram showing an operation flow of another embodiment for performing child lock control using an SS code in a digital VTR.

FIG. 23: AAUX S for recording a rating code
OUR CONTROL PACK AND VAUX SO
It is a figure explaining the structure of a URRE CONTROL pack.

FIG. 24 is a diagram showing an operation flow of an embodiment in which child lock control is performed using a rating code in a digital VTR.

FIG. 25 is a diagram showing an operation flow of another embodiment in which child lock control is performed in a digital VTR using a rating code.

FIG. 26 is a diagram illustrating a configuration of an event when a child lock is performed on a desired portion on a recorded tape.

FIG. 27: TAG pack, ZONE END pack, A
It is a figure explaining the structure of AUX START pack and AAUX END pack.

FIG. 28: VAUX START pack, VAUX E
It is a figure explaining the structure of an ND pack.

FIG. 29 is a diagram illustrating an operation flow of an embodiment in which child lock control is performed using an event.

FIG. 30 is a diagram showing an operation flow relating to a ZONE event of another embodiment for performing child lock control using an event.

FIG. 31 is a diagram showing an operation flow relating to a VAUX event of another embodiment in which child lock control is performed using an event.

FIG. 32 is a diagram showing an operation flow regarding an AAUX event of another embodiment in which child lock control is performed using an event.

FIG. 33 is a diagram illustrating a configuration in a case where child lock control is performed at a desired portion on a tape by an event using a SOURCE CONTROL pack.

FIG. 34 is a diagram illustrating a format of an EDS signal.

FIG. 35 is a diagram illustrating a transmission state of an EDS signal.

FIG. R. FIG. 4 is a diagram illustrating a data configuration of information.

FIG. R. FIG. 2 is a diagram illustrating a circuit configuration of a compatible receiver.

FIG. 38 is a view showing an operation flow of child lock control in the image receiver.

FIG. 39 is a diagram showing a recording format of one track of a digital VTR.

FIG. 40 shows a pre-SYNC block and a post-SYNC
It is a figure showing the structure of a block.

FIG. 41 is a diagram illustrating the framing format of AUDIO and the structure of one SYNC block.

FIG. 42 is a diagram illustrating blocking of image data for one frame.

FIG. 43 is a diagram showing a VIDEO framing format to which an error correction code is added.

FIG. 44 is a diagram illustrating a configuration of a VIDEO buffering unit and one SYNC block.

FIG. 45 is a diagram illustrating the structure of a SUBCODE area for one track.

FIG. 46 is a diagram illustrating the structure of an ID part of a SYNC block in an AUDIO area and a VIDEO area.

FIG. 47 is a diagram illustrating the structure of an ID part of a SYNC block in a SUBCODE area.

FIG. 48 is a diagram showing a basic structure of a pack.

FIG. 49 is a diagram illustrating grouping of packs by large items.

FIG. 50 is a diagram illustrating the structure of an AAUX area for one frame.

[Explanation of symbols]

55, 100: signal processing microcomputer; 67, 82: mode processing microcomputer; 68, 84: MIC 85: mechanical control microcomputer; 301: switching control circuit;
302: blue back signal generation circuit, 303: character display control circuit, 305: addition circuit,

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/76-5/956 G11B 5/09

Claims (5)

(57) [Claims] 1. A digital video / audio signal recording / reproducing apparatus which encodes a video signal and an audio signal constituting a television signal and records / reproduces the recording / reproducing on a recording medium. An image data recording circuit for recording in an image data recording area; (2) an audio data recording circuit for recording an encoded output of an audio signal in an audio data recording area of a recording medium; and (3) a vertical blanking period of a television signal. Inserted in
And accompanying data recording circuit for recording data associated with the input to the associated data recording area of the recording medium, (4) within the vertical blanking period in the television signal
A control code recording circuit for recording a control code based on the inserted program evaluation code in the ancillary data recording area; and (5) processing the image data or audio data reproduced from the recording medium from the ancillary data recording area. A digital video / audio signal recording / reproducing device, comprising: a blocking circuit for blocking based on a reproduced control code. 2. The digital video / audio signal recording / reproducing apparatus according to claim 1, wherein a component in the program evaluation code is directly used as the control code. 3. A method according to claim 1, further comprising: a key code input unit; and a blocking circuit control unit, wherein the blocking circuit control unit determines whether a value of the key code input by the key code input unit matches a predetermined code value. 3. The digital video / audio signal recording / reproducing apparatus according to claim 1, wherein the operation of the blocking circuit is forcibly stopped. 4. The digital video / audio signal recording / reproducing apparatus according to claim 3, wherein the predetermined code value is stored in the digital video / audio signal recording / reproducing apparatus. 5. The digital video / audio signal recording / reproducing apparatus according to claim 3, wherein the predetermined code value is recorded in an associated data recording area of a recording medium.