JP3310096B2 - Integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, and more particularly, to a system for performing a scan operation in parallel in an integrated circuit device having a structure for facilitating test by an internal scan circuit and a boundary scan circuit. The present invention relates to a circuit structure for a terminal.

[0002]

2. Description of the Related Art With the recent development of integrated circuit technology, L
SIs are becoming larger and more complex. Accordingly, LSI testing has become extremely difficult.

When designing an internal circuit of an LSI in response to such a situation, it has become essential to design a circuit in consideration of testability such as a scanning method.

On the other hand, with the progress of surface mounting technology in recent years,
The surface mounting density of printed circuit boards has been increasing.
As a result, the in-circuit test, which has been widely used as a test method for a printed circuit board, cannot be applied. Therefore, a test method called “JTAG boundary scan” has been standardized by IEEE in order to facilitate testing of a printed circuit board.

[0005] By the way, this standard, May 2, 1990
Established on 1st, IEEE Standard 1149.1,
“IEEE Standard Test Accesses
sPort and Boundary-Scan A
rtitle ".

This standard points out that it is necessary to provide a boundary scan mechanism inside an LSI for a printed circuit board test.

FIG. 6 is a schematic configuration diagram of a general integrated circuit device incorporating a test facilitation circuit configured from such a viewpoint, and shows the configurations of a test control circuit and a circuit under test in an LSI. is there. As shown in the drawing, the integrated circuit device 18 includes a circuit block under test 19-1 to 19-4 to be tested and a scan register 1- 1 constituting a scan path in the circuit blocks 19-1 to 19-4 to be tested. 1 to 1-4. Further, the boundary scan register 2 is provided in the integrated circuit device 18.
Are provided for each terminal. Note that the test control circuit 2
0 controls the operation of the scan registers 1-1 to 1-4 and the boundary scan register 2 to test the circuit blocks under test 19-1 to 19-4. For this reason, the test control circuit 20 supplies the test clock signal T
CK, test mode signal TMS, scan-in signal TD
I is supplied, and test output data TDO is output from test control circuit 20.

In the configuration described above, the scan registers 1-1 to 1-4 store the test data transmitted via the test control circuit 20 in the circuit block 19 under test.
-1 to 19-4, and each circuit block under test 19
The test results generated inside -1 to 19-4 are output to the outside via the test control circuit 20. The boundary scan register 2 includes scan registers 1-1 to 1-4.
, Data which cannot be given to the circuit blocks under test 19-1 to 19-4.
1 to 19-4, or scan registers 1-1 to
It is used for observing an output that cannot be observed in 1-4, and is also used for a printed circuit board wiring test defined in IEEE1149.1.

FIG. 7 is a block diagram of a conventional circuit test apparatus, particularly showing a scan path portion in the configuration of FIG. In FIG. 7, a multiplexer 4 transmits a control signal from a selection signal input terminal 5 to select one of a plurality of scan paths including scan registers 1-1 to 1-4 and a boundary scan register 2. Work based on. The multiplexer 4 responds to the scan-in signal TDI given as serial data,
Test output data TDO is obtained as an operation result of any one of the scan paths of −1 to 1-4 and the boundary scan register 2.

In the configuration of FIGS. 6 and 7 described above, one of the scan paths of the scan registers 1-1 to 1-4 and the boundary scan register 2 selected by the test control circuit 20 of FIG. Only the scan path works. Then, the selected scan path operates according to the serial data input as the scan-in signal TDI, and the output signal thereof is selected by the multiplexer 4 based on the control signal from the selection signal input terminal 5, and the test output The data is output to the outside as data TDO.

The above configuration has an advantage that the number of terminals is small because the scan path can be accessed with only one scan-in signal TDI and one test output data TDO. In addition, each scan register 1-1 to 1-4
Since the length of the scan path is shorter than the method of connecting and configuring as a single scan path, there is also an advantage that the test time is shortened when a test is performed for each circuit block.

However, the number of scan paths is large for the scan registers 1-1 to 1-4 and the boundary scan register 2. Therefore, there is a problem that as each path becomes longer, it becomes difficult to perform a test in a practical time.

On the other hand, in order to shorten the test time, there is a method of operating each scan path in parallel.
When the input / output of the scan data is realized by the test dedicated terminal, there is a disadvantage that the number of terminals is increased. On the other hand, there is also a method in which this is also used as a system terminal. However, there is a problem that an additional circuit for this causes a delay overhead in input / output of the original system signal.

FIG. 8 shows a configuration of a boundary scan cell constituting the boundary scan register 2. In the figure, a multiplexer 21 selects and outputs an input signal IN given to an input terminal A and an input signal SI given to an input terminal B based on a shift mode signal SM. On the other hand, the D-type flip-flop 8 receives the output of the multiplexer 21 at the data input terminal D, receives the shift clock signal SCLK at the clock input terminal C, and sends out the output signal SO from the data output terminal Q. The update D-type flip-flop 9 receives a signal from a data output terminal Q of the D-type flip-flop 8 at a data input terminal D, receives an update clock signal UPCLK at a clock input terminal C, and further outputs data. A signal is output from terminal Q. The multiplexer 6 receives the input signal IN given to the input terminal A.
And one of the output signals from the data output terminal Q of the D-type flip-flop 9 supplied to the input terminal B, based on the test mode signal TM, and sends it out as the output signal OUT.

In the configuration described above, when operating in a normal mode, the test mode signal TM may be set to "0". Thereby, the data of the input signal IN can be output through the input terminal A of the multiplexer 6 as the output signal OUT. As a result, even when such a boundary scan cell is placed on the external terminal of the integrated circuit chip, the state of the external terminal can be prevented from being affected at all.

On the other hand, to output the boundary scan cell data as the output signal OUT, the test mode signal TM may be set to "1". Thus, the output from the data output terminal Q of the D-type flip-flop 9 that operates based on the update clock signal UPCLK applied to the input terminal B of the multiplexer 6 can be derived as the output signal OUT. That is, data from the boundary scan cell can be used as the output signal OUT instead of the data of the input signal IN.

Further, to observe the state of the input signal IN, the shift mode signal SM may be set to "0". As a result, the input signal IN is applied to the data input terminal D of the D-type flip-flop 8 through the input terminal A of the multiplexer 21, and the shift clock signal SCLK is further applied to the clock input terminal C of the D-type flip-flop 8. be able to. Thereby, the data of the input signal IN can be taken into the D-type flip-flop 8.

The setting and observation of data in the boundary scan cell are performed as follows. That is, by switching the input selection to the input terminal B side by the multiplexer 21, the data from another boundary scan cell is taken in from the input terminal B as the input signal SI. The output of the shift register stage composed of the D-type flip-flop 8 is connected as an output signal SO to another boundary scan cell to operate the shift register.

In the boundary scan cell shown in FIG. 8, the multiplexer 6 is inserted in the path from the input signal IN to the output signal OUT, which causes a delay in input and output during normal operation. That is, in order to share input / output of scan data with the system terminal, simply adding a simple additional circuit for sharing the terminal, for example, a circuit such as the multiplexer 6, causes further delay overhead.

[0020]

The conventional circuit test apparatus is configured to perform a scan operation while selecting a plurality of scan paths in an integrated circuit device having an internal scan and a boundary scan. There is a problem that the time required is long. Further, even if the test time is reduced by operating a plurality of scan paths in parallel, it is necessary to realize input / output of scan data by a dedicated terminal, so that the number of terminals increases. On the other hand, even if an attempt is made to share the system terminal and the test terminal, the additional circuit for the dual purpose has an overhead of delaying the system signal, which is a problem.

The present invention solves the above-mentioned problems of the prior art, and operates the internal scan circuit and the boundary scan circuit of the integrated circuit device in parallel, thereby shortening the test time and improving the test terminals. It is an object of the present invention to provide an integrated circuit device capable of minimizing the occurrence of a delay time during a normal operation with respect to a system terminal that is also used as a system terminal.

[0022]

To achieve the above object, a first integrated circuit device of the present invention comprises an internal circuit, a system output terminal, and a connection between the internal circuit and the system output terminal. A boundary scan circuit on the output side, and an internal scan circuit, wherein the boundary scan circuit includes a through path that directly passes an output signal from the internal circuit, a test path that incorporates a test circuit, and a test path that includes the test path. And a first output for selectively outputting either the first output of the internal scan circuit or the second output from the internal scan circuit.
A switching means, and a second switching means for selectively outputting one of the output from the first switching means and the output from the through path and applying the selected output to the system output terminal. is there.

According to a second integrated circuit device of the present invention, in the first integrated circuit device, the first switching unit is connected between the update data storage unit and the second switching unit in the test path. It is what was done.

According to a third integrated circuit device of the present invention, in the second integrated circuit device, the data storage means is a flip-flop, and the first and second switching means are multiplexers.

According to a fourth integrated circuit device of the present invention,
In the integrated circuit device, a system input terminal, an input-side boundary scan circuit connected between the system input terminal and the internal circuit, and a second input terminal connected between the system input terminal and the internal scan circuit. 3 switching means, wherein the third switching means is configured to selectively output either an input signal to the system input terminal or a scan-in signal and to apply the signal to the internal scan circuit. is there.

[0026]

The output from the internal scan circuit is applied to the input side of the first switching means in the boundary scan circuit on the output side. The first switching means selectively applies one of the input and the input from the test path to the input side of the second switching means. The second switching means selectively applies one of the input and the input from the through path to the system output terminal. In other words, while the output from the internal scan circuit can be output from the system output terminal, the output from the internal circuit passes through the through path and the delay is suppressed as much as possible via only one stage of the second switching means. It is given to the system output terminal.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a circuit test apparatus according to an embodiment of the present invention. As shown in the figure, the scan-in signal TDI is supplied to the input terminals of the boundary scan register 2 and the input terminals A of the multiplexers 3-1 to 3-n.
Is input to The scan-in signals PSI1 to PSIn are input to the input terminals B of the multiplexers 3-1 to 3-n. The multiplexers 3-1 to 3-n select and output one of the input signals of the input terminal A or the input terminal B in accordance with the control signal PM, and output the corresponding scan registers 1-1 to 1-1. -N as an input signal.
On the other hand, the output signals of the multiplexers 3-1 to 3-n are derived as scan-out signals PSO1 to PSOn and supplied to the multiplexer 4. Based on the control data from the selection signal input terminal 5, the multiplexer 4 outputs the scan-out signals PSO1 to PSOn output from the scan registers 1-1 to 1-n and the scan-out signal BSO output from the boundary scan register 2 based on the control data. Is selected and output as test output data TDO.

In the configuration described above, on the scan-in side of the scan registers 1-1 to 1-n,
By providing the multiplexers 3-1 to 3-n, the system terminal and the test terminal can be shared. Further, the scan registers 1-1 to 1-1 are controlled by the control signal PM.
−n can be determined whether to scan in parallel.

On the other hand, on the scan-out side of the scan registers 1-1 to 1-n, a multiplexer 4 is provided so that the scan-out signals PSO1 to PSOn
Is selectively output to the external terminal, thereby enabling the system terminal and the test terminal to be used together.

FIG. 4 is a block diagram showing a configuration in which an external input terminal of an LSI (not shown) is also used as a scan-in terminal. As shown in FIG.
A boundary scan cell 13 is arranged between the internal scan circuit 12 and the internal circuit 12. A buffer 14 is arranged between the external input terminal 11 and the boundary scan cell 13, and a buffer 15 is also arranged between the boundary scan cell 13 and the internal circuit 12. The boundary scan cell 13 has the same configuration as the boundary scan cell shown in FIG. Incidentally, the buffer 15 has a higher driving capability than the buffer 14 in order to drive the internal circuit 12.

Now, in the configuration of FIG.
Is supplied via the boundary scan cell 13, and therefore has no relation to the value supplied to the external input terminal 11. Therefore, the external input terminal 11 can be used as a scan-in dual-purpose terminal.

In the configuration shown in FIG. 4, for the dual use of scan-in, the input signal IN to the subsequent stage of the buffer 14, that is, the input signal IN to the boundary scan cell 13, is branched as the signal PSIi immediately before the boundary scan cell 13, and FIG.
May be connected to a corresponding one of the scan-in signals PSI1 to PSIn. Therefore, there is no need to modify the circuit such as the boundary scan cell 13.

On the other hand, in the case of double use of scan-out, it is necessary to correct the boundary scan cell 13.

FIG. 2 is a block diagram showing a configuration of a boundary scan cell for both scan-out. As shown in the figure, the signal from the data output terminal Q of the D-type flip-flop 9 is input to the input terminal A of the multiplexer 7.
Supplied to On the other hand, the input terminal B of the multiplexer 7 has one of the scan-out signals PSO1 to PSOn
i is supplied. The output of the multiplexer 7 is provided to the input terminal B of the multiplexer 6. Incidentally, the multiplexer 7 selects an input signal applied to either the input terminal A or the input terminal B based on the control signal PM, and outputs the selected signal to the input terminal B of the multiplexer 6.

FIG. 5 is a block diagram showing the configuration of an external input terminal of an LSI (not shown) which is also used for scanning out. As shown in the figure, external output terminal 1
A boundary scan cell 13 is provided between the internal circuit 7 and the internal circuit 12. A buffer 16 is arranged between the boundary scan cell 13 and the external output terminal 17. The boundary scan cell 13 has the same configuration as that shown in FIG.

Now, in the configuration of FIG. 5, the output to the external output terminal 17 is performed via the boundary scan cell 13 so as to be also used for scanning out. Here, the dual use of the scan-out is performed by using the scan-out signals PSO1 to
This is performed by connecting one POSi of the PSOn to the input terminal B of the multiplexer 7 inside the boundary scan cell 13. On the other hand, whether to scan in parallel is set based on the control signal PM.

In the configuration shown in FIG. 5, when the output from the internal circuit 12 is observed by the boundary scan cell 13, the output is observed using the output signal SO without using the external output terminal 17. Therefore, the external output terminal 17 can be used as a shared terminal for scan-out.

By the way, in the configuration of FIG. 5, in the boundary scan mode, the multiplexer 6 receives the output of the D-type flip-flop 9 through the multiplexer 7.
The path leading to the input terminal B is valid. Through this path, the state of the scan-out signals PS01 to PSOn can be observed at the external output terminal 17.

By the way, in the configuration of FIG. 5, the post-stage of the multiplexer 6 may be considered as a position where the multiplexer 7 which is also used is added. But if you do this,
The delay of the system path, that is, the path from the internal circuit 12 to the external output terminal 17 via the input terminal A of the multiplexer 6 and the buffer 16 is increased, which is an obstacle to operating the system at high speed.

On the other hand, as shown in FIG. 5, a multiplexer 7 is connected to a D-type flip-flop 9 for updating.
When the signal is added between the multiplexor and the multiplexer 6, there is no effect such as an increase in delay on the system path.

FIG. 3 is a block diagram showing another example of the configuration of the boundary scan cell 13 which is also used for scanning out. As shown in the figure, the output from the data output terminal Q of the D-type flip-flop 8 is supplied to respective data input terminals D of the D-type flip-flop 9 and the D-type flip-flop 10. Note that a shift clock signal SCLKA and a shift clock signal SCLKB, which are two-phase clocks, are supplied to respective clock input terminals C of the D-type flip-flop 8 and the D-type flip-flop 10. The data output terminal Q of the D-type flip-flop 9 is connected to the input terminal A of the multiplexer 7, and an output signal SO is derived from the data output terminal Q of the D-type flip-flop 10.

The configuration of FIG. 3 is characterized in that the scanning operation of the D-type flip-flop 8 and the D-type flip-flop 10 is performed by a two-phase clock of the shift clock signals SCLKA and SCLKB, and the output signal SO is the shift clock. The data is output in synchronization with the signal SCLKB, and the data output terminal Q of the D-type flip-flop 9 is transferred to the multiplexer 7 in synchronization with the update clock signal UPCLK. Other operations are the same as those in FIG.

As described above, the circuit test apparatus according to the embodiment of the present invention is configured to operate a plurality of internal scan circuits and a boundary scan circuit in an integrated circuit device in parallel and to suppress signal delay. Since the test terminal can also be used as the system terminal, the test time can be shortened, and a configuration for facilitating the test can be realized in which the overhead of the delay in the normal operation can be minimized.

[0045]

According to the present invention, the second output from the internal scan circuit is provided on the test path parallel to the through path in the output-side boundary scan circuit connected between the internal circuit and the system output terminal. In addition to the first switching circuit, the first switching circuit selectively applies one of the second output and the first output from the test path to the second switching circuit. The output of the through scan and the output of the first switching circuit are selectively applied to the system output terminal, so that the output from the internal scan circuit can be output from the system output terminal. The output from the circuit can be applied to the system output terminal via only one stage of the second switching means while minimizing the delay.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram showing a first example of a boundary scan cell for both scan-out;

FIG. 3 is a block diagram showing a second example of boundary scan cells for both scan-out.

FIG. 4 is a block diagram showing a configuration that is also used for scan-in.

FIG. 5 is a block diagram showing a configuration that is also used for scan-out.

FIG. 6 is a schematic configuration diagram of an integrated circuit device having a test facilitation circuit.

FIG. 7 is a block diagram of a conventional circuit test apparatus.

FIG. 8 is a block diagram illustrating a configuration of a boundary scan cell.

[Explanation of symbols]

 1-1 to 1-n Scan register 2 Boundary scan register 3-1 to 3-n 3, 4, 6, 7, 21 Multiplexer 5 Selection signal input terminal 8, 9, 10 D-type flip-flop 11 External input terminal 12 Internal circuit DESCRIPTION OF SYMBOLS 13 Boundary scan cell 14, 15, 16 Buffer 17 External output terminal 18 Integrated circuit device 19-1 to 19-4 Circuit under test 20 Test control circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/28-31/3187 G06F 11/22 360

Claims (4)

(57) [Claims] An internal circuit, a system output terminal, an output-side boundary scan circuit connected between the internal circuit and the system output terminal, an internal scan circuit,
The boundary scan circuit comprises: a through path for passing an output signal from the internal circuit as it is; a test path incorporating a test circuit; a first output from the test path and a second output from the internal scan circuit. First switching means for selectively outputting any one of: a second switching means for selectively outputting any one of the output from the first switching means and the output from the through path to the system output terminal; An integrated circuit device configured to have: 2. The integrated circuit device according to claim 1, wherein said first switching means is connected between said update data storage means and said second switching means in said test path. 3. The integrated circuit device according to claim 2, wherein said data storage means is a flip-flop, and said first and second switching means are multiplexers. 4. A system input terminal, an input-side boundary scan circuit connected between the system input terminal and the internal circuit, and a second input terminal connected between the system input terminal and the internal scan circuit. 3 switching means, wherein the third switching means is configured to selectively output any one of an input signal to the system input terminal and a scan-in signal and apply the signal to the internal scan circuit.
An integrated circuit device according to claim 1.