JP3306488B2 - Active matrix substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate forming a liquid crystal display panel. In particular, the present invention relates to an improved structure around a lead terminal of a wiring such as a scanning line and a signal line formed on an active matrix substrate.

[0002]

2. Description of the Related Art Although not shown, a liquid crystal display panel generally has a structure in which two substrates are arranged in parallel and opposed to each other with a required space therebetween, and a liquid crystal is interposed in this space.
One of the two substrates is called an active matrix substrate, and the other is called a counter substrate. In some cases, a three-color color filter of RGB or YMC may be provided on the opposite substrate.

FIG. 4 is a circuit diagram showing a configuration of a general liquid crystal display panel. In the drawing, 1 is a gate bus line as a plurality of scanning lines arranged in a row direction, 2 is a source bus line as a plurality of signal lines arranged in a column direction, and 3 is an orthogonal intersection of both bus lines 1 and 2 Are a plurality of pixels provided in a matrix-like region formed by. Pixel 3 is
Mainly pixel electrode 4 and switching element 5 such as TFT
Here, the auxiliary capacity 6 is also provided. Reference numeral 7 denotes an auxiliary capacitance bus line, 8 denotes a common electrode, 1a denotes a lead terminal of the gate bus line 1, and 2a denotes a lead terminal of the source bus line 2.

The gate bus line 1, source bus line 2, pixel 3, and auxiliary capacitance bus line 7 are provided on the active matrix substrate side, and the common electrode 8 is provided on the counter substrate side.

As the aforementioned active matrix substrate,
FIGS. 5 to 7 show structural examples to which the present applicant has already applied for a patent. In this structure, the pixel electrodes 4 arranged in a matrix and the gate bus lines 1 and the source bus lines 2 are not arranged side by side on the same plane, but are arranged up and down via an insulating film. The efficiency and the definition have been improved. FIG. 5 is a plan view showing one pixel on the active matrix substrate, and FIG. 6 is (6)-of FIG.
FIG. 7 is a sectional view taken along the line (6) of FIG. 5, and FIG. 7 is a sectional view taken along the line (7)-(7) of FIG.

In the active matrix substrate 10 shown in the figure, a gate electrode 12, a gate insulating film 13, a semiconductor layer 14, a channel protective layer are formed on a transparent insulating substrate 11 as elements constituting a switching element 5 having an inverted staggered structure. 15,
A source electrode 16 and a drain electrode 17 are formed.
The gate bus line 1 is connected to the gate electrode 12, the source bus line 2 is connected to the source electrode 16, and the drain electrode 1 is connected to the gate electrode 12.
The pixel electrodes 4 are respectively connected to 7 via a first conductive film 18. The auxiliary capacitance 7 is formed of the three layers of the first conductive film 18, the gate insulating film 13, and the second conductive film 19 described above. Further, a thick planarizing insulating film 20 is laminated above the switching element 5 and the auxiliary capacitance 7, and the pixel electrode 4 is formed on the upper surface of the planarizing insulating film 20. Such a flattening insulating film 2
The upper and lower pixel electrodes 4 sandwiching 0 are connected to the first conductive film 18 via contact holes 21 provided in the planarization insulating film 20.

The lead terminals 1a of the gate bus line 1 and the lead terminals 2a of the source bus line 2 are formed on an insulating substrate 11, as shown in FIGS. 8 to 10, and the lead terminals 1a, 2a Are coated with a conductive film 22 for preventing disconnection. Lead terminals 1a, 2a
Are made of the same material as the gate electrode 12, and the conductive film 22 for preventing disconnection is made of the same material as the pixel electrode 4. Since it is necessary to connect a driver IC (not shown) to each of the lead terminals 1a and 2a, the planarization insulating film 20 is exposed above each conductive film 22 for preventing disconnection without being formed. .

[0008]

In the above conventional example, the following problems may occur in the lead terminal 1a of the gate bus line 1 and the lead terminal 2a of the source bus line 2.

In other words, the above-described conductive film 22 for preventing disconnection and the pixel electrode 4 are simultaneously obtained through a film forming step and a patterning step by photolithography. At
Since they are formed in steps from the top of the thick planarizing insulating film 20 to the lead terminals 1a and 2a, a large step is formed at the edge of the planarizing insulating film 20. . Therefore, during patterning of the disconnection prevention conductive film 22 and the pixel electrode 4, exposure failure or the like is likely to occur at a step portion at the edge of the planarization insulating film 20, and in extreme cases, as shown in FIG. The conductive film 22 for preventing disconnection may remain as an etching residue 30 not only on each of the adjacent lead-out terminals 1a and 2a, but also in a region between them, and between the adjacent lead-out terminals 1a and between the lead-out terminals. 2a may be short-circuited. If such a structural defect exists, it will be handled as a defective product. In some cases, correction such as removal of the etching residue 30 by a laser may be performed, but it takes time and effort.

Accordingly, an object of the present invention is to provide an active matrix substrate having a structure in which a structural defect such as a short circuit between a plurality of wiring adjacent terminals does not occur.

[0011]

According to the present invention, there is provided an active matrix substrate comprising: an insulating substrate; a plurality of first wirings provided in parallel with each other on the insulating substrate; an insulating film covering the first wirings; A large number of second wirings provided in parallel with each other in a direction orthogonal to the first wiring, a large number of switching elements provided and connected near respective intersections of both wirings, and a thick film covering all of them. A first insulating film;
A plurality of pixel electrodes provided on the first insulating film so as to correspond to a matrix-like region generated by the orthogonal intersection of the two wirings, and the lead terminals of the two wirings are exposed from the edge of the first insulating film; In this structure, the exposed lead-out terminal is covered with a conductive film for preventing disconnection, and a second insulating film thinner than the first insulating film is provided below the first insulating film. The second insulating film is provided such that an edge of the second insulating film on the lead terminal side is exposed from an edge of the first insulating film on the lead terminal side.

It is preferable that the first insulating film be a polymer compound having at least one of an imide group, an amide group and an acryl group in its structure. It is preferable that the dimension at which the edge of the second insulating film on the lead terminal side is exposed from the edge of the first insulating film on the lead terminal side is set to at least 1 μm or more in consideration of the thickness of the first insulating film. The switching element can be an inverted staggered thin film transistor. The disconnection preventing conductive film is formed simultaneously with the same material as the pixel electrode.

In the present invention, in short, during film formation in the step of forming a conductive film for preventing disconnection on a lead-out terminal, the first insulating film, which is the upper layer on the insulating substrate, is moved from the thick first insulating film to the insulating substrate. A disconnection preventing conductive film is formed in a stepwise manner over the lead terminal serving as a lower layer of the first insulating film. When patterning of the disconnection preventing conductive film is performed, exposure is performed at a step portion at an edge of the first insulating film. Failure may occur,
In such a case, a part of the conductive film for preventing disconnection remains as an etching residue at the step portion at the edge.
However, in the case of the present invention, the above-mentioned etching residue remains on the second insulating film on the lead-out terminal and does not remain in the region between the adjacent lead-out terminals as in the related art. The short circuit between the lead terminals does not occur.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the embodiments shown in FIGS.

FIGS. 1 to 3 relate to an embodiment of the present invention. FIG. 1 is a perspective view around an extraction terminal, FIG. 2 is a plan view around an extraction terminal, and FIG. 3 is (3) in FIG. It is a-(3) line sectional view.

Here, the same basic structure as the active matrix substrate 10 shown in FIGS. 5 to 7 is taken as an example. The present embodiment differs from the conventional example in the configuration around the lead terminal 1a of the gate bus line 1 and the lead terminal 2a of the source bus line 2.

The lead terminals 1a and 2a are made of the same material as the gate electrode 12, and the disconnection preventing conductive film 22 covering the lead terminals 1a and 2a is made of the same material as the pixel electrode 4.
Since it is necessary to connect a driver IC (not shown) to each of the extraction terminals 1a and 2a, the respective extraction terminals 1a and 2a
The insulating film 20 for planarization is not formed above the conductive film 22 for preventing disconnection that covers the
Surface is exposed.

Then, between the switching element 5 and the planarizing insulating film 20, a short-circuit preventing insulating film 23 having a thickness similar to that of the lead terminals 1a and 2a is formed. In addition, the edges of the short-circuit prevention insulating film 23 on the side of the lead terminals 1a and 2a are set to be more exposed than the edges of the planarizing insulating film 20.

By doing so, the conductive film 22 for preventing disconnection is provided.
Even if the etching residue 30 is generated in the process of forming the pixel electrode 4, the above-described etching residue 30 remains on the short-circuit preventing insulating film 23. In addition, the above-described etching residue 30 does not remain in the region between the lead terminals 2a of the source bus line 2. For this reason, even if the etching residue 30 is generated in the process of forming the disconnection prevention conductive film 22 and the pixel electrode 4,
The lead-out terminal 1a of the adjacent gate bus line 1 and the lead-out terminal 2a of the source bus line 2 are not short-circuited.
Note that, in this example, the planarizing insulating film 20 is a first insulating film.
The short-circuit preventing insulating film 23 corresponds to the second insulating film in the claims.

Next, a method for manufacturing the active matrix substrate 10 will be described. That is, the manufacturing method of the present embodiment differs from the conventional example in that a step of forming the short-circuit preventing insulating film 23 is added.

On a transparent insulating substrate 11 such as a glass substrate, a 400 nm-thick conductive film such as tantalum, titanium, molybdenum, aluminum, copper, indium tin oxide, or polysilicon doped with impurity ions is formed by a sputtering method. The gate electrode 12, the gate bus line 1, and the lead terminal 1a of the gate bus line 1 are formed by forming and patterning this conductive film by photolithography. In addition,
An anodic oxide film for compensation may be formed on the surface of the gate electrode 12 by an anodic oxidation method.

On the entire upper surface of the insulating substrate 11, an insulating film such as silicon dioxide, silicon nitride, tantalum pentoxide, etc., which becomes the gate insulating film 13 by a chemical vapor deposition method, an amorphous silicon layer which becomes the semiconductor layer 14, and a channel Three layers of the SiNx layer serving as the protective layer 15 are successively laminated to a thickness of 100 nm, 50 nm, and 20 nm, respectively.

The uppermost SiNx formed in the above process
By patterning the layer, the channel protection layer 15
To form

The semiconductor layer 14 is formed by patterning the intermediate amorphous silicon layer formed in the above steps.

A conductive film such as tantalum, titanium, molybdenum, aluminum, copper, indium tin oxide, or polysilicon doped with impurity ions is formed to a thickness of 300 nm over the entire upper surface of the insulating substrate 11 by sputtering. By patterning this conductive film, the source electrode 16 and the drain electrode 1 are formed.
7. The source bus line 2 and the lead terminal 2a of the source bus line 2 are formed.

A 200-nm-thick silicon nitride film is formed on the entire upper surface of the insulating substrate 11 by a chemical vapor deposition method, and the silicon nitride film is patterned to form a lead terminal 1 a of the gate bus line 1 and a source bus. Insulation film 2 for preventing short circuit above lead terminal 2a of line 2
3 is removed.

A flattening insulating film 20 made of an organic polymer material such as polyimide, polyamide, polyamideimide, or acrylic or a silicon-based inorganic polymer material is formed on the entire upper surface of the insulating substrate 11 by spin coating.
The flattening insulating film 20 is patterned with a thickness of μm. The thickness of the resist film (not shown) at the time of patterning is larger than the thickness of the planarizing insulating film 20.
For example, it is set to 2.1 μm. In the patterning, the edge of the planarizing insulating film 20 is removed so as to be recessed by a required dimension from the edge of the short-circuit preventing insulating film 23 formed as described above. That is, the exposed dimension of the short-circuit preventing insulating film 23 is set to be equal to the thickness of the planarizing insulating film 20 or the thickness of the resist film, for example, at least 1 μm, preferably 3 μm or more. Note that the present invention is not limited to the spin coating method, and may be a film forming method such as dipping, slot coating, bar coating, or capillary coating. Further, depending on the film thickness, a method such as flexographic printing or vacuum vapor deposition polymerization can be applied.

After a contact hole is formed in the planarizing insulating film 20, an ITO film is formed to a thickness of 100 nm on the entire upper surface of the insulating substrate 11 by a sputtering method.
By patterning the ITO film, the pixel electrode 4 and the conductive film 22 for preventing disconnection are formed.

As described above, by exposing the edge of the short-circuit preventing insulating film 23 below the edge of the planarizing insulating film 20, the patterning of the ITO film in the above process can be performed. Even if the etching residue 30 remains on the edge of the planarization insulating film 20, the etching residue 30
Only remaining on the short-circuit preventing insulating film 23 does not remain in the region between the adjacent lead terminals 1a and between the lead terminals 2a. In short, the etching residue 3 of the ITO film in the above-described step is formed due to the formation of the thick insulating film 20 for planarization.
Although the occurrence of 0 cannot be completely prevented,
This etching residue 30 can reliably prevent a short circuit between the lead terminals 1a of the adjacent gate bus lines 1 and the lead terminals 2a of the source bus lines 2. Therefore, the incidence of structural defects can be significantly reduced as compared with the related art. Furthermore, it is possible to eliminate waste such as eliminating the need for troublesome work of repairing a short-circuited portion.

It should be noted that the present invention is not limited to only the above embodiment, and various applications and modifications are conceivable.

(1) Insulating film 2 for preventing short circuit of the above embodiment
3 can be replaced by the gate insulating film 13 of the switching element 5. In this case, as the lead terminal 2a of the source bus line 2, the lead terminal 1a of the gate bus line 1 is used.
At the same time as above, a gate insulating film 13 is formed between the source bus line 2 and the lead terminal 2a, and a contact hole is formed in the gate insulating film 13. It is necessary to have a structure in which the source bus line 2 and the lead terminal 2a are connected via the contact hole. With such a structure, the gate insulating film 13 can be used as the short-circuit preventing insulating film 23.

(2) The switching element 5 has been described using an inverted staggered thin film transistor (TFT) using amorphous silicon as an example. However, other thin film transistors using polysilicon or single crystal silicon, or staggered It can be a three-terminal type having a structure and a planar structure. Alternatively, a two-terminal switching element such as a varistor or a diode can be used. When the switching element 5 has a staggered structure or a planar structure, the interlayer insulating film between the gate electrode and the source electrode can be used instead of the short-circuit preventing insulating film 23 described above.

(3) Although the manufacturing method described in the above embodiment also exemplifies a general method, this is not particularly limited.

(4) The active matrix substrate 1
0 can be used to construct a liquid crystal display panel,
The liquid crystal display panel may be of any mode, such as a twisted nematic type, an electric field controlled birefringent type, a guest host type, and those of various modes.

[0035]

According to the present invention, since a short circuit between adjacent lead terminals of a large number of wirings can be avoided, the rate of occurrence of structural defects can be reduced, and the need to repair structural defects can be eliminated. This can contribute to total cost reduction.

Therefore, according to the present invention, a high-quality and inexpensive active matrix substrate can be provided.

[Brief description of the drawings]

FIG. 1 is a perspective view of the vicinity of a lead terminal according to an embodiment of the present invention.

FIG. 2 is a plan view of the vicinity of a lead terminal of FIG. 1;

FIG. 3 is a sectional view taken along line (3)-(3) of FIG. 2;

FIG. 4 is a circuit diagram showing a configuration of a general liquid crystal display panel.

FIG. 5 is a plan view showing one pixel on a conventional active matrix substrate.

FIG. 6 is a sectional view taken along line (6)-(6) of FIG. 5;

FIG. 7 is a sectional view taken along line (7)-(7) of FIG. 5;

FIG. 8 is a perspective view showing the vicinity of a lead terminal in a conventional example.

FIG. 9 is a plan view of the vicinity of a lead terminal of FIG. 8;

FIG. 10 is a sectional view taken along line (10)-(10) in FIG. 9;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gate bus line 1a Gate bus line lead terminal 2 Source bus line 2a Source bus line lead terminal 3 Pixel 4 Pixel electrode 5 Switching element 10 Active matrix substrate 11 Insulating substrate 12 Gate electrode 13 Gate insulating film 16 Source electrode 17 Drain electrode Reference Signs List 20 insulating film for flattening 22 conductive film for preventing disconnection 23 insulating film for preventing short circuit 30 etching residue

Claims (5)

(57) [Claims] 1. An insulating substrate, a plurality of first wirings provided in parallel on the insulating substrate, an insulating film covering the first wirings, and an insulating film on the insulating film parallel to each other in a direction orthogonal to the first wirings. A large number of second wirings provided, a large number of switching elements provided and connected in the vicinity of each intersection of both wirings, a thick first insulating film covering all of them,
A plurality of pixel electrodes provided on the first insulating film so as to correspond to a matrix-like region generated by the orthogonal intersection of the two wirings, and the lead terminals of the two wirings are exposed from the edge of the first insulating film; An active matrix substrate having a structure in which a conductive film for preventing disconnection is coated on a surface of the exposed lead terminal, and a second film, which is thinner than the first insulating film, is formed in a region below the first insulating film. An active matrix substrate provided with an insulating film and provided so that an edge of the second insulating film on the lead terminal side is exposed from an edge of the first insulating film on the lead terminal side. 2. The active matrix substrate according to claim 1, wherein said first insulating film is a polymer compound having at least one of an imide group, an amide group, and an acrylic group in its structure. 3. A dimension in which a lead terminal side edge of the second insulating film is exposed from the lead terminal side edge of the first insulating film is set to at least 1 μm or more in consideration of the thickness of the first insulating film. ,
The active matrix substrate according to claim 1. 4. The active matrix substrate according to claim 1, wherein said switching element is formed of an inverted staggered thin film transistor. 5. The active matrix substrate according to claim 1, wherein the disconnection preventing conductive film is formed simultaneously with the same material as the pixel electrode.