JP3398056B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, more specifically, a DRAM (Dynanic Rand).
It is suitable for memory devices such as om access memory).

[0002]

2. Description of the Related Art A conventional semiconductor device and its manufacturing method will be described below with reference to FIG.

FIG. 7 is a sectional view of a conventional semiconductor device.
Reference numeral 1 is a semiconductor substrate, 2 is an element isolation film, 3 is an impurity layer, 4 is a gate electrode, and 5 is a wiring.

Reference numeral 6 is an insulating film that covers the gate electrode 4, 7 is a bit line that is in contact with the impurity layer 3, and 8 is an insulating film that covers the bit line 7.

Further, 9 is a storage node (hereinafter referred to as ST) as a capacitor lower electrode which contacts the impurity layer 3, and 10 is a capacitor dielectric film.
1 is a cell plate (hereinafter,
Call it SP. ), And the capacitor 1 with 9, 10, 11
Make up 2.

Reference numeral 13 is an interlayer insulating film that covers the capacitor 12, and each contact portion is formed through the interlayer insulating film 13. That is, for example, a contact portion 14A that contacts the substrate 1 and a contact portion 14B that contacts the SP 11 are formed.

At this time, there is a large difference in contact depth between the shallowest contact portion (eg, contact portion 14B on SP11) and the deepest contact portion (eg, contact portion 14A on the substrate 1). Become.

Therefore, if the etching necessary for opening the deepest contact portion is performed, the shallowest contact portion will considerably overetch the underlying polysilicon film of SP11.

Therefore, it is necessary to make the polysilicon film thicker than necessary. However, in this case, the absolute level difference between the memory cell section and the peripheral circuit section is further increased.

Although a method of dividing the contact portion forming process into a plurality of steps depending on the depth of the contact portion can be considered, in this case, the productivity is lowered.

[0011]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device having a good and highly productive contact portion and a method for manufacturing the same.

[0012]

Therefore, the present invention provides a semiconductor device having a stack type capacitor cell structure,
A dummy pattern 19 having a capacitor structure formed in the vicinity of the lower electrode ST9 of the capacitor, a capacitor dielectric film 20 formed so as to cover the lower electrode ST9 and the dummy pattern 19 of the capacitor, and the capacitor dielectric film 20 being covered. The upper electrode SP21 of the capacitor thus formed, the interlayer insulating film 23 formed so as to cover the upper electrode SP21 of the capacitor, and the interlayer insulating film 2
3 is formed on the upper electrode SP21 of the capacitor.

Then, the manufacturing method is such that the lower electrode S of the capacitor is formed on the upper surfaces of the insulating films 6 and 8 and in the contact portion 30.
T9 is formed and the lower electrode ST of the capacitor is formed.
A dummy pattern 19 having a capacitor structure is formed on the insulating films 6 and 8 in the vicinity of 9. Next, a capacitor dielectric film 20 is formed so as to cover the lower electrode ST9 of the capacitor and the dummy pattern 19, and the capacitor dielectric film 20 is formed.
Forming an upper electrode SP21 of the capacitor. And forming an interlayer insulating film 23 so as to cover the upper electrode SP21 of the capacitor, and then forming a contact portion 24B that contacts the upper electrode SP21 of the capacitor through the interlayer insulating film 23. It is characterized by that.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings. The same components as those of the conventional structure are designated by the same reference numerals, and the description will be simplified.

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention, and FIG. 2 is a simplified plan view showing the capacitor structure thereof, and the structure above the storage node of the capacitor is omitted.

In FIG. 1, reference numeral 1 is one conductive film type, for example, P
Type semiconductor substrate, 2 is an element isolation film, 3 is a reverse conductive film type, for example, N + type impurity layer, 4 is a gate electrode, 5
Is wiring. The impurity layer 3 includes LDD and DD, which are conventionally known low-concentration impurity layers and high-concentration impurity layers.
It may be an impurity layer having a D structure. Further, 6 is an oxide film that covers the gate electrode 4 and the like, 7 is a bit line that is in contact with the impurity layer 3, and 8 is an oxide film that covers the bit line 7.

Further, 9 is a storage node (hereinafter referred to as ST) as a lower electrode of the capacitor, and 19 is a dummy pattern having the same structure as ST9 of the capacitor which is a feature of the present invention, as shown in FIG. ST of the capacitor
9 (in the front and rear of the paper surface of FIG. 1) in parallel with each other, and in a discontinuous state in a formation region of a contact portion 24B which contacts a cell plate (SP) 21 of a capacitor described later.

Reference numeral 20 is a capacitor dielectric film that covers the ST9 of the capacitor and the dummy pattern 19, and 21 is a cell plate (hereinafter referred to as SP) as a capacitor upper electrode. The capacitor 22 is configured. In addition, in the present embodiment, a capacitor having the same structure as ST9 is referred to as a dummy pattern 19, but it can be said that 19, 20, 21 form a dummy pattern.

Reference numeral 23 is an interlayer insulating film which covers the capacitor 22 and the dummy pattern 19, and each contact portion is formed through the interlayer insulating film 23. That is, for example, there are a contact portion 24A that contacts the substrate 1 and a contact portion 24B that contacts the SP 21, and in each of the contact portions 24A and 24B, a tungsten plug 26 is provided via a barrier metal film 25.
Is buried and Al wiring 2 is formed on each tungsten plug 26.
7 are formed.

At this time, by forming the dummy pattern 19 having the same structure as the capacitor 22 in the vicinity of the capacitor 22, the film thickness of the interlayer insulating film 23 in the region where the contact portion 24B is formed can be increased, When the shallowest contact portion (for example, the contact portion 24B on the SP21) of the related art is formed in this region, the depth of the shallowest contact portion and the deepest contact portion (for example, the substrate 1
The difference in contact depth with the contact portion 24A) that contacts the upper portion is drastically reduced compared to the conventional case.

The method of manufacturing the semiconductor device of the present invention will be described below.

First, as shown in FIG. 3, the element isolation film 2 is formed in a region other than the active region on the one conductive film type, for example, P type semiconductor substrate 1, and the region other than the element isolation film 2 is gate-insulated. A film is formed, and a conductive film made of a polysilicon film or the like is patterned on the gate insulating film to form the gate electrode 4 and the wiring 5. The gate electrode 4 and the wiring 5 are not limited to the polysilicon film, but may be a laminated film made of, for example, a polysilicon film and a tungsten polycide (WSix) film.

Further, using the gate electrode 4 as a mask, a reverse conductive film type, for example, phosphorus ions are ion-implanted to form an N + type impurity layer 3 on the surface layer of the substrate 1 adjacent to the gate electrode 4, and the gate electrode 4 is formed. An oxide film 6 to cover is formed. Further, after forming a contact portion that contacts the impurity layer 3 through the oxide film 6, a bit line 7 is formed in the contact portion, and an oxide film 8 that covers the bit line 7 is formed.

Further, a contact portion 30 for forming a capacitor is formed on the portion of the oxide films 6 and 8 on the impurity layer 3 which is not on the bit line 7 side.

Next, as shown in FIG.
Lower electrode S of the capacitor contacting the impurity layer 3 of
A dummy pattern 1 having the same structure as ST9 of the capacitor is formed by forming a conductive film for forming T9 and patterning the conductive film.
9 is formed. As the conductive film, for example, a polysilicon film is used to form ST9 of the capacitor and the dummy pattern 19 having a film thickness of about 6000Å.

Subsequently, as shown in FIG. 5, the capacitor dielectric film 20 having a film thickness of about 80Å to 100Å and the upper electrode of the capacitor having a film thickness of about 1000Å to 1500Å so as to cover the ST9 of the capacitor and the dummy pattern 19. Form SP21. The capacitor dielectric film 20
Is a laminated film of, for example, a SiN film and a SiO2 film, and SP21 of the capacitor is formed by patterning a polysilicon film, for example.

Next, as shown in FIG. 6, an interlayer insulating film 23 made of, for example, a TEOS film or a BPSG film is formed so as to cover the SP9 and the dummy pattern 19 of the capacitor, and the interlayer insulating film 23 is interposed therebetween. Each contact part 24
A and 24B are formed (see FIG. 2).

At this time, a dummy pattern 19 having the same structure as ST9 of the capacitor, which is a feature of the present invention, is formed in the vicinity of ST9 of the capacitor, so that the shallowest contact portion (for example, the contact on SP21) as in the conventional case is formed. Part 24B) (dummy pattern 19 is formed in the vicinity of capacitor 22 to increase the film thickness of interlayer insulating film 23 formed in this part, so that when forming this shallowest contact part. The film thickness of the interlayer insulating film 23 on SP21 approaches the film thickness of the interlayer insulating film 23 at the position where the deepest contact portion (for example, the contact portion 24A that contacts the substrate 1) is formed, and the contact on SP21 To drastically reduce the difference between the depth of the portion 24B and the contact depth of the contact portion 24A that contacts the substrate 1 as compared with the conventional case. It can be.

For example, in a 0.35 μm DRAM, the deepest contact portion has a depth of about 1.5 μm,
The shallowest contact depth is 0.3 μm (on SP)
However, since the dummy pattern 19 is interposed, the depth of the contact portion on the SP is increased by the film thickness (6000Å) of the dummy pattern and is 0.8 μm to 0.9 μm.
It was about μm, and the difference in depth from the deepest contact part was drastically reduced.

In this embodiment, the contact portion 2
Although the 4B formation region is formed in the region where the dummy pattern 19 and the dummy pattern 19 are discontinuous as shown in FIG. 2, the present invention is not limited to this, and there is a space margin between the ST9 of the capacitor and the dummy pattern 19. If so, a contact portion may be formed between them.

Subsequently, as shown in FIG. 1, a tungsten film is formed in each of the contact portions 24A and 24B via a barrier metal film 25, and the tungsten film is etched back to form the contact portions 24A and 24B. A tungsten plug 26 is formed inside. Then, an Al wiring 27 is formed on the tungsten plug 26 to form the semiconductor device shown in FIG.

As described above, in the present invention, the dummy pattern 19 having the same structure as ST9 of the capacitor is formed in the vicinity of ST9 of the capacitor, so that the shallowest contact portion (for example, on the SP21) as in the conventional case is formed. Of the inter-layer insulating film 23 at the location where the contact portion 24B) is formed, the film of the inter-layer insulating film 23 at the location where the deepest contact portion (for example, the contact portion 24A that contacts the substrate 1) is formed. The thickness approaches the thickness, and even if the etching required to open the deepest contact portion as in the conventional case is performed, the base layer S at the shallowest contact portion is formed.
It is possible to prevent the polysilicon film of P21 from being over-etched more than necessary. Therefore, it is not necessary to make the polysilicon film thicker than necessary, and it is possible to suppress an increase in the absolute level difference between the memory cell section and the peripheral circuit section.

Further, it is not necessary to divide the step of forming the contact portion into a plurality of times according to the depth of the contact portion, and the productivity can be improved.

In this embodiment, the contact portion 2
Although the tungsten plugs 26 are formed in the 4A and 24B via the barrier metal film 25 and the Al wirings 27 are formed, the invention is not limited to this, and the contact portions 24A and 24B, for example.
A structure in which an Al wiring is directly formed inside the barrier metal film 25 may be used.

[0035]

According to the present invention, by forming a dummy pattern having the same structure as the capacitor in the vicinity of the capacitor, it is possible to increase the thickness of the interlayer insulating film in the region where the contact portion is formed. By drilling the SP upper contact portion in this region, the difference between the depth of the SP upper contact portion and the contact depth between the deepest contact portion can be drastically reduced, and a good SP upper contact portion can be formed.

Further, it is not necessary to divide the step of forming the contact portion into a plurality of times according to the depth of the contact portion, which leads to improvement in productivity.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic plan view of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device of the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the method for manufacturing the semiconductor device of the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the method for manufacturing the semiconductor device of the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device of the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a conventional semiconductor device.

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Claims (2)

(57) [Claims] 1. A semiconductor device having a stack type capacitor cell structure, a base insulating film formed to cover a base pattern and having a contact portion, and a capacitor formed on an upper surface of the base insulating film and in the contact portion. On the base insulating film near the bottom electrode of the capacitor and the bottom electrode of the capacitor.
A dummy pattern of the formed capacitor structure and covers the lower electrode and the dummy pattern of the capacitor
And a capacitor dielectric film formed to cover the capacitor dielectric film.
And an upper electrode of Pashita, formed so as to cover the upper electrode of the capacitor
The interlayer insulating film and the dummy pattern formed on the interlayer insulating film and adjacent to each other.
A capacitor is placed on the upper electrode of the capacitor located between turns.
Semi-characterized by having a tact contact part
Conductor device. 2. A stack type capacitor cell structure is provided.
In a method of manufacturing a semiconductor device, a process of forming a base insulating film so as to cover a base pattern.
And a capacitor on the upper surface of the base insulating film and in the contact part.
Of the lower electrode of the capacitor together with the step of forming the lower electrode of
A dummy of a capacitor structure on the base insulating film near the electrodes
Forming a pattern and covering the lower electrode of the capacitor and the dummy pattern
To form a capacitor dielectric film so that the capacitor dielectric film is coated on the capacitor.
A step of forming a partial electrode and an interlayer insulating film so as to cover the upper electrode of the capacitor.
And the step of forming the dummy pattern between the dummy patterns adjacent to each other through the interlayer insulating film.
Contact on the upper electrode of the capacitor located at
And characterized by a step of forming a that contact portion
Of manufacturing a semiconductor device.