JP3396448B2 - Driver circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driver circuit provided in a liquid crystal display (hereinafter referred to as LCD) device or the like, which selects a driving voltage by switching and outputs the driving voltage.

[0002]

2. Description of the Related Art LCD devices include integrated circuits (hereinafter referred to as ICs).
Called a) LCD driver IC is provided. The LCD driver IC plays a role of driving a liquid crystal element by applying a driving voltage in a segment direction or a common direction perpendicular to the segment direction. Conventional LCD driver IC
Has two types of power supply voltages, that is, a power supply voltage VDD for internal logic and a power supply voltage VUO for liquid crystal output. The voltage for driving the liquid crystal element varies from 6 to 50 [V] and varies depending on the type of liquid crystal. Therefore, the power supply voltage VUO used for driving the liquid crystal element cannot be used as it is for the logic circuit inside the IC, and the power supply voltage VDD is used for the logic circuit. Therefore, the voltage for driving the liquid crystal is such that the logic signal generated by the logic circuit is converted into a signal using the power supply voltage VUO and is output. A specific example thereof is shown in FIG.

FIG. 2 is a circuit diagram showing a conventional driver circuit. This driver circuit is a circuit provided in the output stage of the driver IC, and inputs the logic signal S _in generated by a logic circuit (not shown) via the inverter 1 and the inverter 2 in series with the level shifter 10. And two switch circuits 21 and 22. The inverters 1 and 2 are VDD type circuits which receive a voltage supply from the power supply voltage VDD. The level shifter 10
A P-channel type MOS transistor (hereinafter referred to as a PMOS) connected in series between the power supply voltage VUO and the ground GND.
11) and an N-channel M0S transistor (hereinafter referred to as NM0S) 12, and between the power supply voltage VUO and the ground GND, the PMOS 11 and NM0S12 have PM0S13 and NM0S14 connected in parallel. A connection node N1 between PM0S11 and NM0S12 is connected to the gate of PM0S13, and a connection node N between PM0S13 and NM0S14.
2 is connected to the gate of the PMOS 11. The connection node N1 shows the converted voltage level-shifted by the power supply voltage VUO. The power supply voltage VUO may be given from the outside, but the recent trend is that the power supply voltage VDD
In many cases, the voltage level of is doubled or tripled by the booster circuit in the driver IC.

The switch circuit 21 includes PM0S21a and N0S21a.
The transfer gate is composed of M0S21b and is connected between the power supply voltage VUO and the output node Nout. The voltage of the connection node N1 of the level shifter 10 is inverted and applied to the gate of the PM0S21a by the inverter 23, and the output signal of the inverter 23 is inverted and applied to the gate of the NM0S21b. . On the other hand, the switch circuit 22
Is composed of a transfer gate composed of PM0S22a and NM0S22b, and is connected between the ground GND and the output node Nout. The voltage of the connection node N1 of the level shifter 10 is applied to the gate of NM0S22b via the inverter 23, and the output signal of the inverter 23 is applied to the gate of PM0S22a.
It is a connection given through 4.

This driver circuit includes PM0S and NM0S
And the inverters 1, 2, 23, 24 are also PM
0S and NM0S, respectively. The size of the transistor in the driver circuit is shown in parentheses in FIG. The size of the transistor is also shown in parentheses in FIGS. 1 and 7 described later. Each inverter 1,2
In PM0S that configures, as shown in () in the vicinity,
For example, the gate length is 1 μm and the gate width is 10 μm (P1
0/1). The gate length of NM0S is 1μ
m, and the gate width is 10 μm (N10 / 1). In contrast, the inverter 23, the power collector
A circuit Vuo system receives voltage supply from pressure Vuo,
The gate length of PM0S of the inverter 23 is 1 μm and the gate width thereof is 3 μm (P3 / 1). The gate length of NM0S of the inverter 23 is 1 μm and the gate width thereof is 3 μm.
It is formed to a μm (N3 / 1). The gate length of PM0S of the inverter 24 is 1 μm, and the gate width is 10 μm.
NM0 of the inverter 24 formed in (P10 / 1)
The gate length of S is 1 μm, and the gate width is 5 μm (N5 /
It is formed in 1). Each PM0 in the level shifter 10
The gate length of S11 and S13 is 30 μm, and the gate width is 3
The thickness is 3 μm (3/30). Each NM0
The gate length of S12, 14 is 1 μm, and the gate width is 30
It is formed by μm (30/1). P of switch 21
M0S21a has a gate length of 1 μm and a gate width of 50 μm
The gate length of the NM0S21b is 1 μm and the gate width is 30 μm (30/1). The PM0S22a of the switch 22 has a gate length of 1 μm and a gate width of 50 μm (50/1). The NM0S22b has a gate length of 1 μm and a gate width of 3 μm.
It is formed to 0 μm (30/1).

3 (i) to 3 (iii) are waveform charts showing the simulation result (1) of FIG.
Is a waveform of the logic signal S _in and the node N1 _in FIG. 2, (ii) is an enlarged view of part A in FIG. (I), and (iii) is an enlarged view of part B in FIG. Shown respectively. This Figure 3
The operation of the driver circuit in FIG. 2 will be described with reference to (i) to (iii). A logic signal S _in generated by a logic circuit (not shown) is transmitted via the inverter 1 to the level shifter 1
It is given to the gate of MM0S12 of 0 and is given to the gate of NM0S14 via the inverter 1 and the inverter 2. The logic signal S _in repeats “H” and “L” as shown _in FIG. 3I. The conduction states of the NMOSs 12 and 14 change according to the level of the logic signal S _in , and the voltages of the nodes N1 and N2 also change. Each changes. As a result, the conduction state of each PM0S11, 13 also changes, and the voltage of the node N1 changes to the power supply voltage VUO and PM0S11 and NM.
It is set in the conducting state of 0S12, and exhibits a larger amplitude than the logic signal S _in . Similarly, the voltage of the node N2 is also set in the conductive state of the power supply voltage VUO and PM0S13 and NM0S14. The level shifter 10 applies the voltage of the node N1 to the inverter 23, and the switch circuits 21 and 22
Switching. That is, the inverter 23 inverts the voltage level of the connection node N1 and outputs the output signal S23, and the inverter 24 inverts the voltage level of the output signal S23 and outputs the output signal S24. These output signals S23 and S24 are given to the switch circuits 21 and 22. For example, when the voltage of the connection node N1 is high,
The switch circuit 21 is turned on to close the connection between the power supply voltage VUO and the output node Nout. The switch 22 is turned off to cut off the connection between the output node Nout and the ground GND.
At this time, the power supply voltage VUO is applied to the liquid crystal element via the output terminal OUT. When the voltage of the connection node N1 is low, the switch 22 is turned on to close the ground GND and the output node Nout, and the switch 21 is turned off.
At this time, the voltage of the ground GND is the output terminal OUT
Is given to the liquid crystal element through.

[0007]

However, the driver circuit provided in the conventional LCD driver IC has the following problems. 4 (i) to (iii)
FIG. 3 is a diagram showing a simulation result (No. 2) of FIG. 2, where (i) is a waveform of the signals S23 and S24 in FIG. 2, and (ii) is an enlargement of the C portion of (i). The figure and the same figure (iii) have each shown the D section enlarged view of the same figure (i). Problems of the driver circuit of FIG. 2 will be described with reference to FIGS. 4 (i) to 4 (iii). When the logic level of the logic signal S _in input from the logic circuit is switched, FIG.
As in (i), the output signals S2 of the inverters 23 and 24
3, the levels of S24 transit at the same time. Thus, on the scan <br/> acme switch circuits 21, 22, off also switched at the same timing. At this time, as shown in FIGS. 4 (ii) and (iii),
Although there is a moment, there is a section in which both the switch circuits 21 and 22 are turned on (simultaneous ON), and a through current flows from the power supply voltage VUO to the ground GND. This allows the power consumption
The power also increases.

As described above, when the power supply voltage VUO is generated by the booster circuit, the power supply voltage VUO has a weak characteristic in load characteristics, so that the power supply voltage VUO is leveled down by the flow of the through current. To do. If the level is lowered, the liquid crystal display will of course be affected. To prevent this through <br/> current the interval where both of the switching circuits 21 and 22 are turned off (hereinafter, referred to as OFF-OFF period)
It becomes necessary to make. However, even if a circuit for creating an OFF-OFF section can be realized by newly adding many gates, the driver IC requires the driver circuits of FIG. 2 for the number of liquid crystal elements in the segment direction, for example. Therefore, layout issues remain.

[0009]

In order to solve the above-mentioned problems, the present invention provides a driver circuit which receives an input logic signal.
Output the voltage corresponding to the clock signal to the first connection node
Consists of a level shifter, PMOS and NMOS
The first selection signal is detected by detecting the voltage of the first connection node.
A first inverter for outputting and the first inverter
The size of the constituent PMOS and NMOS is
Comprising different PMOS and NMOS, the first
Detecting the voltage of the connection node and outputting a second selection signal;
It has two inverters. In addition, the first power source
Voltage or second power supply voltage output node, and
Connected between the first power supply voltage and the output node,
It is turned on or off by the first selection signal.
The first switch circuit, the second power supply voltage and the output
It is connected between the power node, and more to the second selection signal
And a second switch circuit that is turned on or off
Have By adopting such a configuration,
Based on the voltage output to the first connection node of the bell shifter
The first inverter and the second inverter.
The first selection signal and the second selection signal with different
To live. According to the first selection signal and the second selection signal,
The first switch circuit and the second switch circuit simultaneously
These first switch times without turning on
The path and the second switch circuit are turned on and off.

In the driver circuit, for example,
And the gate length of the PMOS forming the first inverter,
The gate of the PMOS forming the second inverter
The length is different from that of the N
Comprising the gate length of the NMOS and the second inverter
The gate length of the NMOS is different.

In the driver circuit, for example,
The level shifter has a second connection with the first connection node.
A node, the first power supply voltage, and the first connection node
And the control electrode is connected to the second connection node.
A first transistor of a first conductivity type connected to the first transistor;
1 is connected between the connection node and the ground, and the control electrode
A phase of the first conductivity type to which the logic signal is input.
A complementary second transistor of the second conductivity type and the first transistor
It is connected between a power supply voltage and the second connection node,
A control electrode connected to the first connection node;
An electrically conductive third transistor, and the second connection node
It is connected to the ground and the control electrode has the logic
The second conductivity type fourth signal to which a reverse phase signal of the clock signal is input.
And a transistor.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS ( First Embodiment ) FIG. 1 is a configuration diagram of a driver circuit showing a first embodiment of the present invention. This driver circuit is provided in the output stage of the driver IC and outputs the voltage of the ground GND, which is the first power supply voltage VUO or the second power supply voltage, as a drive voltage, and is generated by a logic circuit (not shown). A logic signal S _in is inputted through an inverter 1 similar to that of FIG. 2 of the related art and an inverter 2 in series therewith, and a level shifter 30 for converting the voltage with the power supply voltage VUO;
The switch circuit 41 and the second switch circuit 42 of
I have it. The inverters 1 and 2 have a third power supply voltage VD
It is a VDD-type circuit that operates by receiving voltage supply from D. The level shifter 30 has a power supply voltage VUO and a ground G.
First and second transistors PMOS31 and NM0S32 which are connected in series with ND, and third and third PMOS31 and NM0S32 which are connected in parallel between the power supply voltage VUO and the ground GND. 4 transistors PM0S33 and NM0S34. The first connection node N1 between PM0S31 and NM0S32 is connected to the gate that is the control electrode of PM0S33, and the second connection node N2 between PM0S33 and NM0S34 is connected to the gate of PMOS31. A voltage level-shifted by the power supply voltage VUO is output from the connection nodes N1 and N2.

The switch circuit 41 includes PM0S41a and N0S
M0S41b and a transfer gate, and is connected between the power supply voltage VUO and the output node Nout. The output node Nout is connected to the output terminal OUT. The output signal S43 of the inverter 43 whose input voltage is the voltage of the connection node N1 of the level shifter 10 is connected to the gate of the PM0S41a. The output signal S43 is a first selection signal for selecting the switch circuit 41. At the gate of NM0S41b,
The connection is such that the output signal S44 of the inverter 44 whose input voltage is the output signal S43 of the inverter 43 is applied. On the other hand, the switch circuit 42 includes PM0S42a and N
It is composed of a transfer gate composed of M0S42b and is connected between the ground GND and the output node Nout. The output signal S45 of the inverter 45 whose input voltage is the voltage of the connection node N2 of the level shifter 10 is connected to the gate of the PM0S42a. The output signal S45 is a second selection signal for selecting the switch circuit 42. The output signal S46 of the inverter 44 having the output signal S45 of the inverter 45 as an input voltage is connected to the gate of NM0S42b. That is, the inverters 43 to 46 are connected to the level shifter 3
In combination with 0, the switch circuits 41 and 42 are complementarily turned on,
A selection means for turning off is configured. The driver circuit, similarly to FIG. 2 showing a conventional circuit, PM0S and N
M0S and inverters 1, 2, 43-46
Is also composed of PM0S and NM0S, respectively.

As shown in parentheses in FIG. 1, each of the VDD type inverters 1 and 2 is formed so that the gate length of PM0S is 1 μm and the gate width is 10 μm (P10 / 1). . The gate length of NM0S is 1 μm, and the gate width thereof is 10 μm (N10 / 1). On the other hand, the inverters 43 to 46 are
This is a VUO system circuit that receives a voltage supply from the voltage VUO. The PM0S of the inverter 43 has a gate length of 1 μm and a gate width of 3 μm (P3 / 1), and the inverter NM0S has a gate length of 1 μm and a gate width of 3 μm (N3 / 1). . Inverter 4
5 is also similar to the inverter 43, the gate length of PM0S is 1 μm and the gate width is 3 μm (P3 / 1), and the gate length of NM0S of the inverter 45 is 1 μm and the gate width is 3 μm (N3 / 1). Has been formed.

The gate length of PM0S of the inverter 44 is 1
μm, and the gate width is 10 μm (P10 / 1), and the gate length of NM0S of the inverter 44 is 1 μm.
And the gate width is 5 μm (N5 / 1).
Similarly, the gate length of PM0S of the inverter 46 is 1μ.
m, and the gate width is 10 μm (P10 / 1), and the gate length of NM0S of the inverter 46 is 1 μm.
And the gate width is 5 μm (N5 / 1).
Each of the PM0Ss 31 and 33 in the level shifter 30 has a gate length of 30 μm and a gate width of 3 μm (3/30). Each of the NM0Ss 32 and 34 is formed to have a gate length of 1 μm and a gate width of 30 μm (30/1). PM0S41 of switch circuit 41
a has a gate length of 1 μm and a gate width of 50 μm (50
/ 1), the gate length of NM0S41b is 1μ
m, and the gate width is 30 μm (30/1). The PM0S 42a of the switch circuit 42 has a gate length of 1 μm and a gate width of 50 μm (50/1), and the NM0S 42b has a gate length of 1 μm and a gate width of 30 μm (30/1).

FIGS. 5 (i) to 5 (iii) are waveform charts showing the simulation result (1) of FIG.
Is a waveform of the logic signal S _in and the nodes N1 and N2 _in FIG. 1, FIG. (Ii) is an enlarged view of an E portion of FIG. (I), and (iii) is an enlarged portion of an F portion of FIG. Each figure is shown. 6 (i) to 6 (iii) are waveform charts showing the simulation result (part 2) of FIG. 1, FIG. 6 (i) shows the waveforms of the signals S43 to S46 in FIG. 1, and FIG. Same figure (i)
The enlarged view of the G portion of FIG. 3 and the enlarged view of (iii) of FIG. These FIG. 5 (i) to (iii)
The operation of the driver circuit of FIG. 1 will be described with reference to FIGS. 6 (i) to 6 (iii). A logic signal S _in generated by a logic circuit (not shown) is inverted by the inverter 1 and given to the gate of the MM0S32 of the level shifter 30 and also NM0S3 via the inverter 1 and the inverter 2.
It is given to the gate of 4. When the logic signal S _in that repeats “H” and “L” as shown _in FIG. 5 (i) rises from 0 [V] to 2 [V] as shown _in FIG. 5 (iii), each NMOS
The conduction states of 32 and 34 change according to the level of the logic signal S _in , and the voltages of the connection nodes N1 and N2 also change in opposite directions. As a result, the conduction state of each PM0S31, 33 also changes, and the voltage of the connection node N1 is 5 [V],
The voltage of the connection node N2 becomes 0 [V]. As shown in FIG. 5 (ii), when the logic signal S _in falls from 2 [V] to 0 [V], the conduction states of the NMOSs 32 and 34 are changed to the signal S.
It changes according to the level of _in , and the voltages of the connection nodes N1 and N2 also change in opposite directions. As a result, each PM0
The conduction states of S31 and S33 also change, and the voltage of the connection node N1 becomes 0 [V] and the voltage of the connection node N2 becomes 5 [V]. That is, the power supply voltage VUO and PM0S31 and NM0
The voltage of the connection node N1 is set by the conduction state of S32, and the power supply voltage VUO and PM0S33 and NM0S34 are set.
The voltage of the connection node N2 is set depending on the conduction state of, and the voltage swings at 0 to 5 [V].

The voltages at connection nodes N1 and N2 are applied to inverter 43 and inverter 45. Each connection node N
The timings of the voltage waveforms of 1 and N2 are deviated depending on whether they rise or fall, as shown in FIGS. 5 (ii) and (iii). Due to this timing shift, the timing at which the level of the output signal S43 of the inverter 43 is inverted and the timing at which the level of the output signal S45 of the output signal S45 of the inverter 45 is inverted are as shown in FIGS. 6 (ii) and (iii). It shifts. For example, when the voltage of the connection node N1 is 5 [V] and the voltage of the connection node N2 is 0 [V], the output signal S43 is 0 [V], the output signal S44 is 5 [V],
The output signal S45 is 5 [V], and the output signal S46 is 0.
The switch circuit 41 is turned on and the switch circuit 42 is turned off. Here, the logic signal S
_When the change of in occurs, first, the voltage of the connection node N1 starts the transition, the output signal S43 drops, and the output signal S
44 rises. As a result, the switch circuit 41 is turned off. After that, the voltage of the connection node N2 starts transition after the connection node N1 is delayed. This transition causes the output signal S45 to fall and the output signal S46 to rise, turning on the switch circuit 42. That is, an OFF-OFF section occurs in which both the switch circuits 41 and 42 are both turned off.

When the voltage of the connection node N1 is 0 [V] and the voltage of the connection node N2 is 5 [V], the output signal S43 is 5 [V], the output signal S44 is 0 [V], and the output signal S45. Is 0 [V] and the output signal S46 is 5 [V], the switch circuit 41 is off and the switch circuit 42 is on. Here, when the change of the logic signal S _in occurs, first, the voltage of the connection node N2 starts the transition, the output signal S46 drops and the output signal S45 rises. As a result, the switch circuit 42 is turned off. After that, the voltage of the connection node N1 changes to the connection node N2.
The transition is started later. This transition causes the output signal S
The output signal S44 rises as 43 falls, and the switch circuit 41 is turned on. That is, both switch circuits 4
An OFF-OFF section occurs in which both 1 and 42 are turned off.
When the switch circuit 41 is turned on, the output node Nou
t is connected to the power supply voltage VUO, and the power supply voltage VUO is output via the output terminal OUT. When the switch circuit 42 is turned on, the output node Nout is connected to the ground GND, and the voltage of the ground GND is output via the output terminal OUT.

As described above, in the first embodiment,
Inverters 45 and 46 connected to the connection node N2 are provided, and output signals S45 and S46 of the inverters 45 and 46 are provided.
The switching circuit 42 is switched by. Therefore, when the level of the logic signal S _in transitions, consist timing shift due to different voltage waveform at the connection node N1, N2, to set the OFF-OFF period of the switch circuits 41 and 42 are both turned off, through The current can be prevented. Moreover, two inverters 45 and 4 are added to the circuit of FIG. 2 showing the conventional circuit .
Since it is only 6, it does not develop into a layout problem.

( Second Embodiment ) FIG. 7 is a configuration diagram of a driver circuit showing a second embodiment of the present invention. This driver circuit is a circuit that is provided at the output stage of the driver IC and outputs the power supply voltage VUO and the voltage of the ground GND as drive voltages. The driver circuit outputs the logic signal S _in generated by a logic circuit (not shown) to the inverter 1 and it. It is provided with a level shifter 50 which inputs through the inverter 2 in series and converts the voltage with the power supply voltage VUO, a switch circuit 61 and a switch circuit 62. The inverters 1 and 2 have the same power supply voltage V as in the first embodiment.
It is a VDD system circuit that operates by receiving voltage supply from DD. The level shifter 50 is similar to the level shifter 30 of the first embodiment, and has the power supply voltage VUO and the ground GND.
And PMOS51 and NM0S5 connected in series between
2 between the power supply voltage VUO and the ground GND.
PM connected in parallel with MOS51 and NM0S52
0S53 and NM0S54. PM0S5
1 and NM0S52, the first connection node N1 is PM0
The PM0S53 and NM0S are connected to the gate of S53.
The second connection node N2 between 54 is connected to the gate of the PMOS 51. The switch circuit 61 is PM0S6.
It is composed of a transfer gate composed of 1a and NM0S61b, and is connected between the power supply voltage VUO and the output node Nout. The output node Nout is the output terminal OU
It is connected to T. The output terminal of the first inverter 63 is connected to the gate of the PM0S61a. NM
The gate of 0S61b, the output terminal of the inverter 64 connected to the output terminal of the inverter 63 is connected.

On the other hand, the switch circuit 62 is PM0S62.
It is composed of a transfer gate composed of a and NM0S62b, and is connected between the ground GND and the output node Nout. The output terminal of the second inverter 65 is connected to the gate of NM0S62b, and the PMOS 62a
The output terminal of the inverter 66 connected to the output terminal of the inverter 65 is connected to the gate of the. Inver
Output signals S6 from the output signals 63, 64, 65 and 66, respectively.
3, S64, S65, S66 are output. The inverters 63 and 65, together with the level shifter 50, constitute a selection means for selecting the switch circuits 61 and 62, and output signals S63 and S6 of the respective inverters 63 and 65.
5 is a first and a second for selecting the switch circuits 61 and 62.
Selection signal. Unlike the first embodiment, the input terminals of the inverters 63 and 65 are both connected to the connection node N.
Connected to 1.

Here, an example of forming a transistor in the driver circuit will be described. As shown in FIG. 7, the gate length of PM0S forming each of the VDD-based inverters 1 and 2 is 1 μm.
m and the gate width are 10 μm (P10 / 1), NM
The gate length of 0S is 1 μm and the gate width is 10 μm (N1
0/1). On the other hand, the inverters 63 to 66
Is a VUO system circuit that receives a voltage supply from the power supply voltage VUO. The gate length of PM0S of the inverter 63 is 3μ
m, and gate width are formed on 3μm (P3 / 3), the gate length of NM0S of the inverter 63 is 1 [mu] m, and gate width are formed on 3μm (N3 / 1). The PM0S of the inverter 64 has a gate length of 1 μm and a gate width of 10 μm (P10 / 1).
4 NM0S has a gate length of 1 μm and a gate width of 5 μm
m (N5 / 1). The inverter 65 is
Unlike the first embodiment, it is not the same as the inverter 63, the PM0S has a gate length of 1 μm, and a gate width of 3
μm (P3 / 1), the NM of the inverter 65
The gate length of 0S is 3 μm, and the gate width is 3 μm (N3
/ 3). The gate length of PM0S of the inverter 66 is 1 μm, and the gate width is 10 μm (P10 /
The gate length of NM0S of the inverter 66 is 1 μm and the gate width is 5 μm (N5 / 1).

Each PM0S 51, 5 in the level shifter 50
Similar to the first embodiment, the gate length of 3 is 30 μm, and the gate width is 3 μm (3/30). The gate length of each NM0S 52, 54 is 1 μm, and the gate width is 30 μm (30/1). The PM0S51a of the switch circuit 51 has a gate length of 1 μm and a gate width of 50 μm (50/1), and the NM0S51b has a gate length of 1 μm and a gate width of 30 μm (30/1). Switch times
The PM0S52a of the path 52 is formed to have a gate length of 1 μm and a gate width of 50 μm (50/1).
b has a gate length of 1 μm and a gate width of 30 μm (30
/ 1).

FIGS. 8 (i) to 8 (iii) are waveform charts showing the simulation result (1) of FIG. 7, and FIG.
7 is a waveform of the logic signal S _in and the node N1 _in FIG. 7, FIG. 7 (ii) is an enlarged view of portion J in FIG. 7 (i), and FIG. 7 (iii) is an enlarged view of portion K in FIG. 7 (i). Shown respectively. Figure 9
(I) to (iii) are waveform charts showing the simulation result (part 2) of FIG. 7, and FIG.
The waveforms 63 to S66, FIG. 7 (ii) shows an enlarged view of the L part in FIG. 7 (i), and FIG. 13 (iii) shows an enlarged view of the M part in FIG. 8 (i) to (iii) and FIG.
The operation of the driver circuit of FIG. 7 will be described with reference to (i) to (iii). The logic signal S _in generated by a logic circuit (not shown) is inverted by the inverter 1 and applied to the gate of the MM0S52 of the level shifter 50, and also to the gate of the NM0S54 via the inverter 1 and the inverter 2. When the logic signal S _in rises from 0 [V] to 2 [V] as shown _in FIG. 8 (ii), each NMOS 5
The conduction states of Nos. 2 and 54 change according to the level of the logic signal S _in , and the voltages of the connection nodes N1 and N2 also make transitions in the opposite directions. As a result, the conduction state of each PM0S 51, 53 also changes, and the voltage of the connection node N1 becomes 5 [V] and the voltage of the connection node N2 becomes 0 [V]. Logic signal S
_{When in} falls from 2 [V] to 0 [V], each NMOS
The conduction states of 52 and 54 change according to the level of the signal S _in , and the voltages of the connection nodes N1 and N2 also change in the opposite directions. As a result, the conduction state of each PM0S 51, 53 also changes, and the voltage of the connection node N1 becomes 0 [V] and the voltage of the connection node 2 becomes 5 [V]. That is, the power supply voltage VUO
And the conductive state of PM0S51 and NM0S52 set the voltage of the connection node N1, and the voltage of the connection node N1 is 0.
The voltage swings at about 5 [V].

The voltage of connection node N1 is applied to inverter 63 and inverter 65. The voltage of the connection node N1 rises and falls like the waveforms of FIGS. 8 (ii) and 8 (iii). For example, when the voltage of the connection node N1 is 5 [V] and the voltage of the connection node N2 is 0 [V], the output signal S63 is 0 [V] and the output signal S64 is
Is 5 [V], the output signal S65 is 0 [V], and the output signal S66 is 5 [V], the switch circuit 61 is on and the switch circuit 62 is off. At this time, when the logic signal S _in transitions, first, the transition of the voltage of the connection node N1 toward 0 [V] is started. Inverter 63
And the inverter 65 are different in the sizes of PM0S and NM0S forming them, that is, the gate width and the gate length are different. Therefore, the inverter 63 detects the fall of the voltage of the connection node N1 faster than the inverter 65, and outputs the signal S63 that transits to “H”. As a result, the output signal S64 of the inverter 64 also becomes "L", and the switch 61 is turned off. After that, the inverter 65
Detects the fall of the connection node N1 and outputs the output signal S65 which has transited to "H". As a result, the output signal S66 of the inverter 66 also becomes "L", and the switch circuit 6
2 is turned off. Therefore, both switch circuits 6
An OFF-OFF section occurs in which both 1 and 62 are turned off.

[0026] When the voltage of the mains voltage at the connection node N1 is at 0 [V] Roh <br/> over node N2 is in a state of 5 [V], the output signal S63 is 5 [V], the output signal S64 is 0 [ V], the output signal S65 is 5 [V], and the output signal S66 is 0 [V], the switch circuit 61 is off and the switch circuit 62 is on. At this time, when the logic signal S _in transitions, the voltage of the connection node N1 starts transitioning toward 5 [V]. The inverter 63 and the inverter 65 are
The size of PM0S and NM0S that compose them is different.
Since that, the inverter 6 5 outputs a signal S65 that transition the rise of the voltage at the connection node N1 inverter 63 Restaurant faster detection to the "L". This allows the inverter 66
Output signal S66 also goes to "H", and the switch 62 is turned off. After that, the inverter 63 is connected to the connection node N1.
Of rising edge of output signal S6
3 is output. Thus, the output signal S of the inverter 64
64 also becomes "H", and the switch circuit 61 is turned off. Therefore, an OFF-OFF section occurs in which both switch circuits 61 and 62 are both turned off. When the switch circuit 61 is turned on, the output node Nout changes to the power supply voltage VUO.
And the power supply voltage VUO is output via the output terminal OUT. When the switch circuit 62 is turned on, the output node Nout is connected to the ground GND, and the voltage of the ground GND is output via the output terminal OUT.

As described above, in the second embodiment,
An inverter 63 is connected to the connection node N1 of the level shifter 50,
65 is connected to the output signals S6 to the switch circuits 61 and 62.
3, S65 while to give, the inverter 6
Since the sizes of the PMOS and NM0S constituting the circuits 3, 65 are changed, the switch circuits 61, 62 are turned OFF-OF.
It can be turned on and off so that the F section occurs. Therefore, it is possible to prevent harmful through current, Ki de simply by adding two inverters driver circuit does not flow through-current in the conventional circuit, there is no layout problem.

The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) Each switch circuit 41, 42, 61, 62 has a P
M0S41a, 42a, 61a, 62a and NM0S41
Although the transfer gates b, 42b, 61b, and 62b are used, it is also possible to use only one switching element, for example, NM0S41b, 42.
b, 61b and PM0S62a may be omitted. In this case, the inverters 44, 46, 64, 66 become unnecessary. (2) In the second embodiment, the level shifter 50 and the inverters 63 to 66 constitute the selection means. However, as in the first embodiment, the selection means is turned off based on the deviation of the voltage transition of the two connection nodes N1 and N2. Since the -OFF section is not set, the voltage corresponding to the logic signal S _in can be changed to another voltage output means generated from the connection node N1 instead of the level shifter 50. For example, instead of the level shifter 50, a voltage output unit that shapes the waveform of the logic signal S _in with the power supply voltage VUO may be used.

[0029]

As described in detail above, according to the present invention.
Then, the first inverter composed of PMOS and NMOS
The data and the PMOS and NMOS have different sizes.
A second inverter composed of PMOS and NMOS,
The first switch circuit and the second switch
Turn the circuit on and off so that there is an OFF-OFF section.
The first power supply voltage, the output node, and the
It is possible to prevent a through current between the two power supply voltages. This
As a result, it is possible to reduce the number of elements
The harmful fluctuation of the power supply voltage can be prevented. Besides, the driver times
Reduces unnecessary shoot-through current in the level shifter
The entire driver circuit, and further the driver of the present invention
It is possible to reduce the overall power consumption of a display device equipped with a circuit.
You can

[Brief description of drawings]

FIG. 1 is a configuration diagram of a driver circuit showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional driver circuit.

FIG. 3 shows a simulation result (1) of FIG.
It is a waveform diagram.

FIG. 4 shows a simulation result (2) of FIG.
It is a waveform diagram.

5 is a waveform chart showing the simulation result (1) of FIG.

FIG. 6 is a waveform chart showing the simulation result (2) of FIG.

FIG. 7 is a configuration diagram of a driver circuit showing a second embodiment of the present invention.

FIG. 8 is a waveform chart showing the simulation result (1) of FIG. 7.

FIG. 9 is a waveform chart showing the simulation result (2) of FIG. 7.

[Explanation of symbols]

30, 50 Level shifter 31, 33, 51, 53 PM0S 32, 34, 52, 54 NM0S 41, 42, 61, 62 Switch circuit 43-46, 63-66 Inverter S _in Logic signal VUO Power supply voltage

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 17/00 H03K 19/00

Claims (3)

(57) [Claims] 1. A voltage corresponding to an input logic signal.
, A P-channel type MOS transistor and an N-channel type NM
Of the first connection node
A first invar for detecting a voltage and outputting a first selection signal
And a P-channel MO that constitutes the first inverter.
S-transistor and N-channel NMOS transistor
P-channel type MOS transistor with different size from the star
And an N-channel type NMOS transistor,
The second selection signal is detected by detecting the voltage of the first connection node.
A second inverter that outputs and an output that outputs the first power supply voltage or the second power supply voltage
A node between the first power supply voltage and the output node.
ON state or OFF state according to the first selection signal
Is connected between the first switch circuit and the second power supply voltage and the output node.
ON state or OFF state according to the second selection signal
And a second switch circuit that
Driver circuit. 2. The P which constitutes the first inverter.
The gate length of the channel type MOS transistor and the second
The P-channel type MOS transistor forming the inverter
The gate length of the star is different, and the N-channel type NM that constitutes the first inverter.
The gate length of the OS transistor and the second inverter
A gate of the N-channel type NMOS transistor constituting
The dry length according to claim 1, wherein the dry length is different.
Bus circuit. 3. The level shifter has a connection between the first connection node, a second connection node, and the first power supply voltage and the first connection node.
And the control electrode is connected to the second connection node.
The first transistor of the first conductivity type is connected between the first connection node and the ground,
The first conductive material to which the logic signal is input to the control electrode
A second transistor of a second conductivity type complementary to the second type and a connection between the first power supply voltage and the second connection node.
And the control electrode is connected to the first connection node
A third transistor of the first conductivity type is connected between the second connection node and the ground.
The reverse phase signal of the logic signal is input to the control electrode.
And a fourth transistor of the second conductivity type
The driver circuit according to claim 1, wherein: