JP3388542B2 - Exposure method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure method for a semiconductor wafer in a semiconductor device manufacturing process, and more particularly to measuring alignment marks in a plurality of exposure shots of a wafer and statistically processing position errors. , A global alignment exposure method for determining the position of each field and exposing.

[0002]

2. Description of the Related Art Global alignment is currently generally used as a method for aligning a reticle pattern with a pattern formed on a wafer.

The procedure of global alignment is as follows. Normally, about 8 to 20 alignment measurement shots are designated from all shots formed on the wafer, the wafer alignment mark positions formed in those shots are measured by the alignment optical system, and the wafer from the design value is measured. Alignment measurement shot alignment error Δx
1 to Δxn and Δy1 to Δyn are obtained. From these, a shot array correction value that minimizes the shot array expansion / contraction amount / rotation amount / offset error for the entire wafer is obtained using a statistical method such as the least square method. At the time of exposure of each shot, the position of the XY stage is corrected by the shot arrangement correction value calculated above.

[0004]

However, at present, one specific underlayer is used for the wafer alignment mark measurement, but the alignment accuracy often becomes very poor due to the difference in the underlayer film thickness between lots. There are cases.

An object of the present invention is to provide an exposure method in which stable alignment accuracy is obtained, and the alignment accuracy is not deteriorated due to the difference in the underlayer film thickness between lots and the like, resulting in a decrease in product yield. It is in.

[0006]

According to a first exposure method of the present invention, a substrate in which first alignment marks for position detection are regularly arranged in a matrix in a vertical and horizontal direction according to a predetermined rule is used as a first layer. When the first material film deposited on the layer and having the second alignment mark arranged at a position different from the first alignment mark according to the predetermined rule is the second layer, and n is an integer of 3 or more, Depositing on the (n-1) th layer,
-1) A chip array substrate having an (n-1) th material film having an nth alignment mark at a position different from the alignment mark as an nth layer is prepared, and the mask of the nth layer is provided over the entire chip array substrate. In performing exposure for forming a pattern for each exposure shot, a plurality of exposure shots are selected in advance as sampling exposure shots, and a lower layer below the nth layer in the sampling exposure shots. Among them, at least one layer is the detection target layer, the position of the alignment mark of the detection target layer is detected to obtain the alignment error of the chip array substrate , and a plurality of the lower layers are selected to select the target layer. Alignment of the selected layer as a selected layer Detecting the position of the mark seeking alignment errors of the chip sequence substrate, moving, exposing the chip sequence substrate based on the correction value for correcting the sequence error
An exposure method, which comprises aligning the selected layer
Alignment of the chip array board by detecting the position of the
The step of obtaining the column error is performed by first selecting the selected layer.
The alignment mark of the uppermost layer
To obtain the first arrangement error of the chip arrangement board,
The first residual error after removing the linear component of the first array error.
When the random alignment error is within the reference alignment accuracy
Is the first array error, and the first residual error is corrected data.
When the random alignment error exceeds the standard alignment accuracy
Puts the selected layer directly under the top layer
Each layer is selected from the layer up to the bottom layer
The residual random alignment error in the layer is
As long as it exceeds the
And each of the selected layers has a selected layer.
The position of the alignment mark
Obtain the second array error of the substrate and the second residual random array error
Therefore, the second residual random array error is the reference alignment.
When it falls within the precision, the second residual random array
The selected item whose error is within the standard alignment accuracy
Use the second array error in the layer as correction data
It is characterized by being a process .

The second exposure method of the present invention is for position detection.
Align the first alignment mark vertically and horizontally according to the prescribed rules.
The substrate that is regularly arranged repeatedly is used as the first layer, and
The first alignment mark deposited on the first layer
The second array arranged in a position different from
The first material film having the alignment mark as the second layer
Then, sequentially, when n is an integer of 3 or more, the (n-
1) Deposition on the layer, the (n-1) th alignment
The n-th alignment mark at a position different from the mark
Chip array with the (n-1) th material film as the nth layer
A substrate is prepared, and the chip array substrate is entirely covered by the first substrate.
Exposing the exposure to form the n-layer mask pattern
Before performing each light shot, the exposure shot
Select multiple exposure shots from the
As a light shot, the sampling exposure shot
The lower layer below the nth layer.
Then, at least one layer is the detection target layer
The alignment mark of the detection target layer
Position to detect the array error of the chip array board.
So, select multiple layers from the lower layers
The selected layer is an array that the selected layer has
Of the chip array board by detecting the position of the
The array error is calculated and based on the correction value for correcting the array error.
And an exposure method for moving and exposing the chip array substrate.
The alignment mark of the selected layer
Position to detect the array error of the chip array board
The first step is to select the top layer of the selected layers.
The alignment mark of the layer is detected and the
Find the first array error for the exposure device of the array substrate,
The first residual after removing the linear component of the first array error.
Random sequence error is within the standard alignment accuracy
In this case, the first array error is used as correction data and the first residual error
When the residual random sequence error exceeds the standard alignment accuracy
The selected layer directly above the top layer.
From the bottom layer to the bottom layer, the bottom layer
Move to the layer of
Detects the position of the alignment mark of the selected layer
Then, the array error of the chip array substrate is calculated, and the lower layer
In the process of moving to the
Before the alignment mark of the uppermost layer
Through the serial sequence error of the first alignment errors and the each the selected layer chromatography
The total residual random array error when calculated is the reference error.
The total array when it falls within the
The process is characterized in that an error is used as correction data.

The third exposure method of the present invention is for position detection.
Align the first alignment mark vertically and horizontally according to the prescribed rules.
The substrate that is regularly arranged repeatedly is used as the first layer, and
The first alignment mark deposited on the first layer
The second array arranged in a position different from
The first material film having the alignment mark as the second layer
Then, sequentially, when n is an integer of 3 or more, the (n-
1) Deposition on the layer, the (n-1) th alignment
The n-th alignment mark at a position different from the mark
Chip array with the (n-1) th material film as the nth layer
A substrate is prepared, and the chip array substrate is entirely covered by the first substrate.
Exposing the exposure to form the n-layer mask pattern
Before performing each light shot, the exposure shot
Select multiple exposure shots from the
As a light shot, the sampling exposure shot
The lower layer below the nth layer.
Then, at least one layer is the detection target layer
The alignment mark of the detection target layer
Position to detect the array error of the chip array board.
So, select multiple layers from the lower layers
The selected layer is an array that the selected layer has
Of the chip array board by detecting the position of the
The array error is calculated and based on the correction value for correcting the array error.
And an exposure method for moving and exposing the chip array substrate.
The alignment layer of the selected layer
Position to detect the alignment error of the chip array board.
All layers of the selected layer are
Align the position of the alignment mark on the selected layer.
Start from the top layer and sequentially detect each layer until reaching the bottom layer.
To obtain the array error of the chip array board for each layer.
Line formation of the array error obtained for each layer.
The residual random array error after removing
Element accuracy, it was calculated for each layer.
The smallest residual random array error among the array errors is obtained.
This is the process of using the array error of the layer to be corrected data.
It is characterized by

In the above-described exposure method, the residual random array error is the absolute value of the vector when the deviation of the position of the alignment mark that the selected layer has for each sampling exposure shot from the exposure device is expressed by a vector. The coordinate of the alignment mark which is obtained by the non-linear component of the value and which is included in the selected layer is designated for each layer.

[0010]

[0011]

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A feature of the exposure method of the present invention is that the overlay accuracy is improved by automatically searching for a base layer that provides the desired wafer alignment mark measurement accuracy.

Next, a first embodiment of the present invention will be described with reference to FIGS.
Will be described with reference to.

FIG. 1 is a flowchart showing an exposure method according to an embodiment of the present invention. FIG. 2 is a top view showing positions on the wafer of alignment shots to be detected when measuring the alignment marks. Also, FIG.
FIG. 2 is a schematic cross-sectional view for explaining “measurement layer candidates” shown in the flowchart of FIG. 1.

Before explaining the exposure method of this embodiment,
The “measurement layer candidate” will be described with reference to FIGS.

First, as shown in FIG. 2A, a wafer 1 is prepared, and in this example, 10 alignment shots 2 are selected as shown by the hatched portion. Each alignment shot 2
2 has an alignment mark 4 at a position of coordinates (X, Y) with reference to the alignment shot center 3 as shown in the enlarged view of FIG.

Next, the vertical structure of the wafer 1 in the alignment shot 2 is as shown in the schematic sectional view of FIG. Here, as an example, a silicon substrate 5, a nitride film 6, a gate polysilicon film 7, a BPSG interlayer film 8 and a resist 9 are deposited in this order from the bottom to form first to fifth layers. The first to fourth layers below the fifth layer each have an alignment mark, and
~ 1st AM (abbreviation of alignment mark) 10, 2nd AM 11, 3rd AM 1 corresponding to each 4th layer
2 and the fourth AM 13 .

Here, before transferring the mask pattern to the resist 9 which is the uppermost fifth layer, it is necessary to correct the position of the wafer 1 with respect to the exposure apparatus. However, in order to obtain the position correction data, the alignment mark is obtained. (Hereinafter, Al
In measuring the alignment mark), the BPSG interlayer film that is the fourth layer immediately below the resist 9 that is the fifth layer (the fifth layer is abbreviated as L5; the same applies below) is used to measure the alignment mark. 8 (L4) alignment mark, 4th AM
13 is set as the first candidate for alignment mark detection, and the gate polysilicon film 7 (L3) is sequentially formed in the lower layer.
, The third AM12 is a second candidate, the nitride film 6 (L2) is an alignment mark, the second AM11 is a third candidate, the silicon substrate 5 (L1) is an alignment mark, and the first AM10 is a fourth candidate. In the above method, n shown in FIG. 1 is the case of n = 4, but the present invention is not limited to the above method, and n =
The case of 3 is also possible. That is, the BPS under the resist 9
Of the G interlayer film 8, the gate polysilicon film 7, the nitride film 6 and the silicon substrate 5, three layers of the BPSG interlayer film 8, the gate polysilicon film 7 and the silicon substrate 5 are selected to be the BPSG interlayer which is the fourth layer. The alignment mark of the film 8, the fourth AM 13 as the first candidate, the alignment mark of the gate polysilicon film 7 that is the third layer, the third AM12 of the second candidate, the alignment mark of the silicon substrate 5 that is the first layer, 1st AM1
It goes without saying that a method of setting 0 as the third candidate is also possible.

In the exposure method of this embodiment, as shown in the flow chart of FIG. 1, first, a layer to be measured for alignment marks on a wafer is selected and a candidate order of the selected layers L1 to Ln is designated. Every
Starting from the position measurement of the alignment mark of the nth layer, the measurement result of the alignment mark in the x-axis direction and the measurement result of the y-axis direction are the respective allowable values Ax and Ay set in advance.
If it is larger than the above, the n-th layer is determined to be unsuitable, and the algorithm proceeds to position measurement of the alignment mark of the next (n-1) -th layer. Exposure is performed.

The exposure method of this embodiment will be described in more detail below.

First, prior to alignment exposure, required alignment accuracy in global alignment (for example, residual random array error 3σ <25n for both x and y).
m) is specified. Further, the first candidate of the alignment measurement layer is the nth layer, the second candidate is the (n-1) th layer, ... (For example, the nth layer is a BPSG interlayer film process, and the (n-1) th layer is a gate poly. Silicon process). Alignment shots, mark coordinates, etc. are also specified.

Next, the first candidate nth layer (Ln)
Mark measurement. Mark measurement (10 shots in FIG. 2) of all designated alignment shots is performed to measure the amount of positional deviation of the alignment mark from the exposure device in the x-axis direction and y-axis direction, Δx (Ln), Δy (Ln). Then, using the method of least squares, Δ for all alignment shots
The absolute value of the vector component of the alignment error obtained from x (Ln) and Δy (Ln) is calculated, and the residual random array error 3σ (alignment accuracy), which is a non-linear component obtained by removing the linear component of these absolute values, is obtained.

If this satisfies the required alignment accuracy designated by, the alignment mark measurement after the (n-1) th layer (L (n-1)) of the second candidate is omitted and the nth candidate of the first candidate is omitted. The shot array is corrected by using the shot array correction values such as offset and scaling calculated in the layer (Ln) layer, and exposure is performed.

When the alignment accuracy of the nth layer (Ln) of the first candidate is insufficient, the (n-1) th layer of the second candidate is selected.
Mark measurement of the layer (L (n-1)) is performed. Second
(N-1) layer alignment accuracy, or
If the alignment accuracy when using the measurement results of all the second candidate layers satisfies the required alignment accuracy
(If the both are satisfied, of course, the better result may be used). The alignment mark measurement of the third and subsequent (n−2) th layers is omitted, and the shot arrangement is corrected and exposure is performed. The above process may be followed when proceeding to the measurement on and after the (n−2) th layer of the third candidate.

The above-mentioned processes (1) to (3) will be illustrated below with more concrete numerical values.

The required alignment accuracy is designated as residual random array error 3σ ≦ 25 nm for both x and y. In the nth layer of the first candidate, 3σx = 40 nm, 3σy = 45 nm
Therefore, the required alignment accuracy was not satisfied. Therefore, the process proceeds to the (n-1) th layer of the second candidate. Second (n-
1) In the layer, 3σx = 20 nm, 3σy = 30 nm
Therefore, the required alignment accuracy was not satisfied again.
Therefore, the process proceeds to the (n-2) th layer of the third candidate. The (n
-2) In the layer, 3σx = 15 nm, 3σy = 20n
Since m is satisfied and the required alignment accuracy is satisfied, the alignment is corrected and exposure is performed based on the alignment error data of the (n−2) th layer.

In the above, the case where the alignment mark of the selected measurement layer is measured and the required alignment accuracy is finally satisfied has been described. However, when the required alignment accuracy is not finally satisfied, the following process is followed. .

The exposure is performed by correcting the shot arrangement using the correction value of the layer having the smallest residual random arrangement error in the calculation results up to that point (the apparatus may notify the operator by issuing an alarm or message). .

Although the exposure method in the step-and-repeat type or step-and-scan type projection exposure apparatus has been described in the above embodiment, the present invention is not limited to this embodiment, and other than this embodiment,
Needless to say, it can be applied as it is to an electron beam exposure apparatus, an X-ray exposure apparatus, a defect inspection apparatus, a defect correction apparatus, an overlay deviation measurement apparatus, or any other apparatus that needs to position a wafer on which a large number of shots have been formed. is there.

[0030]

As described above, according to the exposure method of the present invention, a plurality of layers under the resist to be exposed are measured, and the alignment marks of those layers are measured and obtained from the measured values. Since the position of the wafer with respect to the exposure device is corrected based on the correction value obtained, better alignment accuracy can be obtained and the overlay accuracy is greatly improved compared to the wafer position correction method that targets a single layer under the resist. To do.

[Brief description of drawings]

FIG. 1 is a flowchart showing an exposure method according to an embodiment of the present invention.

FIG. 2 is a schematic top view showing alignment shots and alignment marks for explaining an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing a layer to be measured in the exposure method of the embodiment of the present invention.

[Explanation of symbols]

1 wafer 2 Alignment shot 3 Alignment shot center 4 alignment marks 5 Silicon substrate 6 Nitride film 7 Gate polysilicon film 8 BPSG interlayer film 9 Resist 10 1st AM (alignment mark) 11 2nd AM (alignment mark) 12 3rd AM (alignment mark) 13 4th AM (alignment mark)

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/027 G03F 9/00

Claims (4)

(57) [Claims] 1. A substrate in which first alignment marks for position detection are regularly arranged in a matrix in the vertical and horizontal directions according to a predetermined rule is used as a first layer, and the first layer is deposited on the first layer and is at a position different from the first alignment mark. The first material film having the second alignment marks arranged according to the predetermined rule as the second layer, and when n is an integer of 3 or more in sequence, the first material film is deposited on the (n-1) th layer, and A chip array substrate having an (n-1) th material film having an nth alignment mark at a position different from the (n-1) th alignment mark as an nth layer is prepared, and the nth array substrate is entirely covered by the nth array substrate. When performing the exposure for forming the mask pattern of the layer for each exposure shot, a plurality of exposure shots are selected in advance from the exposure shots and the sampling A ring exposure shot, and in the sampling exposure shot, at least one layer of the lower layers lower than the nth layer is set as a detection target layer, and the position of an alignment mark included in the detection target layer is detected to detect the chip arrangement. The array error of the substrate is obtained, a plurality of layers among the lower layers are selected as a selected layer, the position of the alignment mark of the selected layer is detected to obtain the array error of the chip array substrate, and the array An exposure method for moving and exposing the chip array substrate based on a correction value for correcting an error , wherein the selected layer is
The chip by detecting the position of the alignment mark
The step of obtaining the array error of the array substrate is performed by first selecting the selected
Alignment of the top layer of the layers
The first alignment error of the chip array substrate by detecting the mark
After removing the linear component of the first array error
The first residual random alignment error of is less than the reference alignment accuracy.
If it is within the range, the first array error is used as correction data,
Note that the first residual random alignment error increases the reference alignment accuracy.
When it exceeds, the selected layer is moved to the top layer.
From the layer directly below the layer to the bottom layer.
And the residual random array error in each selected layer is
Subsequent layers as long as the reference alignment accuracy is exceeded
Move to the selected layer and select the selected layer for each selected layer.
The position of the alignment mark of the
Second array error of the chip array substrate and second residual random array
The column error is calculated, and the second residual random array error
If it falls within the alignment accuracy,
Random alignment error is within the standard alignment accuracy
The correction data for the second array error in the selected layer is corrected.
An exposure method comprising the steps of: 2. A first alignment mark for position detection
A group that is regularly arranged vertically and horizontally according to a predetermined rule.
The plate as the first layer, and depositing on the first layer,
The predetermined alignment is provided at a position different from the first alignment mark.
Has a second alignment mark arranged according to a rule
The first material film is used as the second layer, and n is sequentially adjusted to 3 or more.
In terms of the number, it is deposited on the (n-1) th layer,
At a position different from the (n-1) th alignment mark,
The (n-1) th material film having the n alignment mark
Prepare a chip array substrate for n layers
The mask pattern of the nth layer over the entire array substrate
Exposure for each exposure shot
In advance, a plurality of exposure shots of the exposure shots are
Select a sampling exposure shot and
Below the nth layer in pulling exposure shot
At least one of the lower layers in the layer
Is the detection target layer, and the detection target layer is
Position of the alignment mark
Calculate the array error of the row board and
Select the layer to be the selected layer,
By detecting the position of the alignment mark that the layer has
Obtaining the array error of the chip array substrate,
Move the chip array board based on the correction value
In the exposure method of exposing, the step of detecting the position of the alignment mark of the selected layer to obtain the alignment error of the chip array substrate is performed by first aligning the alignment of the uppermost layer of the selected layers. When a first array error of the chip array substrate with respect to the exposure apparatus is detected by detecting marks and a first residual random array error after removing a linear component of the first array error is within a reference alignment accuracy, When the first sequence error is used as the correction data and the first residual random sequence error exceeds the reference alignment accuracy, the selected layer is sequentially arranged from the layer immediately below the top layer to the bottom layer. Move to the layer and change the position of the alignment mark of the selected layer for each selected layer. Then, in the process of obtaining the alignment error of the chip array substrate and moving to the lower layer, the first alignment error of the alignment mark of the uppermost layer of the selected layers and the alignment of each selected layer. An exposure method , characterized in that, when the total residual random array error when the errors are added is within the reference alignment accuracy, the total array error is used as correction data. 3. A first alignment mark for position detection
Were regularly arrayed vertically and horizontally according to a predetermined rule
The substrate is the first layer and is deposited on the first layer
However, the location is different from the first alignment mark.
Has a second alignment mark arranged according to a fixed rule
The first material film is used as the second layer, and n is 3 or more sequentially.
Is deposited on the (n-1) th layer.
At a position different from the (n-1) th alignment mark
(N-1) th material film having the nth alignment mark on the
Prepare a chip array substrate with the n-th layer as
Of the mask layer of the n-th layer over the entire substrate.
To perform exposure to form turns for each exposure shot
Prior to the
Select a sampling exposure shot and select
In the sampling exposure shot, the nth layer
At least one of the lower layers
The ear is the detection target layer, and the detection target layer is
The position of the alignment mark of the
Of the lower layer of the lower layer
Select multiple layers to make them
Detects the position of the alignment mark of the selected layer
Then, the alignment error of the chip array substrate is calculated, and the alignment error
The chip array substrate is transferred based on the correction value to correct the difference.
In the exposure method of moving / exposing, the step of detecting the position of the alignment mark of the selected layer to obtain the alignment error of the chip array substrate includes the steps of positioning the alignment marks of all the layers of the selected layer. Is sequentially detected for each layer starting from the uppermost layer of the selected layer to the lowermost layer, the array error of the chip array substrate is obtained for each layer, and the linear component of the array error obtained for each layer is calculated. When all the residual random array errors after the removal exceed the reference alignment accuracy, it is a step of using the array error of the layer that provides the minimum residual random array error among the array errors obtained for each layer as correction data. An exposure method characterized by the above . 4. The residual random array error is a non-linear component of the absolute value of the vector when the deviation of the position of the alignment mark that the selected layer has for each sampling exposure shot from the exposure apparatus is represented by a vector. The exposure method according to claim 1, 2 or 3, which is obtained by