JP3388484B2 - Timing generator with malfunction / misconfiguration detection function - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing generator used in, for example, an IC tester for testing a semiconductor integrated circuit element (IC).

[0002]

2. Description of the Related Art FIG. 6 shows a schematic configuration of an IC test apparatus, particularly an apparatus for testing a memory IC. In the figure, TES indicates the entire IC test apparatus. IC test equipment TES is the main controller 1
1, pattern generator 12, timing generator 13, waveform formatter 14, logical comparator 15, driver group 1
6, an analog comparator group 17, a failure analysis memory 18, and the like.

The main controller 11 is generally composed of a computer system, and mainly a pattern generator 12 and a timing generator 1 are used in accordance with a test program prepared by a user.
3, the test pattern data is generated from the pattern generator 12, the test pattern data is converted into a test pattern signal having an actual waveform by the waveform formatter 14, and the test pattern signal is amplified by the logical amplitude reference voltage source. It is applied to the IC under test 19 through the driver group 16 and stored.

The response signal read from the IC under test 19 is compared with the reference voltage of the comparison reference voltage source in the analog comparator group 17 to determine whether or not it has a predetermined logic level (H logic voltage, L logic voltage). The signal determined to have the predetermined logic level is compared with the expected value output from the pattern generator 12 by the logical comparator 15, and if the expected value does not match, the read address is read. It is determined that the memory cell has a defect, the defective address is stored in the defect analysis memory 18 for each occurrence of the defect, and it is determined whether the defective cell can be relieved at the end of the test.

Here, the timing generator 13 is the I to be tested.
The timing for defining the rising timing and the falling timing of the waveform of the test pattern signal given to C19 and the strobe pulse timing for defining the logical comparison timing are generated by the logical comparator 15. Each of these timings is described in the test program created by the user, and is configured so that the IC 19 under test can be operated at the timing intended by the user and whether or not the operation is normal can be tested.

FIG. 7 shows a schematic structure of a timing generator conventionally used in an IC test apparatus. The timing generator shown in FIG. 7 is a timing generator that generates the timing of one system (for example, the timing that defines the rise and fall of the test pattern signal applied to one terminal). Therefore, the timing generator 13 shown in FIG. 6 is provided with a large number of timing generators shown in FIG. 7, and the main controller 11 sets the setting values for timing generation so that each timing generator generates various timings. Given that it works.

The timing generator shown in FIG. 7 includes the master clock MCL shown in FIG. 8A and this master clock MCL.
8B having a cycle that is an integer multiple of the cycle pulse PC. That is, the rising edge of the periodic pulse PC is used as the reference timing, and the timing pulses P ₁ , P ₂ , P ₃ ... Having the delay times T ₁ , T ₂ , T ₃ (FIG. 8C) designated from this reference timing are generated as the timing signals. 8D, the timing pulse P ₄ may be delayed from a certain reference timing over several cycles of the periodic pulse PC, as shown in FIG. .

In the case of the IC test apparatus TES, each delay time of each timing pulse P ₁ , P ₂ , P ₃ ... Or P ₄ is constructed so that it can be set with a resolution of, for example, 1 ns. Incidentally, one cycle of the master clock MCL is, for example, 1
The period of 6 ns and the period pulse PC is set to about 16 × 4 = 64 ns. The timing generator shown in FIG. 7 is provided with an integer delay circuit 13A on the front side, and this integer delay circuit 13A generates delay timing of a cycle that is an integral multiple of the cycle of the master clock MCL, and the master clock MCL on the rear side. It is configured by connecting a fraction delay circuit 13B for providing a fraction delay timing shorter than the cycle. Therefore, for example, when generating a delay timing delayed by 17 ns from the reference timing, the integer delay circuit 13A has a delay timing of 16 ns corresponding to one cycle of the master clock MCL.
And the integer delay circuit 13A gives a start pulse to the fraction delay circuit 13B at a timing delayed by 16 ns from the reference timing. The fraction delay circuit 13B gives a delay time corresponding to a fractional value (1 ns in this case) in the set delay time to the given start pulse, and outputs it to the output terminal O.
Output pulse to UT.

Therefore, the periodic pulse P is applied to the integer delay circuit 13A.
When C is given and its reference timing is given, a timing pulse is output to the output terminal OUT at a timing 17 ns after the reference timing. For this reason, for example, when the main controller 11 is set in each timing generator while the test program is being executed, the timing data is divided by the cycle of the master clock MCL to obtain the divisible integer value and the remainder fraction. The integer value is the integer delay circuit 13
A delay operation having an integer multiple of the synchronization of the master clock MCL is generated by performing an integer delay operation on A, and when the delay timing elapses, a start pulse is applied to the fraction delay circuit 13B.

The fractional delay circuit 13B cascade-connects a plurality of delay elements DY1 to DY4 having weighted delay times, for example, 1 ns, 2 ns, 4 ns, and 8 ns, and the delay elements DY1, DY2, DY3, DY4 are connected between the stages. Are connected to multiplexers MUX1, MUX2, MUX3, MUX4, and these multiplexers MUX1 to MUX4 are switched and controlled by a control circuit CONT according to a given fractional value to selectively set whether to pass delay elements DY1 to DY4. To obtain a desired delay time.

For example, when the fractional value is 1 ns, the multiplexer MUX1 is switched and controlled so as to select the input terminal A, and the other multiplexers MUX2 to MUX4 are controlled so as to select the input terminal B. The output start pulse is delayed by 1 ns and is output to the output terminal OUT. Multiplexer MUX
By switching 1 and MUX2 to the input terminal A and controlling the other multiplexers MUX3 and MUX4 to the input terminal B, the fraction delay circuit 13B becomes (1 + 2) ns.
Generates the delay timing of. Similarly, the fractional delay circuit 13B outputs 1 ns, 2 ns, 3 ns, 4 ns, 5 n
Delay timing can be generated with a resolution of 1 ns up to s, 6 ns, 8 ns, 9 ns, ... 15 ns.

FIG. 9 shows a schematic structure of an integer delay circuit 13A which has been conventionally used. The integer delay circuit 13A latches the count value of the master clock counter 21 that counts the number of master clocks MCL, and the count value latched by this latch circuit 22 is applied to one input terminal to set the setting. An integer value obtained by dividing the value (delay time) by the cycle of the master clock MCL is given to the other input terminal, and the adder 23 that outputs the sum of these values
Then, the addition result of the adder 23 is taken into the first stage register 24A every time the periodic pulse PC rises, and the periodic pulse P
A multi-stage shift register 24 that sequentially shifts to the register of the next stage for each supply of C, an addition value stored in the registers 24A, 24B, 24C of each stage of the multi-stage shift register 24 and a count value latched in the latch circuit 22. A plurality of comparators 25A, 25B, 25C for comparing the two, and a plurality of comparators 25A, 25B, 25C provided corresponding to each of the plurality of comparators 25A, 25B, 25C.
5A, 25B, 25C are provided with a gate signal for permitting output of the comparison result, and comparators 25A, 25B, 25C are provided.
When any one of them outputs a coincidence signal, the next periodic pulse PC
Until the input is made, comparison operation control means 26A, 26B, 26C for outputting a gate signal for preventing the comparison result from being output again from the comparator that has output the coincidence signal,
When any one of the comparators 25A, 25B and 25C detects a match, the output circuit 27 outputs a start pulse STP to the fraction delay circuit 13B.

In the example of FIG. 9, the shift register 29 for shifting the fractional value in the integer delay circuit 13A as well as the integer value is used.
The case where A, 29B, and 29C are provided is shown. That is, the fractional value is output from the main controller 11 shown in FIG. 6 together with the integer value and latched in the latch circuit 28. The latched fractional value is registered in register 2 in synchronization with the rising edge of the periodic pulse PC.
9A, 29B, and 29C are sequentially shifted in this order.

The main operation of the integer delay circuit 13A will be described below. The count value of the master clock MCL output by the master clock counter 21 is output in a multi-bit digital data type. The digital data is latched in the latch circuit 22 at the rising timing of the master clock MCL. Therefore, the latch circuit 22 is composed of 19 D-type flip-flops in this example, and the adder 2
3, shift registers 24A, 24B, 24C, comparator 2
5A, 25B, and 25C will be described as having a circuit structure for handling 20-bit digital data.

The master clock counter 21 is reset to 0 at the start of the test, and is explained as being reset to 0 for the sake of simplification of the explanation. With the start of the test, the master clock counter 21 is incremented by +1 at each rising timing of the master clock MCL. The count value is incremented by one and the number of master clocks MCL is continuously counted until the test is completed. That is, it can be considered that an address is assigned to the passage of time during the test.

In the test program prepared by the user, the delay time is set in the timing generator according to the address assigned in the time axis direction. This is shown in FIG.
In the example shown in FIG. 10, 64 ns is set in the cycles CU1 to CU4. As shown in FIG. 4D, the count value is # 0.
30n in the cycle CU1 starting with (# is a symbol that represents the count value)
s is set and the count value starts at # 4 and the cycle CU2 is 32.
ns, 38 ns for cycle CU3, 40 n for cycle CU4
The case where s is set is shown.

By setting the delay time in the test program in this manner, an integer value (1) of 30/16 = 1 is input to the input terminal A of the adder 23 at the start of the test, and the latch circuit 28 receives the integer value. The fractional value 14 ns is input.
At this point in time, since the count value # 0 has been fetched from the master clock counter 21 into the latch circuit 22, the adder 23
Adds the count value # 0 and the integer value (1), and the register 24A captures the addition result. As a result, the register 24A
The addition value (1) is stored in.

A comparator 25A compares the added value (1) stored in the register 24A with the count value fetched by the latch circuit 22. The count value becomes # 1 at the rising edge of the second cycle of the master clock MCL, and coincides with the added value (1) stored in the register 24A. When the coincidence is detected, the comparator 25A outputs an H logic signal to the AND gate AND ₁₁ . The other input terminal of the AND gate AND ₁₁ is supplied with the gate signal G1 from the comparison operation control means 26A. As shown in FIG. 10I, this gate signal G1 is H logic-inverted at the rising timing of the periodic pulse PC (when the periodic pulse PC rises to H logic, the multiplexer selects the input terminal B and the D type The flip-flop reads the H logic and inverts the gate signal G1 to the H logic.) The AND gate AND ₁₁ outputs the H logic coincidence detection signal A1. The coincidence detection signal A1 is output to the output terminal 31 through the output circuit 27 and is given to the fraction delay circuit 13B described in FIG. 7 as the start pulse STP. At this time, the fractional value is also output from the fractional output terminal 32 to the fractional output terminal 32 through the AND gate AND ₂₁ and the fractional output circuit 30, and is output from the fractional output terminal 32 to the fraction delay circuit 13B.

Match detection signal A output from the comparator 25A
1 matches the rising timing when the count value changes to # 1 as shown in FIG. 10H. Therefore, if the rising edge of the periodic pulse PC is used as the reference timing, the timing is a timing when a delay time (16 ns in this example) corresponding to one cycle of the master clock MCL has elapsed from this reference timing. The coincidence detection signal A1 is supplied to the inverting input terminal of the gate forming the comparison operation control means 26A. Therefore, the output of this gate is L while the coincidence detection signal A1 rises to H logic.
Output logic. As a result, since the D-type flip-flop reads this L logic through the multiplexer at the rising timing of the master clock MCL, the gate signal G
1 outputs the H logic from the time when the match detection signal A1 is output until the master clock MCL has passed one cycle, and falls to the L logic at the rising timing of the master clock MCL. Therefore, the comparator 25A then outputs the periodic pulse P
Until C rises to the H logic, the coincidence detection signal is prevented from being output again.

Since the delay setting value is 32 ns in the cycle CU2, the integer value is (2) and the fractional value is 0. The latch circuit 22 reads the count value of the master clock counter 21 at the rising timing of the periodic pulse PC. In this example, the count value # 4 is read. The adder 23 adds the count value # 4 and the integer value (2), and stores the addition result # 4 + 2 = 6 in the register 24A. The added value (6) stored in the register 24A does not change until the next periodic pulse PC is input. On the other hand, the count value latched by the latch circuit 22 is incremented by +1 like # 4, # 5, # 6, and # 7 according to the rising timing of the master clock MCL.
Therefore, when the count value reaches # 6, the comparator 25A outputs the coincidence detection signal A2 again. The rising timing of the coincidence detection signal A2 corresponds to the time 32 ns for two cycles of the master clock MCL from the rising timing of the second periodic pulse PC, and the fraction delay circuit 1 together with the fraction value 0 ns.
Sent to 3B.

In the case of the set values of 38 ns and 40 ns set in the cycles CU3 and CU4, the integer is (2).
The added value stored in the register 25A is # 8 + 2 = 10 in the cycle CU3 and # 12 + 2 = 14 in the cycle CU4. Therefore, in the cycle CU3, when the count value reaches # 10, the coincidence detection signal A3 is output, and in the cycle CU4, the count value is # 10.
When it reaches 14, the coincidence detection signal A4 is output. These coincidence detection signals A3 and A4 each come at a timing 32 ns after the reference timing.

In the example of the set values shown in FIG. 10, the case where the period of the periodic pulse PC is smaller than 64 ns has been described.
In the case of such set values, the coincidence detection signal can be output from the first-stage comparator 25A. As a result, the gate signals G2 output from the comparison control means 26B and 26C are output.
G3 remains in the L logic. That is,
The first-stage comparator 25A causes the coincidence detection signals A1, A2, A
When 3 and A4 are output, the comparison operation control means 26A outputs L logic. Therefore, even if the next periodic pulse PC is given, the comparison operation control means 26B and 26 of the second and third stages are provided.
Since C reads L logic, the gate signals G2 and G3 are L
It remains in logic.

FIG. 11 shows that the set value is larger than 64 ns.
An example of setting 0 ns and 180 ns is shown. 100
When ns is set, the integer value is (6) and the fractional value is 4n.
s. If the timing at which 100 ns is set is used as the test start timing, the added value is # 0 + 6 = 6. While the added value (6) is stored in the register 24A, the count value of the master clock counter 21 changes only from # 0 to # 3. Accordingly, the register 25B and the comparison operation control means 26B remain without the comparator 25A outputting the coincidence signal.
A periodic pulse PC is applied to the. When the periodic signal PC is given without the coincidence signal being output from the comparator 25A, the added value (6) stored in the register 24A is shifted to the register 24B, and the comparison operation control means 26 of the first stage is also provided.
Since A still outputs the H logic, the second comparison operation control means 26B outputs the H logic output from the first comparison operation control means 26A at the rising timing of the second periodic pulse PC. Is read, the gate signal G2 is inverted to H logic, and the comparator 25B is given permission for the comparison operation. Therefore, when the count value reaches # 6, the comparator 25B outputs the coincidence signal A5.
Is output.

At the timing when the third periodic pulse PC rises, the comparator 25B outputs the L logic as shown in FIG. 11J immediately after the coincidence detection signal A5 is output, so that the third stage comparison operation is performed. The L logic is given to the control means 26C. Therefore, the third-stage comparison operation control means 26C is L
Continue to output logic. At the timing when the fourth periodic pulse PC is supplied, the comparison operation control means 26C of the third stage is set to H.
It outputs a gate signal G3 of logic and gives the comparator 25C permission of the comparison operation.

On the other hand, when the second periodic pulse PC is given in FIG. 11, the set value 1 is input to the input terminal of the adder 23.
An integer value (11) of 80 ns is input. At this timing, the count value of the master clock counter 21 is # 4, so the adder 23 outputs the addition value # 4 + 11 = 15. Therefore, the added value (15) is stored in the register 24A.
Is stored.

At the timing when the third periodic pulse is supplied, the added value (1
5) shifts, and the added value (15) shifts to the register 24C at the timing when the fourth periodic pulse is given. As a result, the count value of the master clock counter 21 is #
When it reaches 15, the comparator 25C outputs the coincidence detection signal A6. The rising timing of this coincidence detection signal A6 corresponds to the cycle of 11 master clocks MCL from the rising timing of the second periodic pulse PC 176n.
It is the timing when s has elapsed. The remaining fractional value of 4 ns is sent from the fractional value output terminal 32 to the fractional delay circuit 13B, added with a delay of 4 ns in the fractional delay circuit 13B, and output.

[0027]

With the above description, the IC
It will be understood that the general construction and operation of the timing generator 13 used in the test apparatus. Since the structure of the timing generator 13 is as shown in FIG. 9, the delay value that can be set is limited. When the integer delay circuit 13A is composed of three comparison stages, it is not possible to set a timing longer than the added value of the cycle values of CU1 to CU3 starting from CU1.

It is not possible to set a delay value such that the coincidence detection signals are simultaneously output from a plurality of comparators. It is not possible to set timing closer to the cycle of the master clock MCL in the cycle of the cycle pulses adjacent to each other. The delay value set in the subsequent cycle must not be longer than the delay value set in the previous cycle.

The existence of such a limitation is well known to programmers who write test programs. However, there are cases where you accidentally make settings that touch the restrictions of. When such a phenomenon occurs, the test result expected by the programmer cannot be obtained, so that the IC under test is erroneously determined to be defective.

Therefore, it is possible to warn that an incorrect timing generating operation has been executed due to an incorrect setting that touches the above-mentioned restrictions (1) to (3), thereby improving the reliability of the IC test. An object of the present invention is to provide a timing generator having a function capable of detecting malfunction and erroneous setting.

[0031]

SUMMARY OF THE INVENTION The timing generator proposed in claim 1 of the present invention is a timing generator capable of detecting a state in which an erroneous operation and an erroneous setting touching the above-mentioned limitation have been made and which has been executed. It is intended to provide a device. For this reason, in claim 1 of the present application, the coincidence detection signal is not output from the comparator in the latter stage in the state where the comparison operation control means gives the gate signal permitting to output the comparison result. Timing detection with a malfunction and erroneous setting detection function, which is provided with a first error signal generator for generating a first error signal when the time-out detection means detects a time-out It is the one that proposes a container.

Therefore, according to the timing generator proposed in the first aspect, even though the set value has been shifted to the final stage register of the multi-stage shift register, the next cycle without the coincidence detection signal being output. Pulse is input,
A state in which a time longer than the settable timing has elapsed can be detected, and the state can be warned by the first error signal.

The timing generator proposed in claim 2 of the present invention is intended to provide a timing generator having a function of detecting a malfunction / mis-setting which touches the above-mentioned restriction. Therefore, in claim 2, the duplicate output detection means for detecting the output of the coincidence detection signal from each of the plurality of comparators at the same timing, and the duplicate output detection means from the plurality of comparators simultaneously detect the overlap detection signal. It is proposed to provide a configuration provided with a second error signal generating means for outputting a second error signal when it is detected that is output.

Therefore, according to the timing generator proposed in this aspect, it is possible to detect a malfunction or an erroneous setting such that a coincidence detection signal is output from a plurality of comparators at the same timing. it can. The timing generator proposed in claim 3 of the present invention is intended to provide a timing generator having a function of detecting an erroneous operation or an erroneous setting which touches the above-mentioned limitation.

Therefore, in claim 3, the adjacent period detecting means for detecting that the comparator outputs the coincidence signal at the period of the adjacent master clocks, and the adjacent period detected by the adjacent period detecting means are set. Compare the fractional values
Comparing means for detecting that the time interval of the timing signal to be output from the fractional delay circuit is shorter than the cycle of the master clock; and the time interval of the timing signal to be output by the fractional delay circuit by the comparing means is shorter than the cycle of the master clock. When this is detected, a timing generator having a malfunction / erroneous setting detection function, which is configured by adding a third error signal generating means for outputting a third error signal, is proposed.

According to the timing generator proposed in claim 3, the master IC has a cycle of 16 ns in the IC under test.
It is possible to avoid such a disadvantage that a test pattern signal having a shorter cycle is supplied or a strobe pulse is supplied to a logical comparator or the like at a time interval shorter than the master clock cycle. The timing generator proposed in claim 4 of the present invention proposes a timing generator having a function of detecting an erroneous operation or erroneous setting that touches the above-mentioned restriction.

Therefore, in the present invention, the condition of the gate signal output from the comparison operation control means is compared and it is detected that the comparator on the front stage side outputs the coincidence detection signal before the comparator on the rear stage side. The present invention proposes a timing detecting means and a timing generator including a fourth error signal generating means for outputting a fourth error signal when the reverse timing detecting means detects occurrence of reverse timing.

According to the timing generator proposed in the fourth aspect, for example, the IC under test is caused by the reverse timing phenomenon.
In addition, it is possible to detect an accident in which a test pattern that is not set at an unintended timing is given.

[0039]

FIG. 1 shows an embodiment of the timing generator according to the present invention. The embodiment shown in FIG. 1 comprises all of the first error signal generating means, the second error signal generating means, the third error signal generating means, and the fourth error signal generating means proposed in claims 1 to 4, that is, 6 shows a configuration of a timing generator proposed in claim 5.

In FIG. 1, the portions corresponding to those in FIG. 9 are designated by the same reference numerals and their duplicate description is omitted. However, in the present invention, the time-out detecting means 41, the duplicate output detecting means 42 and the second error signal generating means 43 are provided. , An adjacent period detecting means 44, a fraction comparing means 45, a third error signal generating means 46, a reverse timing detecting means 47 and a fourth error signal generating means 48.

The time-out detecting means 41 proposed in claim 1 is a multiplexer MUX and a D-type flip-flop D.
It can be configured by FF. The periodic pulse PC is input to the control terminal S of the multiplexer MUX. Further, the output signal C3 (the output of the gate of the comparison operation control means 26C shown in FIG. 9) of the termination comparison operation control means 26C is input to the input terminal B of the multiplexer MUX.

Here, as shown in FIG. 2, the integer delay circuit 1
220n, which is larger than the maximum value of 192ns that can be set to 3B
If s is set, the integer value in this case is (13). If it is the timing of starting the test, the added value is # 0 + 13 = 13. As a result, the first-stage comparison operation control means 26A and the second-stage comparison operation control means 26
B, the third stage comparison operation control means 26C is a periodic pulse PC
Is output, the output signals C1, C2 and C3 are output as shown in FIG.
As shown by I, J, and K, they are sequentially inverted to H logic. When the fourth periodic pulse PC is supplied while the comparison operation control means 26C of the third stage is outputting the H logic, the multiplexer MUX constituting the time-out detection means 41 switches to the input terminal B, The H logic output from the comparison operation control means 26C is input to the D-type flip-flop DFF. As a result, the time-out detecting means 41 causes the fourth periodic pulse P
When C is supplied, as shown in FIG.
The error signal ERR1 is output.

Next, as shown in FIG. 3, assuming that a set value of 85 ns is set as the initial timing and 23 ns is set in the next cycle, the integer values are (5) and (1) in this case, and the added value is # 0 + 5 = 5 and # 4 + 1 = 5.
When such a setting is made, when the count value of the master clock counter 21 reaches # 5, the first comparator 2
5A and the second-stage comparator 25B output coincidence signals A1 and A2, respectively. As a result, the AND gate AND ₃₁ forming the duplicated output detecting means 42 outputs H logic, and this H logic is taken into one D-type flip-flop forming the second error signal generating means 43 and is output from the output terminal 43A. The second error signal ERR2 shown in 3L is output.

Such erroneous setting or erroneous operation may occur between the first-stage and third-stage comparators 25A and 25C, and the state is AND gate AND ₃₂ which constitutes the duplicated output detecting means 42. And the second error signal ERR2 is output from the output terminal 43B of the second error signal generating means 43. In addition, the second and third comparators 25B and 2
When the coincidences are simultaneously detected in 5C, they are detected by the AND gate AND ₃₃ which constitutes the duplicated output detection means 42, and in this case, the second error signal ERR2 is output from the output terminal 43C of the second error signal generation means 43. .

Next, as shown in FIG. 4, for example, when 70 ns is set in the first cycle and 17 ns is set in the second cycle, the time interval of the timing signal to be finally output from the fraction delay circuit 13B is the master. 1 cycle of clock MCL 1
The configurations and operations of the adjacent period detection means 44 and the fraction comparison means 45 for detecting erroneous settings or malfunctions that become shorter than 6 ns will be described.

The adjacent period detecting means 44 reads the start pulse (signal sent to the fraction delay circuit 13B) output to the output terminal 31 at the rising timing of the master clock MCL, and the D-type flip-flop DFF, and the output terminal 3
1 and an AND gate AND ₄₁ for detecting that both outputs of the D-type flip-flop DFF are in the H logic state.

That is, the adjacent period detecting means 44 continuously outputs the coincidence signals A1, A2 and A3 for two cycles from any combination of the comparators 25A and 25B or 25B and 25C at each rising timing of the master clock MCL. Then, it is detected that the state of the output terminal 31 is the H logic for two consecutive cycles, and when the H logic is output for two consecutive cycles, the adjacent cycle detecting means 44 outputs the H logic shown in FIG. 4I.
This H logic detection signal is given to the control terminal S of the comparator 45A provided in the fraction comparing means 45. The comparator 45A has input terminals A and B, inputs the fractional value AA currently output to the input terminal A, and inputs the fractional value BB one cycle before to the input terminal B. For this reason, a D-type flip-flop is connected to the input terminal B to store the fractional value BB output to the fractional output terminal 32 at the rising edge of the previous cycle, and the fractional value BB one cycle before is output now. The comparator 45A compares the fractional value AA.

The comparator 45A executes the comparison operation when the control terminal S is given H logic, and outputs the comparison result to the output terminal. As the comparator 45A, a comparator generally called a magnitude comparator can be used, and a fractional value AA input to the input terminal A and a fractional value B input to the input terminal B are used.
When B has a relation of AA <BB, H logic is output. That is, the fractional value B of one cycle before is detected in the state where the adjacent cycle detection means 44 detects that the coincidence signal is output in the adjacent cycle.
B is larger than the fractional value AA output in the next cycle A
When A <BB, the time interval of the timing pulse to be output from the fraction delay circuit 13B is the master clock M
One CL cycle, in this example, is a time interval shorter than 16 ns.

An example of this will be described with reference to FIG. In the example of FIG. 4, the first cycle CU1 has a set value of 70 ns and the second cycle CU.
2 shows the case where the set value is set to 17 ns. First cycle C
In U1, the integer value is (4) and the fractional value is 6 ns. Second
In the cycle CU2, the integer value is (1) and the fractional value is 1 ns. The coincidence signal A1 in the first cycle is generated when the count value is # 4,
The coincidence signal A2 in the second cycle is generated with the count value # 5. That is, the coincidence signals A1 and A2 are generated in adjacent cycles of the master clock MCL.

The fraction delay circuit 13 is set according to the setting of the first cycle.
As shown in FIG. 4J, the timing signal to be output from B is a timing delayed by 6 ns from the rising timing of the coincidence signal A1. On the other hand, the timing signal to be output from the fractional delay circuit 13B by the setting of the second cycle is 1n from the rising timing of the coincidence signal A2.
This is a timing delayed by s. Therefore, the interval between them is 11 ns, and one cycle of the master clock MCL is 16
Since the time interval is smaller than ns, the third error signal generating means 46 reads the H logic output from the fraction comparing means 45 and generates the third error signal ERR3 shown in FIG. 4I.

Next, the structure and operation of the reverse timing detecting means 47 will be described. The reverse timing detecting means 47 can be composed of an AND gate 47A, a NOR gate 47B, and an inhibit AND gate 47C. The AND gate 47A is a comparison operation control means 26 at the end.
C is a gate signal G3 that allows the comparator 25C to perform a comparison operation.
Despite being output, the previous comparator 25A or 2
Either one of 5B operates to detect the state in which the coincidence signal A1 or A2 is output. That is, when either one of the comparators 25A and 25B outputs the coincidence signal A1 or A2, either one of the output signals C1 and C2 of the comparison operation control means 26A or 26B becomes L logic in synchronization with this. Fall down. When one of the output signals C1 and C2 falls to the L logic, the NAND gate 47B outputs the H logic, and the AND gate 47A also outputs the H logic. The H logic constitutes the fourth error signal generating means 48. It is taken in by one AND gate, and the fourth error signal E is output from the output terminal 48A.
RR4-1 is output.

On the other hand, the inhibit-and-gate 47C outputs the output of the comparison operation control means 26A regardless of whether the output signal C2 of the comparison operation control means 26B is the H logic, that is, even if the numerical value is set in the register 24B. The state where the signal C1 falls to the L logic (the state where the first stage detects the coincidence before the second stage) is detected and the H logic is output. This H logic is read into the other D-type flip-flop which constitutes the fourth error signal generating means 48, and the output terminal 48B.
Outputs a fourth error signal ERR4-2. FIG. 5 shows a setting situation in which the fourth error signal ERR4-2 is generated and an operation state. In the example shown in FIG. 5, 12 in the first cycle CU1
A case where 0 ns is set and 24 ns is set in the next cycle CU2 is shown. According to this setting, the integer value is (7), the fractional value is 8 ns, and the added value is # 0 + 7 = 7 in the first cycle. In the second cycle CU2, the integer value is (1) and the fractional value is 8n.
s, the added value is # 4 + 1 = 5.

Therefore, the coincidence signal A1 of the first cycle CU1 is generated with the count value # 7 as shown in FIG. 5H, and the coincidence signal A2 of the second cycle is generated with the count value # 5. Comparison operation control means 2
The output signal C1 of 6A is inverted to H logic when the count value is # 0, and the output signal C2 of the comparison operation control means 26B is inverted to H logic when the count value is # 4. Therefore, when the count value is # 4, the comparison operation control means 26A and 26B both output the H logic.

On the other hand, when the count value advances to # 5, the comparator 25A outputs the coincidence signal A2 (FIG. 5H), so that the comparison operation control means 26A receives the coincidence signal A2 as shown in FIG.
As indicated by I, the count value is lowered to L logic at the timing of # 5. Therefore, inhibit and gate 47C
Indicates that the L logic is input to the inverting input terminal and the H logic is input to the other non-inverting input terminal, so that the inhibit and gate 47C outputs the H logic, and the H logic is read by the fourth error signal generating means 48. The fourth error signal ERR4-2 of H logic is output to the output terminal 48B.

[0055]

As described above, according to the present invention, by providing the time-out detecting means 41, when the set value exceeds the replacement time which can be set in the integer delay circuit 14A, or the set value is exceeded. If an erroneous operation that outputs an addition value in which an integer value is obtained from the integer value and the count value is added is longer than the delay time of the integer delay circuit 13A, the erroneous setting or operation is detected. Since the first error signal ERR1 is generated, even if the result of testing the IC under test at this timing is determined to be defective,
The determination result can be specified as the cause of the erroneous setting or malfunction. Therefore, the test result of the IC under test is not erroneously processed, and the reliability of the IC test result can be improved.

Further, in the present invention, since the structure provided with the duplicate output detecting means 42 for detecting the output of the coincidence signals from the plurality of comparators at the same timing is proposed, the integer value obtained from the set value and each It is possible to detect an erroneous setting or an erroneous operation in which the added value of the count value of the timing becomes the same value and the coincidence is detected at the same timing. As a result, even when a plurality of coincidences occur at the same timing, it is determined that the wrong setting or malfunction has occurred and the second error signal ERR2-
Since 1 to ERR2-3 are generated, even if the test result of the IC under test is determined to be defective, the cause of occurrence of the defect can be known and can be distinguished from the defect of the IC under test.
Therefore, also in this case, there is an advantage that the reliability of the test result of the IC test can be improved. Further, the second error signals ERR2-1 to ERR2-3 are useful because it is possible to know the error occurrence status.

In the present invention, the adjacent period detecting means 4
Since the configuration including 4 and the fraction comparison means 45 is also proposed, when this configuration is added, the detection of coincidence occurs in the adjacent cycles of the master clock MCL, and the delay time to be delayed by the fraction delay circuit is still present. Is the delay time BB of the first cycle
And the delay time AA of the second cycle have a relation of AA <BB, the time interval of the timing pulse output from the fraction delay circuit 13B is shorter than the cycle of the master clock MCL. The signal ERR3 can be output to notify. Therefore, also in this case, it is possible to distinguish from the test result of the IC under test, and there is an advantage that the reliability of the IC test result can be improved.

Further, since the present invention proposes a configuration in which the reverse timing detecting means 47 is provided, by adding this configuration, the set value set later due to an erroneous setting precedes the set value set earlier. It can be detected that a match is output. Therefore, also in this case, it is possible to distinguish the test result of the IC under test from the malfunction and the malfunction based on the erroneous setting, remove the inconvenience of erroneously processing the IC test result, and improve the reliability of the IC test result. The advantage that can be obtained is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the time-out detecting means proposed in claim 1 of the present invention.

FIG. 3 is a waveform diagram for explaining the operation of the duplicate output detecting means proposed in claim 2 of the present invention.

FIG. 4 is a waveform diagram for explaining the operations of the adjacent period detecting means and the fraction comparing means proposed in claim 3 of the present invention.

FIG. 5 is a waveform diagram for explaining the operation of the reverse timing detecting means proposed in claim 4 of the present invention.

FIG. 6 is a block diagram for explaining the overall configuration of an IC test apparatus as a preferred example to which the present invention is applied.

FIG. 7 is a block diagram for explaining the configuration and operation of a conventional integer delay circuit and fractional delay circuit.

FIG. 8 is a waveform diagram for explaining the operation of the timing generator provided in the conventional IC test apparatus.

FIG. 9 is a block diagram for explaining the configuration and operation of a conventional integer delay circuit.

10 is a waveform chart for explaining the operation of the block diagram shown in FIG.

11 is a waveform diagram for explaining the operation of the block diagram shown in FIG.

[Explanation of symbols]

13A integer delay circuit 13B fraction delay circuit 21 Master clock counter 22 Latch circuit 23 adder 24 Multi-stage shift register 24A-24C register 25A to 25C comparator 26A to 26C Comparative operation control means 27 Output circuit 29A to 29C registers 30 fraction output circuit 31 output terminals 32 fractional output terminal 41 Time-out detection means 42 duplicate output detection means 43 Second error signal generating means 44 Adjacent cycle detection means 45 Fraction comparison means 46 Third error signal generating means 47 Reverse timing detection means 48 Fourth error signal generating means MCL master clock PC periodic pulse

Claims (5)

(57) [Claims] 1. A. An integer value obtained by dividing the set delay value by the cycle of the master clock is supplied to one input terminal, and the count value of the master clock is supplied to the other input terminal to calculate the added value. And B. A multi-stage shift register that takes in the added value output from the adder in synchronization with a periodic pulse generated at a cycle of a predetermined multiple of the master clock, and sequentially shifts the added value to the next stage each time the periodic pulse is supplied; ． A plurality of comparators provided corresponding to the registers of the respective stages of the multi-stage shift register and comparing the added value stored in the registers of the respective stages with the count value of the master clock; An output circuit which detects that any one of the plurality of comparators outputs a coincidence signal and outputs a start signal to the fraction delay circuit; Provided corresponding to each of the plurality of comparators,
Each time the periodic pulse is supplied, a gate signal that permits the comparison result to be sequentially output to the comparator from the preceding stage side is given, and when one of the plurality of comparators outputs a coincidence signal, the next periodic pulse is output. And a comparison operation control means for outputting a gate signal for preventing the comparison result from being output again from the comparator that has output the coincidence signal until the input signal is input. A gate signal for permitting the comparison operation control means to output a comparison result is given to a comparator for comparing the added value stored in the final stage register of the multi-stage shift register with the count value of the master clock. G., the time-out detection means for detecting that the comparator does not output the coincidence detection signal until the timing at which the next periodic pulse is applied. A timing generator having a malfunction / erroneous setting detection function, characterized in that a first error signal generator for generating a first error signal when the time-over detecting means detects a time-over is added. 2. A. An integer value obtained by dividing the set delay value by the cycle of the master clock is supplied to one input terminal, and the count value of the master clock is supplied to the other input terminal to calculate the added value. And B. The added value output by this adder is taken in by a periodic pulse generated at a period of a predetermined multiple of the master clock,
A multi-stage shift register that sequentially shifts the added value to the next stage each time a periodic pulse is supplied; A plurality of comparators provided corresponding to the registers of the respective stages of the multi-stage shift register and comparing the added value stored in the registers of the respective stages with the count value of the master clock; An output circuit which detects that any one of the plurality of comparators outputs a coincidence signal and outputs a start signal to the fraction delay circuit; Provided corresponding to each of the plurality of comparators,
Each time the periodic pulse is supplied, a gate signal that permits the comparison result to be sequentially output to the comparator from the preceding stage side is given, and when one of the plurality of comparators outputs a coincidence signal, the next periodic pulse is output. A comparison operation control means for outputting a gate signal for preventing the comparison result from being output again from the comparator that has output the coincidence signal until the input signal is input; Duplicate output detection means for detecting that a coincidence detection signal is output from each of the plurality of comparators at the same timing, and G. When the duplicated output detection means detects that a plurality of coincidence signals are simultaneously output from the plurality of comparators, the second output is detected.
A timing generator equipped with a second error signal generating means for outputting an error signal, and a malfunction / erroneous setting detection function. 3. A. An integer value obtained by dividing the set delay value by the cycle of the master clock is supplied to one input terminal, and the count value of the master clock is supplied to the other input terminal to calculate the added value. And B. The added value output by this adder is taken in by a periodic pulse generated at a period of a predetermined multiple of the master clock,
A multi-stage shift register that sequentially shifts the added value to the next stage each time a periodic pulse is supplied; A plurality of comparators provided corresponding to the registers of the respective stages of the multi-stage shift register and comparing the added value stored in the registers of the respective stages with the count value of the master clock; An output circuit which detects that any one of the plurality of comparators outputs a coincidence signal and outputs a start signal to the fraction delay circuit; Provided corresponding to each of the plurality of comparators,
Each time the periodic pulse is supplied, a gate signal that permits the comparison result to be sequentially output to the comparator from the preceding stage side is given, and when one of the plurality of comparators outputs a coincidence signal, the next periodic pulse is output. A timing generator configured to include a comparison operation control unit that outputs a gate signal that prevents the comparison result from being output again from the comparator that has output the coincidence signal until it is input; Adjacent period detecting means for detecting that the comparators output coincidence signals at periods of adjacent master clocks, G. Fractional comparison means for comparing the fractional values set in the adjacency cycle detected by the adjacency cycle detection means, and detecting that the time interval of the timing signal to be output from the fractional delay circuit is shorter than the cycle of the master clock, H. A third error signal generating means for outputting a third error signal when the fraction comparing means detects that the time interval of the timing signal to be outputted from the fraction delay circuit is shorter than the cycle of the master clock. Timing generator with malfunction and erroneous setting detection feature. 4. A. An integer value obtained by dividing the set delay value by the cycle of the master clock is supplied to one input terminal, and the count value of the master clock is supplied to the other input terminal to calculate the added value. And B. The added value output by this adder is taken in by a periodic pulse generated at a period of a predetermined multiple of the master clock,
A multi-stage shift register that sequentially shifts the added value to the next stage each time a periodic pulse is supplied; A plurality of comparators provided corresponding to the registers of the respective stages of the multi-stage shift register and comparing the added value stored in the registers of the respective stages with the count value of the master clock; An output circuit which detects that any one of the plurality of comparators outputs a coincidence signal and outputs a start signal to the integer delay circuit; Provided corresponding to each of the plurality of comparators,
Each time the periodic pulse is supplied, a gate signal that permits the comparison result to be sequentially output to the comparator from the preceding stage side is given, and when one of the plurality of comparators outputs a coincidence signal, the next periodic pulse is output. A timing generator configured to output a gate signal that prevents a comparison result from being output again from the comparator that has output the coincidence signal until the input signal is input; Reverse timing detection means for comparing the states of the gate signals output by the comparison operation control means and detecting that the front side comparator has output the coincidence detection signal before the rear side comparator; A timing generator having a malfunction / erroneous setting detection function, characterized in that a fourth error signal generating means for outputting a fourth error signal when the reverse timing detecting means detects occurrence of reverse timing is added. 5. A timing generator having an erroneous operation / erroneous setting detection function, which is configured to include all the functions added to the respective timing generators according to claim 1. Description: