JP3382151B2 - Memory system and storage system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a flash EEPROM.
The present invention relates to a nonvolatile semiconductor memory device using M.

[0002]

2. Description of the Related Art Conventionally, magnetic disk devices have been widely used as storage devices for computer systems. However, magnetic disk drives have the following disadvantages:
It has a highly precise mechanical drive mechanism and is vulnerable to impact.
There are disadvantages such as poor portability due to weight, high power consumption, difficulty in battery operation, and inability to access at high speed.

[0003] In recent years, attention has been paid to such defects, and
Development of a semiconductor memory device using a ROM has been advanced. Semiconductor memory devices generally have such advantages,
That is, it has advantages such as being resistant to impacts because it does not have a mechanical drive portion, being highly portable because of its light weight, being easily driven by batteries because of its low power consumption, and being capable of high-speed access.

[0004] As one of the EEPROMs, a NAND cell type EEPROM which can be highly integrated is known. It has the following structure. That is, the plurality of memory cells are arranged, for example, in the column direction. Sources and drains of adjacent cells among these cells are sequentially connected in series. By such a connection, a plurality of memory cells are connected in series to form a unit cell group (NADA cell). Such a unit cell group is connected to a bit line as one unit.

A memory cell usually has an FETMOS structure in which a charge storage layer and a control gate are stacked. The memory cells are integratedly formed in an array in a p-type well formed on a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to a bit line via a select gate.
The source side of the NAND cell is connected to a source line (reference potential wiring) via a selection gate. The control gate of each memory cell is connected to a word line arranged in the row direction.

The writing operation of this NAND type EEPROM is as follows. By the previous erase operation, NAND
The thresholds of all memory cells in the cell have been made negative. Thereafter, data writing is performed in order from the memory cell located farthest from the bit line. A high voltage Vpp (approximately 20 V) is applied to the control gate of the selected memory cell, and an intermediate potential VM (approximately 10 V) is applied to the control gate and select gate of the memory cell on the bit line side. 0 V or an intermediate potential is applied to the bit line according to write data. When 0 V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, and electrons are injected from the drain to the floating gate. As a result, the threshold value of the selected memory cell shifts in the positive direction.
This state is set to “0”, for example. When an intermediate potential is applied to the bit line, no electron injection occurs. Therefore, at this time, the threshold value of the memory cell does not change. That is, the threshold value takes a negative value. This state is set to “1”.

[0007] Data erasure is performed simultaneously on all memory cells in the NAND cell. That is, all control gates and select gates are set to 0 V, bit lines and source lines are set in a floating state, and a high voltage of 20 V is applied to the p-type well and the n-type substrate.
Is applied. As a result, electrons in the floating gate of all the memory cells are extracted to the p-type well, and the threshold value of the memory cells is shifted in the negative direction.

The data read operation is performed as follows. That is, the control gate of the selected memory cell is set to 0V
The control gate and the selection gate of the non-selected memory cell are set to the power supply potential Vcc (= 5 V). In this state, it is detected whether or not a current flows through the selected memory cell. It can be seen that "1" data is stored if the data flows, and "0" data is stored if the data does not flow.

As is clear from the above description of the operation, NA
In the ND cell type EEPROM, at the time of write and read operations, unselected memory cells act as transfer gates. For this reason, there is a limit on the threshold voltage of the written memory cell. For example, a preferable range of the threshold value of the memory cell in which “0” is written must be about 0.5 to 3.5 V. In consideration of a change over time after data writing, a variation in memory cell manufacturing parameters, and a variation in power supply potential, the threshold distribution after data writing needs to be smaller than the above range.

However, in the conventional method in which the write potential and the write time are fixed and data is written to all memory cells under the same condition, it is difficult to keep the threshold range after "0" write within an allowable range. . For example, memory cells have variations in cell characteristics due to variations in the manufacturing process. For this reason, a memory cell which is easy to be written and a memory cell which is hard to be written occur. Focusing on such a writing characteristic difference, in order to perform writing so that the threshold value of each memory cell falls within a desired range, the length of writing time is adjusted, and writing is performed while verifying. It has also been proposed to put it in.

However, when such a method is employed, it is necessary to output the data of the memory cell to the outside of the device in order to determine whether the writing has been sufficiently performed. For this reason, there was a problem that the total writing time was long.

Regarding the erase verify, see Japanese Patent Laid-Open No. Hei 3-2
As disclosed in U.S. Pat. No. 59499, a technique is known in which the outputs of a plurality of sense amplifiers are input to an AND gate and their logics are taken to generate a batch erase verify signal. , Can be used only for NOR type erase verify, and cannot be applied to write verify. The reason is that the write data takes both values of "1" and "0", and collective verification cannot be performed by taking the logic of the sense amplifier output. As described above, since write verification cannot be performed collectively, when writing data,
Writing and verify reading must be repeated to output the data of each memory cell one by one to the outside of the chip each time. This is a factor that hinders the speeding up of the writing operation.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of the difficulty in achieving the above-mentioned high speed.
An object of the present invention is to provide an EEPROM capable of speeding up a write operation and a write verify operation and an erase operation and an erase verify operation without increasing the area of a control circuit, and a system using the EEPROM.

[0014]

SUMMARY OF THE INVENTION A memory system according to the present invention comprises a plurality of memory circuits, each of which has a plurality of memory cells, and includes one page of data of a predetermined number of bits. A write operation of latching the group of data, writing the latched data group to the memory cell, and further performing a verify operation after the write operation to determine whether data of the data group has been properly written. A plurality of memory circuits configured to output a collective verify signal when data is written properly, and at least two or more capacities of the data group, for writing to the memory circuits. A cache memory for storing the plurality of data groups, and a memory of the plurality of memory circuits When the road has output the batch verify signal receives the batch verify signal, 1
A control circuit for transferring and latching the new data group for the page to another memory circuit, performing a data transfer operation, and controlling one of the plurality of memory circuits.
The write operation and the verify operation in one of the memory circuits and the data transfer operation to another memory circuit are repeatedly performed in parallel with each other.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a NAND type EEP according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a ROM. A bit line control circuit 2 is provided for performing data write, read, rewrite, and verify read with respect to the memory cell array 1. This bit line control circuit 2 is connected to a data input / output buffer 6. The address signal from the address buffer 4 is applied to the bit line control circuit 2 via the column decoder 3. A row decoder 5 is provided for controlling a control gate and a selection gate in the memory cell array 1. A substrate potential control circuit 7 is provided to control the potential of the p-type region (p substrate or p-type well) where the memory cell array 1 is formed.

The program end detecting circuit 8 detects data latched in the bit line control circuit 2 and outputs a write end signal. The write end signal is output from data input / output buffer 6 to the outside.

The bit line control circuit 2 mainly has a CMOS flip-flop (FF). These FFs perform latching of data for writing, sensing operation for detecting the potential of the bit line, sensing operation for verify reading after writing, and latching of rewritten data.

FIGS. 2A and 2B are a plan view and an equivalent circuit diagram of one NAND portion of the memory cell array, respectively. FIGS. 3A and 3B respectively show FIGS.
It is the sectional view on the AA 'line and the BB' sectional view of (a).
A plurality of memory cells, that is, a memory cell array having a plurality of NAND cells is formed in the p-type region 11 surrounded by the element isolation oxide film 12. Below is one NAND
A description will be given focusing on cells. In this embodiment, eight memory cells M1 to M8 are connected in series to form one NAND cell. Each memory cell is above the substrate 11,
The floating gate 14 (14 ₁ , 1
4 _2, ..., 14 ₈₎ are formed. Above these floating gates 14, control gates 16 (16 ₁ , 16 ₂ ,..., 16 ₈ ) are formed via an interlayer insulating film 15. Each n-type diffusion layer 19 is shared as a source in one of two adjacent memory cells and as a drain in the other. Thereby, each memory cell is connected in series.

[0019] The drain and source sides of NADA cells, respectively, selected formed by the same process as the floating gate and the control gate of the memory cell gate 14 _9,
19 ₉ and 14 _10, 16 ₁₀ are provided. The upper side of the substrate on which the elements are formed is covered with the CVD oxide film 17. Bit line 18 is provided on oxide film 17. The bit line 18 is in contact with the drain-side diffusion layer 19 at one end of the NAND cell.
The control gates 14 of the same row of a plurality of NAND cells arranged in the row direction are connected in common and control gate lines C running in the row direction are connected.
G1, CD2, ..., CG8. These control gate lines are so-called word lines. Select gate 14 _9, 16 ₉ and 14 _10, 16 ₁₀ also, each of which is arranged as a selection gate line SG1, SG2 running in the row direction. The gate insulating film 13 between the select gates 14 ₁₀ and 16 ₁₀ and the substrate 11 can be thicker than the gate insulating film of the memory cell. With such a thickness, reliability can be improved.

FIG. 4 shows an equivalent circuit of a memory cell array in which the plurality of NAND cells are arranged in a matrix.

FIG. 5 shows a specific configuration example of the bit line control circuit 2 in FIG. The CMOS flip-flop FF serving as a data latch and sense-up circuit includes first and second 2
It has two signal synchronous CMOS inverters IV1 and IV2. The first signal synchronous CMOS inverter IV1 is
E type, p-channel MOS transistors Qp1, Qp2
And an E type n-channel MOS transistor Qn3,
Qn4. Second synchronous CMOS inverter IV
2 is an E type, p-channel MOS transistor Qp
3 and Qp4, and E-type, n-channel MOS transistors Qn5 and Qn6.

The output node of the CMOS flip-flop FF and the bit line BLi are connected via an E-type, n-channel MOS transistor Qn7 controlled by a signal φF.

Between the bit lines BLi and Vcc, an E type controlled by the output node of the flip-flop FF,
An n-channel MOS transistor Qn8 and an E-type, n-channel MOS transistor Qn9 controlled by a signal φV are connected in series. By these transistors, the bit line BLi is set to (V) in accordance with the data of the CMOS flip-flop FF at the time of verify reading.
(cc-Vth).

E type, p-channel MOS transistor Qp5 and D type, n-channel MOS transistor Q
The series circuit of D1 is a circuit for precharging the bit line BLi to Vcc. The transistor QD1 is provided to prevent a high voltage from being applied to the transistor Qp5 during erasing or writing. E type, n channel MO
The S transistor Qn10 is a reset transistor for resetting the bit line BLi to 0V.

The two nodes N11 and N12 of the CMOS flip-flop FF are connected to input / output lines / IO, IO via two transfer gates (E type, n-channel MOS transistors Qn1 and Qn2) controlled together by a column selection signal CSLi. Each is connected to an IO.

The node N11 of the CMOS flip-flop FF is connected to the gate of an E type n-channel MOS transistor Qn11. The output of the transistor Qn11 is used as a write end detection signal VDTC.

FIG. 6 shows a connection relationship between the bit line control circuit 2, the memory cell array 1, and the program end detection circuit 8.

The E-type, p-channel MOS transistor Qp6 in the program end detection circuit 8 outputs a write end detection signal VDTC. As shown as a general example surrounded by a broken line in FIG. 6, FF is symbolized for convenience.

The circuit operation of this embodiment at the time of writing and at the time of confirmation will be described below. In the following description, it is assumed that one NAND cell is configured by a series circuit of eight memory cells as described above.

Prior to writing, data in a memory cell is applied to a p-type region (p substrate or p well) by about 20 V (Vp).
p) is applied, and the control gates CG1 to CG8 are set to 0 V to erase the data. By this erasing, the threshold value of the memory cell becomes 0 V or less.

FIG. 7 shows the operation at the time of writing / writing confirmation. In FIG. 5, the write data is output line I
O. / IO is latched by the CMOS flip-flop FF. Thereafter, the precharge signal φP becomes “H”,
φP becomes "L", and the bit line BLi is precharged to Vcc. Further, the voltages VMB and φF change from Vcc to the intermediate potential VM (（10 V). Due to the latched data, the bit line BLi becomes 0 V in the case of "0" writing, and becomes VM in the case of "1" writing. At this time, FIG.
In the case where the selection gate SG1 is VM and SG2 is 0V, and CG2 is selected as the control gate,
CG1 is VM, CG2 is high voltage Vpp (up to 20V),
G3 to CG8 are VM.

Select gates SG1, SG2, control gate C
When G1 to CG8 are reset to 0V, the signal .phi.F becomes "L" and the reset signal .phi.R becomes "H", and the bit line BLi is reset to 0V. Subsequently, a write confirmation operation is performed.

In the write confirmation operation, first, the precharge signal φp becomes “H” and / φp becomes “L”, and the bit line BL
i is precharged to Vcc. Thereafter, the selection gate and the control gate are driven by the row decoder 5. After the data of the memory cell is read out to the bit line, the selection gates SG1, SG2 and the control gates CG1 to CG8 are reset. After this, the verify signal φV becomes “H”,
Only to the bit line BLi to which "1" has been written (Vcc-Vt
h) is output.

Thereafter, φSP and φRP become “H”, and φS
N and φRN become “L”, and φF becomes “H”. Signal φS
P becomes “L”, φSN becomes “H”, and the bit line potential is sensed. Thereafter, the signal φRP becomes “L”, and φφ
RN becomes “H”, and the rewrite data is latched.
At this time, the relationship among the write data, the memory cell data, and the rewrite data is shown in Table 1 below.

Table 1 Write data 0 0 1 1 Memory cell data 0 1 0 1 Rewrite data 1 0 1 1 After that, the write end detection signal / φDV becomes “L”. If all the rewrite data is "1", the write end detection signal VDTC becomes "H". If any one is "0", VDTC is "L". The write / write check operation is repeated until VDTC becomes "H". And
The detection result is the data input / output pin or READY / BU
Output to the outside from the SY pin.

In this embodiment, erasing, writing, reading,
Bit line BLi and select gate SG at the time of write confirmation
1, SG2, and the potentials of the control gates CG1 to CG8 are shown in Table 2. Here, a case where CG2 is selected is shown.

Table 2 Erase Write Read Write “0” “1” Confirmation bit line BLi Floating 0V 10V 5V 5V Select gate SG1 0V 10V 10V 5V 5V Control gate CG1 0V 10V 10V 5V 5V 〃 CG2 0V 20V 0V 20V 0V 20V 0V 20V 0V 20V 0V 20V 0V 20V 0V 20V 0V 5V 〃 CG30V 10V 10V 5V 5V 〃 CG4 0V 10V 10V 5V 5V 〃 CG50V 10V 10V 10V 5V 5V 5V Source Line Floating 0V 0V 0V 0V Substrate 20V 0V 0V 0V 0V 0V FIG. 8 shows a NAND type EEPROM according to the second embodiment of the present invention.
It is a block diagram which shows M. The basic configuration is the same as in FIG. The second embodiment is different from the first embodiment in that the cell array 1
Is divided into two blocks 1A and 1B, and a bit line control circuit 2 is provided commonly to these cell blocks 1A and 1B.

FIGS. 9 and 10 show the bit line control circuit 2 and the program end detection circuit 8. FIG. In FIG. 9, E
Type, n-channel MOS transistors Qn16, Qn1
7 and E type, p-channel MOS transistor Qp7,
An FF is constituted by Qp9. The E type n-channel MOS transistors Qn14 and Qn15 are FF equalizing transistors. The E type, n-channel MOS transistors Qn27 and Qn28 are data detection transistors.

The E-type, n-channel MOS transistor Qn18 and the E-type, p-channel MOS transistor Qp8 are FF activation transistors. E type,
The n-channel MOS transistors Qn19 and Qn20 are
F, two nodes N1 and N2 and cell array block 1
A, 1B, bit lines BLai (i = 0, 1,...), BL
bi (i = 0, 1,...).
E type, n channel MOS transistors Qn21 to Qn
n24 is a transistor for charging the bit line to Vcc-VTH according to the data. Qn25 and Qn26 are bit line precharge and reset transistors. In FIG. 10, E type p-channel MOS transistors Qp10 and Qp11 are transistors for detecting the end of a program. / ΦDVA and / φDVB are program end detection signals, and φVEA and φVEB are program end detection signals.

Next, the EEPROM constructed as described above will be described.
The operation of confirming writing to the memory will be described with reference to FIG. Here, it is assumed that bit line BLai of memory cell array 1A is selected.

As in the previous embodiment, for example, 0.5 V is applied to the selected control gate instead of 0 V, and a verify signal φAV is output. First, the bit line BLai is precharged to 3V and BLbi is precharged to 2V. Thereafter, the precharge signals φPA and φPB go to the “L” level, and the bit lines BLai and BLbi float. The control gate and the selection gate are selected by the row decoder 5, SG1, CG1, CG3 to CG8 are Vcc, CG2.
Is, for example, 0.5V. In normal reading, if the threshold value of the memory cell is 0 V or more, reading is performed as "0", but in verify reading, "0" is not read unless it is 0.5 V or more.

Thereafter, if the bit line BLai has been written to "1", (V)
(cc-Vth). Here, the voltage level of the precharge performed by the verify signal may be equal to or higher than the precharge voltage of the selected bit line. The equalizing signal φE is output, and the CMOS flip-flop is reset. Thereafter, .phi.A and .phi.B become "H", and the nodes N1 and N2 are connected to the bit lines BLai and BLbi, respectively. φP goes low and φN goes high, and data on bit line BLai is read. The read data is latched and becomes the next rewrite data.
At this time, the rewrite data is converted from the data of the memory cell at the time of the verify read by the previous write data. This data conversion is the same as Table 1 in the previous embodiment.

Thereafter, / φDVA becomes “L”, and as in the previous embodiment, if writing is completed, VDTCA becomes “H”, and the program end detection signal φVEA becomes “L”,
The write operation ends. At this time, the detection result is output to the outside from the data input / output pin or the READY / BUSY pin.

The verify read / rewrite of this embodiment also suppresses an unnecessary rise in the threshold value of the memory cell to which "0" is written, as in the previous embodiment.

In this embodiment, the potentials of the control gates CG1 to CG8 and the select gates SG1 and SG2 at the time of erasing, writing, verify reading and reading are as shown in Table 3. Table 3 shows the potential relationship when the control gate CG2 is selected and the bit line BLai is selected.

Table 3 Erase Write Read Write "0""1" Confirmation bit line BLai Floating 0V 10V 3V 3V Bit line BLbi @ 0V 0V 2V 2V Select gate SG1 0V 10V 10V 5V 5V Control gate CG1 0V 10V 10V 5V 5V CG2 0V 20V 20V 5V 0. 5V 〃 CG30V 10V 10V 5V 5V 〃 CG4 0V 10V 10V 5V 5V 〃 CG50V 10V 10V 10V 5V 5V 5V Source Line Floating 0V 0V 0V 0V Board 20V 0V 0V 0V 0V 0V FIG. 12 schematically shows the data latch section in the bit line control circuit 2 and the program end detection circuit 8 in the present invention in relation to the selected bit line. It is shown in a typical manner. FIG. 9A shows the first embodiment. E type, n-channel MOS transistors QnD0 to QnDm
Corresponds to the transistor Qn11 in FIG. E type, p
The channel MOS transistor Qp12 corresponds to the transistor Qp6 of the program end detecting circuit 8 in FIG.

FIG. 6B shows an E type for data detection, n
This is one in which channel MOS transistors are connected in series. If all the gates of the data detection transistors QnD0 to QnDm are at "H", the program ends, and Vx becomes "L".
It becomes.

In FIGS. 9C and 9D, an E type p-channel MOS is used as a data detecting transistor.
The transistors QpD0 to QpDm are used, and an E-type, n-channel MOS transistor Qn29 is used for the program end detecting circuit 8. Even in such a configuration,
As in (a), it is possible to detect whether or not to end writing.

When the detection transistors Qn DO to Qn Dm are connected in parallel as shown in FIG. 12A, proper detection is possible even when the number of bit lines is several thousand bits. When these transistors are connected in series as shown in FIG. 3B, the source and drain of adjacent transistors can be shared, so that the pattern area can be reduced.

FIG. 13 shows an embodiment in which the circuit of FIG. 12 is applied to a one-transistor type (NOR type) flash EEPROM. NOR type flash EEP
In a ROM, data is inverted at the end of writing. Therefore, as shown in FIG. 13, the terminal of the FF opposite to that of FIG. 12 may be connected to the transistor for data detection.

Next, a NOR type flash EEPROM
An example of will be described. JP-A-3-250
FIG. 6 of Japanese Patent Publication No. 495 discloses a memory that achieves a high degree of integration similar to that of a NAND type while adopting a NOR type memory cell structure. In this memory, both writing and erasing operations can be performed by FN tunnel current. By applying the batch verification circuit in the embodiment of the present invention to the memory as described above, the write verification time can be significantly reduced.

Such an embodiment will be described with reference to FIGS. The circuit configuration of this embodiment is shown in FIG. This device differs from the NAND type E ² PROM in the following points. That is, the memory cell block M
Data to be written to the memory cell MC in the CB is latched by the data latch DR. A signal is output from the node on the opposite side of the data latch DR to the detection transistor.

FIG. 15 shows the distribution of the threshold value _Vth of the cell in which data has been written and the cell in which data has been erased.

Table 4 shows the voltage applied to each part in multiple operations of erasing, erasing, writing and writing.

_{Table 4} BSL BL WL V _SS Erase 0v Floating 20v 0v Write “0” write (V _th > 5) 22v 0v 0v floating “1” write (V _th <5) 22v 20v 0v floating Unselected cell 22v 0v / 20v 10v floating Read 5v 0v / 5v 5v 0v Next, the erase operation will be described. A block to be rewritten is selected by a row decoder of the block. In addition, the bit line corresponding to the selected memory cell is set to the floating state, and the word line is set to 20v. Thereby, electrons are injected into the floating gate of the selected memory cell. This injection is performed by the FN current. Therefore, the amount of current is extremely small. Therefore, erasing can be performed on memory cells of several thousand bits at the same time.

The verify operation after erasing is performed by a batch verify operation. That is, for example, 5 V is added to the word line. At this time, the memory cell to be erased is turned on / off depending on whether or not its threshold value is sufficiently shifted in the positive direction by the erasing operation. That is, if it is off, it is understood that the erasure is OK.

More specifically, the verify operation is performed as follows. The signal PRE goes to "L" level, and the transistor T _PRE turns on. As a result, the precharge line PRECL is set to V through the transistor T _PRE.
Precharged by _cc . At this time, the select line SG is turned on by setting the select line BSL to 5v.
Thereby, the bit line BL is also precharged. The word line WL to be selected is 5v. At this time, of the memory cells, those which have been erased / erased sufficiently are turned off / on. When the memory cell is turned off / on, the precharge potential of the bit line BL, that is, the precharge line PRECL is held / discharged. At this time, the potential of the precharge line PRECL is detected by the sense amplifier and latched in the data latch DR. Thereafter, the signal ERV is set to “H”, and the contents of the data latch DR are read out to the node NA. The potential of the node NA becomes “L” when all of the plurality of memory cells in the column corresponding to the node NA are erase OK, and becomes “H” when at least one of the memory cells has erase NG. The potential of the node NA is applied to the gate of the verify transistor T _VE . This transistor T _VE
Is turned off / on by “L / H” of the node NA. By turning off / on, the potential of the collective verify sense line L _VE does not reach the V _SS level. The above operation is performed for each column. Therefore, the batch verify sense line L _VE
Is verified OK for all cells in all columns.
In this case, it becomes "H", and in the case where at least one cell in any column is a verify NG, it becomes "L".

Next, a write operation (program operation) will be described. The word line of the block to be programmed is set to 0v. Word line of other blocks is 1
The voltage is set to 0 V, and the electric field stress between the drain and the gate in each memory cell is reduced. In the block to be programmed, a bit line connected to a memory cell from which electrons are to be extracted from the floating gate is selectively set to 20 V and programmed.

In the program verify, the potential of the precharge line PRECL at the time of verify read is set to “H”.
/ L ”level and the program data“ 0/1. ”However, the batch verification is performed based on the signal PR.
This is performed by setting V to "H". Then, in the case of the program NG, rewriting is performed. In this rewriting, the precharge line PRECL connected to the cell of “0” write OK is discharged to “L” level. Therefore, at the time of rewriting, since the bit line is at the "L" level, no emission of electrons from the floating gate occurs. On the other hand, the threshold of the "1" write OK cell is sufficiently low. For this reason, at the time of reprogramming, the precharge potential is discharged through the “1” write OK cell and becomes the “L” level. Therefore, even if reprogramming is performed, the threshold value of the “1” write OK cell does not change. On the other hand, the program NG, that is, “1”
In the case of light NG, there is no decrease due to the discharge of the precharge potential. Therefore, the “H” level is latched again,
Will be programmed again.

The embodiment described above has the following effects. Since the cell structure is the same as that of the NAND type cell, miniaturization is possible and the chip can be downsized.
Further, since the cell itself is of the NOR type, the operating current I
_{The cell} is large and random access at high speed is possible. Further, page write / page read is possible.

In the embodiment shown in FIGS. 12B and 12C, the same operation can be realized by directly connecting the gate of the data detecting transistor to the bit line BLi. Such examples are shown in FIGS. 16A and 16B, respectively. Similarly, in the embodiment shown in FIGS. 13A and 13D, the same operation can be realized by directly connecting the gate of the data detection transistor to the bit line BLi. This is shown in FIG.
(A) and (b) respectively show.

Further, in FIGS. 12, 13, 16 and 17, the single bit line system is employed, but an open or folded bit line system may be employed. The configurations of the data detection transistor, the COMS flip-flop FF, and the selected bit line may be the same as those in this embodiment.

FIGS. 12, 13, 16 and 17 schematically show the structure of a data detecting transistor, a CMOS flip-flop FF and a selected bit line. The same can be applied to various bit line systems. it can.

Next, still another embodiment of the present invention will be described. In each of the embodiments described above, one end of the CMOS flip-flop (data latch / sense amplifier circuit) provided at one end of the bit line is connected to the gate electrode of the detection transistor. Then, regardless of the address signal, it is detected whether or not the contents in all the data latches are "1" write data, thereby detecting whether or not the write state is sufficient.

For this reason, data of the data latch circuit at the defective column address or the unused redundant column address provided for rescue is also detected. Normally, the write state is sufficient, but detection is performed as if it were insufficient, which causes a problem that writing is not completed. In other words, there is a possibility that the write state checking operation after data writing may malfunction due to the influence of a defective column address or an unused column address.

Therefore, in this embodiment, means is provided to remedy a malfunction of the detection circuit for detecting rewrite data.
As a result, it is possible to detect the write state of only the originally used column address without being affected by the write state of the defective column address or unused column address.

The basic structure is the same as that of the first embodiment shown in FIGS. In addition to the first embodiment, in this embodiment,
As described later, a fuse and a non-volatile memory are connected to the write end detecting MOS transistor to remedy a malfunction of the write end detecting circuit.

FIG. 18A shows an algorithm at the time of writing / writing confirmation. When a program command is input, "1" program data is automatically latched in the data latch circuits of all column addresses including the redundant column. Here, when the cell array is divided and the data latch circuit is also divided, all the column addresses indicate all the column addresses of the selected divided part.

The write operation is exactly the same as in the first embodiment, and the write confirmation operation is almost the same as in the first embodiment. However, in Table 1 above, the memory cells at the defective column address and the unused column address are set to “1” before data input.
Has been reset to Therefore, the rewrite data is always "1" regardless of the write data or the data of the memory cell.

By performing the write / write confirmation operation in accordance with the algorithm shown in FIG. 18A, even if there is a memory cell in which "0" cannot be written at the defective column address, the write operation is affected by this memory cell. The detection operation does not malfunction. More specifically, even though the write state is sufficient, the write cell is erroneously detected as insufficient write and is not terminated due to the influence of the memory cell at the defective column address or unused column address. Can be prevented beforehand.

FIG. 18B shows another algorithm.
For example, assume that a bit line at a certain defective column address is short-circuited to the ground potential. In this case, when "1" program data is set as shown in FIG. 18A, the intermediate potential VM is applied to this bit line. As a result, the intermediate potential VM is short-circuited to the ground potential. As a result, the VM generated by the booster circuit may not be boosted to a predetermined voltage.

For this reason, in the algorithm shown in FIG. 18B, "0" program data is automatically set only in unused column addresses (including defective addresses) after external data input. After the verify read, "1" program data is automatically set at an unused column address. By doing so, the NAND cell type EE with high reliability is not affected by the defect of bit line leakage.
A PROM is realized. In each of FIGS. 18A and 18B, the portion within the broken line is automatically set in the EEPROM.
Indicates that this is done internally.

FIG. 19A shows the structure of the CMOS shown in FIG.
5 schematically shows a flip-flop data latch / sense amplifier and a write end detection transistor. FIGS. 17B and 17C show examples in which fuses Fu1 and Fu2 are connected to the write-end detecting MOS transistor in order to remedy a malfunction of the write-end detecting circuit. FIG.
In (b), a fuse Fu1 made of a poly-Si line or an Al line is provided between the source of the write completion detection MOS transistor and the ground line. After the EEPROM test, among the fuses Fu1, the fuse Fu1 at a defective column address or an unused column address is cut by a laser beam or the like. As a result, the write end detection operation is not performed for the column address where the fuse Fu1 has been cut.

FIG. 19C shows a fuse Fu2.
This uses a nonvolatile memory cell. In order to use this nonvolatile memory cell as a fuse, ultraviolet light is first applied to erase (initialize) the fuse data. That is, for example, _{Vth of the} memory cell Fu2 is set to negative, or
<V _th <V _cc . To program the fuse data, VF1 is applied to, for example, a VM of _Vcc or more,
VF2 is set to 0V, and VDTC is set to _Vcc . "0" program data is latched by a latch connected to a column address to be disconnected between the source of the write end detection MOS transistor and the ground potential. "1" program data is latched in a latch connected to a column address which is not to be disconnected. A memory cell (fuse Fu) at a column address latching “0” data
In 2), a current flows, and _Vth thereof increases due to hot electron injection. Since no current flows through the cell (fuse Fu2) at the column address latching the "1" data, its _Vth does not rise. In this case, VF
2 may be set to _Vcc and VDDTC may be set to 0v.

During normal operation, the potential of each section is set as follows. That is, V of the memory cell at the time of erasing the fuse data.
_{When th} becomes negative, V _th of the memory cell is made positive,
VF1 is set to the ground potential, and the memory cell (fuse Fu)
2) is set to the cutting state. When V _{th of the} memory cell is in the range of 0 <V _th <V _cc at the time of data erasing, V _th of the memory cell is set to V _th > V _cc and VF1 = V _cc ,
VF2 is grounded to obtain a disconnected state of the memory cell.

In erasing the data in the fuse memory Fu2, VF1 is set to the ground potential, VF2 is set to about VM of _Vcc or more, and _Vth of the fuse is set to _Vth by the tunnel current.
_th <0v or 0v < _Vth < _Vcc .

FIG. 20 (a) focuses on one column in the circuit shown in FIG. 19 (c). FIG.
0 (b) is a plan view of the write completion detecting MOS transistor and the nonvolatile memory for fuse of FIG. 20 (a). FIG. 20C is a sectional view taken along the line XX ′ of FIG. The write completion detecting MOS transistor and the nonvolatile memory for the fuse are formed at the same time when the NAND type memory cell is formed. The gate electrode of the write completion detection MOS transistor has a two-layer structure, similarly to the select gate of the NAND cell, and these two-layer gates are connected to each other on the isolation insulating film 12.

A first element such as a write end detecting MOS transistor and a nonvolatile memory cell for a fuse includes an NA
It is formed similarly to the second element such as the selection transistor and the memory cell in the ND cell. For example, the concentration of the n-type diffusion layer of the first element may be slightly increased by injection of hot electrons to facilitate programming. For example, the concentration of the n-type diffusion layer of the first element is set to the concentration of the n-type diffusion layer of a peripheral transistor having a higher n-type diffusion layer than the second element. Then, the second element may be formed simultaneously with the n-type diffusion layer of the peripheral transistor.

FIG. 21 shows another example of a write end detecting MOS transistor and a nonvolatile memory cell for fuse. FIG. 3A is a cross-sectional view of the device structure, and FIGS.
3 is an equivalent circuit diagram of FIG. The programming of the nonvolatile memory cell for the fuse is performed in the same manner as in FIG. When programming with VF2 grounded, see FIG.
1 (b). FIG. 21C shows a case where the VDDTC is grounded and programmed. This structure is formed in the same manner as the transistor shown in FIG.

When programming the nonvolatile memory cells shown in FIGS. 20 and 21, it is efficient to set the power supply potential _Vcc higher than during normal operation. Further, it is more efficient to program the power supply VMB of the CMOS flip-flop with a VM of, for example, _Vcc or more.

FIG. 22 shows a NAND cell type EE in the circuit having the fuses shown in FIGS. 19 (b) and 19 (c).
4 shows a program algorithm for a PROM.

After inputting the program / command (S1), "0" program data is automatically set to all column addresses including the unused column address (including the defective column) (S2). Thereafter, program data is input in the page mode (S3), and writing / writing confirmation / writing end detection is automatically performed (S4 to S7). The reason why “0” program data is set in the unused column is to prevent the intermediate potential VM from being applied to the unused bit line during programming. In addition, if VM is the output of the booster circuit and the unused bit line is short-circuited to, for example, the ground potential, the VM is not boosted to a predetermined potential.

FIG. 23 shows another example of FIG. A write end detection MOS transistor is connected to bit lines sharing the same column address selection signal CSLi. The fuses for these transistors may be shared. This results in a smaller layout area.
Of course, this fuse may be replaced with a nonvolatile memory.

Next, an embodiment in which the above-described rescue means is applied to the second embodiment shown in FIGS.
The basic operation is the same as in the second embodiment. Also in this embodiment, if the programming is performed by the algorithm shown in FIG. 18, the malfunction of the write completion detecting circuit due to the influence of the unused column address can be reduced as much as possible.

As shown in FIG. 24, programming may be performed in accordance with the algorithm shown in FIG. 22 using fuses. In the case of FIG. 24A, two write detection MOS transistors are connected to one data latch and sense amplifier. One fuse is connected to each of these two transistors. Fuse cutting at the time of programming is performed simultaneously for two fuses. Therefore, one fuse may be used as shown in FIG. FIG. 24 (a),
In (b), a nonvolatile memory can be used as the fuse.

The circuits shown in FIGS. 19B and 19C are
The same function can be provided even if each is changed as in (a) and (b). In addition, FIG.
As shown in (b), as the detection MOS transistor, p
A channel E type MOS transistor may be used.
FIG. 27 shows an example in which a MOS transistor for detection is directly connected to a bit line. Also in this example, a nonvolatile memory can be used for the fuse.

FIG. 28 is a time chart for explaining the third embodiment. This is for explaining the operation of collectively latching "0" and "1" program data in the data latch and sense amplifier circuits at all column addresses, respectively.

In FIG. 6A, φF is maintained at “L”, I / O becomes “H”, / I / O becomes “L”,
φSP = “L” and φSN = “H”. Then, φR
P = “L”, φRN = “H”, and the “1” latch ends.

In the case of the "0" latch, I / O = "L" and / I / O = "H" as shown in FIG. After the FF becomes inactive, first, φRP = “L”, φRN =
It becomes "H". Subsequently, φSP = “L”, φSN =
It becomes "H".

FIG. 29 is a time chart for explaining the fourth embodiment. This chart shows that data latch and sense amplifiers at all column addresses have "0" or "1".
The operation when latching program data is shown. φA and φB remain “L”, and the potential of I / O and / I / O is determined according to data “0” or “1”. φP =
“H”, φN = “L”, and the FF is inactivated.
Thereafter, φE becomes “H” and is equalized. After the equalization is completed, the all-column selection signal CSL becomes “H”, φP = “L”, φN = “H”, and latched.

It should be noted that all columns in FIGS. 28 and 29 are, for example, when a cell array is divided and a data latch / sense amplifier is also divided accordingly. Refers to all columns.
In FIG. 8, the open bit line system is used, but the same can be applied to the folded bit line system.

FIG. 30 shows a modification of the third embodiment.
This shows a case where two CMOS flip-flops FF are shared by two adjacent bit lines. P-channel E-type write detection MOS transistors T1, T2 are provided at the end of bit line BL opposite to flip-flop FF.
2 gates are connected. Same column selection signal CSL
fuses F of write detection transistors T1, T1; T2, T2 whose gates are connected to the bit line selected by i
1 and F2 can be shared as shown in FIG. Further, the fuses F1 and F2 can be inserted between the power supply potential _Vcc and the sources of the write detection transistors T1 and T2 (FIG. 31A). In this case, the two fuses
One fuse F can be shared (FIG. 31)
(B)).

As described above, according to the third and fourth embodiments,
In addition to the effects similar to those of the first and second embodiments described above,
The following effects can also be obtained. That is, when detecting the result of the write verify read, the write state can be confirmed without being affected by the unused column address or the defective column address. As a result, it is possible to obtain an EEPROM having a write end detection circuit with extremely few malfunctions.

Next, a fifth embodiment of the present invention will be described. FIG. 32 shows a NAND cell type EEPROM according to the fifth embodiment.
It is a block diagram of M. For the memory cell array 1,
A bit line control circuit 2 for performing data write, read, rewrite, and verify read is provided. This bit line control circuit 2 is connected to a data input / output buffer 6. The output of the column decoder 3 is applied to the memory cell array 1 via the bit line control circuit 2.
The column decoder 3 receives an address signal from the address buffer 4 and a redundant address signal output from the column redundancy circuit 10. The address signal from the address buffer 4 is applied to the column redundancy circuit 10. Further, a row decoder 5 is provided to control a control gate and a selection gate in the memory cell array 1. A substrate potential control circuit 7 is provided to control the potential of the p substrate or the n substrate on which the memory cell array 1 is formed.

The program end detecting circuit 8 detects the data latched in the bit line control circuit 2 and outputs a write end signal. The write end signal is output to the outside via the data input / output buffer 6. Also, since the bit line is charged to a predetermined voltage regardless of the address signal,
A bit line charging circuit 9 is provided. An equivalent circuit of the memory cell array 2 is shown in FIG.

FIG. 33 shows a specific configuration of the memory cell array 1, bit line control circuit 2, and bit line charging circuit 9. The NAND cells NC shown in FIG. 2 are arranged in a matrix. NCijr (i = 0 to k, j = 0 to
n) is a redundant part. Data latch and sense amplifier R /
W0 to R / Wm and R / W0r to R / Wkr are n-channel, E-type MOS transistor data transfer transistors QFn0 to QFnm and QFn0r to QF, respectively.
bit lines BL0 to BLm, BL0r to
It is connected to BLkr. Column select signals CSL0 to CSL which are inputs of a data latch and sense amplifier R / W
m, CSL0r to CSLkr are the outputs CSL0 to CSLm of the column decoder 4 and the outputs (CSL0r to CSLkr) of the redundancy circuit 10, respectively. Bit line BL0
ＢＬBLm, up to (k + 1) lines can be replaced with the bit lines BL0r〜BLkr of the redundant portion.

N channel E type MOS transistor Q
Rn0 to QRnm and QRn0r to QRnkr are reset transistors for resetting the bit lines to the ground potential. n-channel E-type MOS transistors QPn0 to QPnm, QPn0r to QPnkr
Is a charging transistor for transferring the bit line charging voltage VBL to the bit line as required.

The fuses F0 to Fm and F0r to Fkr are
This is for disconnecting between the charging transistor and VBL, and all the components connected to the unused bit lines including the defective bit line are disconnected. For example, when the bit line BL2 is replaced with the redundant bit line BL0r, the fuse F2 is cut. The remaining redundant bit lines BL1r to BLk
When r is not used, all the fuses F1r to Fkr are cut.

FIG. 34 shows the operation at the time of writing. Prior to the write operation, all data latches and sense amplifiers R /
W is reset to “0” program data. Thereafter, the program data is transferred from the data lines I / O and / I / O to the R / W and latched. While data is latched in all R / Ws, bit lines, control gates, and select gates are precharged. After the bit line reset signal φR becomes “L”, the bit line precharge signal φP and the charging voltage VBL become the power supply voltage _Vcc . Bit lines other than the unused bit lines, that is, the bit lines used are V
_Charged to _cc . Control gates CG1-C of NAND cell
G8 and select gate SG1 are charged to _Vcc . The selection gate SG2 is set to the ground potential during the writing operation. Thereafter, the bit line precharge signal φP and the charging voltage VBL are boosted to the intermediate potential VM (about 10 V), and the bit line B
L, the control gates CG1 to CG8, and the selection gate SG1 are also V
It is boosted to M.

After the data latch is completed, the precharge signal φP changes to “L”, the data transfer signal φF changes to _Vcc , and then the voltage is boosted to VM. By the latched program data, only the bit line where the “0” data is latched is set to the ground potential. Also, the selected control gate (here, CG2) has a high voltage V _pp (about 20 V).
Up to Unused bit lines including the defective bit line remain at the ground potential because the corresponding R / W is reset to “0” program data before the data latch operation. In a memory cell connected to a bit line in which “0” program data is latched in R / W, the threshold value increases. In a memory cell connected to a bit line in which “1” is latched in R / W, the threshold value does not change and the threshold value at the time of erasing is maintained.

After the control gates CG1 to CG8 and the selection gate SG1 are reset to the ground potential, the data transfer signal φF is grounded, the reset signal φR becomes “H”, and the bit line is reset to the ground potential.

During the write operation, the operation of resetting all R / Ws to “0” program data and the fuse cutting operation of the bit line charging circuit, which are performed prior to the data loading, cause the unused bit lines to be used. No intermediate potential VM is applied.

FIG. 35 shows a read operation. The reset signal φR becomes “L” and the precharge signal φP becomes “H”. As a result, all bit lines other than the unused bit lines are charged to VBL (typically V _cc ). The selected control gate (here, CG2) is grounded, and the remaining control gates CG1, CG3 to CG8 are set to “H”.
(Typically V _cc ). Since the threshold value of the memory cell in which the “0” data is written is high (V _th > 0 V), the bit line potential remains at “H”. Since the threshold value of the memory cell in which the “1” data is written is low (V _th <0v), the bit line potential becomes “L”. After the data of the memory cell is output to the bit line as a bit line voltage, the data transfer signal φF becomes “H”, and the bit line voltage is sensed by the data latch / sense amplifier R / W. Note that the potential of each part of the memory cell is the same as in Table 2.

As described above, according to the present embodiment, defective bits can be relieved by cutting the fuse of the bit line charging circuit, and the same effects as those of the third and fourth embodiments described above can be obtained. .

FIG. 36 shows the sixth embodiment, and FIG.
9 shows a specific configuration of the memory cell array 1, the bit line control circuit 2, and the bit line charging circuit 9.

Two adjacent bit lines BLai and BLb
i, BLajr and BLbjr (i = 0... m, j = 0.
k) for the data latch and sense amplifier R /
Wi, R / Wjr (i = 0... M, j = 0... K) are arranged one by one. Data transfer signal φFa, reset signal φRa, precharge signal φP for bit line BLai
a is prepared. ΦFb, φ with respect to bit line BLbi
Rb and φPb are prepared. The bit line charging voltage power supply VBL is prepared in common for BLai and BLbi.

FIG. 37 and FIG. 38 show the write and read operations, respectively. When BLai is selected, BLa
For i, the operation is the same as in the embodiment of FIG. The unselected bit line BLbi prevents erroneous writing to the memory cell connected to BLbi while being charged to the intermediate potential VM during the writing operation. BLbi keeps the ground state during the read operation, and functions to suppress coupling noise between bit lines. Table 5 shows the potential of each part of the memory cell.
Shown in

Table 5 Erase write read “0” “1” Bit line BLai Floating 0v 10v 5v Bit line BLbi 10v 10v 0v Select gate SG1 0v 10v 10v 5v Control gate CG1 0v 10v 10v 5v Control gate CG2 0v 20v 20v 0v Control gate CG3 0v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v 10v CG5 0v 10v 10v 5v Control gate CG6 0v 10v 10v 5v Control gate CG7 0v 10v 10v 5v Control gate CG80v 10v 10v 5v Select gate SG2 0v 0v 0v 5 Source line floating 0v 0v 0 v0 v0 v0 v0 base 0 FIG. 39 is a modification of the embodiment of FIG. here,
Four types of data I / O lines I / O0 to I / O3 are used, and a common column selection signal CSLi is input to four data latch / sense amplifiers R / W. If any one of the four bit lines to which CSLi is commonly input has a leak failure, it must be repaired collectively. For this reason, in this embodiment, four fuses are combined into one. In the embodiment shown in FIG. 36, similarly, as shown in FIG. 40, fuses of a plurality of bit lines that commonly input CSLi can be combined into one.

FIG. 41 is a modification of the embodiment shown in FIG. The example of FIG. 41 differs from the embodiment shown in FIG. 40 in that the fuse is divided into a fuse Fa for BLai and a fuse Fb for BLbi. In this case, the provision of the two fuses Fa and Fb inevitably increases the circuit area. However, since relief can be performed separately for BLai and BLbi, the relief efficiency is increased.
This rescue method will be described in detail with reference to FIGS.

FIG. 42 schematically shows the embodiment of FIG. When the repair is performed using only the column selection signal CSLi, BLai and BLbi are simultaneously replaced as shown in FIG. Similarly, in the case of FIG. 40, BLai0 to BLai3 and BLbi0 to BLbi3
Will be replaced at the same time. In contrast, FIG.
In the embodiment of FIG. 42, as shown in FIG. 42B, only the BLai or only the BLbi is replaced with the redundant portion BLajr or BLb.
jr can be replaced without any problem in operation. For this purpose, the column selection signal CSLi and the data transfer signal φF
The relief is performed by the logical product with a (or φFb).

FIG. 43 schematically shows FIG. 41. Similar to FIG. 42 (b), only BLai0 to BLai3 are BL
ajr0 to BLajr3 or BLbi0 to BLbi
Only 3 can be replaced with BLbjr0 to BLbjr3. In this case, the fuses may be connected as shown in FIG. As is clear from FIGS. 42 and 43, B
What is necessary is just to protect even the arrangement relation of La and BLb.

FIG. 44 shows an embodiment in which one data latch and sense amplifier R / W is shared by four bit lines. BLa1i and BLbli are adjacent to each other. R
BLa2i and BLb2i are arranged symmetrically with respect to / W. Even in such a case, CSLi and φFa1, φFa2, φ
By taking the logic of Fb1 and φFb2, various relief methods can be implemented as shown in FIGS.

Specifically, in FIG. 45A, the same R
/ W connected to four bit lines BLa1i, BLa2
i, BLb1i and BLb2i are simultaneously replaced. FIG.
5 (b), two bit lines BLa1i and BLa2i
Alternatively, replacement is performed using BLb1i and BLb2i as a unit.
In FIG. 46A, two bit lines BLa1i and BLb
1i or BLa2i and BLb2i as a unit. In FIG. 46B, each bit line is replaced with a bit line of a redundant portion.

In the embodiments of FIGS. 39, 40, and 41, as shown in FIGS. 47, 48, and 49, a precharge MOS transistor and a reset MOS transistor are replaced with a bit for forcing a column selection signal CSLi. Lines may be shared. When the bit line is precharged or reset, that is, φR or φP is “H”
Is set to "H". In this example, the signal φ
Although PR is required separately, the number of reset or precharge MOS transistors can be reduced.

In the fifth and subsequent embodiments, a fuse is provided between the bit line charging circuit and the terminal voltage power supply line for repairing a defective bit. However, these embodiments, the third and fifth embodiments, Can also be used in combination.

As described above, various circuit configurations for shortening the write verify time have been described using the first to sixth embodiments. Next, an embodiment using the present invention for erase verification will be described.

FIG. 50 shows a NAN according to a seventh embodiment of the present invention.
FIG. 2 is a block diagram illustrating a nonvolatile semiconductor memory device using a D-type EEPROM. The memory cell array 1 is connected to a sense amplifier / latch circuit 2 for performing data write, read, write, and erase verify. The memory cell array 1 is divided into blocks composed of a plurality of pages. This block is the minimum erasing unit. The sense amplifier / latch circuit 2 is connected to a data input / output buffer 6. An address signal from the address buffer 4 is input to the column decoder 3. The output from the column decoder 3 is input to the sense amplifier / latch circuit 2. A row decoder 5 is provided in the memory cell array 1 to control a control gate and a selection gate.
Is connected. P on which the memory cell array 1 is formed
A substrate potential control circuit 7 for controlling the potential of the mold region (p-type substrate or p-type well) is connected to the memory cell array 1.

The verify end detecting circuit 8 detects data latched in the sense amplifier / latch circuit 2 and
Outputs a verify end signal. The verify end signal is output to the outside through the data input / output buffer 6.

FIG. 51 shows a sense amplifier / latch circuit 2,
The connection relationship between the memory cell array 1 and the verify end detection circuit 8 is shown. In the circuit of FIG. 51, a detection means (detection transistor Qn12) controlled by the first output of the sense amplifier / latch circuit FF is provided.
As the detection transistor Qn12, an E-type n-channel MOS transistor is used. This transistor Qn12 is provided in each sense amplifier / latch circuit FF connected to each bit line BLi.
As shown in FIG. 51, the detection transistors Qn12 are provided in parallel by connecting their drains to the sense line VDTCE in common.

Next, the erasing operation will be described first with reference to the flowchart shown in FIG. When an erase command is input, the operation enters an erase verify cycle. If the erased state is detected, the erase is terminated at that point (YES in step 101). If it is detected in step 101 that the memory cell has not been erased, the erase operation is started (step 102), and then a verify operation is performed (step 103). If verify is NG, erase and verify are repeated a predetermined number of times (step 10).
4).

Next, the erasure confirmation operation will be described. In the erase operation, a high voltage (for example, 20 V) is applied to a p-type region (p-type substrate or p-well) where a memory cell is formed, and VSS is applied to a control gate. As a result, the threshold value of the memory cell shifts in the negative direction. Next, data of the memory cell is read. "H" of ΦF
First, Φsp is “H”, Φsn is “L”, Φr
p is set to “H”, Φrn is set to “L”, and the C ² MOS inverter is deactivated. Thereafter, / ΦP is set to “L” to precharge the bit line to VCC. Next, the selected control gate is set to VSS, and the unselected control gate is set to VCC.
Then, the selected gate is held at VCC for a certain period of time. At this time, if the selected memory cell is erased and has a negative threshold, a cell current flows and the bit line is discharged until it reaches VSS. Next, Φsp is set to “L” and Φsn is set to “H”, and the bit line potential is detected. Then, Φrp is set to “L”, Φrn
Is set to “H” to latch data. After that, it is confirmed whether the verification is completed by using the detection transistor. As described above, the sense line VDTCE is commonly connected to the drains of the sensing transistors of the plurality of sense amplifier / latch circuits. If all the memory cells have a negative threshold, the sense line VDTCE goes "H". In this case, check the next page. If at least one cell having a positive threshold value remains, VDTCE goes to the “L” state. In that case, the erasure is repeated until VDTCE is detected as "H". The detection result is output to the outside from the data input / output pin or the READY / BUSY pin.

In this embodiment, the data is confirmed page by page. However, the confirmation operation may be performed at once for all pages in one NAND block. In this case, VSS is applied to all the control gates in the selected block, and the read operation is performed in this state. At this time, if one memory cell still has a positive threshold value, the bit line is not discharged, so that it can be detected by the same method as in the above embodiment.

The voltage applied to the control gate does not necessarily need to be at the VSS level. A negative voltage may be applied to include a margin. Further, even when VSS is applied to the control gate and a positive voltage is applied to the source or the source and the p-type substrate or the p-well, a state in which a negative voltage is applied to the control gate is created. Good.
Further, a fuse may be provided between the source of the detection transistor and VSS. If the fuse of the sense amplifier / latch circuit corresponding to the defective bit line or the unused bit line for redundancy is cut off, there is no operational problem. As described above,
The state of erasure can be detected.

Further, these operations can be controlled systematically. In this case, the system is a NAND type EE
Each PROM block has a management table that stores whether the block is in an erased state. The host system or the controller that controls the nonvolatile semiconductor memory device performs NAND erasing when performing erasing.
First, the management table is referred to in order to detect whether or not the block to be erased of M is in the erased state. If the reference result is not erased, erase is performed. In the case of indicating that erasure has been completed, further erasure operation may not be performed.

Confirmation of erasure is also effective before a write operation. Before the write operation, it may be confirmed whether or not the area to be written is erased. In this case, it may be performed on a block basis or on a page basis.

In FIG. 51, the write verify operation is almost the same as the conventional one, so that the detailed description is omitted.

FIG. 53 shows an eighth embodiment of the present invention. The basic configuration is the same as FIG. In the eighth embodiment, the cell array is divided into two blocks 1A and 1B, and a common sense amplifier / latch circuit 2 is provided for these cell array blocks 1A and 1B. FIG. 54 shows the configuration of the sense amplifier / latch circuit. E type n
Channel MOS transistors Qn16 and Qn17 and E
The type p-channel MOS transistors Qp7 and Qp9 constitute a flip-flop FF. E type n
The channel MOS transistors Qn14 and Qn15 are
F is a transistor for equalizing. Qn27, Qn
28 is a detection transistor.

E-type n-channel MOS transistor Q
n18 and an E-type p-channel MOS transistor Qp
Reference numeral 8 denotes a FF activation transistor. E type n
The channel MOS transistors Qn19 and Qn20 are
F, two nodes N1 and N2 and cell array block 1
These are transistors for connection with bit lines in A and 1B.
Qn25 and Qn26 are transistors for precharging and resetting bit lines. Qn21 to Qn24 are transistors for connection between the bit line and the VCC line.

The verify operation after erasure having such a configuration will be described. Here, a case where bit line BLai of memory cell array 1A is selected will be described.

First, the bit line BLai is set to 3v, BLb
i is precharged to 2v (reference potential).
Thereafter, the precharge signals ΦPA and ΦPB become “L”, and the bit lines BLai and BLbi enter a floating state. Next, the selected control gate is connected to VSS,
The non-selected control gate is set to VCC, and the selected select gate is set to VCC, and held for a certain period of time. After the CMOS flip-flop is reset by the equalize signal,
ΦA and ΦB become “H”, and the nodes N1 and N2 are connected to the bit lines BLai and BLbi, respectively. ΦP becomes “L” and φN becomes “H”, and the bit line BLai is read. The read data is latched. afterwards,
The detection is collectively performed by the detection transistor Qn27.

Next, the bit line B of the memory cell array 1B
It is assumed that Lbi is selected. First, the bit line BLb
i is precharged to 3v and BLai is precharged to 2v (reference potential). Thereafter, the precharge signals ΦPA and ΦPB become “L”, and the bit lines BLai and BLbi
Becomes a floating state. Next, the selected control gate is set to VSS, the non-selected control gate is set to VCC, and the selected select gate is set to VCC, and held for a certain period of time.
The CMOS flip-flop is reset by the equalizing signal. Thereafter, ΦA and ΦB become “H”,
Nodes N1 and N2 are connected to bit lines BLai and BLb, respectively.
i is connected. ΦP becomes “L” and φN becomes “H”, and the bit line BLbi is read. The read data is latched. Thereafter, the detection transistor Qn28
Is detected collectively.

At the time of write verification of the memory cell array 1A, Qn28 is used as a sensing transistor. At the time of write verification of the memory cell array 1B, Qn27 is used as a detection transistor. In this manner, which detection transistor is used in the verify operation is controlled according to the memory address and the erase / write mode. Thus, the verify operation can be performed by one detection transistor.

FIG. 55 shows a ninth embodiment of the present invention. In the seventh embodiment of FIG. 51, the detection transistors are connected to both nodes of the sense amplifier / latch circuit. In contrast, in the ninth embodiment, a p-type detection transistor and an n-type detection transistor are connected to one node of the circuit. At the time of write verification, an n-type detection transistor is used as in the related art. At the time of erase verification, a p-type detection transistor is used. After erasing,
Perform the reading operation. If there is an insufficiently erased memory cell, "H" is latched at the node on the bit line side of the sense amplifier / latch circuit, and "L" is latched at the node opposite to the bit line. As a result, the p-type detection transistor is turned on, and VDTCE becomes “H” level. This potential is detected, and the erase operation is performed again.

FIG. 56 shows a tenth embodiment of the present invention. In the eighth embodiment shown in FIG. 54, the detection transistors are connected to both nodes of the sense amplifier / latch circuit. In contrast, in the embodiment, a p-type detection transistor and an n-type detection transistor are connected to one node of the circuit. For the write verification of the memory cell array 1A, an n-type detection transistor Qn28 is used. Qp is used for erase verification of the memory cell array 1A.
29 p-type detection transistors are used. For write verification of the memory cell array 2A, a p-type detection transistor of Qp29 is used. For the erase verification of the memory cell array 2A, an n-type detection transistor Qn28 is used.

The embodiment using the present invention for erase verify has been described above. Needless to say, this configuration can also be applied to a NOR type cell as in the above-described write verify.

As described above, by using the present invention for erase verification, the following effects can be obtained. That is, the erase verify operation can be performed at a high speed without reading data to the outside. Further, when the cell array is composed of two blocks, one detecting means
Erase verification of one memory cell array block;
It can be used for write verification of the other memory cell array block. As a result, the area of the batch verify circuit can be reduced. Further, prior to the erasing operation, a means for detecting whether or not the selected block is in an erasing state is provided. For this reason, it is not necessary to perform an unnecessary erasing operation at the time of rewriting or the like. As a result, it is possible to increase the speed and increase the reliability.

Subsequently, the first batch verification means is used to perform both the erase verification and the write verification.
One embodiment will be described.

The features of this embodiment are as follows. That is, program verify and erase verify
Read all 256 bytes at once and click OK
Batch verification control circuit B to determine whether
BC was provided. Further, the data register circuit DR is configured to be capable of performing batch verification, and is configured not to write again to the program completion bit when re-programming is performed as program verification NG after program verification. Further, a reprogram control circuit RPC for controlling the data register circuit DR as described above is provided.

Hereinafter, the EEPROM of FIG. 57 will be generally described. The EEPROM shown in FIG. 57 has a byte configuration having an output of 8 bits and a configuration of 256 bytes per page. The memory cells are arranged in a matrix of m rows × 256 bytes in the memory cell array MCA. That is, m word lines are emitted from the row decoder RD. Further, in each byte, 8 NAND cells B in which eight rows of memory cells are vertically connected
Eight Cs are arranged in the row direction to form one NAND cell row unit RU, and (m / 8) of the row units RU are arranged in the column direction. In each unit RU, the drain of each 8 NAND cell BC is connected to the corresponding bit line BL.
, And all sources are commonly connected to V _SS .

In each unit, the control gates and eight select gates of eight memory cells arranged vertically are connected to a row decoder RD via eight word lines WL and SGD and SGS.

Each bit line BL'OO is connected to a data register circuit DR for latching data at the time of reading and writing. This data register circuit D
R outputs two types of signals, an output IO amplified according to whether the potential of the bit line BL'OO is high or low and an inverted signal NIO thereof. The IO and NIO signals are input to a common IO bus line I / OBUS via a column gate transistor CGT which is turned on and off by output signals of the column decoders CDI and CDII. Signals IO and NIO are input from each common IO bus line I / OBUS to the sense amplifier circuit S / A. The output signal d ^* of the sense amplifier circuit is input to the output buffer circuit I / OBUF.

A write precharge circuit WPC for raising the bit line BL to a high potential at the time of writing and a read precharge circuit RPC for precharging the bit line BL at the time of reading are connected to each bit line BL. ing. The write pre-charge circuit WPC, the drain and the signal BLCRL is, the signal BLCD to the gate is configured to the other end (source) bit lines are connected, a transistor TW ₁ of the n-channel type. Also,
The read precharge circuit RPC has a power supply V _{DD at} one end,
A transistor TR ₁ which gate signal PRE bit line is connected to the other end, the bit line to one end, gate signal RST, V _SS is connected to the other end transistor TR ₂
It is composed of

The data register circuit DR includes a latch circuit composed of two inverters IV1 and IV2, and a signal B
The LCD has a transistor TT which is input to a gate and is connected to a bit line of a memory cell. Further, it has two transistors T _PV and T _EV connected to the respective output terminals of the two inverters IV 1 and IV 2.
One end of the transistor T _PV is the signal IO is applied, the signal PROVERI is input to the gate. One end of the transistor T _EV is connected to NIO, the gate signal E
RAVERI is input. The other _ends of these transistors T _PV and T _EV are commonly connected to the gate of the transistor T ₁₄ . One end of the transistor T ₁₄ is connected to V _SS, the other end collective verify control circuit BB
C has been entered. In addition, it has transistors T ₁₁ and T ₁₂ . Transistor T ₁₁ is n-type, one end of which is connected to the power supply BLCRL, signal NIO is input to the gate, the other end is connected to one end of the transistor T _12. The gate of the transistor T _12, the output signal PV of reprogramming control circuit RPCC is input. Transistor T ₁₂ and the other end is connected to the bit line BL'00.

The batch verify control circuit BBC outputs the signal P
It has a two-input NOR circuit NOR1 to which the ROVERI and the signal ERAVERI are input. The NOR circuit NOR
1 is input to the respective gates of the transistors TP ₁ and TN ₁ . One end of the transistor TP ₁ is to supply V _CC, the other end is connected to one terminal of the transistor TN _1. The other end of the transistor TN ₁ is connected to V _SS. The midpoint between the transistors TP ₁ and TN ₁ is connected to the transistor T ₁₄ in each data register circuit DR and to the input side of the inverter IV 3. The output signal PEOK of the inverter IV3 is output to the outside via an IO buffer circuit (not shown) as a determination signal of whether or not it is OK at the time of verification.

The reprogram control circuit RPCC has an inverter IV _RP and a flip-flop circuit FF _RP .
Signal PROVERI is input to inverter IV _RP . An output signal and an inverted signal of the inverter IV _RP are input to each of two NOR circuits in the flip-flop circuit FF _RP . Output signal P of flip-flop circuit FF _RP
V is input to the gate of n-channel transistor T ₁₂ of the data register circuit DR as the control signal.

Next, the EEPROM constructed as described above will be described.
Will be described. At the time of erasing, a high voltage (about 20 V) boosted by the erase boosting circuit SU6 is applied to the substrate (p-well) on which the memory cells are formed.
At the same time, the word lines WL1 to WLm and the select gates SGD, SGS are controlled by the row decoder RD.
Is set to “0” V, and the electrons are erased by extracting electrons from the floating gate to the substrate.

Next, the read operation will be described. The row decoder RD sets the select gates SGD and SGS of the row unit RU having the cell to be selected to “H” level for selection. Further, a target cell is selected by setting its word line WL to "0" V.
After this state, applying a predetermined pulse signal as a signal PRE, by turning the transistor TR _1, the bit line BL
Is precharged to “H” level. At this time, when "0" data is written in the memory cell to be read, the memory cell is turned off and no current flows. Therefore, the level of the bit line BL maintains the “H” level, and the level H is latched by the data register circuit DR.
On the other hand, when "1" data is written in the selected cell, the memory cell turns on. Therefore, the bit line BL
Becomes "1" level, and that level is latched by the data register circuit DR. At this time, 256 connected to the selected (low level) word line
All data of the byte is latched by the data register circuit DR connected to each bit line.
Then, by changing the serial column address A _c added to the column address buffer CAB from "00" to "FF", the column gate transistors CGT in bytes 1 to 256 are sequentially turned on, the common bus line IO bus Are sequentially read via the.

At this time, due to the structure of the NAND cell, the ON current of the memory cell is very small, about several μA, and it takes about several μsec to charge and discharge. However, once the data is read out and taken into the data register circuit DR, only the data is output via the common bus line I / OBUS, so that a high-speed access of about 100 nsec is possible.

Next, the write operation will be described. FIG. 58 shows a timing chart for explaining the writing operation.

When the program command PC is input, the mode is changed to the program mode. At this time, the signal BLCD for controlling the transmission transistor TT of the data register circuit DR becomes “L” level, and the transistor TT
Turns off. At the same time, the booster circuit SU starts to operate, and the signals BLCRL and BLCU input to the write precharge circuit WPC gradually increase in voltage.
It rises to about V. At this time, the potential of the bit line BL'OO in the memory cell array group also rises with the rise of BLCRL. At this time, the selected WL is 20 V
The potential of the select gate transistor on the source side of the NAND cell group is set to 0 V, and the other gates are set to 1
Each is set to an intermediate level of about 0V.

In this state, the column address _Ac is sequentially changed, and write data is input to the data register circuit DR. At this time, the write data input to the data register circuit DR is latched there. When 256 bytes of write data are latched in the data register circuit DR, the signal BLCU goes to "L" level and the write precharge circuit WPC is turned off. At the same time, the signal BLCD rises to about 10 V, the transistor TT turns on, and the bit line BL'OO and the data register circuit DR are connected. At this time, the power supply VBIT supplied to the data register circuit DR also rises to about 10V. If "1" level is latched in the circuit DR, the high level of the bit line BL is maintained as it is. If the "0" level is latched in this circuit DR, the level of the precharged bit line BL is discharged to "L" level, and electrons are injected into the floating gate. In this way, writing for 256 bytes is performed simultaneously.

In the following, each operation of program → program verify → reprogram will be described with reference to a timing chart shown in FIG.

The first program operation is the same as in FIG. That is, when the program mode is entered by inputting the program command PC, the control signal BLCD becomes “L”.
Level, the transmission transistor TT in the data register circuit DR is turned off, and the data register circuit DR is disconnected from the bit line. At the same time, the booster circuits SU1 to SU6 start operating, and the signals BLCRL, B input to the write precharge circuit WPC.
The LCU gradually increases its voltage to reach about 10V. At this time, the potential of the bit line in the memory cell array MCA also rises to a high potential with the rise of the signal BLCRL. At this time, the selected WL is set to a high potential of about 20 V,
Source side select gate transistor T ₂ in the cell group
Gate (select line SL2) is the "0" V, the other transistor T ₁ of the gate (select line SL1) is set to an intermediate level of about 10V.

In this state, the column address _Ac is sequentially changed, and 8-bit write data for a certain byte n is input to the eight data register circuits DR and latched. This is repeated 256 times, and 256 bytes of write data are latched in all the register circuits DR. Thereafter, the signal BLCU becomes "L" level, and the write precharge circuit WPC is turned off. At the same time, when the signal BLCD rises to about 10 V, the transistor TT turns on and the bit line and the data register circuit DR are connected. At this time, the power supply VBIT supplied to the data register circuit DR also rises to about 10V. If "1" level data is latched in the data register circuit DR, the level of the bit line is maintained at a high level. Further, the data register circuit D
If the “0” level is latched in R, the high level of the precharged bit line is reduced to “L” level by discharging, and electrons are injected into the floating gate in the selected memory cell, ie, “0”. "Data writing occurs. Such writing is performed simultaneously for 256 bytes. The writing operation so far is the same as in the case of FIG.

Next, when the above-mentioned writing is completed, a verify command VC is inputted, and the program mode is released. The signal BLCD becomes “0” V, and BLCR
L goes to “5” V, the signal VBIT goes to 5V,
The bit line is discharged by the reset signal RST. At this time, in this embodiment, the latch data in the data register circuit DR is not reset. That is, the write data remains latched in the data register circuit DR. In this state, an H-level control signal PRE is applied to the read precharge circuit RPC, and the bit line is precharged. Now, consider a case where “0” data is written. Due to the latch circuit in the data register circuit DR, the signal IO is at "1" level, and the inverted signal NIO is at "0" level. In this case, at a program verify mode, the transistor T ₁₂ of the data register circuit DR is turned on, the transistor T ₁₁ is the level of that of the gate signal is turned off for "0" level, this path Is not charged to the bit line.

After such a “0” write operation, there are two cases, that is, the case where the writing becomes NG and the case where the writing becomes OK. That is, when it becomes OK, the threshold voltage of the memory cell is shifted in the positive direction, and the precharged potential is maintained as it is. Then, a signal BLCD for controlling the transmission transistor TT
Becomes "1" level, the data register circuit D
R and the bit line are connected, and N which has been at "0" level until now
The potential of IO is increased by the bit line charged to a high potential.
It is charged to “1” level. Therefore, the signal PROVER
I is via the transmission transistor TT inputted "0" level is input to the gate of the transistor T _14, the transistor T ₁₄ is turned off.

On the other hand, consider the case where the writing is NG. That is, despite writing "0", the threshold voltage of the memory cell exists in the negative direction, so that the potential is discharged to the "0" level while being precharged. And the transmission transistor TT
Is turned to "1" level, the transistor TT is turned on, and the data register circuit D
R and the bit line are connected. However, this time, the potential of NIO remains "0" level, the gate of the transistor _T 14 is "1" level signal is input, the transistor T ₁₄ is turned on.

Next, consider the case where "1" data is written. When "1" is written, the signal IO is set to "0" level and the signal NIO is output by the latch circuit in the data register circuit DR.
Is at the “1” level.

[0159] When performing the verify operation in this state, transistor T ₁₁ of the data register circuit DR is turned on. For this reason, the bit line continues to be charged through the transistors T ₁₁ and T ₁₂ during the verify operation. Read transistor TR ₂ for precharging is set as a smaller conductance gm is discharged to "0" level by the on current when the memory cell is turned on in the read. However, the conductance gm of the transistors T ₁₁ and T ₁₂
Is set to a large value so that the bit line is always charged to the “1” level by the verify operation after the “1” write. That is, the gate is "0" level signal of the transistor T ₁₄ is inputted.

In addition, there may be a case where the threshold value of the memory cell is increased due to erroneous writing despite writing "1". In such a case, even if the verify operation is performed, the transistor T
A signal of "0" level is input to the gate ₁₄ . Therefore, there is a problem that it cannot be distinguished from the above case.
However, the presence or absence of such erroneous writing is determined by a test at the time of product shipment. For this reason, such erroneous writing hardly needs to be considered in practical use.

[0161] In this manner, the gate of the transistor T ₁₄ of the data register circuit DR connected to each bit line, in response to the read data by performing a verify operation "0" level or "1" The level is entered. That is, when the bits of the program NG exists even one, the input signal to the gate of the transistor T ₁₄ is "1" level. Thus, transistor T ₁₄ is turned on, the signal PEOK becomes "1" level, indicating a verify NG.

At this time, a new program command PC
Enter II to reprogram. At the time of this reprogramming, unlike the first programming, of the latch data in the data register circuit DR, the program O
The data of the K bit has been changed to "1" write data. Therefore, "0" write is performed only for the NG bit. In other words, no additional writing is performed on the bits that have been programmed OK as a result of the programming, and therefore no further increase in the threshold voltage occurs. In this way, re-programming is performed several times, and when all bits become program OK,
All the gate signals of the transistors are at "0" level. At this time, the signal PEOK becomes the "0" level for the first time, and the program ends.

By using the above method of the present invention, at the time of verification, the column address is not changed sequentially,
The verify operation can be performed collectively. Therefore, the verification time can be shortened, which leads to a reduction in the programming time. Also, when re-programming is performed at the time of verify NG, the program completion bit is not re-programmed. Therefore, the distribution of the threshold voltage can be reduced, and the read margin can be improved.
FIG. 60 shows the V _th distribution during the write operation when the present invention is used. When writing is performed from the erased state, the memory cell FMC in which writing is fast is OK, but the cell SMC in which writing is fast is NG. When reprogramming is performed in this state, no additional writing is performed on the memory cells for which verification is OK. For this reason,
No threshold rise occurs. In other words, the distribution width of the threshold voltage at the time when the cell SMC in which writing is slow becomes verify OK can be narrower than V _th DB. As a result, a sufficient read margin RM can be secured.

The above description has been made on the basis of the program operation. However, in the case of the erase operation, the read operation of whether or not the erase is OK can be performed collectively as in the case of the program verify. That is, erase verify is to be input a signal NIO to the transistor T _14. For this reason, when the erase is OK, the signal PEOK is “0”.
Level and batch verification becomes possible.

FIG. 61 shows a flowchart in the erase mode. As can be seen from FIG. 61, in the erase mode, the erase operation itself is the same as the conventional one,
Verify operation can be performed at once. Therefore, the verification time can be reduced.

In FIG. 57, I / O BUF is an output circuit, the details of which are shown in FIG. 62, for example.

FIG. 63 showing a conventional example shows a part of an array in which a plurality of memory cells are arranged as a memory cell array in a matrix of m rows × 256 bytes.

The bit line is usually formed of an Al film having a thickness of several thousand angstroms and a pitch of several μm.
They are arranged at a pitch. Therefore, there is an interlayer capacitance between adjacent bit lines. In the figure shows the inter-layer capacitance of the bit lines BL1 and BL2 C _12, an interlayer capacitance of the bit line BL2 and bit line BL3 as C _23.
Further, since the bit lines are wired on the memory cells, there is also a capacitance with respect to the substrate. This is called C ₁ , C ₂ , C
Expressed as ₃ . The memory cell is connected to a bit line via a selection transistor. Therefore, capacitance also exists at the junction of the selection transistor. These are represented as C _1j , C _2j and C _3j .

For example, taking as an example a 16M NAND E ² PROM composed of 8192 × 256 bytes of memory cells, the capacitance between the bit line and the substrate C ₁ = C ₂ = C ₃ = 0.3
9 pF, interlayer capacitance C ₁₂ = C ₂₃ = 0.
14 pF, capacitance C _1j = C _2j = C _3j = 0.11p at the junction
F.

As described above, when data is read from the memory cell, the bit line is precharged to the level of the power supply voltage Vcc and whether or not the precharged potential is discharged is performed. That is, in the case of the "1" cell, the memory cell is turned on to discharge the precharged potential. Also,
In the case of the "0" cell, the precharged potential is held as it is because the memory cell remains off. now,
Consider three adjacent bit lines. Bit lines BL1 and B
L3 is connected to a "1" cell, and only the bit line BL2 is connected to a "0" cell. When reading, the bit line BL2 is not discharged, and the bit lines BL1 and BL3 are discharged. At this time, since the above-described capacitance exists, the bit line BL2 is affected by the potential fluctuation. That is,
If the voltage displaced by the influence is ΔV, It becomes.

As described above, a potential drop of about 1.8 V occurs. This applies not only to the read operation but also to the verify operation at the time of programming. At the time of program verification, there may be memory cells that have not been sufficiently written, so that the operation margin is further strict.

The description is given below. FIG. 64 shows a timing chart at the time of program verification.

When a program command PC (not shown) is input, a program mode is set. At this time, the transmission transistor T of the data register circuit DR
The signal BLCD for controlling T becomes "L", and the transistor TT turns off. At the same time, the booster circuit SU starts operating, and the signals BLCRL and BLCU input to the write precharge circuit WPC (see FIG. 55) gradually increase to about 10V. At this time, the potential of the bit line BL in the memory cell array group also rises with the rise of BLCRL. At this time, the selected WL
Is set to a high potential of about 20 V, the gate of the select gate transistor on the source side of the NAND cell group is set to 0 V, and the other gates are set to an intermediate level of about 10 V.

In this state, the column address AC is sequentially changed, and write data is input to the data register circuit DR. At this time, the write data input to the data register circuit DR is latched there. When 256 bytes of write data are respectively latched in the data register circuit DR, the signal BLCU becomes "L" and the write precharge circuit WPC is turned off. At the same time, the signal BLCD rises to about 10 V and the transistor TT
Turns on, the bit line BL and the data register circuit DR
Is connected. At this time, the power supply VBIT supplied to the data register circuit DR also rises to about 10V. If "1" is latched in this circuit DR, the bit line B
“H” of L is maintained as it is. If "0" is latched in the data register circuit DR, the level of the precharged bit line becomes "L", and electrons are injected into the floating gate. In this way, writing for 256 bytes is performed simultaneously.

When the writing is completed, a verify command VC (not shown) is input, and the program mode is released. The signal BLCD becomes 5V and BLCRL becomes 0.
V, the signal VBIT becomes 5V, and
The bit line BL is discharged by the reset signal RST.
At this time, the write data is simultaneously reset in the data register DR.

In this state, the read precharge circuit RP
The transistor TR1 in C is turned on by the control signal PRE, and the bit line is precharged. Then, the data in the memory cell is read out as described above, and the write data is verified.

That is, by setting the signals Pv and BLCD to the "H" level in anticipation of the time when the bit lines have been sufficiently discharged, the "L" and "H" levels of the bit lines are transferred to the data latch circuit DR. Transfer and re-latch the reprogram data. If verify NG, that is, if “1” is read out despite writing “0”, the bit line is at “L” level. Therefore, the “L” level is latched as it is.
At the time of rewriting, "0" is written again. On the other hand, when the verification is OK, the bit line is at the “H” level. At this time, the signals Pv and BLCD become "H".
When the level becomes the level, the “H” level of the bit line is transferred to the data latch circuit DR, and the latch data is inverted from “0” data to “1” data. That is, when reprogramming, the threshold voltage does not rise because "1" is written. The bit line to which "1" is written is discharged to "L" level at the time of verification. Signal Pv is "H"
When it is level, the gate for "1" in the transistor T ₁₁ is the data register DR is latched to the "H" level. Thereby, the transistors T ₁₁ ,
Bit line via a T ₁₂ becomes "H" again level. When the signal BLCD goes to “H”, the bit line goes to “H”.
The level is again latched by the data latch circuit DR. In this way, N of the bit lines to which "0" is written
Reprogram is performed only for the G bit.

However, when such a program verify operation is performed, there are the following problems. Next, the problem will be described.

FIG. 65 is a diagram showing a combination of write data WD and verify data VD for three adjacent bit lines.

In the figure, "1" is written to the bit lines BL1 and BL3, "0" is written to the bit line BL2, and the bit for which "0" is written is a verify NG. That is, in the verify operation, the precharged potential is discharged to “L” level for all three bit lines. When the bit line is sufficiently discharged, the signal Pv goes to "H" level, and reprogram data is set. That is, since the bit lines BL1 BL3 are "1" write, as the description, the charge from the transistor T _11, T ₁₂ becomes "H" level. At this time, the transistors T _11, T _12, through the memory cell, the DC current paths exist toward the power supply Vcc to the Vss. Therefore, the gm of the transistors T ₁₁ and T ₁₂ is set to be sufficiently large with respect to the gm of the memory cell so that the “H” level thereof is sufficiently ensured.

The bit line BL2 is set to “0” write NG
Therefore, the bit line BL2 is also discharged to the "L" level and the bit line BL2 remains at the "L" level even if the signal CON goes to the "H" level. At this time, the problem is that the potential of the bit line is recharged from "L" level to "H" level when reprogramming data is set in the bit line to which "1" is written. That is, as described above, the level of the bit line BL2 also rises due to the influence of the coupling between the adjacent bit lines (Tup). For example, considering the drop of the threshold due to the transistor T _11, when the power supply voltage Vcc is 5V,
Lift from 0V to 4V. At this time, the bit line BL
The level of 2 will change by ΔV = 0.358 × 4 = 1.4V.

In addition, the distribution of the potential level after the predetermined verification also varies due to the variation in the threshold distribution of the memory cell writing “0”. This is shown in FIG. The level after the verification may be completely discharged to “0” V or may be discharged only to about 1 V. At this time, under the influence of the above-described coupling, the potential fluctuates up to 2.4 V and exceeds the sense level. In other words, a memory cell that should become “0” write NG is erroneously detected as “0” write OK, and the operating margin of the memory cell is reduced.
In the example of the combination shown in FIG. 65, there is no combination that malfunctions due to coupling.

A method for solving the above problem will be described below. The operation of writing data to the memory cells after the program command is input is the same as the operation described with reference to FIG. The difference is the operation at the time of program verification. In the program verify mode, the bit line is precharged by the signal PRE. When the precharging of the bit line is completed, a verify read operation is performed. At this time, the signal Pv is also set to the “H” level. As a result, for the bit line to which “1” is written, the transistors T ₁₁ ,
Since T ₁₂ is turned on, it will be charged. Therefore,
The "H" level is maintained without being discharged to the "L" level. Then, after a predetermined time, the signal BL
By setting CD to “H” level, the potential level of the bit line is transferred to the data latch circuit DR, and detected and latched. That is, the bit line to which "1" is written is always at "H" level, and "0" is written to verify OK.
Also goes to "H" level. Verify N
The G bit line will be discharged. By doing so, the bit line of "1" write is not discharged as described above. Therefore, when the rewrite data is set, the above-described potential change from the “L” level to the “H” level does not occur.

Therefore, data can be detected without being affected by coupling. For this reason, there is no possibility of erroneous data detection. This is shown in FIG.
It can be seen that the combination of FIG. 68 is improved compared to the case described in FIG. This is shown in FIG. 69 in comparison with FIG. As described above, at the time of rewriting setting, lifting due to the influence of bit line coupling is eliminated, so that data can be read correctly.

FIG. 70 shows a rewrite setting transistor T
₁₁ and ₁₂ show other examples. (A) is an example used in the above description, and (b) is another example. As the transistor T _11, by using a transistor having a threshold voltage near 0V, the "H" level of the bit line at the time of verification can be set close to Vcc. The gate of the transistor T _12, by inputting the boosted potential, further effect increases. That is, the amount of potential drop (threshold drop) with respect to the power supply voltage Vcc is reduced, so that a larger margin is obtained in the read operation.

FIGS. 71 to 77 are general circuit diagrams used to carry out the above-described method, and a description thereof will be omitted.

By performing the verify operation in such a manner, the influence of bit line coupling can be ignored.

Although not particularly mentioned in the above description, at the time of program verification, the gate of the memory cell is raised by about 0.5 V in order to obtain a margin for the "0" cell.

[0189] As described above, with respect to the "1" write to that cell, when the verify operation, always transistors T _11, T ₁₂ is turned on, the current through the memory cell,
It will be flowing.

The sources of the memory cells are commonly connected outside the memory cell array, and a high voltage of about 20 V is applied at the time of erasing, and is connected to a Vwell circuit for setting to the GND level at the time of programming and reading. That is, the wiring resistance of the source line exists. It is assumed that a current of about 10 μA flows per cell during verification. When "1" is written for about one page, 2
A current always flows through the 56-byte memory cell. That is, 256 × 8 × 10 μ = 20 mA.

Assuming that a resistance of about 20Ω exists in the source line, the voltage of the source line rises by 0.4 V. On the other hand, when “0” is written for almost one page, almost no current always flows. Therefore, the potential of the source hardly rises and becomes the GND level. That is, there is a problem that the source potential at the time of program verification changes due to the write pattern.

At the time of reading, since there is no path for a current which always flows, the level of the source is almost at the GND level. Therefore, the distribution of the memory cells differs depending on the write pattern, and the operation margin of the memory cells differs. Also, when writing the "1" pattern for most of the cells for one page, the source potential at the time of program verification is different from that at the time of reading. Therefore, even if the verification is OK, it will be NG if actually read.

FIG. 78 shows the structure of a chip. At the time of program verification, the ground of the circuit that raises the gate of the memory cell by about 0.5 V is connected to the Vss line of the peripheral circuit. The source line of the memory cell is connected to the Vwell circuit. Therefore, even if the source line of the memory cell floats due to the write pattern, the source of the verify level setting circuit does not float, resulting in a difference in the potential of the source line. Therefore, it is assumed that the verify level is set to 1.0 V in anticipation of floating of the source. Assuming that the threshold voltage distribution of the written memory cells is 2.5 V, when "0" is written in almost all cells of one page, the upper limit of the written memory cells is (1 V + 2.5 V =) 3.5 V. . On the other hand, when almost "1" is written, the potential of the source also increases by about 0.5 V, so that the gate of the memory cell is equivalent to 0.5 V, and the upper limit is 0.5 V + 2.5 V. The threshold value is 3.0V. This difference results in a difference in AC characteristics and a difference in reliability.

[0194] As shown in FIG. 79 to solve this problem, the source of the verify level setting circuit via a transistor T _A, is commonly connected to the source of the memory cell. _A signal "PROVERI" which becomes "H" level during program verify is applied to the gate of the transistor TA. With this configuration, at the time of program verification, the source of the verify level setting circuit is common to the source of the memory cell, and therefore, a change in the source potential of the memory cell can be directly reflected.

Therefore, if the source floats by 0.5 V, the output potential also becomes higher than the set value by 0.5 V, so that a constant voltage is always applied between the source and the gate of the memory cell. . That is, no matter what pattern you write,
The same distribution can be obtained, and higher reliability can be obtained.

FIG. 80 shows a verify level setting circuit, and FIG. 81 shows a Vwell circuit. Next, a description will be given of a modification of the eleventh embodiment in which the same effect as that of the eleventh embodiment (FIG. 55) can be obtained with another circuit configuration. In FIG. 82 showing this modification, the same reference numerals are given to circuits equivalent to those in the eleventh embodiment (FIG. 55). FIG. 82 shows a memory cell array for one column and peripheral circuits corresponding thereto.

In this modification, unlike the eleventh embodiment, the data latch circuit DR has two data latch circuits DR1 and DR2. The first data latch circuit DR1 has two inverters connected directly in anti-parallel between IO and NIO. Second data latch circuit DR2, via a transistor T _31, T _32, with two inverters connected between the IO and NIO. The transistors T ₃₁ and T ₃₂ are controlled by the signal SDIC. Further, output signals of the first and second data latch circuits DR1 and DR2 are applied to an exclusive NOR circuit XNOR. That is, only when the logic levels of the two input signals match, the signal becomes “H” level. The output of the exclusive NOR circuit XNOR is connected to a transistor T controlled by a signal VREAD.
Added to IO via ₂₁ . Inverted signal of the output of this circuit XNOR through the transistor T ₂₂ which is controlled by a signal VREAD, applied to NIO. In FIG. 82, the transistors T ₁₁ and T
₁₂ has been removed because it is not needed.

The read operation and erase operation of the device shown in FIG. 82 are the same as those of the eleventh embodiment, and the description is omitted.

Hereinafter, the write operation will be described. The program operation is the same as that described above. The program command PC is input and the program mode is set. A column address and a page address indicating a page are input from the outside. At this time, the signal BLCD becomes "L" and the transistor TT turns off. At the same time, the booster circuit SU starts to operate, and gradually the write precharge circuit W
The signals BLCRL and BLCU input to the PC are boosted and rise to about 10V. At this time, the potential of the bit line BL in the memory cell array group also rises with the rise of BLCRL. At this time, the selected WL is 20 V
The potential of the select gate transistor on the source side of the NAND cell group is set to 0 V, and the other gates are set to 1
Each is set to an intermediate level of about 0V.

In this state, the column address AC is sequentially changed, and write data is input to the data register circuit DR. At this time, the write data input to the data register circuit DR is latched by the first data latch circuit DR1. After 256 bytes of write data are respectively latched in the first data circuit DR1, the signal BLCU is output.
Becomes "L", and the write precharge circuit WPC is turned off. Further, when the signal SDIC becomes “H”, the transistors T ₃₁ and T ₃₂ are turned on, and the second data latch circuit D
The write data is latched in R2. Then, the signal SD
Transistor T _31, T ₃₂ IC becomes "L" is turned off. The signal SDIC is set to “H” at the same time as the write data input.
As the level, the first and second data latch circuits may simultaneously perform a latch operation. At this time, VREAD
Transistors T _21, T ₂₂ because is "L" is OFF. At the same time, the signal BLCD rises to about 10 V, the transistor TT turns on, and the bit line BL and the data register circuit DR are connected.

At this time, the power supply VBIT supplied to the data register circuit DR also rises to about 10V. First
If "1" is latched in the data latch circuit DR1, the "H" of the bit line BL is maintained as it is. If "0" is latched in the first data latch circuit DR1, the level of the precharged bit line becomes "L", and electrons are injected into the floating gate. In this way, writing for 256 bytes is performed simultaneously.

Subsequently, as described above, after the program operation is completed, a verify command CF is input. As a result, the signal BLCD becomes 0V, and the BLCRL becomes 5V.
Then, the signal VBIT becomes 5 V, and the bit line is discharged by the reset signal RST. At this time, the write data remains latched in the second latch circuit DR2 in the data register circuit DR. In this state,
The control signal RP of "H" is supplied to the read precharge circuit RPC.
C is added and the bit line is precharged.

Subsequently, the signal BLCD becomes 5V, and accordingly, the read data is latched by the first latch circuit. At this time, the data is compared with the data latched by the second latch circuit DR2. Then, the signal BLCD
Becomes 0 V, and the data latch circuit is disconnected from the memory cell. Then, next signal VREAD is 5V, the transistors T _21, T ₂₂ is turned on, comparator result is latched by the first latch circuit DR1. This level is
An error is also determined under the condition that the write data is "1" and the verify data is "0", which is surrounded by a broken line. That is, the write data is “1” and the verify data is “0”.
The verify NG signal is output even under the condition ignored in the eleventh embodiment.

The verify read operation is the same as in the eleventh embodiment. That is, when a verify read command CF is input after a lapse of a predetermined time from the program operation, a verify output mode is entered. Then, / RE changes to “H” →
By sequentially changing from “L” to “H” to “L”, the column address AC is incremented one after another, and the contents of the latch data are sequentially stored in 256 bytes (256 times).
Output. In the circuit configuration of FIG. 82, the result of comparison described in FIG. 83 is output. That is,
"1" data is output in parallel with the verify NG bit, and "0" data is output in parallel with the other bits.

In the above description, a method of performing program, verify, and reprogram by inputting a command has been described. However, by inputting a program command, a verify operation and a reprogram operation are performed by an internal auto operation, and a PASS / FAIL judgment is performed. Can be performed, and this makes it easier to use.

FIG. 84 and FIG. 85 are basic conceptual block diagrams. The program autocommand is decoded by the command register circuit CR. Based on the output of the circuit CR, the logic circuit LOG1 outputs the pulse signal AUTOPules.
Is output. The signal AUTOPules is input to the flip-flop FF1, and is latched when the program mode signal PRO is at the “H” level.

Next, the program is started when the signal of PRO becomes "H" level. After a predetermined program time, the flip-flop FF1 and the command register circuit CR are reset by the program end signal PROE from the logic circuit 2. Program end signal PROE
Is input to the flip-flop FF1 as well as to the flip-flop FF11, and the verify mode is set. The predetermined verify time is determined by the binary counter B
Counted by C11.

At this time, the verify operation as described above is performed, and it is determined whether or not the verify is OK. If N
In the case of G, a counter P for counting the number of programs
The NC count value is incremented by one and reprogramming is performed. If OK, pass.

By doing so, it is possible to judge PASS or FAIL simply by inputting an auto program command, and it becomes easy to use.

Although the above description has been made based on the program operation, the erase operation can be considered in exactly the same manner.

Next, the combination of the verify read and the auto program will be described. If the verification remains NG after performing the reprogramming a predetermined number of times, the page (256 bytes) is treated as an error. Here, it is possible to identify from the outside how many bits of cells are verified NG. Here, this is called a verify read mode. Hereinafter, the operation of the program → verify read will be described with reference to the time chart of FIG.

The program operation is the same as that described above. When the program command PC is input, the mode is changed to the program mode. A column address and a page address indicating a page are input from the outside. At this time, the transmission transistor T of the data register circuit DR
The signal BLCD for controlling T becomes "L", and the transistor TT turns off (see FIG. 55). Also, with this,
The booster circuit SU starts operating, and the signals BLCRL and BLCU input to the write precharge circuit WPC gradually increase to about 10V. At this time, the potential of the bit line BL in the memory cell array group is also changed to BLCR
It increases as the potential of L increases. At this time, the selected W
L is set to a high potential of about 20 V, the gate of the select gate transistor on the source side of the NAND cell group is set to 0 V, and the other gates are set to an intermediate level of about 10 V.

In this state, the column address AC is sequentially changed, and write data is input to the data register circuit DR. In the figure, / WE functions as a latch signal for input data. At this time, the write data input to the data register circuit DR is latched there. 256 bytes of write data are stored in the data register circuit D, respectively.
When latched by R, the signal BLCU becomes "L" and the write precharge circuit WPC is turned off. With this,
The signal BLCD rises to about 10 V, the transistor TT turns on, and the bit line BL and the data register circuit DR are connected. At this time, the data register circuit DR
The power supply VBIT supplied to the power supply also rises to about 10V. If "1" is latched in the circuit DR, "H" of the bit line BL is maintained as it is. If “0” is latched in the data register circuit DR,
The level of the precharged bit line becomes “L”,
Electron injection into the floating gate occurs. Thus, 2
Writing for 56 bytes is performed simultaneously.

Subsequently, after a lapse of a predetermined time, not the batch verify command VC but the verify read command CF
To enter the verify output mode. The column address AC is incremented one after another, and the contents of the latch data are sequentially output for 256 bytes (256 times). "1" is output in parallel with the verify NG bit, and "0" is output in parallel with the other bits.

As described above, with the configuration using the batch verify circuit, it is possible to output whether or not the verification is NG to the outside of the chip. Here, the output data is not a data actually written in the cell as in the related art, but a verify NG signal indicating whether rewriting should be performed. Therefore, the number of cells having a write error can be counted without having to provide a comparator circuit or the like externally. The total of cells to which "0" is output in the verify read is the total of verify NG in "1" page. Also, of course, it is possible to specify at which address the verify NG was found.

Next, verify NG count and ECC
An embodiment combined with (error correction circuit) will be described. In general, a method of adding a redundant cell to compensate for an error cell has been used to improve the reliability of stored data.
For example, 64 bits of redundant bits are provided for a page of 256 bytes (2K bits). By performing Hamming coding using the Hamming distance as redundant bit data, data errors of up to 6 bits can be corrected. More generally, for an M-bit data string, N
By adding redundant bits of bits, T-bit error that satisfies is satisfied.

FIG. 87 is a flowchart of the embodiment having the ECC circuit. When a write operation is started and a program is started, data for one page (256 bytes) is written. Further, redundant data is written to a 64-bit redundant cell of the error correction circuit. Subsequently, the verify operation is started. If the verify operation is OK, the write operation is completed without any abnormality, and the write operation is completed. If the verification is NG, the counter is compared with a counter indicating the number of times of reprogramming, and if this is the third time or less, reprogramming is performed. Set number of reprogramming (3 in this case)
Times), verify read is performed. here,
As described above, the number of NG bits for one page is counted. Subsequently, a comparison is made as to whether the count result can be corrected with a predetermined number of redundant bits (in this case, 64 bits), and if this can be done, the writing is OK and the writing operation ends. If the number of NG bits is too large to save even the redundant bits, a write error occurs.

In this way, even if a write NG bit occurs, a write error does not occur within a range that can be remedied by ECC. Therefore, when the storage device is configured as described above, the number of write errors as seen from the outside is significantly reduced as compared with the conventional case. In particular, EEPRO with deterioration over time
At M, the effect is remarkable.

When an ECC circuit is added in the above configuration, a write error may not occur even though NG bits are present. However, NG bit is ECC
It is possible to know how close the ECC is to the rescue limit while judging whether it is within the rescue range.
For example, a warning may be issued when 80% of the ECC rescue limit becomes NG bits. In particular, in the case of an EEPROM that has deteriorated with time, it serves as a means for determining the life of the chip.

Further, as described in the embodiment shown in FIGS. 55 and 6, the verify operation can be performed collectively. Therefore, the writing time including the verification is not so long.

Although the embodiment in which the ECC is added has been described above, the embodiment may be constituted by one chip or a plurality of ECCs.
It may be configured as a storage system including an EPROM chip. The effect remains the same. Although the Hamming method is used as a method for generating a redundant code, the present invention is not limited to this, and various coding methods such as a Reed-Solomon coding method, an HV coding method, a fire coding method, and a cyclic coding method are used. Method may be used.

In the above, the description has been given of the method of performing the address control by the external input. Hereinafter, an example in which the address pin and the data input pin are used in common will be described.

FIG. 88 shows an example. Where AL
E, NWP, CE, NWE, and RE are external control signals. These signals are input from the corresponding input pins, respectively, and the operation mode of the chip is determined. Further, a signal indicating whether the chip is accessible or not is output from the control circuit to the outside via the Ready / Busy pin.
The external signal CLE determines the command input mode. The external control signal ALE determines an address input mode. The external control signal CE is a chip select signal. The external control signal NWE functions as a clock signal for taking in respective input data in the command input mode, the address input mode, and the data input. The external control signal RE is a clock signal that has an address increment and an output buffer enable function when reading a continuous address from the input address when reading data.

FIG. 88 is a timing chart showing the external control mode when writing is performed. Here, first,
In the command input mode, the serial data input command 8
0H is input. Thus, the chip enters the address input mode to input the program start address.
In the address input mode, a column address and a page address are fetched into an address buffer by a three-step clock of an external control signal NWE, and each internal address signal is determined to have a predetermined logic level corresponding to input address data. At this time, the Ready / Busy output terminal is configured to hold the Ready signal. When the address input operation is completed, the signal SDIC changes from “L” to “H” level. Therefore, the common bus lines IOi / IOiB
Then, the write data and its inverted data are transferred from the I / O input terminal. Next, while the external control signal NWE is at the "L" level, the column decoder output signal CSLn corresponding to the input column address is at the "H" level.
Level. In this way, data is transferred into the data register.

As a result, the contents of the data registers from address 0 to address N-1 are data "1" at the time of initialization. Data registers from address N to address N + j are input from the I / O input / output terminal.
Data is latched.

After the data input mode, when the auto program command 10H is input in the command input mode, the chip writes to the memory cells.

Thereafter, the operation described above (program →
Verify → Reprogram) is performed automatically.

During the write operation, a Busy signal is output from the Ready / Busy output terminal. It is set so that a READY signal is automatically output after a predetermined writing time has elapsed. The detection of whether the write mode has been completed normally is performed by inputting a 70H flag read command in the command input mode, and verifying the result (signal PE).
OK) can be read out from the I / O input / output terminal.

FIG. 89 shows an input waveform of an external control signal and data input timing when writing is performed in the semiconductor memory without using an autocommand.
In the command input mode, the serial data input command 8
0H is input. As a result, the chip enters the address input mode to input the program start address. In the address input mode, the column data output signal corresponding to the column address, which is input while the external control signal WE is at the "L" level, is at the "H" level, as in the above-described read mode. As a result, the latch contents of the data register are written to the write data latch on the common bus line. In this way, the write data is sequentially latched. When the latch is completed, the program command “40H” is input, and the mode shifts to the program mode.

Next, when a verify command is input,
The word line corresponding to the internal address signal in the address buffer circuit corresponding to the row address is selected. Further, after a predetermined delay time, one page of memory cell data in which the control gate is connected to the selected word line is read out via the bit line and latched in the data register. Next, the content PE of this data register is
“H” → “L” → “H” is changed, the column address is incremented, and data is sequentially called out of the chip. The read data is compared with the external storage write data by the chip. This makes it possible to determine at what address and how many bits have an error.

FIG. 90 shows input waveforms of external control signals and data input timings when the write and verify operations are performed. First, in the command input mode, a serial data input command 80H is input. This allows
The chip enters an address input mode to input a program start address. In the address input mode, the column address and the page address are changed by the three-step clock of the external control signal WE, as in the above-described read mode.
Each address buffer circuit takes in the data and sets each internal address signal to a predetermined logic level corresponding to the input address data. Thereafter, the column data output data corresponding to the column address, which is input while the external control signal WE is at the “L” level, is at the “H” level. As a result, the contents of the latch of the data register are written to the write data on the common bus line. In this way, the write data is sequentially latched. When this latch is completed, a program command “40H” is input,
Move to program mode. At the time of this data writing, writing is performed until the next verify read command is input.

Next, when a verify command (batch verification) is input, batch verification is performed as described above. Next, in this state, as described above, R
E is changed from “H” → “L” → “H”, the column address is incremented, and data is sequentially read out of the chip.

In this manner, "0" data is output from a bit that has been written NG, and "1" data is output from a bit that has been written OK. For this reason, the number of defective bits can be determined, although it is pseudo. Figure 91
Is another example of the system shown in FIG. here,
After inputting the verify read command, move RE,
The example has been described in which the flag read command “70H” is input without incrementing the column address, and whether or not the program is OK is output. Even if the system is configured in this way, the judgment of Fail / Pass is possible.

As is well known, data is written into a NOR type memory cell by injecting hot electrons into a floating gate. Therefore, when writing,
A write current of about 1 to 2 mA is consumed per one memory cell. Therefore, although it is possible in NAND E ² type, can not be performed is the page write such 256 bytes in NOR type. However, the NOR type is used because it has advantages such as a high read speed.

[0235] NOR type, thus E ^2, it is possible to rewrite the data on the on-board. First, an address is specified, write data is input, writing is performed on a memory cell, then data at the written address is read, data is compared, and it is determined whether or not writing has been performed.

When such an operation is performed on the board, the CPU generates signals necessary for data write and verify operations. Therefore, during this time, the CP
There is a problem that U is occupied.

Therefore, it is common to open the CPU by automating the write and verify operations inside the chip.

At this time, there is an example in which a circuit for latching write data, a circuit for latching read data, and a circuit for comparing the data are also provided (Japanese Patent Application No. 3-125).
399). In this example, there is a problem that the pattern area becomes relatively large and the chip size becomes large.

In the embodiment described below, a relatively small pattern area can be used not only for writing but also for erasing.

That is, the embodiments described so far are based on the NAN
Although a memory cell having a D structure is taken as an example, a batch verification method using a two-layer NOR type cell will be described below. That is, FIG.
1 shows an example of a memory cell (EEPROM) having a layer structure.

FIG. 92 is a plan view of the pattern, and FIG.
94 is a sectional view taken along the line BB ', and FIG. 94 is a sectional view taken along the line CC' in FIG. In these figures, reference numeral 211 denotes a floating gate (FG) made of first-layer polycrystalline silicon. 21
2 is a control gate (C
G). This control gate 212 is used as a word line of a memory cell.

Reference numeral 213 denotes a P-type substrate. 21
4 and 215 are N ⁺ layers formed on the substrate 214.
A source (S) and a drain (D) composed of a type diffusion layer. 216 is a contact hole. 217 is connected to the drain 21 through the contact hole 217.
6 is an aluminum layer (bit line BL) connected to the aluminum layer 6. Reference numeral 218 denotes a gate insulating film for the floating gate transistor, and has a thickness of 100 Å. Reference numeral 219 denotes an insulating film provided between the floating gate 211 and the control gate 12, and is formed of, for example, a three-layer structure film of an O-N-O structure (Oxide-Nitride-Oxide) and has a thickness of It is about 200 angstroms in terms of an oxide film. 220 is a field insulating film, and 221 is an interlayer insulating film.

Next, the operation principle will be described. At the time of erasure,
An erase voltage of 12 V is applied to the source 214 and the drain 21
5 in a floating state, and the control gate 213
And Thereby, through the thin gate insulating film 18,
A high voltage is applied between the floating gate 211 and the source 214. As a result, electrons in the floating gate 211 are emitted to the source 214 by the Fowler-Nordheim tunnel effect, and erasing is performed.

At the time of writing, about 6 V is applied to the drain 215.
0V to the source 214 and 12V to the control gate 213
Are respectively applied. As a result, impact ionization occurs near the drain, electrons are injected into the floating gate 11, and writing is performed.

At the time of reading, 1 V is applied to the drain 215.
And 0 V to the source 214 and 5 V to the control gate 213. At this time, the floating gate 211 is turned off / on depending on whether there is an electron in the floating gate 211, and indicates data "0" or "1", respectively.

A semiconductor integrated circuit using such a memory cell, for example, a flash type EEPROM with a 4-bit configuration
M is configured as shown in FIG.

In FIG. 95, A _{0 to} A _i are row address input signals, which are amplified and shaped by the row address buffer circuit 1 and then input to the row decoder circuit 2. B _{i + 1 to} B _j are column address input signals, which are amplified and shaped by the column address buffer circuit 3 and then input to the column decoder circuit 4. The row decoder circuit 2 selects only one of the plurality of word lines WL. The column decoder circuit 4 selectively turns on one gate 6A in each column selection gate circuit 6, and selects one bit line BL for each I / O, that is, only four bit lines BL for convenience. As a result, four memory cells MC are selected from the memory cell array 5, one for each I / O. Information of each selected memory cell MC is detected and amplified by the sense amplifier circuit 7, respectively. The output of each sense amplifier circuit 7 is read out of the chip via each output buffer circuit 8. That is, four pieces of information are simultaneously output to the outside.

In FIG. 95, the memory cell array 5 includes four memory cell array units (MCAU) 5A. Each unit 5A has four word lines WL, four bit lines BL, 1
It has six memory cells MC and four reference memory cells RMC. 4 bit lines B
L, the gate 6 in the column selection gate circuit 6
A also has four. One of these gates 6A
One is turned on by the column decoder circuit 4. The reference memory cell RMC includes a reference bit line RBL having a reference gate RBT on the way.
Is connected to the sense amplifier circuit (SA) 7.

[0249] 4 for the EEPROM having such a configuration.
Writing of bit data is performed as follows. That is, four data are read from four input / output pads (not shown) for each I / O. The writing circuit 10 sets the potential of the bit line BL according to the read data. That is, the write circuit 10 supplies a high potential when the write data is “0” and a low potential when the write data is “1” to the bit line BL selected by the input address signal. At this time, a high potential is also output to the word line WL selected by the input address signal.

That is, when "0" data is written, the selected word line WL and the bit line BL to which data is to be written have a high potential. Thereby, the memory cell MC
Hot electrons generated near the drain D are injected into the floating gate FG of the memory cell MC. As a result, the threshold voltage of the memory cell MC is shifted in the positive direction, and “0” data is stored.

On the other hand, when writing "1" data, the bit line BL is set to a low potential. Thereby, the floating gate FG
No electrons are injected into the memory cell MC, and the threshold voltage of the memory cell MC does not shift. As a result, "1" data is stored.

On the other hand, when erasing data, the source of the memory cell is set to a high voltage. Thereby, the floating gate FG
Are injected by FN (Fowler-Nordheim) tunnel effect.

FIG. 96 specifically shows a part of FIG. 95. In these figures, the same reference numerals indicate the same circuits. FIG. 96 specifically shows the sense amplifier circuit (SA) 7 and the comparator circuit 9 in particular. Further, a circuit INCIR for inputting one signal to be compared to the comparator circuit 9 and a batch verify circuit VECIR for receiving an output of the comparator circuit 9 are shown.

As described above, MC is a memory cell composed of a floating gate type MOS transistor, RMC is a reference memory cell (dummy cell) composed of a floating gate type MOS transistor, BL is a bit line, RBL is a reference bit line, RBT is a dummy bit line selection transistor equivalent to one of the column selection gate transistors 6A. The transistor RBT is, V _CC potential is supplied to a gate, which is inserted into the reference bit line RBL. BAS is a bus line to which a plurality of column select gate transistors 6A, 6A,... Are connected in parallel, LD1 is a first load circuit (bias circuit) connected to the bus line BAS, and LD2 is a reference bit. This is a second load circuit (bias circuit) connected to the line RBL. The potential Vin of the bit line BL 'on the output side of the first load circuit LD1 and the potential (reference potential) Vref of the reference bit line RBL' on the output side of the second load circuit LD2 are determined by the data detection circuit 28 (for example, CMOS
Current mirror).

In the sense amplifier circuit (SA) 7, a P-channel transistor P4 for activation control is connected between the _Vcc power supply and the data detection circuit section. The gate of this transistor P4 has an inverted signal / CE
* 1 is given. When the transistor P4 is off, the data detection circuit unit 28 is in a non-operating state, and current consumption is reduced. Further, between the output terminal DSO of the data detection circuit unit 28 and the ground terminal, the inverted signal / CE is connected to the gate.
* 1 is connected to an N-channel transistor N7.

In sense amplifier circuit 7, reference potential Vref of reference bit line RBL generated based on the data of reference memory cell RMC and bit line BL generated based on the data read from the selected memory cell are set. Is compared with the potential Vin. Based on the comparison result, the storage data in the memory cell is detected,
Output to the output buffer circuit 8 via three inverters.

The output of the sense amplifier circuit 7 is also input to one input terminal of the comparator circuit 9. The signal (write data) applied to the I / O pad is applied to the other input terminal of the comparator circuit 9. In the comparator circuit 9, these two input signals are compared, and
The result (VR0) is added to the batch verify circuit VECIR. The batch verify circuit VECIR has the output V from the comparator circuit 9 for the other three bits.
R1, VR2, VR3 are also added. The batch verify circuit VECIR outputs these outputs VR0, VR1, VR
2 and VR3 allow the output from the output circuit Dout only when the writing is OK. In other cases, that is, when even one of the outputs VR0 to VR3 indicates a write NG, the output from the output circuit Dout is blocked.

FIGS. 97 and 98 show the output VR0 from the comparator circuit 9 at the time of program verify and at the time of erase verify, respectively. FIG. 97 (a)
Indicates the case of "1" write. Program OK
In this case, the sense amplifier output DS0 becomes “1”. As a result, the compare output VR0 also indicates "1", that is, the program OK. FIG. 97B shows the case of “0” write. In the case of “0” write NG, the sense amplifier output DS0 indicates “1”. Therefore, the output VR0 of the comparator circuit is "0", that is, indicates the program NG.
FIG. 97 (c) shows the case of "0" write. When “0” write is OK, the sense amplifier output DS0 is “0”
Is shown. Therefore, the output VR0 of the comparator circuit indicates "H", that is, the program OK. When all of the comparator circuit outputs VR0 to VR3 indicate "H (program OK)", the batch verify circuit output PV
FY indicates "H". As can be seen from FIG. 98, in the case of erase OK / NG, the sense amplifier output DS0 is “1”.
/ O ". In response, the comparator circuit output V
R0 indicates "1 / O". Comparator circuit output VR
When all of 0 to VR3 indicate erasure OK, the batch verification circuit output EVFY becomes "1". When at least one of the comparator circuit outputs VR0 to VR3 indicates the erase NG, the output EVFY becomes “0”.

Next, FIG. 99 shows still another embodiment. In this embodiment, a collective verify circuit is incorporated in the memory cell shown in FIG. 6 of Japanese Patent Application Laid-Open No. 3-250495. In FIG. 99, the same circuits as those in FIG. 96 are denoted by the same reference numerals.

Table 6 shows the voltages applied to the respective parts at the time of erasing, writing, and reading in the apparatus shown in FIG.

Table 6 I / O pad BSL BL WL Vss erase-0 V Flow 20 V 0 V ^{(Electron injection)} V 22 V 20 V 0 V Floating unselected cell − 22 V 0 V / 20 V 10 V Floating lead − 5 V 1 V 5 V 0 V The operations of the program verify and the erase verify in the device in FIG. 99 are the same as the operations in FIG. 90 described above, and thus the description will be omitted.

Next, an example of a storage system using a nonvolatile semiconductor memory device having the above-described batch verify function will be described.

Normally, storage systems are hierarchically structured in order to maximize the capacity at the minimum cost. A cache system as one of them utilizes the locality of memory access. A computer using a normal cache system includes a high-speed and small-capacity SRAM and a low-speed and large-capacity DRAM in addition to a CPU. In such a cache system, a part of a main memory constituted by a DRAM or the like having a long access time is used.
The SRAM is replaced with an SRAM having a short access time, thereby shortening the effective access time. That is, CPU
When data is accessed from the SRAM, if there is data in the SRAM (that is, when the cache hits), the data is read from the SRAM that can operate at high speed. Is read. If the cache capacity and the replacement method are appropriate, the hit rate exceeds 95%, and the average access is greatly accelerated.

In the above-mentioned NAND type EEPROM or the like, writing and erasing can be performed in page units (for example, 2K bits). The processing on a page basis makes writing and erasing extremely fast. However, in such an apparatus, since a random access is sacrificed, a cache memory including a RAM such as an SRAM or a DRAM is essential. NAND type EE
When the cache system is applied to a nonvolatile storage device such as a PROM, the number of times of writing is reduced, and as a result, the life of the chip is extended.

A description will be given of a first embodiment of the memory system using the nonvolatile semiconductor memory device. FIG. 100 shows the circuit configuration. This system has a ROM 121 and a control circuit 122. The ROM 121 has a batch verify function. The control circuit 122 controls writing to the ROM 121 and has at least an internal write data register. This write control circuit 122
Outputs page data to be written next in response to the batch verify signal output from the ROM 121. This control circuit may be configured by using a CPU, or may be configured by a plurality of chips including a gate array and an SRAM.

In the NAND type EEPROM as described above, the batch erase block usually covers several pages. Therefore, when a system such as a cache memory is configured, writing is performed for each batch erase block. For example, a NAND EE having the above-described 8 NAND type memory cells
In the PROM, one batch erase block is composed of 2K bits (1 page) × 8 = 16K bits (8 pages), and writing is performed in units of this block. Therefore, the writing operation always involves writing of eight pages.

In the circuit shown in FIG.
The write operation of the next page is performed using the batch verify signal VFY output by the. That is, after latching the data of the first page, writing and verifying are repeated inside the ROM. When writing of all data for one page is completed, a batch verify signal VFY for the first page is output. The control circuit 122 detects the batch verify signal VFY, and latches the data of the second page in the ROM 121. Then, 2 inside the ROM
The writing and verifying for the page are repeated, and when the writing of all data for one page is completed, a batch verify signal VFY for the second page is output. The third and subsequent pages are written in the same manner as described above.

For example, in the above-described NAND type EEPROM having 8 NAND type memory cells, in one write operation, the control circuit 122 transfers data for eight pages, and collectively performs the second and subsequent pages in the previous page. After detecting the verify signal, the page data is transferred.

As described above, according to the present embodiment, the transfer of the write page data from the control circuit 122 to the ROM 121 can be performed based on the batch verify signal. Conventionally, a comparison circuit and a large-capacity register for verify reading are provided outside, but this is not necessary in the present embodiment. Thereby, the configuration of the control circuit 122 becomes very simple.

The above embodiment shows a configuration in which the control circuit 122 has one ROM 121. On the other hand, a memory system having a plurality of ROMs that output the batch verify signal can be configured. FIG. 101 shows an example of this. This system has a batch verify function as described above. This system has ROM 101-
103, a RAM 104, and a control circuit 105. R
The OMs 101 to 103 output a collective verify signal when the writing is completed. The RAM 104 stores C (not shown)
Used as a cache memory for access from the PU. The control circuit 105 includes a RAM 104 and a ROM 1
Control of data transfer between 01 and 103 is performed. RAM
Data transfer between the ROM 104 and the ROMs 101 to 103 is performed via the data bus 106. ROM10
1 to 103 constitute a main memory, and have a much larger capacity than the RAM 104 used as a cache memory.
Although a general 4-way mapping method is desirable, various existing mapping modes such as direct mapping and full associative are possible. The block in the cache memory has the same capacity as the batch erase block.

Next, a case where the batch erase block is 16K and the mapping method is 4-way will be described. At this time, SRA
M is 64K bits and has four 16K blocks. These blocks temporarily hold the copy data of the batch erase block in the ROM. For example, R
It is assumed that access is being made to data in the second, third, fourth, and fifth batch erase blocks in the OM. At this time, copy data of these data is temporarily held in four blocks in the SRAM.

It is assumed that a CPU (not shown) performs a write and erase operation on, for example, a third batch erase block. In this case, the copy of the data is already S
Since there is (hit) in the RAM, data is exchanged only through a high-speed SRAM without directly accessing the ROM.

It is assumed that a CPU (not shown) reads data from, for example, a sixth batch erase block. In this case, the copy of the data of the block erase block is
Since it does not exist in the SRAM (mis-hits), RO
It is necessary to transfer the data read from M to the SRAM. However, prior to this, one of the blocks in the SRAM needs to be written back to the ROM. For example, 2
The data of the first batch erase block from SRAM to ROM
When writing back to the memory, all the data in the batch erase block in the ROM is erased, and subsequently, the block data in the SRAM is sequentially transferred and written. In this write-back operation, an erase verify signal can be used. This erase verify signal (indicating that the erase operation has been completed)
, The data of the first page is transferred from the SRAM. Subsequently, the transfer of the data of the second and subsequent pages can be performed by detecting the batch verify signal of the previous page as described above. In the above-described 8-NAND EEPROM, data transfer for 8 pages is necessary. Then, all data in the sixth batch erase block is
The data is copied to an empty block of the SRAM, and the data at the address is output to the CPU by the SRAM.

It is assumed that a CPU (not shown) writes data to, for example, the seventh batch erase block. In this case, the copy of the data of the block erase block is
It does not exist in the SRAM (miss hit). Therefore,
The above-described write-back operation and read operation need to be performed prior to the write operation to the SRAM. For example, the data of the third batch erase block is transferred from SRAM to ROM
When writing back to the memory, all the data in the batch erase block in the ROM is erased, and subsequently, the block data in the SRAM is sequentially transferred and written. In this write-back operation, an erase verify signal can be used. This erase verify signal (indicating that the erase operation has been completed)
, The data of the first page is transferred from the SRAM. Subsequently, the transfer of the data of the second and subsequent pages can be performed by detecting the batch verify signal of the previous page as described above. In the above-described 8-NAND EEPROM, data transfer for 8 pages is necessary. Then, all data in the seventh batch erase block is replaced with S
The data is copied to an empty block of the RAM, and data requested to be written by the CPU is written to a corresponding area in the SRAM.

As described above, a ROM that outputs a batch verify signal can easily constitute a cache system in combination with an SRAM or the like. This is because the collective verify signal is used for data write-back at the time of a mishit.

Next, a description will be given of a third embodiment of the memory system having the batch verify function. FIG. 102 shows an example of the circuit. That is, it has ROMs 111 and 112 having a batch verify function and a control circuit 113 which controls writing and has at least a write data register therein. The control circuit 113 may be configured by using a CPU, or may be configured by a plurality of chips including a gate array and an SRAM. Further, the ROM 111 and the ROM 112 may be mixedly mounted on one chip, or may be constituted by a plurality of chips.

The continuous page data is stored in the ROM 111 and R
It is stored alternately with the OM 112. For example, 1, 3, 5,
..., the (2N-1) th page is stored in the ROM 111 as
The fourth, sixth,..., (2N) th pages are stored in the ROM 112. As described above, the operation in the write mode includes the operation of transferring the page data to the write data latch inside the chip, and the subsequent write and verify operations. In this system, while writing data is being transferred to the ROM 111, writing and verification of the ROM 112 are performed. Further, when writing data over a plurality of pages, the ROM 111 and the ROM 11
2 and alternately perform data transfer.

In the circuit configuration shown in FIG. 101 as well, write data transfer is controlled using a batch verify signal output from the ROM. First, the data of the first page is R
The data is transferred to the OM 111, and then the write and verify operations are performed on the ROM 111. While the write and verify operations are being performed on the ROM 111, the control circuit 113 transfers the data of the second page to the ROM 112 and subsequently performs the write and verify operations. R
When the writing of the first page for the OM 111 is completed, a batch verify signal is output. In response, the control circuit 113 transfers the data of the third page to the ROM 111, and subsequently performs a write and verify operation. 4
The same applies to the page writing for the pages after the first page.

As described above, according to the third embodiment, the transfer of the write page data from the control circuit 113 to the ROMs 111 and 112 can be performed based on the batch verify signal. In the present embodiment, unlike the related art, there is no need to externally provide a comparison circuit or a large-capacity register for verify reading, and the configuration of the control circuit 112 is greatly simplified. Further, since the writing is performed alternately, the writing time becomes faster. However, the size of the batch erase block is doubled.

[0280]

According to the present invention, whether or not the writing and erasing of each of a plurality of memory cells are properly performed is quickly detected, and the writing and erasing of all the target memory cells are performed. It can be performed quickly, and even if writing and erasing are repeated, the threshold value of the memory cell can be prevented from excessively changing.

[Brief description of the drawings]

FIG. 1 is a NAND cell type EEPROM according to a first embodiment;
FIG. 2 is a block diagram illustrating a configuration of an OM.

FIG. 2 is a plan view and an equivalent circuit diagram showing a NAND cell configuration in the first embodiment.

FIG. 3 is a sectional view taken along line AA ′ and line BB ′ of FIG.

FIG. 4 is an equivalent circuit diagram of the memory cell array in the first embodiment.

FIG. 5 is a diagram illustrating a configuration of a bit line control circuit unit according to the first embodiment.

FIG. 6 is a diagram showing a connection relationship between a bit line control circuit unit and other circuits in the first embodiment.

FIG. 7 is a timing chart showing a data write / write check operation in the first embodiment.

FIG. 8 shows a NAND cell type EEPROM according to the second embodiment.
FIG. 2 is a block diagram illustrating a configuration of an OM.

FIG. 9 is a diagram illustrating a configuration of a bit line control circuit according to a second embodiment.

FIG. 10 is a diagram illustrating a configuration of a program end detection circuit according to a second embodiment.

FIG. 11 is a timing chart showing a write confirmation operation in the second embodiment.

FIG. 12 is a diagram showing another embodiment of a data latch unit and a program end detection circuit.

FIG. 13 is a diagram showing another embodiment of a data latch unit and a program end detection circuit.

FIG. 14 is a circuit diagram of an example of a NOR flash EEPROM.

FIG. 15 is a threshold distribution diagram.

FIG. 16 is a diagram showing another embodiment of the data latch unit and the program end detection circuit.

FIG. 17 is a diagram showing another embodiment of the data latch unit and the program end detection circuit.

FIG. 18 is a diagram showing an algorithm at the time of writing / writing confirmation in the third embodiment.

FIG. 19 is a diagram schematically showing a data latch / sense amplifier and a write end detection transistor.

FIG. 20 is a diagram showing a configuration of a writing end detection transistor and a nonvolatile memory for fuse of FIG. 19;

FIG. 21 is a diagram showing a configuration example different from the configuration in FIG. 20;

FIG. 22 is a diagram showing a program algorithm when the circuit in FIG. 19 is used.

FIG. 23 is a diagram showing a circuit configuration different from that of FIG. 19;

FIG. 24 is a diagram illustrating a configuration of a bit line control circuit according to a fourth embodiment.

FIG. 25 is a diagram showing another configuration example of the bit line control circuit in the third and fourth embodiments.

FIG. 26 is a diagram showing another configuration example of the bit line control circuit in the third and fourth embodiments.

FIG. 27 is a diagram showing another configuration example of the bit line control circuit in the third and fourth embodiments.

FIG. 28 is a diagram showing the timing of the operation of latching the same data in the data latch section of the bit line control circuit in the third embodiment.

FIG. 29 is a diagram showing an operation timing for collectively latching the same data in the data latch unit of the bit line control circuit according to the fourth embodiment.

FIG. 30 is a modification of the third embodiment, in which one CMOSF is used.
FIG. 9 is a diagram showing a circuit configuration in which F is shared by two adjacent bit lines.

FIG. 31 is a view showing another example of the configuration of FIG. 30;

FIG. 32 shows a NAND cell type EEP according to a fifth embodiment.
FIG. 2 is a diagram illustrating a configuration of a ROM.

FIG. 33 is a diagram showing a specific configuration of a memory cell array and peripheral circuits thereof.

FIG. 34 is a timing chart showing an operation at the time of writing in the fifth embodiment.

FIG. 35 is a timing chart showing a read operation in the fifth embodiment.

FIG. 36 is a diagram showing a specific configuration of a memory cell array and its peripheral circuits in a sixth embodiment.

FIG. 37 is a timing chart showing a write operation in the sixth embodiment.

FIG. 38 is a timing chart showing a read operation in the sixth embodiment.

FIG. 39 is a view showing a modification of the thirty-third embodiment.

FIG. 40 is a view showing a modification of the embodiment shown in FIG. 36;

FIG. 41 is a view showing a modification of the embodiment shown in FIG. 36;

FIG. 42 is a diagram schematically showing replacement of bit lines in the embodiment shown in FIG. 36;

FIG. 43 is a diagram schematically showing replacement of bit lines in the embodiment shown in FIG. 36;

FIG. 44 is a diagram showing an embodiment in which a data latch and sense amplifier is shared by four bit lines.

FIG. 45 is a diagram schematically showing replacement of bit lines in the embodiment in FIG. 44;

FIG. 46 is a diagram schematically showing replacement of bit lines in the embodiment in FIG. 44;

FIG. 47 is a view showing a modification of the embodiment shown in FIG. 39;

FIG. 48 is a view showing a modification of the embodiment shown in FIG. 40;

FIG. 49 is a view showing a modification of the embodiment shown in FIG. 41;

FIG. 50 is a block diagram showing a seventh embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 51 is a circuit diagram of a sense amplifier / launch circuit according to a seventh embodiment.

FIG. 52 is a flowchart for explaining an erasing operation in the seventh embodiment.

FIG. 53 is a block diagram showing an eighth embodiment of the present invention.

FIG. 54 is a circuit diagram of a sense amplifier / latch circuit according to an eighth embodiment.

FIG. 55 is a circuit diagram of a sense amplifier / latch circuit according to a ninth embodiment of the present invention.

FIG. 56 is a circuit diagram of a sense amplifier / latch circuit according to a tenth embodiment of the present invention.

FIG. 57 is an overall configuration diagram of an eleventh embodiment of the present invention.

FIG. 58 is a timing chart of FIG. 57.

59 is an explanatory diagram of a read margin in FIG. 57.

FIG. 60 is an erasing flowchart of FIG. 57;

FIG. 61 is an erase flowchart.

FIG. 62 is a detailed example of the output circuit in FIG. 57;

FIG. 63 is a partial view of a conventional memory.

FIG. 64 is a timing chart at the time of program verification.

FIG. 65 shows write data WD and verify data VD
FIG.

FIG. 66 is a diagram showing a potential level distribution after verification and a threshold value dependence of a bit line.

FIG. 67 is a timing chart of program verification.

FIG. 68 shows write data WD and verify data VD
FIG.

FIG. 69 is a view showing the distribution of the potential level after the verification and the dependence of the bit line on the threshold.

FIG. 70 illustrates another example of a rewrite transistor.

FIG. 71 is a general circuit diagram used to implement the present invention.

FIG. 72 is a general circuit diagram used to implement the present invention.

FIG. 73 is a general circuit diagram used to implement the present invention.

FIG. 74 is a general circuit diagram used to implement the present invention.

FIG. 75 is a general circuit diagram used to implement the present invention.

FIG. 76 is a general circuit diagram used to implement the present invention.

FIG. 77 is a general circuit diagram used to implement the present invention.

FIG. 78 is a chip circuit diagram and a threshold distribution diagram as an example.

FIG. 79 is another circuit diagram of a chip as an example.

FIG. 80 is a verify level setting circuit.

FIG. 81 is a detailed example of a Vwell circuit.

FIG. 82 is a modification of the eleventh embodiment (FIG. 55).

FIG. 83 is a chart for explaining the operation of FIG. 82;

FIG. 84 is a conceptual diagram of an auto program.

FIG. 85 is a flowchart of FIG. 84;

FIG. 86 is a timing chart of the verify operation after the program operation;

FIG. 87 is a flowchart of an embodiment having an ECC circuit.

FIG. 88 is a timing chart 1 of the external control mode.

FIG. 89 is a timing chart 2 of the external control mode.

FIG. 90 is a timing chart 3 of the external control mode.

FIG. 91 is a timing chart 4 of the external control mode.

FIG. 92 is a plane pattern diagram of the EEFROM.

93 is a sectional view taken along line BB of FIG. 92.

94 is a sectional view taken along line CC of FIG. 92.

FIG. 95 is a block diagram of a 4-bit flash EEPROM.

FIG. 96 is a partial detailed view of FIG. 95;

FIG. 97 is a timing chart at the time of program verification;

FIG. 98 is a timing chart at the time of erase verify;

FIG. 99 is a circuit diagram of still another embodiment.

FIG. 100 is a storage system as an embodiment.

FIG. 101 is a storage system as another embodiment.

FIG. 102 shows a storage system as still another embodiment.

   ────────────────────────────────────────────────── ─── Continuation of front page    (31) Priority claim number Japanese Patent Application No. 4-77946 (32) Priority date March 31, 1992 (1992.3.31) (33) Priority claim country Japan (JP) (31) Priority claim number Japanese Patent Application No. 4-105831 (32) Priority date March 31, 1992 (1992.3.31) (33) Priority claim country Japan (JP) (31) Priority claim number Japanese Patent Application No. 4-175693 (32) Priority date July 2, 1992 (7.27.2.1992) (33) Priority claim country Japan (JP) (72) Inventor Hideo Kato               580-1 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba Corporation Semiconductor System Technology Center               Inside (72) Inventor Hiroto Nakai               580-1 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba Corporation Semiconductor System Technology Center               Inside (72) Inventor Yoshiyuki Tanaka               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba R & D Center (72) Inventor Riichiro Shirada               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba R & D Center (72) Inventor Seiichi Aridome               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba R & D Center (72) Inventor Norio Ito               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba R & D Center (72) Inventor Yoshihisa Iwata               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba R & D Center (72) Inventor Hiroshi Nakamura               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba R & D Center (72) Inventor Hideko Ohira               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba R & D Center (72) Inventor Yutaka Okamoto               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba R & D Center (72) Inventor Masamichi Asano               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba R & D Center (72) Inventor Tokushige Yoshiyoshi               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba R & D Center                (56) References JP-A-4-141759 (JP, A)                 JP-A-4-324194 (JP, A)                 JP-A-3-286497 (JP, A)                 JP-A-63-48688 (JP, A)                 JP-A-2-62687 (JP, A)                 Showa 64-64 (JP, U)

Claims (1)

(57) [Claims] 1. A plurality of memory circuits, wherein each of the memory circuits has a plurality of memory cells, and latches a data group of one page including data of a predetermined number of bits,
A write operation for writing the latched data group to the memory cell is performed, and after the write operation, a verify operation is performed to determine whether or not the data of the data group has been properly written. In this verify operation, the data is properly written. A plurality of memory circuits configured to output a collective verify signal, a cache memory for storing a plurality of the data groups to be written to the memory circuit, and a plurality of the memory circuits A data transfer operation in which, when one of the memory circuits outputs the batch verify signal, receiving the batch verify signal, transfers the new data group for one page to another memory circuit and latches it. And a control circuit, wherein: a control circuit is provided before one of the plurality of memory circuits. A memory system, wherein the write operation and the verify operation in the memory circuit and the data transfer operation to another memory circuit are repeatedly performed in parallel with each other.