JP3362717B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern for evaluating alignment accuracy in a photolithography process for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Miniaturization and densification of semiconductor elements are still vigorously pursued, and at present, ultra-high-integration or ultra-high-speed semiconductors such as logic devices or memory devices, which are designed with a dimensional standard of 0.13 μm. The device is being developed and prototyped. With the high integration of such semiconductor devices, there has been a strong demand for further improvement in mask alignment accuracy in the photolithography process, which is essential for forming a semiconductor element structure.

Usually, in the manufacture of semiconductor devices, patterns formed of various materials such as a metal film, a semiconductor film, and an insulator film are sequentially laminated on a semiconductor substrate to form a semiconductor element having a fine structure. When laminating the pattern for the semiconductor element, it is required to form the next upper layer pattern in the photolithography step by aligning with the lower layer pattern formed in the previous step.

As described above, in the photolithography process, when performing the photolithography process of the upper layer, it is necessary to perform the mask pattern while superposing the mask pattern on the pattern of the lower layer according to a predetermined standard. The predetermined standard regarding the overlay accuracy of this pattern becomes stricter as the semiconductor device is miniaturized. Therefore, the technique for evaluating the overlay accuracy becomes important.

Further, as the semiconductor device becomes finer as described above, various types of exposure apparatuses are used in combination in pattern transfer in the photolithography process. For example, an i-line (exposure wavelength of 365 nm) stepper is used to transfer a relatively rough pattern, and an excimer stepper or an electron beam exposure device is used to transfer a fine pattern. Such a mix-and-match (M & M) exposure method has become an indispensable technique for further ultra-high integration of semiconductor devices.

At present, as a method for easily measuring the position error between two photolithography processes, a method of forming a rectangular pattern having a constant pitch slightly different for each process and reading the position error from the degree of pattern overlap is used. This rectangular pattern is generally called a pattern matching caliper or vernier. Also, in general,
Form a pair of marks on the lower and upper layers of the semiconductor chip,
A method of measuring the degree of superposition of these marks is used.

Hereinafter, a caliper for overlay measurement of a mask pattern and an underlying layer in a conventional photolithography process will be described with reference to FIGS. 7 and 8. Here, FIG. 7 is a plan view of the main scale caliper and the vernier caliper, and FIG. 8 is a cross-sectional view of the main scale caliper index and the vernier caliper index and a plan view thereof.

As shown in FIG. 7 (a), the distance X between the index side 101a of the main scale caliper index 101 and the index side 102a of the vernier caliper index 102, the index side 101b of the main scale caliper index 101 and the vernier caliper. The distance Y between the index 102 and the index side 102b is visually observed with an optical microscope. Here, this main scale caliper index 101 is one groove, that is, one as described above.
It is formed by one indicator opening.

As shown in FIG. 7 (b), the caliper index, ie, the first index 10 which constitutes the above-mentioned main scale caliper.
3, the second index 104, the third index 105, the fourth index 106 and the fifth index 107 are formed, and similarly, the first index 108 and the second index 10 which constitute a vernier caliper are formed.
9, a third index 110, a fourth index 111 and a fifth index 112 are formed.

Here, it is assumed that the main scale calipers indices are arranged at a pitch p and the sub-scale calipers indices are arranged at a pitch q. Then, for example, if q = p + 0.025 μm, in FIG. 7, the degree of overlap between the second index of the main measure and the vernier caliper is the best. In this case,
The amount of overlay misalignment is +0.025 μm. In this way, the amount of deviation can be determined visually with an optical microscope.

Normally, a MOS transistor is formed on the silicon substrate 113 through a predetermined process (not shown). Then, as shown in FIG. 8A, the first interlayer insulating film 114 is formed so as to cover the entire surface.

Next, first wiring layers 115, 115a, 115b having a predetermined pattern are formed on the first interlayer insulating film 114.
Etc. are formed by the photolithography technique and the dry etching technique. Then, the second interlayer insulating film 116 is formed on the entire surface.
Are deposited. In this way, the first wiring layers 115 and 1
The space pattern of 15a or the first wiring layers 115a and 15b serves as a concave main scale caliper index.

Next, a second wiring layer 117 is formed on the second interlayer insulating film 116. Then, for the next photolithography process, an antireflection film 118 is applied and formed on the entire surface as shown in FIG. 8B, and a photoresist film is further uniformly formed. Thereafter, reduction projection exposure and photoresist are performed. Of the resist pattern 119,
119a is formed. Thus, the vernier caliper index is usually composed of such a resist pattern.

The first wiring layers 115, 115a, 115b, which are convex patterns, may be used as they are as the main scale caliper index.

[0015]

However, in the case of the above-mentioned conventional technique, it becomes very difficult to evaluate the amount of deviation of the main-scale caliper index and the vernier-vernier caliper index by visual observation with an optical microscope. This will be described with reference to FIGS. 8B and 8C.

With the miniaturization of semiconductor devices, the exposure wavelength in the photolithography process becomes shorter. When the exposure wavelength is shortened, the amount of reflection from the base increases, which is a great obstacle to the formation of fine patterns. Therefore, when forming a resist pattern that serves as a vernier caliper index, an antireflection film 118, which is an organic coating film, is previously formed on the surface of the second wiring layer 117, as shown in FIG. 8B. . Then, pattern transfer is performed by exposure and development to form resist patterns 119 and 119a that serve as the above-mentioned vernier caliper index.

Here, when the main-scale caliper index and the sub-scale caliper index are visually inspected with an optical microscope in order to evaluate the above-mentioned overlay accuracy, as shown in FIG. 8C, the main-scale caliper index 120, 120a is obtained. Many interference fringes 121 are formed around the. For this purpose, the main scale calipers indicator 120, 120a
It becomes very difficult to read the vernier calipers indexes 122 and 122a by superimposing them with an optical microscope. Such a decrease in overlay reading accuracy is becoming more and more prominent with the miniaturization of semiconductor devices.

The organic coating film used as the antireflection film 118 has a high ability to absorb exposure light in the photolithography process. However, it is highly transparent to visible light under an optical microscope. Therefore, the interference fringes 121 as described above are generated. This is a phenomenon that cannot be avoided if the exposure wavelength becomes shorter with the miniaturization of semiconductor devices.

An object of the present invention is to improve the overlay accuracy of a lower layer pattern and an upper layer pattern during a photolithography process in a manufacturing process for manufacturing a semiconductor device.

[0020]

To this end, the semiconductor device of the present invention has a first mark and a second mark for measuring the amount of superposition of the lower layer pattern and the upper layer pattern of the semiconductor device.
Has a mark of the lower layer and the upper layer of a predetermined area on the semiconductor chip, respectively, the first mark is formed in a convex pattern surrounded by fine space, the second mark is a resist pattern The top of the first mark is
It is formed through an anti-reflection film, and the fine space has the
An antireflection film is filled and the surface is flattened .

Here, the first mark is formed by covering a pattern of a conductive film with an insulating film. Alternatively, the conductive film pattern is formed by covering the insulating film and another conductive film in this order.

Alternatively, the insulating film pattern is formed by coating a conductive film. Alternatively, the insulating film pattern is formed by covering the conductive film and another insulating film in this order.

The first mark is an index of the main caliper of the caliper formed on the semiconductor chip, and the second mark is an index of the vernier caliper. Alternatively, the first mark is an outer box mark for automatic overlay measurement formed on a semiconductor chip, and the second mark is an inner box mark for automatic overlay measurement. Here, the outer box mark is
It is composed of an insulating film partitioned by slit-shaped grooves.

A method of manufacturing a semiconductor device according to the present invention comprises a step of arranging a plurality of convex insulating film patterns on a semiconductor substrate at regular intervals, and an entire surface so as not to fill a space between the plurality of insulating film patterns. Depositing a conductive film to form a fine space between adjacent insulating film patterns, forming an antireflection film on the entire surface so as to fill the fine pattern, and flattening the surface of the antireflection film; Prevention
Forming a resist pattern on the insulating film pattern via a stop film .

In the method of manufacturing a semiconductor device of the present invention, a step of arranging a plurality of convex conductive film patterns on a semiconductor substrate at regular intervals and a space between the conductive film patterns are not filled. Depositing an insulating film on the entire surface to form a fine space between adjacent conductive film patterns, and forming an antireflection film on the entire surface so as to fill the fine pattern and flattening the antireflection film surface, The above
Forming a resist pattern on the conductive film pattern via an antireflection film .

The method of manufacturing a semiconductor device according to the present invention is
A step of partitioning the insulating film to form a slit-like grooves in a predetermined region of the insulating film formed on a semiconductor substrate, wherein forming the anti-reflection film on the entire surface so as to fill the groove the antireflective film
A step of flattening the surface, and
And a step of forming a resist pattern on the partitioned insulating film . Here, the antireflection film is formed of an organic material by coating.

In the present invention, a fine space is formed between the main calipers calipers or around the outer box mark, and this fine space is completely filled with the antireflection film. Then, at the time of superposition reading with the optical microscope, the interference fringes of the antireflection film as described in the conventional technique are not seen at all. For this reason, overlay reading by an optical microscope becomes very easy, and the reading accuracy is greatly improved.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view and a plan view of a caliper for pattern matching according to an example of a first embodiment of the present invention. In the first embodiment, the surface portion of the main scale caliper index is formed of a conductive film.

As shown in FIG. 1A, a first interlayer insulating film is formed on a silicon substrate 1 by depositing a silicon oxide film by a chemical vapor deposition (CVD) method and planarizing by a chemical mechanical polishing (CMP) method. The film 2 is formed.

Then, the first wiring layers 3, 3a, 3b, which have a predetermined pattern of aluminum alloy, are formed on the first interlayer insulating film 2.
3c and 3d are formed. Here, the film thickness of these first wiring layers is about 500 nm, and the space width between adjacent first wiring layers is about 1 μm.

Next, a film thickness of 200 nm is formed by the plasma CVD method.
About a certain amount of silicon oxide film is uniformly deposited. Further, the second wiring layer 5 is formed on the second interlayer insulating film 4. Here, the film thickness of the second wiring layer 5 is 250 nm. In this way, the fine space 6 is provided between the adjacent first wiring layers. Here, the width of the fine space 6 is 100 nm to
Controlled to 200 nm. Then, the first wiring layers 3 and 3
The a, 3b, 3c and 3d and the upper second wiring layer 5 serve as a convex main caliper index.

Next, as shown in FIG. 1B, an antireflection film 7 is applied on the entire surface. Here, the film thickness of the antireflection film 7 is 100 nm to 200 nm. In this way, the fine space 6 is completely filled with the antireflection film 7, and the surface thereof is completely flattened.

Then, for the next photolithography process, a photoresist film is uniformly formed, and then reduction projection exposure and development of the photoresist are performed to form resist patterns 8 and 8a. In this way, the vernier caliper index is formed.

In the present invention, fine spaces 6 are formed between the main scale calipers and the fine spaces 6 are completely filled with the antireflection film 7. Then, as shown in FIG. 1C, the contours of the index sides of the vernier caliper index 9, 9a composed of the patterned photoresist and antireflection film become clear. In this way, the main scale caliper index 9,
The superposition reading of 9a and the vernier caliper index 10, 10a by the optical microscope becomes very easy. Such an improvement in overlay reading accuracy is not impaired by the miniaturization of semiconductor devices.

Next, another example of the first embodiment of the present invention will be described with reference to FIG. FIG. 2 is a sectional view of the caliper for pattern matching according to the present invention. Here, FIG.
The same parts as those are indicated by the same reference numerals.

As shown in FIG. 2, the first interlayer insulating film 2 is formed on the silicon substrate 1. Then, the second interlayer insulating film is formed on the first interlayer insulating film 2, and the insulating film patterns 4a and 4b are formed by the photolithography technique and the dry etching technique in the through hole forming step. Here, the film thickness of the insulating film patterns 4a and 4b is about 500 nm, and the space width between the adjacent insulating film patterns 4a and 4b is about 1.2 μm.

Next, the second wiring layer 5 is formed so as to cover the insulating film patterns 4a and 4b. Where the second
The film thickness of the wiring layer 5 is 500 nm. In this way
A fine space 6 is provided between the adjacent first wiring layers.
Here, the width of the fine space 6 is controlled to about 200 nm. Then, the insulating film patterns 4a and 4b and the second upper layer
The wiring layer 5 serves as a convex main measure caliper index.

Next, the antireflection film 7 is applied to the entire surface in the same manner as in FIG. 1, all the fine spaces 6 are filled with the antireflection film 7, and the surface is completely flattened. Then, resist patterns 8 and 8a are formed. In this way
A vernier caliper index is formed. The effect in this case is shown in FIG.
It is the same as that explained in.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a sectional view of a caliper for pattern matching according to an example of the second embodiment of the present invention. Here, the same components as those in the first embodiment are designated by the same reference numerals. The second embodiment is a case where a surface portion serving as a main scale caliper index is formed of an insulating film.

As shown in FIG. 3, a field oxide film 11 is formed on the silicon substrate 1. Then, the insulating film patterns 4a and 4b are formed on the field oxide film 11. Here, the film thickness of the insulating film patterns 4a and 4b is 500.
The width of the space between the insulating film patterns 4a and 4b is about 1 μm.

Next, the wiring layer 12 having a film thickness of 150 nm is formed on the entire surface.
Is formed and the interlayer insulating film 1 is formed so as to cover the wiring layer 12.
3 are deposited. Here, the film thickness of the interlayer insulating film 13 is 30.
It is 0 nm. In this way, the pattern width is 100n
The fine pattern 6 of m is formed. Here, the insulating film patterns 4a and 4b, the wiring layer 12, and the interlayer insulating film 13 serve as a main scale caliper index. By doing so, the reading accuracy of pattern superposition by the optical microscope is significantly improved.

Then, the antireflection film 7 is applied to the entire surface in the same manner as in FIG. 1, all the fine spaces 6 are filled with the antireflection film 7, and the surface thereof is completely flattened. Then, the resist patterns 8 and 8a are formed, and the vernier caliper index is formed.

Next, another example of the second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a sectional view of the caliper for pattern matching according to the present invention. Here, FIG.
The same parts as those are indicated by the same reference numerals.

As shown in FIG. 4, the first interlayer insulating film 2 is formed on the silicon substrate 1. Then, the first wiring layers 3 and 3a are formed on the first interlayer insulating film 2. here,
The film thickness of the first wiring layers 3 and 3a is about 500 nm, and the space width between the adjacent first wiring layers 3 and 3a is 1 μm.

Next, a second interlayer insulating film 4 is formed so as to cover the first wiring layers 3 and 3a. Here, the film thickness of the second interlayer insulating film 4 is 400 nm. In this way, the first wiring layers 3 and 3a and the second interlayer insulating film 4 serve as a convex main-scale caliper index. Here, the fine space 6 having a space width of 200 nm is provided between the adjacent main-scale calipers indexes.

Thereafter, the antireflection film 7 is applied to the entire surface in the same manner as in FIG. 1, all the fine spaces 6 are filled with the antireflection film, and the surface thereof is completely flattened. Then, the resist patterns 8 and 8a are formed, and the vernier caliper index is formed.

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a plan view and a cross-sectional view of an automatic overlay measurement mark formed on the surface of a semiconductor chip like the above-mentioned caliper. This automatic overlay measurement mark is formed in a shape larger than the size of the caliper.
Here, FIG. 5A is a plan view thereof, and FIG. 5B is a cross-sectional view taken along line AB of FIG. 5A. Note that FIG.
The same parts as those are indicated by the same reference numerals.

As shown in FIGS. 5A and 5B, an interlayer insulating film 13 is formed on the silicon substrate 1. Here, the film thickness of the interlayer insulating film 13 is about 800 nm. Then, the fine space 6 is provided by the slit-shaped groove that divides a predetermined region of the interlayer insulating film 13, and the outer box mark 14 is formed. The width of the fine space 6 is about 200 nm. Then, the antireflection film 7 is applied to the entire surface, the fine spaces 6 are all filled with the antireflection film 7, and the surface thereof is completely flattened. Then, a photoresist pattern is formed and the inner box mark 15 is formed.

Laser light is scanned from above the outer box mark and the inner box mark thus formed,
The positional relationship between these box marks can be accurately measured. This laser light scanning is done automatically,
The automatic overlay measurement between the pattern formed on the upper layer and the pattern on the lower layer is performed at high speed. Here, the wavelength of the laser light is visible light.

Next, another example of the third embodiment of the present invention will be described with reference to FIG. FIG. 6 is a plan view of the automatic overlay measurement mark according to the present invention. In this case, the difference from FIG. 5 is that fine spaces are divided and formed.

That is, as shown in FIG. 6, a slit-shaped fine space 6a is formed in the interlayer insulating film. Outer box mark 1 on the interlayer insulation film in these fine spaces
4a is formed. After that, the inner box mark 15 is formed in the same manner as described with reference to FIG. Also in this case, FIG.
The same effect as described above is produced.

In the above embodiments, calipers and box marks have been described. The present invention is not limited to this. Note that other wafer alignment marks and the like can be similarly applied.

[0053]

As described above, in the semiconductor device of the present invention, the first mark and the second mark for measuring the amount of superposition of the lower layer pattern and the upper layer pattern of the semiconductor device are semiconductors, respectively. The first mark is formed in a predetermined region on the lower layer and the upper layer on the chip, the first mark is formed in a convex pattern surrounded by a fine space, and the second mark is a resist pattern, which is reflected on the upper part of the first mark. Through the prevention film
The antireflection film is formed in the fine space.
It is filled and its surface is flattened .

The method of manufacturing a semiconductor device of the present invention is
A plurality of convex patterns are arranged on a semiconductor substrate with a certain material at regular intervals, another material film is deposited on the entire surface so as not to fill the space between the plural patterns, and the adjacent convex patterns are formed. Form a fine space between them.
Then, an antireflection film is formed on the entire surface so as to fill this fine pattern to form a resist pattern.

The method of manufacturing a semiconductor device according to the present invention is
A slit-shaped groove is formed in a predetermined region of the insulating film formed on the semiconductor substrate to partition the insulating film, and an antireflection film is formed on the entire surface so as to fill the groove to form a resist pattern. The antireflection film is made of an organic material and formed by coating.

By doing so, superposition reading by the optical microscope becomes very easy in the photolithography process. Then, such overlay reading accuracy is significantly improved.

Further, the positional relationship between the box marks can be precisely measured by the automatic scanning of the laser beam, and the automatic overlay measurement between the pattern formed on the upper layer and the pattern on the lower layer can be performed with high accuracy. You will be able to speed up.

Further, according to the present invention, it becomes easy to manufacture a semiconductor device which is miniaturized, highly integrated, speeded up, and highly functionalized, and the manufacturing yield thereof is increased.

[Brief description of drawings]

1A and 1B are a cross-sectional view and a plan view of a caliper for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a caliper for explaining another example of the above embodiment.

FIG. 3 is a layout diagram of calipers for explaining the second embodiment of the present invention.

FIG. 4 is a cross-sectional view of a caliper for explaining another example of the above embodiment.

FIG. 5 is a plan view and a sectional view of a box mark for explaining a third embodiment of the present invention.

FIG. 6 is a plan view of a box mark for explaining another example of the above embodiment.

FIG. 7 is a plan view of a caliper for explaining a conventional technique.

FIG. 8 is a cross-sectional view and a plan view of a caliper according to a conventional technique.

[Explanation of symbols]

1,113 Silicon substrate 2,114 First interlayer insulating film 3, 3a, 3b, 3c, 3d, 115, 115a, 11
5b First wiring layer 4,116 Second interlayer insulating film 4a, 4b Insulating film pattern 5,117 Second wiring layer 6,6a Fine space 7,118 Antireflection film 8,8a, 119,119a Resist pattern 9,9a, 101, 120, 120a Main scale caliper index 10, 10a, 102, 122, 122a Vernier caliper index 11 Field oxide film 12 Wiring layer 13 Interlayer insulating film 14 Outer box mark 15 Inner box mark 101a, 101b, 102a, 102b Index side 103, 108 first index 104, 109 second index 105, 110 third index 106, 111 fourth index 107, 112 fifth index 121 interference fringes

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/027 G03F 9/00

Claims (12)

(57) [Claims] 1. A first mark and a second mark for measuring an overlapping amount of a lower layer pattern and an upper layer pattern of a semiconductor device are provided in predetermined regions of the lower layer and the upper layer on a semiconductor chip, respectively. The first mark is formed in a convex pattern surrounded by a fine space, and the second mark is a resist pattern and is formed on the upper part of the first mark.
It is formed through an anti-reflection film, and it does not
A semiconductor device characterized by being filled with an antireflection film and having its surface planarized . 2. The semiconductor device according to claim 1, wherein the first mark is formed by coating a pattern of a conductive film with an insulating film. 3. The semiconductor device according to claim 1, wherein the first mark is formed by covering a pattern of a conductive film with an insulating film and another conductive film in this order. 4. The semiconductor device according to claim 1, wherein the first mark is formed by covering a pattern of an insulating film with a conductive film. 5. The semiconductor device according to claim 1, wherein the first mark is formed by covering a pattern of an insulating film with a conductive film and another insulating film in this order. 6. The vernier caliper index of a caliper formed on a semiconductor chip, wherein the first mark is
6. The semiconductor device according to claim 1, wherein the mark is a vernier caliper index. 7. The first mark is an outer box mark for automatic overlay measurement formed on a semiconductor chip, and the second mark is an inner box mark for automatic overlay measurement. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 8. The semiconductor device according to claim 7, wherein the outer box mark is composed of an insulating film partitioned by a slit-shaped groove. 9. A step of arranging a plurality of convex insulating film patterns on a semiconductor substrate at regular intervals, and a conductive film is deposited on the entire surface so as not to fill a space between the plurality of insulating film patterns. A step of forming a fine space between the film patterns, and an antireflection film is formed on the entire surface so as to fill the fine pattern, and the surface of the antireflection film is flattened.
And the insulating film pattern through the antireflection film.
And a step of forming a resist pattern thereon. 10. A process of arranging a plurality of convex conductive film patterns on a semiconductor substrate at regular intervals, and an insulating film is deposited on the entire surface so as not to fill a space between the plurality of conductive film patterns, and adjacent conductive films are formed. Forming a fine space between the film patterns, and forming an antireflection film on the entire surface so as to fill the fine patterns, and flattening the surface of the antireflection film
And the conductive film pattern through the antireflection film.
Forming a resist pattern on the semiconductor device. 11. A process for the slit-like groove formed in a predetermined region of the insulating film formed on a semiconductor substrate for partitioning the insulating film, is formed on the entire surface antireflection film so as to fill the groove the The step of flattening the surface of the antireflection film,
And a step of forming a resist pattern on the partitioned insulating film via a stop film . 12. The method according to claim 9, wherein the antireflection film is made of an organic material and formed by coating.
Alternatively, the method of manufacturing a semiconductor device according to claim 11.