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JP3349058B2 - 複数のｉｃチップを備えた半導体装置の構造 - Google Patents

複数のｉｃチップを備えた半導体装置の構造

Info

Publication number
JP3349058B2
JP3349058B2 JP06854097A JP6854097A JP3349058B2 JP 3349058 B2 JP3349058 B2 JP 3349058B2 JP 06854097 A JP06854097 A JP 06854097A JP 6854097 A JP6854097 A JP 6854097A JP 3349058 B2 JP3349058 B2 JP 3349058B2
Authority
JP
Japan
Prior art keywords
chip
bumps
chips
another
connection electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP06854097A
Other languages
English (en)
Other versions
JPH10270637A (ja
Inventor
忠洋 森藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP06854097A priority Critical patent/JP3349058B2/ja
Priority to US09/045,135 priority patent/US6175157B1/en
Publication of JPH10270637A publication Critical patent/JPH10270637A/ja
Application granted granted Critical
Publication of JP3349058B2 publication Critical patent/JP3349058B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、一つのＩＣチップ
の上面に、別のＩＣチップを積み重ねて接続することに
よって、集積度を高めるようにした半導体装置に関する
ものである。
【０００２】
【従来の技術】最近、ＩＣチップを使用した半導体装置
における集積度を高めるために、一つのＩＣチップの上
面に、別のＩＣチップを積み重ね、この別のＩＣチップ
を前記一つのＩＣチップに対して、当該別のＩＣチップ
の周囲に沿って適宜ピッチの間隔で設けた複数個のバン
プにて電気的に接続することが提案されている。
【０００３】
【発明が解決しようとする課題】しかし、一つの上面に
積み重ねた別のＩＣチップを、その周囲に沿って設けた
複数個のバンプにて、前記一つのＩＣチップに対して電
気的に接続するように構成した場合、前記別のＩＣチッ
プのうち前記各バンプより内側の中心部分には、前記一
つのＩＣチップとの間に隙間ができ、換言すると、前記
別のＩＣチップと、その周囲に設けた各バンプにて一つ
のＩＣチップに対して支持されていることにより、この
別のＩＣチップは、当該別のＩＣチップのうち前記各バ
ンプより内側の中心部分に一つのＩＣチップに向かう方
向の外力を受けたときにおいて、前記中心部分が一つの
ＩＣチップに接近するように湾曲変形し易く形態になっ
ており、また、前記一つのＩＣチップも、当該一つのＩ
Ｃチップのうち前記各バンプより内側の中心部分に別の
ＩＣチップに向かう方向の外力を受けたときにおいて、
前記中心部分が別のＩＣチップに接近するように湾曲変
形し易い形態になっているから、前記別のＩＣチップ又
は一つのＩＣチップに割れが発生するばかりか、これら
両ＩＣチップのうち互いに対向する面に形成されている
各種の回路素子にダメージを及ぼすことが多発すると言
う問題があり、特に、これらの問題は、前記一つのＩＣ
チップの上面に積み重ね接続する別のＩＣチップにおけ
る大型化に比例して増大するのであった。
【０００４】本発明は、この問題を解消できるようにし
た半導体装置の構造を提供することを技術的課題とする
ものである。
【０００５】
【課題を解決するための手段】この技術的課題を達成す
るため本発明に係る半導体装置は、「一つのＩＣチップ
の上面に別のＩＣチップを積み重ね、これら両チップに
は、前記別のＩＣチップの周囲に沿うように適宜間隔で
バンプを設け、前記別のＩＣチップを、前記一つのＩＣ
チップに対して、その間に介挿した導電粒子入り接着フ
ィルムにて、前記各バンプが当該接着フィルムを圧縮変
形するように接着して成り、前記一つのＩＣチップが前
記別のＩＣチップに相対する面のうち前記各バンプより
内側の中心部分に、少なくとも一つ以上の捨てバンプを
設け、前記別のＩＣチップが前記一つのＩＣチップに相
対する面のうち前記各バンプより内側の中心部分にも、
少なくとも一つ以上の捨てバンプを設ける。」と言う構
成にした。
【０００６】
【発明の作用・効果】このように構成することにより、
両ＩＣチップが、当該両ＩＣチップのうち各バンプより
内側の中心部分に外力を受けて、前記各中心部分が互い
に接近するように湾曲変形しても、この湾曲変形を、前
記各中心部分に少なくとも一つ以上設けた捨てバンプと
接着フィルムとにて小さい値にとどめることができる
か、前記の湾曲変形を皆無にすることができるのであ
る。
【０００７】従って、本発明によると、一つのＩＣチッ
プの上面に、接着フィルムを介して別のＩＣチップを積
み重ねて、両ＩＣチップにおけるバンプの相互間を、接
着フィルム内の導電粒子を介して電気的に接続する場合
において、両ＩＣチップを大きくしても、これら両ＩＣ
チップに及ぶ外力のために、両ＩＣチップが割れるこ
と、及び、両ＩＣチップにおける回路素子にダメージを
及ぼすことを確実に低減できる効果を有する。
【０００８】特に、「請求項２」に記載したように、前
記捨てバンプを、電気接続用バンプに構成することによ
り、両ＩＣチップの相互間を電気的に接続するバンプの
一部を利用して両ＩＣチップの湾曲変形を小さく又は皆
無にできるから、バンプの数を多くすることを回避でき
る利点がある。
【０００９】
【発明の実施の形態】以下、本発明の実施の形態を、図
１〜図６の図面について説明する。この図において、符
号１は、平面において略矩形に形成したチップマウント
部１ａと、このチップマウント部１ａにおける四つの各
辺から外向きに延びる複数本のリード端子１ｂとを備え
た金属板製のリードフレームを示す。
【００１０】符号２は、前記リードフレーム１における
チップマウント１ａの上面にダイボンディングされる一
つのＩＣチップを示し、この一つのＩＣチップ２は、平
面視において矩形状に形成され、その上面には、中心部
分に図示しない能動素子又は受動素子等のような回路素
子の多数個が形成されていると共に、外側の部分に、外
部への接続用電極パッド１ａの複数個が周囲に沿って適
宜間隔で形成され、この外部への接続用電極パッド１ａ
の内側に、複数個の接続用電極パッド１ｂが周囲に沿っ
て適宜間隔で形成されている。
【００１１】また、符号４は、前記一つのＩＣチップ２
の上面に積み重ねられる別のＩＣチップを示し、この別
のＩＣチップ４は、前記一つのＩＣチップ２よりも小さ
い寸法の矩形状に形成され、その下面には、中心部分に
図示しない能動素子又は受動素子等のような回路素子の
多数個が形成されていると共に、外側の部分に、接続用
電極パッド４ａの複数個が、当該別のＩＣチップ４にお
ける周囲に沿って適宜間隔で形成され、この各接続用電
極パッド４ａの各々には、一つのＩＣチップ２に向かっ
て突出するバンプ４ｂが設けられ、更に、前記別のＩＣ
チップ４の下面のうちその周囲における前記各接続用電
極パッド４ａよりも内側の中心部分には、少なくとも一
つ以上（本実施形態では四個）の捨てバンプ３が、前記
一つのＩＣチップ２に向かって突出するように設けられ
ている。
【００１２】更にまた、符号５は、前記一つのＩＣチッ
プ２における上面と、前記別のＩＣチップ４の下面との
間に介挿した接着フィルムを示し、この両接着フィルム
５には、導電粒子が混入されている。そして、前記一つ
のＩＣチップ２を、前記リードフレーム１におけるチッ
プマウント部１ａの上面に、図３に示すように、一つの
ＩＣチップ２をダイボンディングしたのち、この一つの
ＩＣチップ２の上面に対して、別のＩＣチップ４を、そ
の間に接着フィルム５を挟んで押圧する。
【００１３】この押圧により、前記接着フィルム５は、
両ＩＣチップ２，４に対して接着するから、この接着フ
ィルム５を介して両ＩＣチップ２，４を互いに接着でき
るのであり、これと同時に、この接着フィルム５のうち
別のＩＣチップ４における各接続用電極パッド４ａに設
けたバンプ４ｂに該当する部分が、このバンプ４ｂに
て、図４及び図５に示すように、部分的に強く圧縮変形
されることになり、この強く圧縮変形される部分では、
これに混入した導電粒子が互いに接触することになり、
その結果、前記接着フィルム５のうち前記のように強く
圧縮変形される部分が、厚さ方向についてのみ導電性を
呈することになるから、前記別のＩＣチップ４における
各接続用電極パッド４ａと、前記一つのＩＣチップ２の
上面に設けられている各接続用電極パッド２ｂとの相互
間を、前記接着フィルム５を介して電気的に接続するこ
とができる。
【００１４】この状態で、前記接着フィルム５を乾燥・
硬化することにより、両ＩＣチップ２，４を、その間を
電気的に接続した状態のもとで、一体的に結合できるの
である。この場合において、前記別のＩＣチップ４は、
その周囲に設けた各バンプ４ｂを介して一つのＩＣチッ
プ２に対して支持されると言う形態になっていることに
より、前記別のＩＣチップ４における下面のうちその周
囲の各接続用電極パッド４ａよりも内側の中心部分に捨
てバンプ３が設けられていないときには、前記別のＩＣ
チップ４のうち前記各バンプより内側の中心部分に一つ
のＩＣチップ２に向かう方向の外力を受けたときにおい
て、前記中心部分が一つのＩＣチップ２に接近するよう
に容易に湾曲変形することになるから、当該別のＩＣチ
ップ４又は一つのＩＣチップ２に割れが発生したり、こ
れら両ＩＣチップ２，４のうち互いに対向する面に形成
されている各種の回路素子にダメージを及ぼしたりする
ことが多発するのである。
【００１５】これに対し、前記したように、別のＩＣチ
ップ４における下面のうちその周囲の各接続用電極パッ
ド４ａよりも内側の中心部分に捨てバンプ３を設けると
言う構成にすることにより、両ＩＣチップ２，４が、当
該両ＩＣチップ２，４のうちその周囲における各バンプ
４ｂより内側の中心部分に外力を受けて、前記中心部分
が互いに接近するように湾曲変形しても、この湾曲変形
を、前記中心部分に貼着した軟質フィルム５及び捨てバ
ンプ３にて小さい値にとどめることができるか、或い
は、前記の湾曲変形を皆無にすることができるのであ
る。
【００１６】なお、前記実施の形態は、一つのＩＣチッ
プ２の別のＩＣチップ４との相互間をその周囲において
電気的に接続する各バンプ４ｂを、別のＩＣチップ４に
おける各接続用電極パッド４ａ側に設ける一方、前記両
ＩＣチップ２，４の湾曲変形を小さく規制するか皆無に
するための捨てバンプ３を、別のＩＣチップ４側に設け
た場合を示したが、本発明はこれに限らず、前記バンプ
４ｂを、一つのＩＣチップ２における各接続用電極パッ
ド２ｂ側に設けたり、或いは、一つのＩＣチップ２にお
ける各接続用電極パッド２ｂと別のＩＣチップ４におけ
る各接続用電極パッド４ａとの両方に設けるようにして
も良く、また、前記捨てバンプ３を、一つのＩＣチップ
２側に貼着したり、或いは、両ＩＣチップ２，４の両方
に設けるように構成しても良いことは言うまでもない。
【００１７】更にまた、前記捨てバンプ３を、前記別の
ＩＣチップ４の周囲に設けた各バンプ４ｂと同様に、両
ＩＣチップ２，４の相互間を電気的に接続するものに構
成しても良いのである。このようにして、一つのＩＣチ
ップ２をリードフレーム１にダイボンディングし、この
一つのＩＣチップ２に対して別にＩＣチップ４を固着す
ると、図６に示すように、前記一つのＩＣチップ２にお
ける周囲の各接続用電極パッド１ａと、リードフレーム
１における各リード端子１ｂとの間を細い金属線６にて
ワイヤボンディングしたのち、前記両ＩＣチップ２，４
の全体を、二点鎖線で示すように、熱硬化性合成樹脂の
トランスファ成形によるパッケージ体７にて密封する。
【００１８】次いで、前記各リード端子１ｂを、リード
フレーム１から切り離したのち、図６に二点鎖線で示す
ように、折り曲げることにより、半導体装置の完成品に
するのである。
【図面の簡単な説明】
【図１】本発明の実施の形態を示す分解斜視図である。
【図２】図１の縦断正面図である。
【図３】リードフレームに対して一つのＩＣチップを固
着した状態を示す縦断正面図である。
【図４】前記一つのＩＣチップに対して別のＩＣチップ
を固着した状態を示す縦断正面図である。
【図５】図４の要部拡大図である。
【図６】半導体装置の縦断正面図である。
【符号の説明】
１ リードフレーム １ｂ リード端子 ２ 一つのＩＣチップ ２ａ，２ｂ 接続用電極パッド ３ 捨てバンプ ４ 別のＩＣチップ ４ａ 接続用電極パッド ４ｂ バンプ ５ 接着フィルム ６ 金属線 ７ パッケージ体

Claims (2)

    (57)【特許請求の範囲】
  1. 【請求項１】一つのＩＣチップの上面に別のＩＣチップ
    を積み重ね、これら両チップには、前記別のＩＣチップ
    の周囲に沿うように適宜間隔でバンプを設け、前記別の
    ＩＣチップを、前記一つのＩＣチップに対して、その間
    に介挿した導電粒子入り接着フィルムにて、前記各バン
    プが当該接着フィルムを圧縮変形するように接着して成
    り、 前記一つのＩＣチップが前記別のＩＣチップに相対する
    面のうち前記各バンプより内側の中心部分に、少なくと
    も一つ以上の捨てバンプを設け、前記別のＩＣチップが
    前記一つのＩＣチップに相対する面のうち前記各バンプ
    より内側の中心部分にも、少なくとも一つ以上の捨てバ
    ンプを設けたことを特徴とする複数のＩＣチップを備え
    た半導体装置の構造。
  2. 【請求項２】捨てバンプの一部又は全部を、電気接続用
    のバンプに構成したことを特徴とする請求項１に記載し
    た複数のＩＣチップを備えた半導体装置の構造。
JP06854097A 1997-03-21 1997-03-21 複数のｉｃチップを備えた半導体装置の構造 Expired - Fee Related JP3349058B2 (ja)

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JP06854097A JP3349058B2 (ja) 1997-03-21 1997-03-21 複数のｉｃチップを備えた半導体装置の構造
US09/045,135 US6175157B1 (en) 1997-03-21 1998-03-20 Semiconductor device package for suppressing warping in semiconductor chips

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JP06854097A JP3349058B2 (ja) 1997-03-21 1997-03-21 複数のｉｃチップを備えた半導体装置の構造

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Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6893896B1 (en) * 1998-03-27 2005-05-17 The Trustees Of Princeton University Method for making multilayer thin-film electronics
US6724084B1 (en) 1999-02-08 2004-04-20 Rohm Co., Ltd. Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device
JP2000232235A (ja) * 1999-02-09 2000-08-22 Rohm Co Ltd 半導体装置
JP3418134B2 (ja) * 1999-02-12 2003-06-16 ローム株式会社 チップ・オン・チップ構造の半導体装置
US6348739B1 (en) * 1999-04-28 2002-02-19 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
EP1077490A1 (en) * 1999-08-17 2001-02-21 Lucent Technologies Inc. Improvements in or relating to integrated circuit dies
US6424033B1 (en) 1999-08-31 2002-07-23 Micron Technology, Inc. Chip package with grease heat sink and method of making
JP3405697B2 (ja) 1999-09-20 2003-05-12 ローム株式会社 半導体チップ
US6146984A (en) * 1999-10-08 2000-11-14 Agilent Technologies Inc. Method and structure for uniform height solder bumps on a semiconductor wafer
US6483190B1 (en) * 1999-10-20 2002-11-19 Fujitsu Limited Semiconductor chip element, semiconductor chip element mounting structure, semiconductor chip element mounting device and mounting method
US6376914B2 (en) * 1999-12-09 2002-04-23 Atmel Corporation Dual-die integrated circuit package
US6426559B1 (en) * 2000-06-29 2002-07-30 National Semiconductor Corporation Miniature 3D multi-chip module
JP3683179B2 (ja) * 2000-12-26 2005-08-17 松下電器産業株式会社 半導体装置及びその製造方法
JP2002313995A (ja) * 2001-04-19 2002-10-25 Mitsubishi Electric Corp ランドグリッドアレイ型半導体装置およびその実装方法
KR100415279B1 (ko) * 2001-06-26 2004-01-16 삼성전자주식회사 칩 적층 패키지 및 그 제조 방법
JP3490987B2 (ja) * 2001-07-19 2004-01-26 沖電気工業株式会社 半導体パッケージおよびその製造方法
US20030038356A1 (en) * 2001-08-24 2003-02-27 Derderian James M Semiconductor devices including stacking spacers thereon, assemblies including the semiconductor devices, and methods
US6815832B2 (en) * 2001-09-28 2004-11-09 Rohm Co., Ltd. Semiconductor device having opposed and connected semiconductor chips with lateral deviation confirming electrodes
US6753613B2 (en) * 2002-03-13 2004-06-22 Intel Corporation Stacked dice standoffs
US7276802B2 (en) * 2002-04-15 2007-10-02 Micron Technology, Inc. Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
US6734044B1 (en) * 2002-06-10 2004-05-11 Asat Ltd. Multiple leadframe laminated IC package
US6919642B2 (en) * 2002-07-05 2005-07-19 Industrial Technology Research Institute Method for bonding IC chips to substrates incorporating dummy bumps and non-conductive adhesive and structures formed
TW556961U (en) * 2002-12-31 2003-10-01 Advanced Semiconductor Eng Multi-chip stack flip-chip package
US6870381B2 (en) * 2003-06-27 2005-03-22 Formfactor, Inc. Insulative covering of probe tips
US7074647B2 (en) * 2003-07-07 2006-07-11 Freescale Semiconductor, Inc. Semiconductor component comprising leadframe, semiconductor chip and integrated passive component in vertical relationship to each other
US7547975B2 (en) * 2003-07-30 2009-06-16 Tdk Corporation Module with embedded semiconductor IC and method of fabricating the module
TW200618705A (en) * 2004-09-16 2006-06-01 Tdk Corp Multilayer substrate and manufacturing method thereof
JP4768994B2 (ja) * 2005-02-07 2011-09-07 ルネサスエレクトロニクス株式会社 配線基板および半導体装置
JP2007042736A (ja) * 2005-08-01 2007-02-15 Seiko Epson Corp 半導体装置及び電子モジュール、並びに、電子モジュールの製造方法
JP4535002B2 (ja) 2005-09-28 2010-09-01 Ｔｄｋ株式会社 半導体ｉｃ内蔵基板及びその製造方法
KR100719376B1 (ko) * 2006-01-05 2007-05-17 삼성전자주식회사 실장 불량을 줄일 수 있는 패드 구조체를 구비하는 반도체장치
TWI292614B (en) * 2006-01-20 2008-01-11 Advanced Semiconductor Eng Flip chip on leadframe package and method of making the same
JP2007266111A (ja) * 2006-03-27 2007-10-11 Sharp Corp 半導体装置、それを用いた積層型半導体装置、ベース基板、および半導体装置の製造方法
US8022554B2 (en) 2006-06-15 2011-09-20 Sitime Corporation Stacked die package for MEMS resonator system
TWI310983B (en) * 2006-10-24 2009-06-11 Au Optronics Corp Integrated circuit structure, display module, and inspection method thereof
JP2008227271A (ja) * 2007-03-14 2008-09-25 Fujitsu Ltd 電子装置および電子部品実装方法
FR2918212B1 (fr) * 2007-06-27 2009-09-25 Fr De Detecteurs Infrarouges S Procede pour la realisation d'une matrice de rayonnements electromagnetiques et procede pour remplacer un module elementaire d'une telle matrice de detection.
US20090014870A1 (en) * 2007-07-12 2009-01-15 United Microelectronics Corp. Semiconductor chip and package process for the same
US8205182B1 (en) * 2007-08-22 2012-06-19 Cadence Design Systems, Inc. Automatic synthesis of clock distribution networks
JP4693852B2 (ja) * 2008-02-22 2011-06-01 パナソニック株式会社 半導体装置および半導体装置の製造方法
EP2259666A4 (en) * 2008-03-27 2011-09-07 Ibiden Co Ltd PRINTED CIRCUIT BOARD COMPRISING INTEGRATED ELECTRONIC COMPONENTS, AND METHOD FOR MANUFACTURING THE SAME
KR101632399B1 (ko) 2009-10-26 2016-06-23 삼성전자주식회사 반도체 패키지 및 그 제조방법
US8604614B2 (en) 2010-03-26 2013-12-10 Samsung Electronics Co., Ltd. Semiconductor packages having warpage compensation
US8916969B2 (en) * 2011-07-29 2014-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, packaging methods and structures
US8522186B2 (en) 2011-12-16 2013-08-27 Industrial Technology Research Institute Method and apparatus of an integrated circuit
CN103208501B (zh) 2012-01-17 2017-07-28 奥林巴斯株式会社 固体摄像装置及其制造方法、摄像装置、基板、半导体装置
JP5660260B2 (ja) * 2012-10-05 2015-01-28 株式会社村田製作所 電子部品内蔵モジュール及び通信端末装置
KR102190382B1 (ko) 2012-12-20 2020-12-11 삼성전자주식회사 반도체 패키지
KR102287754B1 (ko) 2014-08-22 2021-08-09 삼성전자주식회사 칩 적층 반도체 패키지
CN110088884A (zh) * 2016-11-30 2019-08-02 深圳修远电子科技有限公司 集成电路多芯片层叠封装结构以及方法
KR102450575B1 (ko) * 2018-07-10 2022-10-07 삼성전자주식회사 뒤틀림의 제어를 위한 채널을 포함하는 반도체 칩 모듈 및 이의 제조 방법
KR102556518B1 (ko) * 2018-10-18 2023-07-18 에스케이하이닉스 주식회사 상부 칩 스택을 지지하는 서포팅 블록을 포함하는 반도체 패키지
KR20220155139A (ko) * 2021-05-14 2022-11-22 삼성전자주식회사 반도체 패키지

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62194652A (ja) * 1986-02-21 1987-08-27 Hitachi Ltd 半導体装置
US5001542A (en) * 1988-12-05 1991-03-19 Hitachi Chemical Company Composition for circuit connection, method for connection using the same, and connected structure of semiconductor chips
JP2876773B2 (ja) * 1990-10-22 1999-03-31 セイコーエプソン株式会社 プログラム命令語長可変型計算装置及びデータ処理装置
US5400950A (en) * 1994-02-22 1995-03-28 Delco Electronics Corporation Method for controlling solder bump height for flip chip integrated circuit devices
US5523628A (en) * 1994-08-05 1996-06-04 Hughes Aircraft Company Apparatus and method for protecting metal bumped integrated circuit chips during processing and for providing mechanical support to interconnected chips
US5686703A (en) * 1994-12-16 1997-11-11 Minnesota Mining And Manufacturing Company Anisotropic, electrically conductive adhesive film
KR100438256B1 (ko) * 1995-12-18 2004-08-25 마츠시타 덴끼 산교 가부시키가이샤 반도체장치 및 그 제조방법
US5813870A (en) * 1996-07-12 1998-09-29 International Business Machines Corporation Selectively filled adhesives for semiconductor chip interconnection and encapsulation

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