JP3341781B2 - Image decoding device and image encoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding apparatus and an image coding apparatus suitable for use in a case where moving image data is compressed and transmitted, and expanded and reproduced on the receiving side. > About.

[0002]

2. Description of the Related Art Conventionally, in a so-called image signal transmission system, such as a video conference system or a video telephone system, for transmitting an image signal composed of a moving image to a remote place, in order to use a transmission path efficiently, An image signal is encoded using a line correlation or an inter-frame correlation of the image signal, thereby increasing the transmission efficiency of significant information.

FIG. 18 is a block diagram showing a configuration of an example of a conventional image encoding apparatus for encoding an image. Image data to be encoded is input to the motion vector detection circuit 1. The motion vector detection circuit 1 processes the image data of each frame as an I picture, a P picture, or a B picture according to a predetermined sequence set in advance. It is determined in advance which of the I, P, and B pictures to process the sequentially input image of each frame. Image data of a frame processed as an I picture is stored in the front original image section 2a, image data processed as a B picture is stored in the original image section 2b, and image data processed as a P picture is stored in the rear original image section. 2c.

Further, when an image of a frame to be processed as a B picture or a P picture is input, the image data of the first P picture which has been stored in the rear original image section 2c is stored in the front original image section 2a. The image data of the next B picture is transferred and stored in the original image section 2b, and the image data of the next P picture is stored (overwritten) in the rear original image section 2c. Such operations are sequentially repeated.

The motion vector detecting circuit 1 includes an original image section 2b
, The image data of the frame is divided into blocks of 8 × 8 pixels, and the I-picture image stored in the front original image section 2a and the I-picture image stored in the rear original image section 2c. A motion vector is detected between the P picture and the P picture. P stored in the rear original image part 2c
For a picture, the image data of the frame is 8 ×
A motion vector is detected between an image of the I picture stored in the front original image section 2a by dividing the image into blocks of 8 pixels. No motion vector is detected for the I picture.

The motion vector detecting circuit 1 outputs the image data whose motion has been detected in block units to the operation unit 3 in the next stage in macro block units.

That is, each frame image data is shown in FIG.
As shown in FIG. 19A, the slice is divided into N slices, and each slice includes M macroblocks as shown in FIG. 19B. Then, as shown in FIG. 19C, each macro block is composed of luminance signal data Y1 to Y4 of a block in units of 8 × 8 pixels, and corresponding color difference signal data Cb and Cr.

At this time, the arrangement of the image data in the slice is such that the image data is continuous in macroblock units, and in this macroblock, the image data is continuous in block units in the order of raster scanning. It has been made like that.

[0009] Here, the macroblock is a 16 × 1 continuous with respect to the luminance signal in the horizontal and vertical scanning directions.
While the image data (Y1 to Y4) of six pixels is used as one unit, two color difference signals Cb and Cr corresponding to the unit are used.
In, the data amount is reduced, and one 8 × 8 pixel block is assigned to each block.

The motion vector detecting circuit 1 outputs the motion vectors of the four blocks of each macro block to the variable length coding circuit 6 and the motion compensating circuit 13 and calculates the sum of the absolute values thereof to make a prediction judgment. Output to the circuit 14.

When the motion vector detecting circuit 1 is reading image data of an I picture from the front original image portion 2a (the sum of absolute values of the motion vectors supplied from the motion vector detecting circuit 1 is 0). Time), the intra-frame prediction mode (mode in which motion compensation is not performed) is set as the prediction mode, and the switch 3d of the calculation unit 3 is switched to the contact a side. Thereby, the image data of the I picture is
DCT (Discrete Cosine Transform) input to DCT circuit 4
Processed and converted to DCT coefficients. The DCT coefficients are input to the quantization circuit 5, quantized in a quantization step corresponding to the data storage amount (buffer storage amount) of the transmission buffer 7, and then input to the variable length coding circuit 6.

The variable length coding circuit 6 corresponds to the quantization step supplied from the quantization circuit 5, the prediction mode supplied from the prediction determination circuit 14, and the motion vector supplied from the motion vector detection circuit 1. The image data (I-picture data in this case) supplied from the quantization circuit 5 is converted into a variable-length code such as a Huffman code and output to the transmission buffer 7.

The transmission buffer 7 temporarily stores the input data and outputs it to the transmission data control circuit 63. The transmission data control circuit 111 outputs the data supplied from the transmission buffer 7 to a transmission path.

On the other hand, the I-picture data output from the quantization circuit 5 is input to the inverse quantization circuit 9 and is inversely quantized in accordance with the quantization step supplied from the quantization circuit 5. The output of the inverse quantization circuit 9 is IDCT (inverse DCT)
After being input to the circuit 10 and subjected to inverse DCT, it is supplied to the forward prediction image section 12 a of the frame memory 12 via the arithmetic unit 11 and stored.

The motion vector detecting circuit 1 converts the sequentially input image data of each frame into, for example,
When each image is processed as a picture of I, B, P, B, P, B,..., The image data of the first input frame is processed as an I picture, and the image of the next input frame is processed as a B picture. , The image data of the next input frame is processed as a P picture. This is because a B picture involves backward prediction and cannot be decoded unless a P picture as a backward predicted image is prepared first.

Then, the motion vector detecting circuit 1 detects a motion vector of the picture data of the P picture stored in the rear original picture section 2c in units of 8 × 8 pixels next to the I picture. Then, the sum of absolute values of the motion vectors of the four 8 × 8 pixel blocks forming the macroblock is supplied from the motion vector detection circuit 1 to the prediction determination circuit 14. When the sum of absolute values of the macroblocks of the P picture is smaller than a predetermined reference value, the prediction determination circuit 14 sets the intra-frame prediction mode as the prediction mode. When the value is larger than the reference value, the forward prediction mode is set.

When the intra-frame prediction mode is set, the arithmetic unit 3 switches the switch 3d to the contact a as described above. Therefore, this data is transmitted to the transmission path via the DCT circuit 4, the quantization circuit 5, the variable length encoding circuit 6, the transmission buffer 7, and the transmission data control circuit 111, like the I picture data. The data is supplied to the backward prediction image section 12b of the frame memory 12 via the inverse quantization circuit 9, the IDCT circuit 10, and the calculator 11, and stored therein.

In the forward prediction mode, the switch 3d is switched to the contact b, and the image data (in this case, the image of the I picture) stored in the forward prediction image section 12a is read out. Motion compensation is performed corresponding to the motion vector output from the motion vector detection circuit 1. That is, the motion compensation circuit 13
When the setting of the forward prediction mode is instructed, the read address of the forward prediction image unit 12a is shifted from the position corresponding to the position of the macroblock currently output by the motion vector detection circuit 1 by the amount corresponding to the motion vector. To read out data to generate predicted image data.

The predicted image data output from the motion compensation circuit 13 is supplied to a computing unit 3a. The arithmetic unit 3a subtracts the predicted image data corresponding to the macroblock supplied from the motion compensation circuit 13 from the data of the macroblock supplied from the motion vector detection circuit 1, and outputs the difference. This difference data is transmitted to the transmission path via the DCT circuit 4, the quantization circuit 5, the variable length encoding circuit 6, the transmission buffer 7, and the transmission data control circuit 111.
The difference data is input to the arithmetic unit 11 via the inverse quantization circuit 9 and the IDCT circuit 10.

The arithmetic unit 11 is also supplied with the same data as the predicted image data supplied to the arithmetic unit 3a. The arithmetic unit 11 adds the prediction image data output from the motion compensation circuit 13 to the difference data output from the IDCT circuit 10. As a result, the original P picture image data is obtained. The P-picture image data is supplied to and stored in the backward prediction image section 12b of the frame memory 12.

The motion vector detecting circuit 1 is as follows.
The data of the I picture and the P picture is
After being stored in a and the backward prediction image unit 12b, a motion vector of the B picture is detected in block units. The prediction determination circuit 14 sets the prediction mode to any of the intra-frame prediction mode, the forward prediction mode, the backward prediction mode, and the bidirectional prediction mode in accordance with the magnitude of the sum of the absolute values of the motion vectors of the blocks constituting the macroblock. Set crab.

As described above, in the intra-frame prediction mode or the forward prediction mode, the switch 3d is switched to the contact point a or b. At this time, the same processing as in the case of the P picture is performed, and the data is transmitted.

On the other hand, when the backward prediction mode or the bidirectional prediction mode is set, the switch 3d is switched to the contact point c or d.

In the backward prediction mode in which the switch 3d is switched to the contact point c, the image (image of the P picture in this case) data stored in the backward prediction image section 12b is read out. , The motion is compensated corresponding to the motion vector output from the motion vector detection circuit 1. That is, the motion compensation circuit 13 is
4, when the setting of the backward prediction mode is instructed, the read address of the backward prediction image unit 12b is changed from the position corresponding to the position of the macroblock currently output by the motion vector detection circuit 1 to the position corresponding to the motion vector. The data is read out by shifting, and predicted image data is generated.

The predicted image data output from the motion compensation circuit 13 is supplied to a computing unit 3b. The calculator 3b subtracts the predicted image data supplied from the motion compensation circuit 13 from the macroblock data supplied from the motion vector detection circuit 1, and outputs the difference. This difference data is transmitted to the transmission path via the DCT circuit 4, the quantization circuit 5, the variable length encoding circuit 6, the transmission buffer 7, and the transmission data control circuit 111.

In the bidirectional prediction mode in which the switch 3d is switched to the contact point d, the image data (image of the I picture in this case) stored in the forward prediction image section 12a and the image data stored in the backward prediction image section 12b. The image data (in this case, an image of a P picture) is read out, and the motion compensation circuit 13 performs motion compensation corresponding to the motion vector output from the motion vector detection circuit 1. That is, when the setting of the bidirectional prediction mode is instructed by the prediction determination circuit 14, the motion vector detection circuit 1 outputs the read addresses of the forward predicted image section 12 a and the backward predicted image section 12 b. The data is read out from the position corresponding to the position of the existing macroblock by an amount corresponding to the motion vector, and predicted image data is generated.

The predicted image data output from the motion compensation circuit 13 is supplied to a calculator 3c. The arithmetic unit 3c subtracts the prediction image data supplied from the motion compensation circuit 13 from the macroblock data supplied from the motion vector detection circuit 1, and outputs the difference. This difference data is transmitted to the transmission path via the DCT circuit 4, the quantization circuit 5, the variable length encoding circuit 6, the transmission buffer 7, and the transmission data control circuit 111.

The picture of the B picture is not stored in the frame memory 12 because it is not regarded as a predicted picture of another picture.

As described above, since image data is transmitted as a variable-length code, for example, when a simple still image continues for a relatively long time, the data to be transmitted may be insufficient. is there. In such a case, an invalid code can be added to the data to be transmitted in order to prevent the transmission data from being lost. This invalid code can be added, for example, in units of slices or macroblocks shown in FIG.

FIG. 20 shows an example in which an invalid code is added in slice units. Each slice is provided with a slice start code at the beginning. This slice start code is composed of a synchronization code and an attribute code. The synchronization code is composed of 2-byte data in which each bit is all logical 0, and 1-byte data in which the LSB is logical 1 and the other bits are logical 0 (total 3 bytes of data). I have. The attribute code is one byte, in which a code indicating data relating to the data of the slice, such as the attribute of the corresponding slice, is arranged. Therefore,
The slice start code is composed of a total of 4 bytes (32 bits) of data.

The invalid code is such that data in which all bits are set to logical 0 is added before the slice start code by a required number of bytes in units of bytes (8 bits). That is, invalidation added to the slice
If the code is called a slice invalid code,
The invalid code for slice is 1 byte data of logical 0.
It is configured as one unit.

FIG. 21 shows an invalid code added to a macroblock. That is, in this case, a total of 11 bits in which the upper 7 bits are logical 0 and the lower 4 bits are logical 1 are regarded as one unit of the invalid code, and the invalid code is a predetermined number of units of the macro block. It is added before the valid code. That is, it is added to the macro block.
Invalid code is called invalid code for macro block.
If, Makuroburo Tsu invalid code for the phrase, "0000
0001111 "as a unit.
You.

When the macroblock invalid code is added to the macroblock data as shown in FIG. 21, the transmission data control circuit 111 shown in FIG.
2 can be configured. In this example, data output from the transmission buffer 7 is input to the N / M converter 121 and converted from data in units of N bits to data in units of M bits. Data is outputted from the N / M converter 121 is input to a multiplexer (MUX) 122, a macroblock adjustment Day
And the invalid code output from the data generation circuit 123.

That is, the macroblock adjustment data generating circuit 123 generates a macroblock invalid code in which the upper 7 bits are logic 0 and the lower 4 bits are logic 1 shown in FIG. Controller 1
24 is a multiplexer 1 corresponding to the transmission buffer information.
Controls 22, when the transmission buffer 7 is unlikely to underflow, when selecting the output of the N / M converter 121, there is a risk of underflow, the macroblock adjustment data
The macroblock invalid code output from the generation circuit 123 is selected. As a result, an arbitrary number of macroblock invalid codes are mixed with the data output from the multiplexer 122.

FIG. 23 is a block diagram showing an example of the configuration of an image decoding device for decoding data encoded by the image encoding device of FIG. The encoded image data transmitted via the transmission path is received by a receiving circuit (not shown), temporarily stored in a receiving buffer 32, and then supplied to the variable length decoding circuit 33 of the decoding circuit 50. . The variable length decoding circuit 33 performs variable length decoding on the data supplied from the reception buffer 32, and outputs the motion vector and the prediction mode to the motion compensation circuit 38, and outputs the quantization step to the inverse quantization circuit 34, respectively. At the same time, it outputs the decoded (variable length decoded) image data to the inverse quantization circuit 34.

The inverse quantization circuit 34 is a variable length decoding circuit 3
3 is inversely quantized according to the quantization step also supplied from the variable length decoding circuit 33, and is output to the IDCT circuit 35. Inverse quantization circuit 3
The data (DCT coefficient) output from 4 is subjected to inverse DCT processing in the IDCT circuit 35 and supplied to the calculator 36.

When the image data supplied from the IDCT circuit 35 is I-picture data, the data is output from the arithmetic unit 36 and is input to the arithmetic unit 36 later (P or B picture data). Is supplied to and stored in the forward prediction image section 37a of the frame memory 37 in order to generate the prediction image data.

This data is output to the D / A converter 3
After the D / A conversion by 9, it is supplied to the display 40 and displayed.

When the image data supplied from the IDCT circuit 35 is P-picture data using the image data one frame before as the predicted image data, the data is stored in the forward predicted image section 37a of the frame memory 37. The image data (I-picture data) one frame before is read out, and the motion compensation circuit 38 performs motion compensation corresponding to the motion vector output from the variable length decoding circuit 33. Then, the arithmetic unit 36 adds the image data (difference data) supplied from the IDCT circuit 35 and outputs the result. The added data, that is, the decoded P picture data, is used to generate a predicted picture data of the picture data (B picture data) to be input later to the arithmetic unit 36. It is supplied to and stored in 37b.

Since this P picture is an image to be displayed next to the next B picture, it is not displayed at this time.

When the image data supplied from the IDCT circuit 35 is B picture data, it is stored in the forward prediction image section 37a of the frame memory 37 in accordance with the prediction mode supplied from the variable length decoding circuit 33. I
The image data of the picture (in the case of the forward prediction mode), the image data of the P picture stored in the backward prediction image section 37b (in the case of the backward prediction mode), or both image data (in the case of the bidirectional prediction mode) The motion vector is read and the motion compensation circuit 38 performs motion compensation corresponding to the motion vector output from the variable length decoding circuit 33.

The data subjected to the motion compensation by the motion compensating circuit 38 in this manner is processed by the arithmetic unit 36 in the IDC.
It is added to the output of the T circuit 35. This addition output is D /
After being D / A converted by the A converter 39, it is supplied to the display 40 and displayed.

However, since this addition output is B picture data, it is not used for generating a predicted image of another image, and is not stored in the frame memory 37.

After the image of the B picture is output and displayed,
The image data of the P picture stored in the backward prediction image section 37b is read and supplied to the arithmetic unit 36 via the motion compensation circuit 38. However, at this time, no motion compensation is performed. Then, this data is output to the display 40 via the D / A converter 39 and displayed.

When the macroblock invalid code is added, the macroblock invalid code is removed by the variable length decoding circuit 33.

[0046]

In the conventional apparatus, the invalid code for the added macroblock is thus used.
The variable length decoding circuit 33 removes the data as a part of the process of decoding data (variable length decoding). As a result, in the variable length decoding circuit 33, Mak
During the period in which the invalid code for block lock is removed, data is not supplied to the circuits subsequent to the inverse quantization circuit 34, and there is a problem that these circuits play. NTS
In the case of the C system, an image of one frame is displayed on the display 40 at a period of 1/30 second. However, if the invalid code is long, the circuits after the inverse quantization circuit 34 correspond to one frame. In some cases, data cannot be processed within 1/30 second, and image display on the display 40 may be interrupted.

The present invention has been made in view of such a situation, and it is an object of the present invention to prevent a display image from being interrupted halfway.

[0048]

An image decoding apparatus according to the present invention.
Temporarily stores the transmitted compressed image data
Storage means for recovering the compressed image data stored in the storage means;
Read out in accordance with the progress of the
One frame within a period equal to or shorter than the period
Decoding means for decoding the image data;
Added to prevent data loss from reduced image data
Removing means for removing and outputting a disabled invalid code, and removing
Supply the compressed image data output from the storage means to the storage means
The invalid code is provided with a unique pattern.
Of the synchronization code and stuffing code
It is specially configured to include
Sign.

The image encoding apparatus according to the present invention has
Divides image data into slices consisting of a predetermined number of lines
Dividing means and a predetermined number of macroblocks
And compression encoding, and lack of image data
When the macro block data is missing data
Adding means for adding an invalid code for preventing
In an image coding device that uses
Consists of turn synchronization code and stuffing code
Must include stuffing start code
It is characterized by.

[0050]

[0051]

[0052]

[0053]

[0054]

[0055]

[0056]

[0057]

[0058]

In the image decoding apparatus according to the present invention, the transmitted
Compressed image data is temporarily stored in the storage means.
You. Further, the compressed image data stored in the storage means
Is read out according to the progress of the decoding process, and the image file is read out.
One frame within a time equal to or shorter than the frame period
Image data is decoded. On the other hand, it has been transmitted
To prevent data loss from compressed image data
The added invalid code is removed and output.
The compressed image data obtained is supplied to the storage unit. This place
Invalid code is a unique pattern synchronization code
A stuffing star consisting of a stuffing code
It is comprised including the code.

In the image encoding apparatus of the present invention, one frame
Frame data consisting of a predetermined number of lines
Divided into slices into a predetermined number of macroblocks.
It is divided and compression-encoded. And the image data is not
When adding, the data of the macro block is missing data
An invalid code for preventing the error is added. in this case
Invalid code is a unique pattern synchronization code
Staffing start consisting of tough code
It is configured to include code.

[0060]

[0061]

[0062]

[0063]

[0064]

[0065]

[0066]

[0067]

[0068]

FIG. 1 is a block diagram showing the configuration of an embodiment of an image encoding apparatus according to the present invention. In the figure, parts corresponding to those of the conventional image encoding apparatus shown in FIG. I have. In other words, this image encoding device has basically the same configuration as the conventional image encoding device, but only the transmission data control circuit 8 has a different configuration from the conventional transmission data control circuit 111. .

FIG. 2 shows a configuration example of the transmission data control circuit 8 in FIG. In this embodiment, the data output from the transmission buffer 7 is supplied to an N / M converter 21, and the data in units of N bits is converted into data in units of M bits, and the multiplexer (M)
UX) 22. Data output from the adjustment data generation circuit 23 or the stuffing start code generation circuit 24 is also selected and supplied to the multiplexer 22 by a multiplexer (MUX) 25. Multiplexers 22 and 25 are
The switching is performed according to the output of the controller 26.

Next, in this embodiment, when an invalid code is added to a macroblock, its format is determined as shown in FIG. That is, in this application
The invalid code used is called the new invalid code.
And the new invalid code can be composed of the stuffing start code and the adjustment data. The stuffing start code is composed of a synchronization code and a stuffing code. The synchronization code is composed of 2-byte data in which each bit is all logical 0, and 1-byte data in which the LSD is logical 1 and the other 7 bits are all logical 0, for a total of 3 bytes of data. This synchronization code is a unique pattern, and it is determined that the same pattern will not occur except for this synchronization code.
In the stuffing code (the portion indicated by x in the figure), information about the data such as the attribute of the data of the corresponding macro block is inserted.

The adjustment data is composed of a one-byte zero code in which all bits are logical 0 and a code of a predetermined number of bits for synchronizing in eight bits.
For example, as shown in FIG. 3, a code for synchronizing in units of 8 bits is obtained by dividing a (preceding) effective code (indicated by * in the figure) of a macroblock in units of 8 bits. Bits which cannot be formed and which remain (1 bit in the case of the embodiment of FIG. 3) are bits added to make data in units of 8 bits (accordingly, the embodiment of FIG. 3) In the case of the example, 7-bit logic 0 data). The number of bytes to which the zero code is added is arbitrary, and only the necessary number is added.

[0072] In other words, the new invalid code includes at least a staffing start code of a total of 4 bytes, further
In FIG. 3, if it is necessary to add a code for synchronizing in units of 8 bits, this is added. When it is necessary to further lengthen the new invalid code, a predetermined number of byte-based zero codes are added.

Next, referring to the flowchart of FIG.
The operation will be described. 2, the stuffing start code shown in FIG. 3 is generated by a stuffing start code generation circuit 24, and the adjustment data is generated by an adjustment data generation circuit 23. The controller 26 controls the multiplexers 22 and 25 according to the transmission buffer information supplied from the transmission buffer 7 and the byte alignment information.

That is, first, the macroblock data supplied from the N / M converter 21 is output to the transmission line via the multiplexer 22 (step S1), and the controller 2
At 6, based on the transmission buffer information (the amount of data stored in the transmission buffer 7) supplied from the transmission buffer 7,
It is determined whether it is necessary to add a new invalid code to the data of the macro block supplied from the N / M converter 21 (step S2). When the controller 26 determines that it is not necessary to add a new invalid code to the data of the macroblock supplied from the N / M converter 21, the process returns to step S <b> 1, and is performed via the N / M converter 21. The macroblock data supplied next from the transmission buffer 7 is output to the transmission path via the multiplexer 22.

On the other hand, in the controller 26, N / M
When it is determined that a new invalid code needs to be added to the macroblock data supplied from the converter 21, the multiplexer 22 is switched so as to select the data supplied from the multiplexer 25. .

[0076] At the same time, the controller 26, the adjustment
The multiplexer 25 is switched to select the output of the data generation circuit 23, and the adjustment data generation circuit is determined until it is determined that there is no need to add a zero code to the data of the macro block supplied from the N / M converter 21. The output of 23 is output to the transmission path via multiplexers 25 and 22 (steps S3 and S4).

At the same time, in the controller 26, the data output to the transmission path is byte-aligned based on the byte alignment information supplied from the transmission buffer 7.

Thereafter, N / N
The macroblock data supplied from the M converter 21
When it is determined that it is no longer necessary to add the zero code, the multiplexer 25 is switched so as to select the output of the stuffing start code generation circuit 24, whereby one stuffing start from the stuffing start code generation circuit 24 is performed. The code is output to the transmission path via the multiplexers 25 and 22 (Step S5).

Then, the process returns to step S1, and the above-described processing (the processing of steps S1 to S5) is repeated.

As described above, when there is a possibility that the macroblock data underflows in response to the information from the transmission buffer 7, the multiplexer 22 is controlled and the new invalid code is output to the transmission path.

FIG. 5 is a block diagram showing the configuration of an embodiment of an image decoding apparatus for decoding the data thus encoded and transmitted, and the parts corresponding to those in FIG. Are attached. That is, this image decoding apparatus has the same configuration as that in FIG. 23 except that the invalid code removing circuit 31 is connected to the preceding stage of the reception buffer 32. In this embodiment,
An invalid code removing circuit 3 from the transmitted image data
After the new invalid code is removed in 1, the data is supplied to the reception buffer 32 and stored.

FIG. 6 shows a configuration example of the invalid code removing circuit 31. In this embodiment, the transmitted image data (bit stream) is converted into an M / 8 converter 51.
And converted from data in units of M bits to data in units of 8 bits. M is set to 1 when transmitted in a normal communication device. Accordingly, in this case, the M / 8 converter 51 performs a process of dividing the input 1-bit data into 8-bit data. The output of the M / 8 converter 51 is supplied to a register 52 for timing adjustment, temporarily stored, and then supplied to an 8 / L converter 53, where the data is converted from 8-bit data to L-bit data. It has been made. This L corresponds to the number of write bits of the receiving buffer 32 at the subsequent stage.

The output of the M / 8 converter 51 is also supplied to a zero detection circuit 54, and the data in units of 8 bits is
It is determined whether or not all the logics are 0. Then, when all the bits are logic 0, the zero detection circuit 54 outputs a detection signal to the counter 55. The counter 55 counts the detection signal output from the zero detection circuit 54 and outputs the count value to the write control unit 56. The write control unit 56 controls the write state of the 8 / L converter 53 according to the count value of the counter 55.

Next, the operation will be described with reference to the timing chart of FIG. 7 (in this figure, data is indicated in hexadecimal units in bytes). Each circuit operates in synchronization with a clock a shown in FIG.
The M / 8 converter 51 converts the input M-bit data into 8-bit (1 byte) data b (FIG. 7).
(B)) and outputs the result to the register 52 and the zero detection circuit 54.

The zero detection circuit 54 outputs a detection signal to the counter 55 when the input 8-bit logic is all 0s.
Output to The counter 55 counts the number of detection signals (the number of data in which all 8 bits are all logical 0) that the zero detection circuit 54 continuously outputs (in a clock cycle), and counts the count value (count value). d (FIG. 7D) is output to the write control unit 56.

The count value of the counter 55 is reset when a detection signal is not output from the zero detection circuit 54 in a clock cycle. That is,
When at least one of the 8 bits output from the M / 8 converter 51 becomes non-zero, the counter 55
Are reset.

When the count value d of the counter 55 exceeds a predetermined value (4 in this embodiment), the write control unit 56 outputs the output c of the register 52 of the 8 / L converter 53 (see FIG. 7). A control signal e (FIG. 7 (e)) for inhibiting the writing of (c)) is output.

That is, after the data output from the M / 8 converter 51 is delayed by one clock by the register 52,
The data in which the logic of each of the eight bits is all 0 is input to the L converter 53.
The data is written to the L converter 53. In the data of 3 bytes to C ₁ to C ₃ is written into the 8 / L converter 53, data of C ₄ to C ₇ 7 embodiment, 8 /
Writing to the L converter 53 is prohibited. As a result, 8 /
The L converter 53 sequentially outputs C ₈ and C ₉ after C _{1 to} C ₃ . In the transmitted data,
Although staffing start code by C ₆ to C ₉ is what is configured in the data output from the 8 / L converter 53, staffing start code is constituted by the _{C 2, C 3, C 8} , C 9 Will be.

The write control unit 56 determines that all the logics are 0
The reason why the data of up to 3 bytes is passed is that 2 bytes are necessary to constitute the stuffing start code, and the remaining 1 byte is, as described in FIG. This is to prevent the data from being removed because the data is required for synchronization in units of 8 bits.

Therefore, in this embodiment, the new invalid code
A part of the code, that is, a zero code (0 in 8-bit units) inserted between the stuffing start code shown in FIG. 3 and a code for synchronizing in 8-bit units is substantially removed. Will be.

FIG. 8 shows a specific data write state. As shown in the figure, when 5 bytes of data in which all logics are 0 are continuously input, 3
The data up to the byte is written to the 8 / L converter 53, but the fourth and fifth data are prohibited from being written.

As described above, the data from which a part of the new invalid code has been removed is supplied to the reception buffer 32 and stored. Then, in the decoding circuit 50, in the case of NTSC image data, one frame of data is 1/30.
Processed within seconds. Two-byte data in which all the logics constituting the synchronization code in the stuffing start code are 0 and data in which the logic for synchronizing 8 bits is 0 are variable-length coded as in the conventional case. It is removed in the circuit 33. However, since its length is as short as about 2 bytes, it does not require a long time to remove it, and it is possible to efficiently process valid codes (encoded image data). Becomes

The processing in the decoding circuit 50 is the same as in the conventional case, and a description thereof will be omitted.

Next, FIG. 9 shows a configuration example of the invalid code removing circuit 31 in the case of converting data transmitted in units of M bits into data in units of K bits and removing a new invalid code. In the figure, portions corresponding to those in FIG. 6 are denoted by the same reference numerals. The transmitted image data (bit stream) is supplied to the M / K converter 61, where the data is converted from M-bit data to K-bit data. The output of the M / K converter 61 is supplied to a group of registers 62, each of which is composed of P serially connected K-bit registers (not shown) for timing adjustment, and is delayed by P times the clock cycle. Later, the K / L converter 63
And is converted from K-bit data to L-bit data.

Here, in this embodiment, K is 8
The following values take one of the values 1, 2, 4, or 8. Further, P is defined as 8 / K.

The output of the M / K converter 61 is also supplied to a zero detection circuit 64, and the data in units of K bits is
It is determined whether or not all the logics are 0. When all the bits are logic 0, a detection signal is output from the zero detection circuit 64 to the counter 55. The counter 55 counts the number of detection signals continuously output from the zero detection circuit 64 (the number of data in which all 8 bits are logical 0) and writes the count value (count value) to the write control unit 65. Output to

The write controller 65 determines that the count value of the counter 55 is the maximum number of zeros (23 (FIG. 3)) of the synchronization code of the stuffing start code and the maximum value added for byte alignment. The value obtained by adding the number of zeros (seven) and the number of zeros (defined by the standard) allowed to come to the last part of the immediately preceding effective code (FIG. 3) is added to the value obtained by adding 1 to the number. If the value is equal to or larger than the value obtained by dividing by K (however, rounded down to the decimal point), writing of the output of the register group 62 of the K / L converter 63 is prohibited.

Therefore, as shown in FIG. 10 (a), when data is input in which the number of zeros permitted to come to the last part of the immediately preceding effective code (effective code) is, for example, eight. , The number of zeros (23) in the synchronization code of the stuffing start code, the maximum number of zeros added for byte alignment (7), and the last part of the last valid code (FIG. 3) Is the number of zeros allowed (8
) And 1 are 39 (= 23 + 7 + 8)
+1), the write control unit 65 determines that the count value of the counter 55 is 39 (= 39/1) or more when K = 1 and 19 (= 39/2, where decimal point) when K = 2. When K = 4, 9 (= 39/4, but rounded down below the decimal point) or more, when K = 8, when K = 8, 4 (= 39/8, rounded down below the decimal point), K / L Register group 62 of converter 63
Are respectively inhibited from being written, and the zero code is removed.

However, in the case of FIG. 10A, the data to be removed (removed) is a 2-byte zero code added in units of one byte, but as described in FIG. Means that the two-byte zero part of the synchronization code of the stuffing start code is removed, and the synchronization code of the stuffing start code interpolates the zero- removed part with the zero code of zero, so to speak. Become composed.

That is, in the case shown in FIG. 10A, when K = 1, the counter value of the synchronization code whose counter value is 39 or more is 39 or more.
2 to 0 are removed, and the remaining synchronization codes (0 corresponding to a counter value of 32 to 38 and 1 of the LSB of the synchronization code) and the counter value corresponding to 16 to 31 are removed. The original synchronization code is composed of 2 bytes of 0, that is, the zero code to be removed.

Further, when K = 2, 2 bytes of 0 corresponding to 19 to 26 whose counter value is 19 or more are removed from the synchronization code, and the remaining synchronization code and the counter value are 8 to 15 , The original synchronization code is constituted by 0 corresponding to the above. When K = 4, two bytes of 0 corresponding to 9 to 12 whose counter value is 9 or more are removed from the synchronization code, and the remaining synchronization code is removed. When,
The original synchronization code is constituted by 0 corresponding to the counter value of 4 to 7.

When K = 8, a 2-byte zero code is substantially removed as described with reference to FIG.

Further, as shown in FIG. 10 (b), when data is input in which the number of zeros permitted to come to the last part of the immediately preceding effective code (effective code) is, for example, nine. , The number of zeros (23) in the synchronization code of the stuffing start code, the maximum number of zeros added for byte alignment (7), and the last part of the last valid code (FIG. 3) Is the number of zeros allowed (9
), And the value obtained by adding 1 is 40 (= 23 + 7 +
9), in the write control unit 65, the count value of the counter 55 is equal to or greater than 40 (= 40/1, but rounded down to the decimal point) when K = 1, and 20 (= 40) when K = 2. More than / 2, but rounded down to the decimal point, when K = 4, more than 10 (= 40/4, but rounded down to the decimal point), when K = 8, more than 5 (= 40/8, but rounded down to the decimal point) Then, the register group 62 of the K / L converter 63
Are respectively inhibited from being written, whereby the zero code is substantially removed as in the case of FIG.

Next, FIG. 11 is a block diagram showing the configuration of the second embodiment of the transmission data control circuit 8 of the image coding apparatus of FIG. In the figure, parts corresponding to those in FIG. 2 are denoted by the same reference numerals.

In this embodiment, the data output from the transmission buffer 7 is supplied to an N / M converter 21, and the data in units of N bits is converted into data in units of M bits, and the data is converted into a multiplexer. (MUX) 72. This multiplexer 7
2 also has a stuffing start code generation circuit 2
4 is supplied. The multiplexer 72 is switched in accordance with the output of the controller 71.

In this embodiment, when a new invalid code is added to a macroblock, its format is determined as shown in FIG. That is, in the embodiment of FIG.
Invalid code, stuffing start code and required
Zero code and code for byte alignment
Was to be composed, in the example of FIG. 12, the invalid code is formed only by at least one stuffing start code.

Therefore, in this case, the necessary number of stuffing start codes are added as new invalid codes without byte alignment of data (in FIG. 12, two stuffing start codes are added). .

Next, the operation will be described with reference to the flowchart of FIG. In FIG. 11, FIG.
The stuffing start code shown in FIG. 2 is generated by the stuffing start code generation circuit 24, and the controller 71 controls the multiplexer 72 in accordance with the transmission buffer information supplied from the transmission buffer 7.

That is, first, the data of the macroblock supplied from the N / M converter 21 is output to the transmission path via the multiplexer 72 (step S11), and the controller 71 transmits the transmission buffer information supplied from the transmission buffer 7 to the transmission buffer. It is determined whether or not it is necessary to add a new invalid code to the macroblock data supplied from the N / M converter 21 (step S12). When the controller 71 determines that it is not necessary to add a new invalid code to the data of the macroblock supplied from the N / M converter 21, the process returns to step S <b> 11, and is performed via the N / M converter 21. The macroblock data supplied next from the transmission buffer 7 is output to the transmission path via the multiplexer 72.

On the other hand, in the controller 71, N / M
If it is determined that it is necessary to add a new invalid code to the macroblock data supplied from the converter 21, the multiplexer 72 selects the data supplied from the stuffing start code generation circuit 24. Is switched.

Then, in the controller 71, N /
The macroblock data supplied from the M converter 21
Until it is determined that there is no need to add a new invalid code,
The stuffing start code output from the stuffing start code generation circuit 24 is output to the transmission line via the multiplexer 72 (step S12).
And S13).

Thereafter, N / N
The macroblock data supplied from the M converter 21
If it is determined that it is no longer necessary to add the new invalid code, the process returns to step S11, and the multiplexer 72 is switched so as to select the output of the N / M converter 21, and the data of the next macroblock is transmitted through the transmission path. Is output to

As described above, according to the transmission buffer information from the transmission buffer 7 (information relating to the amount of data stored in the transmission buffer 7), when there is a possibility that the data of the macroblock may underflow, the multiplexer 72 controls the operation. is (here, the new free <br/> effective code consisting only of at least one stuffing start code) new invalid code is output to the transmission path.

FIG. 14 is a block diagram showing the configuration of an embodiment of an invalid code removing circuit 31 for removing an invalid code from transmission data to which an invalid code has been added by the transmission data control circuit 8 shown in FIG. It is. In the figure, portions corresponding to those in FIG. 6 are denoted by the same reference numerals.

The transmitted image data (bit stream) is supplied to an M / 8 converter 51, where the data is converted from data in units of M bits to data in units of 8 bits. M /
The output of the eight converter 51 is supplied to a multiplexer 81 and a decoder 83. The multiplexer 81 selects and outputs one of the output of the M / 8 converter 51 and the output of the register group 82 in bit units based on the mode of the control signal from the decoder 83. The output of the multiplexer 81 is an 8-bit register 82a to 82
After being supplied to a register group 82 composed of 2d and sequentially latched, it is supplied to an 8 / L converter 53, a multiplexer 81 and a decoder 83.

The decoder 83 has an output of the M / 8 converter 51 and an output of the register group 82 (an output of the register 82d), and registers 82a to 82c of the register group 82.
Is supplied. Decoder 83
Detects a stuffing start code from the output of the M / 8 converter 51 and the outputs of the registers 82a to 82d. Upon detecting the stuffing start code, the decoder 83 outputs a control signal in a predetermined mode to the multiplexer 81 and outputs a detection signal to the write control unit 84.

The write control section 84 controls the write state of the 8 / L converter 53 based on the detection signal from the decoder 83. That is, when the write control unit 84 receives the detection signal from the decoder 83,
Writing of the output of the register 82d of the 8 / L converter 53 is prohibited for a time corresponding to 4 bytes as the length of the stuffing start code.

Next, the operation will be described. M / 8
In the converter 51, the input M-bit data is converted into 8-bit (1 byte) data by the M / 8 converter 51, supplied to the register group 82 via the multiplexer 81, The data is sequentially latched at 82a to 82d.

The 8-bit data D from the M / 8 converter 51 and the 8-bit data DA to DD latched by the registers 82a to 82d are supplied to the decoder 83.
Is input to In decoder 83, 8-bit data D from M / 8 converter 51 and register 82a
8-bit data DA to D latched by
From a total of 40 bits of data and D, new invalid shown in FIG. 12
The stuffing start code constituting the code is detected as follows.

That is, the decoder 83 comprises, for example, as shown in FIG. 15, decoding sections 91a to 91h, an encoding section 92, and an OR gate 93. Of the 8-bit data D from the M / 8 converter 51 and the 8-bit data DA to DD latched by the registers 82a to 82d, the decoding unit 91a stores the register 82
The 8-bit data DA to DD latched by a to 82d are input.

Here, hereinafter, 8-bit data D (D
A, DB, DC, and DD) are sequentially converted from MSB to D [7], D [6], D [5], D [4], D
[3], D [2], D [1], and D [0]. Furthermore, bits D [X] to D [X] of 8-bit data D
The data consisting of [X '] is converted to D [X': X] (where X '>
X). Therefore, for example, when representing the data D itself, it is represented as D [7: 0].

In decoding section 91a, register 8
The 8-bit data DA [7: 0] to DD [7: 0] respectively latched in 2a to 82d are converted from the MSB into
DD [7: 0], DC [7: 0], DB [7: 0], D
A 32-bit data (hereinafter, referred to as A [7: 0])
Data $ DD [7: 0], DC [7: 0], DB [7:
0], DA [7: 0]}) and the stuffing start code having 32 bits as one unit shown in FIG.

Then, data $ DD [7: 0], DC
When [7: 0], DB [7: 0], DA [7: 0]} match the stuffing start code, the decoder 91a encodes, for example, the H level among the H and L levels. It is output to the section 92 and the OR gate 93.

The decoding section 91b includes 8-bit data D [7: 0] from the M / 8 converter 51 and 8-bit data DA [7: 0] to DA [7: 0] latched by the registers 82a to 82d. Data [DD [6: 0], DC [7: 0], DB [7: 0],
DA [7: 0], D [7]} are input.

In decoding section 91b, data $ D
D [6: 0], DC [7: 0], DB [7: 0], DA
[7: 0], D [7]} is matched with a stuffing start code having 32 bits as one unit shown in FIG. 12, and data {DD [7: 0], DC [7: 0], D
If B [7: 0], DA [7: 0]} matches the stuffing start code, for example, the H level of the H and L levels is output to the encoding unit 92 and the OR gate 93.

Similarly, in the decoding units 91c to 91h, the data $ DD [5: 0], DC [7: 0], and DB [7:
0], DA [7: 0], D [7: 6], data {DD [4: 0], DC [7: 0], DB [7:
0], DA [7: 0], D [7: 5], data {DD [3: 0], DC [7: 0], DB [7:
0], DA [7: 0], D [7: 4]}, data {DD [2: 0], DC [7: 0], DB [7:
0], DA [7: 0], D [7: 3]}, data {DD [1: 0], DC [7: 0], DB [7:
0], DA [7: 0], D [7: 2]}, or data {DD [0], DC [7: 0], DB [7:
0], DA [7: 0], D [7: 1]} are respectively matched with the stuffing start code having 32 bits as a unit as shown in FIG. Are output to the encoding unit 92 and the OR gate 93, for example.

That is, in the decoding sections 91a to 91h, the five 8/8 signals sequentially output from the M / 8 converter 51 are output.
40-bit data (data $ DD [7: 0], DC [7: 0], DB [7:
0], DA [7: 0], D [7: 0]｝)
A bit string of bits, a bit string of 32 bits from the upper second bit,..., A bit string of 32 bits from the upper 8 bits, and a stuffing start code of 32 bits are respectively matched.

When the outputs of the decoders 91a to 91h are all at the L level, that is, 40 bits composed of five 8-bit data sequentially output from the M / 8 converter 51.
If the stuffing start code is not included in the bit data, the encoder 92 outputs a control signal of mode 0 to the multiplexer 81 (FIG. 14). In this case, in the multiplexer 81, the M / 8 converter 51
Are selected and supplied to the register group 82.

Therefore, if the stuffing start code is not included in the 40-bit data consisting of five 8-bit data sequentially output from the M / 8 converter 51, the output of the M / 8 converter 51 is , A multiplexer 81 and a register group 82, and sequentially output to the 8 / L converter 53.

When the output of decoding section 91a attains an H level, that is, 5 output sequentially from M / 8 converter 51
When the upper 32 bits of the 40-bit data consisting of two 8-bit data are the stuffing start code, the encoder 92 outputs the control signal of mode 0 to the multiplexer 81 and the OR gate 93 outputs the control signal of mode 0. The signal is set to the H level and supplied to the write control unit 84 as a detection signal.

In this case, in the multiplexer 81,
The output of the M / 8 converter 51 is selected and supplied to the register group 82, and the write control unit 84
Writing of the output of the register group 82 of the / L converter 53
The length of the stuffing start code is prohibited by 4 bytes (32 bits).

Therefore, in this case, of the 40-bit data sequentially output from the M / 8 converter 51, the upper 32 bits latched in the registers 82d to 82a in units of 8 bits, ie, the stuffing start code are removed. Will be done.

When the output of the decoding section 91b becomes H level, that is, from the second upper bit of the 40-bit data consisting of five 8-bit data sequentially output from the M / 8 converter 51 When the 32 bits are the stuffing start code, the control signal of mode 1 is output to the multiplexer 81 in the encoder 92, and the output thereof is set to H in the OR gate 93.
Level and supplied to the write control unit 84 as a detection signal.

When the multiplexer 81 receives the control signal of mode 1, first, it receives only the upper 1 bit (the same number of bits as the mode) DD [7] of the data DD [7: 0] latched by the register 82d. Select, then M / 8
The lower 7 bits (the same number of bits as the number obtained by subtracting the mode from 8 bits) D [6: 0] of the data D [7: 0] output from the converter 8 are selected, and a total of 8 bits are selected. The data is supplied to the register 82a.

That is, the data $ DD is stored in the register 82a.
[7], D [6: 0]} are supplied.

At the same time, the write control unit 84
Writing of the output of the register group 82 of the / L converter 53
The length of the stuffing start code is prohibited by 4 bytes (32 bits).

Therefore, in this case, 40-bit data {DD [7: 0], 40 bits sequentially output from the M / 8 converter 51
DC [7: 0], DB [7: 0], DA [7: 0], D
[7: 0]}, upper 32 bits {DD [7: 0], DC latched in registers 82d to 82a
[7: 0], DB [7: 0], DA [7: 0]} are removed, and the data {DD [7], D
[6: 0]} is supplied from the multiplexer 81 to the register 82
output to a.

That is, 40-bit data {DD [7: 0], DC [7:
0], DB [7: 0], DA [7: 0], D [7:
0]}, 32-bit data {DD [6:
0], DC [7: 0], DB [7: 0], DA [7:
0], D [7]} are removed {DD [7], D
[6: 0]} is supplied from the multiplexer 81 to the register 82
a.

Further, when the output of the decoding section 91c becomes H level, that is, from the upper third bit of the 40-bit data consisting of five 8-bit data sequentially output from the M / 8 converter 51, When 32 bits are a stuffing start code, the encoder 92 outputs a control signal of mode 2 to the multiplexer 81, and the OR gate 93 outputs an H-level control signal.
Level and supplied to the write control unit 84 as a detection signal.

When the multiplexer 81 receives the mode 2 control signal, the upper two bits DD [7: 6] of the data DD [7: 0] latched by the register 82d are received.
Is selected, and then the lower 7 bits D [6: 0] of the data D [7: 0] output from the M / 8 converter 8 are selected, and a total of 8 bits of data are supplied to the register 82a. .

That is, the data $ DD is stored in the register 82a.
[7: 6], D [5: 0]} are supplied.

At the same time, the write control unit 84
Writing of the output of the register group 82 of the / L converter 53
The length of the stuffing start code is prohibited by 4 bytes (32 bits).

Therefore, in this case, 40-bit data {DD [7: 0], 40 bits sequentially output from M / 8 converter 51
DC [7: 0], DB [7: 0], DA [7: 0], D
[7: 0]}, upper 32 bits {DD [7: 0], DC latched in registers 82d to 82a
[7: 0], DB [7: 0], DA [7: 0]} are removed, and the data {DD [7: 6], D
[5: 0]} is supplied from the multiplexer 81 to the register 82
output to a.

That is, 40-bit data {DD [7: 0], DC [7:
0], DB [7: 0], DA [7: 0], D [7:
0]}, the 32-bit data {DD [5:
0], DC [7: 0], DB [7: 0], DA [7:
0] and D [7: 6] are removed from the data {DD [7:
6], D [5: 0]} are output from the multiplexer 81 to the register 82a.

In the same manner, the decoding sections 91a to 91-9
When any of the outputs 1h goes to the H level, the data latched in the registers 82a to 82d
Writing to the 8 / L conversion circuit 53 is prohibited, and the input to the multiplexer 81 is selected in units of bits, whereby the 40-bit data sequentially output from the M / 8 converter 51 in units of 8 bits. Stuffing start code is removed.

Note that, in FIG.
The number attached to the left part of the
It indicates the mode of the control signal output when the H level is input from 1a to 91h.

Next, FIG. 16 shows a timing chart when two stuffing start codes as new invalid codes are removed from the transmission data shown in FIG. The data (FIG. 16 (b)) output from the M / 8 converter 51 is supplied to a register group 82 via a multiplexer 81.
The data output from the converter 51 is a clock (FIG. 16)
At the timing of (a)), the data is sequentially latched by the registers 82a to 82d (FIGS. 16C to 16F).

In the case of FIG. 16, the clock T
In FIG. 16 (FIG. 16A), four bits consisting of five 8-bit data sequentially output from the M / 8 converter 51 are used.
0-bit data $ DD [7: 0], DC [7: 0],
From DB [7: 0], DA [7: 0], D [7: 0]}, 32-bit data {DD [0], DC from the upper 8th bit as the first stuffing code
[7: 0], DB [7: 0], DA [7: 0], D
[7: 1]｝ is detected.

Therefore, in this case, the output of the decoding section 91h of the decoder 83 goes high, the control signal of mode 7 is output to the multiplexer 81 in the encoder 92, and the output of the OR gate 93 is high in the OR gate 93. (FIG. 16 (g)), which is supplied to the write controller 84 as a detection signal.

When receiving the control signal of mode 7, the multiplexer 81 first selects only the upper 7 bits DD [7: 1] of the data DD [7: 0] latched by the register 82d (FIG. 16 (i)). ), After supplying the data to the register 82a (portion indicated by the arrow P in the figure), selects the lower 1 bit D [0] of the data D [7: 0] output from the M / 8 converter 8, and The bit data is supplied to the register 82a (the portion indicated by the arrow P 'in the figure).

That is, the register 82a is
The data DD [7: 0] latched at d.
(F)), the valid code (image data) (in the figure,
Upper 7 bits DD [7: 1] as the part indicated by *)
And data D [7: 0] output from M / 8 converter 8
Data {DD [7: 1], D [6]} (FIG. 16 (c)) consisting of the lower 1 bit D [0] of (FIG. 16 (b)) is supplied.

At the same time, the write control unit 84
The output of the register 82d of the / L converter 53 (FIG. 16)
The writing of (f)) is prohibited only for 4 bytes (32 bits) as the length of the stuffing start code, that is, during the clocks T5 to T8 (FIG. 16 (h)).
The first stuffing start code is removed.

During this period (between clocks T5 to T8), the data {DD [7: 1], D
[6] is sequentially latched by the registers 82a to 82c, and is latched by the register 82d at the clock T9.

The clock T9 (FIG. 16)
In (a)), sequentially output from the M / 8 converter 51,
40-bit data $ DD [7: 0], DC [7: 0], DB [7:
0], DA [7: 0], D [7: 0]} from the upper 8 bits as the second stuffing code.
2-bit data $ DD [0], DC [7: 0], DB
[7: 0], DA [7: 0], D [7: 1]} are detected.

Accordingly, in this case, the output of the decoding section 91h of the decoder 83 goes high, the control signal of mode 7 is output to the multiplexer 81 in the encoder 92, and the output of the OR gate 93 is high in the OR gate 93. (FIG. 16 (g)), which is supplied to the write controller 84 as a detection signal.

When receiving the mode 7 control signal, the multiplexer 81 first selects only the upper 7 bits DD [7: 1] of the data DD [7: 0] latched by the register 82d (FIG. 16 (i)). ), After supplying it to the register 82a (indicated by the arrow Q in the figure), selects the lower one bit D [0] of the data D [7: 0] output from the M / 8 converter 8 and selects 8 The bit data is supplied to the register 82a (the portion indicated by the arrow Q 'in the figure).

That is, the register 82a is
The data DD [7: 0] latched at d.
(F)), the valid code (image data) (in the figure,
Upper 7 bits DD [7: 1] as the part indicated by *)
And data D [7: 0] output from M / 8 converter 8
Data {DD [7: 1], D [6]} (FIG. 16 (c)) consisting of the lower 1 bit D [0] of (FIG. 16 (b)) is supplied.

At the same time, the write control unit 84
The output of the register 82d of the / L converter 53 (FIG. 16)
The writing of (f)) is prohibited only for 4 bytes (32 bits) as the length of the stuffing start code, that is, during the clocks T9 to T12 (FIG. 16 (h)).
The second stuffing start code is removed.

During this time (between clocks T9 to T12),
The data $ DD [7: 1] supplied to the register 82a,
D [6]} are sequentially latched by registers 82a to 82c, and latched by register 82d at clock T13.

Then, at this clock T13, 8
The output of the register 82d of the / L converter 53 (FIG. 16)
The write prohibition of (f)) is released, and the register 82d
(FIG. 16 (f)) is written into 8 / L, converted into L-bit data, and supplied to the reception buffer 32.

That is, transmission data from which two stuffing start codes as new invalid data have been removed, ie, encoded image data (clock T1 in FIG. 16 (f)).
3 and the portion indicated by * in T14) are supplied to the reception buffer 32.

As described above, according to the invalid code removing circuit 31 shown in FIG. 14, a new invalid code consisting of at least one stuffing start code can be removed from transmission data that is not byte-aligned.

Further, at least one of the
The removal of the new invalid code consisting of only one stuffing start code is performed by adding the data transmitted in M bits to the K
The conversion can be performed by converting the data into bit units.

In this case, the invalid code removing circuit 31 is configured, for example, as shown in FIG. In FIG. 1, FIG.
The same reference numerals are given to the portions corresponding to the case in FIG.

The M / K converter 104 converts the input transmission data in M bits into data in K bits and outputs the data to the multiplexer 81 and the decoder 102. The register group 101 is composed of P K-bit registers (not shown) serially connected, and delays the output of the multiplexer 81 by P times the clock cycle, and
/ L converter 63, multiplexer 81, and decoder 102.

However, in this case, P is defined by a value obtained by dividing the length (32 bits) of the stuffing start code by K and rounding up the decimal point.

The decoder 102 obtains the output of the M / K converter 104 and the bit string composed of the data latched by each of the P registers constituting the register group 101.
Detects the stuffing start code. When the decoder 102 detects a stuffing start code from a bit string composed of the output of the M / K converter 104 and the output of each of the P registers constituting the register group 101, the decoder 102 outputs a detection signal to the write control unit 103. At the same time, a control signal in a predetermined mode is output to the multiplexer 81.

The write circuit 103 outputs the output of the register group 101 of the K / L converter 63 (P-th register among the registers constituting the register group 101 as the last group register) based on the detection signal from the decoder 102. Control the writing of the register output.

In the invalid code removing circuit 31 configured as described above, first, the M / K converter 104 converts the input transmission data in units of M bits into data in units of K bits. The output of the M / K converter 104 is input to the decoder 102 and also to the register group 101 via the multiplexer 81.

In the register group 101, K-bit data is sequentially latched by P built-in registers.
It is output to the / L converter 63 and the multiplexer 81.

The output of each of the P registers constituting the register group 101 is supplied to the decoder 102 together with the output of the M / K conversion circuit.

In the decoder 102, a stuffing start code is detected from a bit string consisting of the output of the M / K converter 104 and the output of each of the P registers constituting the register group 101. When the stuffing start code is detected in the decoder 102 from the bit string consisting of the output of the M / K converter 104 and the outputs of the P registers constituting the register group 101, the detection signal is written to the write control unit 103.
From the bit string consisting of the output of the M / K converter 104 and the output of each of the P registers constituting the register group 101, detection position information relating to the position at which the stuffing start code is detected. The data latched in each of the P registers are sequentially arranged with the data latched in the register of the final group at the top, and the output of the M / K converter 104 is added to the bottom (P + 1) × K A control signal is output to the multiplexer 81 with a mode number of (the information indicating the higher 32 bits of the bit data, which is the stuffing start code).

In the multiplexer 81, the decoder 102
Based on the mode (mode number) of the control signal from
One of the output of the / K converter 104 and the output of the register group 101 (the output of the P-th register as the last group register among the registers constituting the register group 101) is set in the same manner as in FIG. Are selected in bit units and output to the register group 101.

That is, when the effective code immediately before the stuffing start code is latched in the P-th register among the registers constituting the register group 101, the effective code is replaced with the stuffing start code. Will be moved immediately after

At the same time, when the write circuit 103 receives the detection signal from the decoder 102, the output of the register group 101 of the K / L converter 63 (register group 101
The writing of the output of the P-th register as the register of the last group of the registers constituting the above is prohibited by the length of 4 bytes as the length of the stuffing start code, whereby the stuffing start code is removed.

In the case of K = 1, the stuffing start code and the valid code in the transmission data are latched independently by K bits constituting the register group 101, that is, 1-bit registers. The start code and the valid code have already been separated, so to speak, so that the multiplexer 81 and the signal lines 105 and 106 need not be provided.

In this case, the value of P is a value obtained by dividing the stuffing start code by K and further subtracting 1, that is, 31 in this embodiment.

In the present embodiment, the format of the new invalid code added in units of slices or pictures is the same as the format of the new invalid code added in units of macroblocks.

Therefore, when there is a new invalid code added in units of slices or pictures, the new invalid code is used in the same manner as the new invalid code added in units of macroblocks.
Removed at 1.

[0180]

As described above, according to the image decoding apparatus of the present invention,
According to the invalid code, the synchronization code of the unique pattern
And a stuffing code
Start decryption processing
Invalid code can be easily removed before
The decoding process can be performed efficiently, and the display image is prevented from being interrupted on the way.

[0181]

[0182]

[0183]

According to the image coding apparatus of the present invention, invalid code
Code is a unique pattern of synchronization code and stuffing
Stuffing start code
Therefore, invalid data can be easily removed before starting the decoding process.

[0185]

[0186]

[0187]

[0188]

[0189]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of an image encoding device according to the present invention.

FIG. 2 is a block diagram showing a configuration of one embodiment of a transmission data control circuit 8 of FIG. 1;

FIG. 3 is a diagram illustrating a format of a stuffing start code generated by a stuffing start code generation circuit 24 of FIG. 2;

FIG. 4 is a flowchart illustrating an operation of a controller 26 of FIG. 2;

FIG. 5 is a block diagram illustrating a configuration of an embodiment of an image decoding device according to the present invention.

FIG. 6 is a block diagram showing a configuration of an embodiment of an invalid code removing circuit 31 of FIG. 5;

FIG. 7 is a timing chart for explaining the operation of the embodiment of the invalid code removing circuit 31 of FIG. 6;

8 is a diagram illustrating a write operation of the 8 / L converter 53 of FIG.

FIG. 9 is a block diagram showing a configuration of a second embodiment of the invalid code removing circuit 31 of FIG. 5;

FIG. 10 is a diagram for explaining the operation of the embodiment of the invalid code removing circuit 31 of FIG. 9;

FIG. 11 is a block diagram showing a configuration of a second embodiment of the transmission data control circuit 8 of FIG. 1;

FIG. 12 is a diagram showing transmission data to which a new invalid code has been added by the embodiment of the transmission data control circuit 8 of FIG. 11;

FIG. 13 is a flowchart illustrating an operation of the controller 71 of FIG. 11;

FIG. 14 is a block diagram showing a configuration of a third embodiment of the invalid code removing circuit 31 of FIG. 5;

FIG. 15 is a block diagram showing more details of the decoder 83 of FIG. 14;

FIG. 16 is a timing chart for explaining the operation of the embodiment of the invalid code removing circuit 31 of FIG. 14;

FIG. 17 is a block diagram showing a configuration of a fourth embodiment of the invalid code removing circuit 31 of FIG. 4;

FIG. 18 is a block diagram illustrating a configuration of an example of a conventional image encoding device.

FIG. 19 is a diagram illustrating the structure of image data.

FIG. 20 is a diagram illustrating a format of an invalid code added to a conventional slice.

FIG. 21 is a diagram illustrating the format of a conventional invalid code added to a macroblock.

FIG. 22 is a block diagram illustrating a configuration example of a transmission data control circuit 111 in FIG. 18;

FIG. 23 is a block diagram illustrating a configuration of an example of a conventional image decoding device.

[Explanation of symbols]

Reference Signs List 8 transmission data control circuit 21 N / M converter 22 multiplexer 23 adjustment data generation circuit 24 stuffing start code generation circuit 25 multiplexer 26 controller 31 invalid code removal circuit 51 M / 8 converter 52 register 53 8 / L converter 54 zero detection Circuit 55 Counter 56 Write control unit 71 Controller 72, 81 Multiplexer 82 Register group 83 Decoder 84 Write control unit 91a to 91h Decode unit 92 Encode unit

Claims (6)

(57) [Claims] 1. A storage means for temporarily storing transmitted compressed image data, and reads compressed image data stored in said storage means in accordance with the progress of decoding processing, and is equal to a frame period of an image. Or decoding means for decoding one frame of image data within a shorter time, and preventing loss of data from the transmitted compressed image data.
And <br/> removal means for outputting the added by removing the invalid code to stop, the compressed image data output from said removing means, Bei example and a supply means for supplying to said memory means, said Invalid code is a unique pattern synchronization code and scan
Staffing start consisting of tough code
Image decoding apparatus characterized by configured to include a code. 2. The method according to claim 1, wherein the removing unit detects writing of the compressed image data having a logic value of 0, and a writing unit that writes the compressed image data.
Detection signal when detecting the compressed image data having a logical value of 0
Detecting means for outputting the detection signal, and counting a detection signal output from the detecting means.
Counting means for outputting a count value, in accordance with the count value output from said counting means,
Writing the compressed image data by the writing means
Control means for controlling the count value output from the count means to a predetermined value.
When the writing means is turned on,
The writing of the compressed image data
Removing the invalid code from the compressed image data
2. The image decoding apparatus according to claim 1, wherein: 3. The invalidation code includes one stuffing start code having a logic 0 value.
Characterized by the addition of additional adjustment data
The image decoding device according to claim 1. 4. The method according to claim 1, wherein the invalid code is at least one of the stuffing start codes.
2. The image restoration method according to item 1,
Encryption device. 5. The compressed image data includes a macroblock image.
The compression code is compression-coded in lock units, and the synchronization code is composed of 2 bits in which all bits are logical 0.
Byte data, LSD is logic 1 and other bits are
A total of 3 bytes with 1-byte data of logic 0
The stuffing code is composed of data of the macroblock.
Data attribute.
The image decoding device according to claim 1. 6. A dividing means for dividing one frame of image data into slices composed of a predetermined number of lines, and dividing the slices into a predetermined number of macroblocks for compression encoding, and the image data is insufficient. The data of the macro block to prevent data loss.
In <br/> image encoding device and an adding means for adding an invalid code to stop, the invalid code, the synchronization code and scan of the unique pattern
Staffing start consisting of tough code
Image coding apparatus characterized by configured to include a code.