JP3232343B2 - Horizontal MOS field-effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to SOI (Silicon On I
The present invention relates to a high-voltage, large-current-capacity, lateral MOS field-effect transistor formed on a substrate.

[0002]

2. Description of the Related Art FIG. 10 is a cross-sectional view of a conventional lateral MOS field effect transistor formed on an SOI substrate. FIG. 11 is a lateral MOS field effect transistor obtained by applying a trench isolation technique to this transistor to perform cell isolation. It is a birdcage figure of. In FIG. 10, 1 is 400 to 700 in thickness.
μm single crystal silicon, polysilicon, diamond,
A substrate made of silicon carbide or aluminum nitride; and 2, silicon oxide, silicon nitride, SiON, calcium fluoride, alumina having a thickness of 0.05 to 4 μm;
Or, a buried insulating layer made of tantalum pentoxide and 3 are n ⁺
A source region 4 of n-type silicon; a drain region 5 of n ⁺ -type silicon; a channel region 5 of p-type silicon; and an offset gate region 6 of n ^-- type silicon.

Further, 7 is a gate insulating film made of silicon oxide, SiON or tantalum pentoxide having a thickness of 30 to 100 nm, 8 is a source electrode made of aluminum or copper having a thickness of 0.5 to 2 μm, and 9 is a source electrode. A drain electrode made of aluminum or copper having a thickness of 0.5 to 2 μm, a gate electrode made of polysilicon, molybdenum, tungsten, titanium silicide, or tantalum silicide having a thickness of about 0.5 μm; An interlayer insulating film made of silicon oxide, PSG, BPSG, or silicon nitride having a thickness of about 1 μm, and a gate wiring 12 made of aluminum or copper having a thickness of 0.5 to 2 μm.

Reference numeral 13 denotes a semiconductor active region comprising a source region 3, a drain region 4, a channel region 5, and an offset gate region 6, and has a thickness of 0.1 to 1 μm.
And desirably 0.3 μm or less. In FIG.
Reference numeral 14 denotes an isolation region made of silicon oxide or the like. In addition,
In FIG. 11, for convenience, the source electrode 8, the drain electrode 9, the interlayer insulating film 11, and the gate wiring 12 are not shown, and only one side of the isolation region 14 is shown.

In the conventional lateral MOS field effect transistor shown in FIGS. 10 and 11, the RESURF (reduced surface field) effect is used to obtain a high drain breakdown voltage. The RESURF effect was initially applied to bulk substrate lateral devices (HMJVaes and JAAppel
s, "High Voltage, High Current Lateral Devices", inIE
DM Technical Digest, 1980, pp. 87-90) and then SO
Similar effects have been confirmed for lateral devices with I-substrate (W. Wondrak, R. Held, E. Stein and J. Korec, "A New Ci
ncept for High-Voltage SOI Devices ", in Proceeding
of ISPED, 1992, pp. 278-281).

[0006] The RESURF condition, which is a condition for realizing the RESURF effect, is a relation that the product of the impurity concentration Noff of the offset gate region 6 and the thickness t of the semiconductor active region 13 becomes a constant value P as shown in the following equation. Given by Noff × t = P (1) This constant value P depends on the thickness of the buried insulating layer 2. When the drain voltage is increased while the lateral MOS field-effect transistor satisfies the RESURF condition, the space charge in the offset gate region 6 due to the depletion layer extending from the buried insulating layer 2 side into the semiconductor active region 13 becomes: It acts to make the electric field in the offset gate region 6 uniform, and a maximum drain breakdown voltage is obtained.

When the product of Noff and t is larger than the RESURF condition, the depletion layer extending to the offset gate region 6 becomes small, a high electric field is applied to the pn junction between the channel region 5 and the offset gate region 6, and the drain breakdown voltage is increased. Becomes lower than the maximum drain withstand voltage obtained under the RESURF condition. Conversely, the product of Noff and t is RESURF
When the value is smaller than the condition, the depletion layer extending to the offset gate region 6 increases, and a high electric field is applied to the nn ⁺ junction between the offset gate region 6 and the drain region 4,
The drain withstand voltage is lower than the maximum drain withstand voltage obtained under the RESURF condition.

FIG. 12 is a diagram showing a three-dimensional potential distribution of the lateral MOS field effect transistor of FIG. 11 in an off state. For simplification, a pn junction diode is used in place of the transistor, and this pn junction diode is reverse-biased. It is the simulation result which calculated | required the electric potential distribution by the three-dimensional device simulation in the state. x, y,
z indicates the coordinate direction, and the number indicates the distance from the origin (0) in each direction. Further, the upper surface of FIG.
The grid in the xy plane of 0.5 μm indicates that the semiconductor active region 13 is provided.
The coordinates are in the range of 1.3 to 10.7 μm, and the Z coordinate is in the range of −0.5 to 0 μm.

In this region 13, the x coordinate 0 to 1 μm is a channel region 5 (p-type cathode region of a pn junction diode), and 1 to 11 μm is an offset gate region 6.
(N-type anode region), and 11 to 12 μm is a drain region 4 (n ⁺ -type anode region). Also, y
The area of coordinates 0 to 1.3 μm and 10.7 to 12 μm is the separation area 14, and the Z coordinate of 0 to 1 μm corresponds to the embedded insulating layer 2.
It is. Then, in such a pn junction diode, the cathode region at the x coordinate 0 is grounded, and the x coordinate 12 μm
100V was applied to the anode region of No. 3 to bring it into a reverse bias state.

FIG. 13 is a diagram showing a two-dimensional potential distribution on the bottom surface of the semiconductor active region 13 in FIG. 12, that is, an xy plane at Z coordinate 0, and FIG. 14 is a diagram showing an electric field intensity distribution on this bottom surface, which is A-AA. The line indicates the center of the cell (semiconductor active region 13), and the line B-BB indicates the outer edge of the region 13 where the semiconductor active region 13 and the isolation region 14 are in contact. As is clear from FIG. 13, in the outer edge portion B-BB, the equipotential lines are concentrated on the drain region 4 side (x coordinate 12 μm side). Further, from FIG. 14, the peak value of the electric field intensity on the drain region 4 side is 2.6 × 1 in the cell central portion A-AA.
0 ⁵ V / cm, whereas the outer edge B-BB is 3.
8 × 10 ⁵ V / cm, which is nearly 50% higher. Therefore, RE
The withstand voltage of the cell central portion A-AA where the SURF effect works effectively does not become the withstand voltage of the element, and the outer edge portion B having a higher electric field strength
The breakdown voltage of -BB governs the drain breakdown voltage of the element.

Further, LOCOS is used instead of the trench isolation.
When the (LOCal Oxidation of Silicon) isolation technique is used, the cross-sectional shape of the semiconductor active region 13 in the y direction becomes a trapezoid as shown in FIG. For this reason, the formula (1)
In the case where the impurity concentration Noff is constant, the product of Noff and t becomes smaller toward the tip of the outer edge portion, and the equipotential lines become the offset gate region 6 and the drain region 4 according to the principle described above. Concentrate on the nn ⁺ junction between
The peak value of the electric field intensity increases and the drain breakdown voltage decreases.

[0012]

In a lateral MOS field effect transistor formed on an SOI substrate by trench isolation or LOCOS isolation, the RE is formed at the center of the semiconductor active region.
When the impurity concentration of the offset gate region is set so as to satisfy the SURF condition, a high electric field is generated at the nn ⁺ junction between the offset gate region and the drain region, and the drain breakdown voltage of the element is reduced. there were. An object of the present invention is to obtain a high drain breakdown voltage by suppressing a high electric field generated at a junction between an offset gate region and a drain region in a lateral MOS field effect transistor formed on an SOI substrate.

[0013]

According to the present invention, an offset gate region includes a first offset gate region formed between a channel region and a drain region, and a drain region integrated with the first offset gate region. It comprises a second offset gate region formed between the lateral outer edge and the field region. The first offset gate region is formed such that the width in the direction perpendicular to the lateral direction is larger on the drain region side than on the channel region side, and the second offset gate region is formed on the drain region side with the first offset gate region. It is connected to the gate region.

[0014]

According to the present invention, the intensity of the electric field generated between the offset gate region and the drain region is reduced by forming the second offset gate region between the lateral outer edge of the drain region and the field region. Can be done. Further, the first offset gate region is formed such that the width in the direction perpendicular to the horizontal direction is larger on the drain region side than on the channel region side.

[0015]

FIG. 1 is a perspective view of a lateral MOS field effect transistor showing one embodiment of the present invention, and the same parts as those in FIG. 11 are denoted by the same reference numerals. Reference numeral 6a denotes a first offset gate region similar to the offset gate region 6 in FIG. 11, and 13a denotes a semiconductor active region including a source region 3, a channel region 5, an offset gate region 6a, a drain region 4, and a second offset gate region described later. A region 16 is a second offset gate region formed integrally with the first offset gate region 6a and between the drain region 4 and the isolation region 14 which is a field region.

In FIG. 1, for convenience, the source electrode, the drain electrode, the interlayer insulating film, and the gate wiring are not shown, and the isolation region 14 is shown only on one side. This lateral MOS field-effect transistor is substantially the same as the transistor of FIG. 11, except that an offset gate region 16 is provided between the outer edge of the drain region 4 in the x direction and the isolation region 14.
Was formed. Y of the second offset gate region 16
The width in the direction is 2 μm.

FIG. 2 is a diagram showing a three-dimensional potential distribution in the off state of the lateral MOS field effect transistor. FIG. 3 is a bottom view of the semiconductor active region 13a of FIG.
FIG. 4 shows a two-dimensional potential distribution on the xy plane of FIG. 2 to 4 are simulation results obtained in the same manner as in FIGS.

The device structure simulated in FIG. 2 is almost the same as the example in FIG. 12, except that the first offset gate region 6a has x
The second offset gate region 16 is provided at coordinates 1 to 11 μm and the y coordinate 1.3 to 10.7 μm, and is provided on the near side, that is, on the y coordinate 0 side. Also, the y coordinate 12μ
The m side has the same configuration as the example in FIG.

That is, the second offset gate region 16
Are x-coordinates 11 to 12 μm, y-coordinates 1.3 to 3.3 μm
It will be in the range of. As a result, in FIG. 3, the second offset gate region 16 is on the lower side, and B-BB is on the upper side.
As is clear from the line, the structure of the conventional example shown in FIG. 12 is obtained.

The C-CC line in FIG. 3 indicates the lateral outer edge of the drain region 4, and the D-DD line indicates the region 1 where the semiconductor active region 13a of this embodiment is in contact with the isolation region 14.
3a (here, the outer edge portion of the channel region 5, the first and second offset gate regions 6a and 16) is shown. A comparison between the outer edges C-CC and D-DD of the present embodiment and the outer edges B-BB of the conventional structure on the drain region 4 side (x-coordinate 12 μm side) in FIG. 3 shows that the outer edges C-CC and D It can be seen that the concentration of equipotential lines is reduced in -DD.

FIG. 4 shows that the peak value of the electric field intensity on the drain region 4 side is the central portion AA of the conventional structure.
A, the outer edge portions B-BB are the same as in the example of FIG. 14, and are 2.6 × 10 ⁵ V / cm and 3.8 × 10 ⁵ V / c, respectively.
m. On the other hand, the peak value of the electric field intensity at the outer edge portion C-CC of the present embodiment is 2.8 × 10 ⁵ V / cm, which is reduced to 75% of the outer edge portion B-BB of the conventional structure, It is almost equivalent to A-AA. As described above, the configuration of FIG. 1 can reduce the intensity of the electric field generated in the offset gate region on the drain region 4 side.

FIG. 5 is a horizontal MO showing another embodiment of the present invention.
FIG. 2 is a bird's-eye view of the S field effect transistor, and the same parts as those in FIG. 1 are denoted by the same reference numerals. Reference numeral 6b denotes a first offset gate region formed so that the width in the y direction on the drain region 4 side is larger than that on the channel region 5 side.
“b” is a semiconductor active region including the source region 3, the channel region 5, the offset gate region 6b, the drain region 4, and the second offset gate region 16.

In the example shown in FIG. 1, the second offset gate region 16 is provided so as to extend the first offset gate region 6a between the drain region 4 and the isolation region 14. However, the cell area is limited. In some cases, the result is that the width of the drain region 4 in the y direction is reduced, and this may be disadvantageous when it is desired to increase the area of the drain region 4 due to restrictions such as current capacity.

Therefore, in the direction perpendicular to the above-mentioned lateral direction,
That is, the first offset gate region 6b is formed such that the width in the y direction is larger on the drain region 4 side than on the channel region 5 side. Thereby, the second offset gate region 16 has a structure that is connected to the portion where the width of the first offset gate region 6b is increased.

FIG. 6 is a diagram showing a three-dimensional potential distribution in the off state of the lateral MOS field-effect transistor as in FIG. 2, and FIG. 7 is a diagram showing a two-dimensional potential distribution on the bottom surface of the semiconductor active region 13b in FIG. FIG. 8 is a diagram showing the electric field intensity distribution on the bottom surface. The device structure simulated in FIG. 6 is almost the same as the example in FIG.
a is provided in the range of x coordinate 1 to 9 μm, y coordinate 3.3 to 10.7 μm, x coordinate 9 to 11 μm, y coordinate 1.3 to 10.7 μm, and the second offset gate region 16
Are provided at the same positions as in the example of FIG.

Therefore, FIG. 7 also has the second offset gate region 16 on the lower side, and the upper side has the structure of the conventional example of FIG. In addition, the E-EE line in FIG. 7 indicates the lateral outer edge of the drain region 4, and the F-FF line corresponds to the offset gate region 16 (or the portion where the width of the offset gate region 6b is increased) of the present embodiment. The outer edge of the semiconductor active region 13b in contact with the isolation region 14 is shown.

On the drain region 4 side in FIG. 7, the outer edges E-EE and F-FF of this embodiment and the outer edges BB of the conventional structure are used.
Comparing with B, it can be seen that the concentration of equipotential lines is reduced in the outer edge portions E-EE and F-FF. And FIG.
Accordingly, the peak value of the electric field intensity on the drain region 4 side is the same as that of the example of FIG. 4 for the central portion A-AA and the outer edge portion B-BB of the conventional structure. On the other hand, the peak value of the electric field intensity at the outer edge E-EE of the present embodiment is 3.0 × 10 ⁵ V
/ Cm, which is reduced to 80% of the outer edge portion B-BB of the conventional structure, and almost the same effect as the example of FIG. 1 can be obtained.

If the distance between the drain region 4 and the isolation region 14 is too small, no effect is obtained, and if it is too large, the cell area becomes large. In the examples of FIGS. 1 and 5, the width of the second offset gate region 16 in the y direction is set to 2 μm. However, it is necessary to appropriately set the width in accordance with the structural parameters of the element and the drain breakdown voltage. Although the example of the N-channel MOS has been described in the examples of FIGS. 1 and 5, an effect can be obtained with a similar configuration for the P-channel MOS.

In the examples of FIGS. 1 and 5, the separation region 14 is shown on only one side. However, when the entire upper surface is viewed from above, it is as shown in FIGS. 9A and 9B, respectively. As described above, in one example of FIGS. 1 and 5, one direction of the drain region 4 is in direct contact with the isolation region 14, but as shown in FIGS. It may be surrounded by a region.

[0030]

According to the present invention, the intensity of the electric field generated in the offset gate region on the drain region side is formed by forming the second offset gate region between the lateral outer edge of the drain region and the field region. Can be reduced, and a higher drain breakdown voltage can be realized as compared with the conventional structure. In addition, by forming the first offset gate region to have a larger width on the drain region side than on the channel region side, a high drain withstand voltage can be realized similarly, and the area of the drain region can be increased. Can be.

[Brief description of the drawings]

FIG. 1 is a perspective view of a lateral MOS field-effect transistor showing one embodiment of the present invention.

FIG. 2 is a diagram showing a three-dimensional potential distribution in an off state of the lateral MOS field-effect transistor of FIG.

FIG. 3 is a diagram showing a two-dimensional potential distribution on the bottom surface of the semiconductor active region in FIG. 1;

FIG. 4 is a diagram showing an electric field intensity distribution on the bottom surface of the semiconductor active region in FIG. 1;

FIG. 5 is a bird's-eye view of a lateral MOS field-effect transistor showing another embodiment of the present invention.

6 is a diagram showing a three-dimensional potential distribution in an off state of the lateral MOS field effect transistor of FIG.

FIG. 7 is a diagram showing a two-dimensional potential distribution on the bottom surface of the semiconductor active region in FIG. 5;

8 is a diagram showing an electric field intensity distribution on the bottom surface of the semiconductor active region in FIG. 5;

FIG. 9 is a plan view of a lateral MOS field-effect transistor showing another embodiment of the present invention.

FIG. 10 is a cross-sectional view of a conventional lateral MOS field-effect transistor.

FIG. 11 is a bird's-eye view of a conventional lateral MOS field-effect transistor in which cell isolation is performed by applying a trench isolation technique.

12 is a diagram showing a three-dimensional potential distribution in an off state of the lateral MOS field-effect transistor of FIG.

FIG. 13 is a diagram showing a two-dimensional potential distribution on the bottom surface of the semiconductor active region.

FIG. 14 is a diagram showing an electric field intensity distribution on the bottom surface of the semiconductor active region.

FIG. 15 is a bird's-eye view of a conventional lateral MOS field-effect transistor in which inter-cell isolation is performed by applying the LOCOS isolation technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... substrate, 2 ... buried insulating layer, 3 ... source region, 4 ...
Drain region, 5 channel region, 6a, 6b first offset gate region, 7 gate insulating film, 10 gate electrode, 13 semiconductor active region, 14 isolation region, 16
... Second offset gate region.

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kim Itsunaka 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Toshiaki Yachi 1-16-1 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Takao Fuman Mitsui 1-6-1 Uchisaiwai-cho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Akihiko Sugai 10-13 Minamimachi, Hanno City, Saitama Prefecture Shindengen Industrial Co., Ltd. (72) Inventor Tengo Echigoya 10-13 Minamicho, Hanno-shi, Saitama Shindengen Kogyo Co., Ltd. (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 29 / 786 H01L 21/336

Claims (2)

(57) [Claims] 1. A semiconductor active region in which a source region, a channel region in contact with the source region, an offset gate region in contact with the channel region, a drain region in contact with the offset gate region are arranged in a lateral direction, and each semiconductor active region is In a lateral MOS field-effect transistor in which a field region for isolation is formed on an insulating layer of a substrate, the offset gate region includes a first offset gate region formed between the channel region and a drain region. And a second offset gate region formed integrally with the first offset gate region between the lateral outer edge of the drain region and the field region. . 2. The lateral MOS field-effect transistor according to claim 1, wherein the first offset gate region is formed such that a width in a direction perpendicular to the lateral direction is larger on a drain region side than on a channel region side. The lateral MOS field effect transistor, wherein the second offset gate region is connected to the first offset gate region on the drain region side.