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JP3226251B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP3226251B2
JP3226251B2 JP14158195A JP14158195A JP3226251B2 JP 3226251 B2 JP3226251 B2 JP 3226251B2 JP 14158195 A JP14158195 A JP 14158195A JP 14158195 A JP14158195 A JP 14158195A JP 3226251 B2 JP3226251 B2 JP 3226251B2
Authority
JP
Japan
Prior art keywords
film
heat treatment
insulating film
layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP14158195A
Other languages
Japanese (ja)
Other versions
JPH08335577A (en
Inventor
幹夫 若宮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP14158195A priority Critical patent/JP3226251B2/en
Publication of JPH08335577A publication Critical patent/JPH08335577A/en
Application granted granted Critical
Publication of JP3226251B2 publication Critical patent/JP3226251B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関するもので、特に有機系ソースガスを用いて形成し
た層間絶縁膜の膜質の安定化に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for stabilizing the quality of an interlayer insulating film formed using an organic source gas.

【0002】[0002]

【従来の技術】半導体装置の高集積化に伴い、微細デバ
イスの多層化は必然の傾向となっているが、それを進め
るには、多くの問題を解決しなければならない。その一
つが、層間絶縁膜の膜質改善であり、本件のPSG(Phosph
o-Silicate Glass) 膜又はBPSG( ボロンを添加したPSG)
膜に混入した有機物の除去にあたる。
2. Description of the Related Art With the increase in the degree of integration of semiconductor devices, multilayering of fine devices has become an inevitable trend, but many problems must be solved in order to proceed. One of them is to improve the film quality of the interlayer insulating film, and the PSG (Phosph
o-Silicate Glass) Film or BPSG (PSG with boron)
This is to remove organic substances mixed in the film.

【0003】なぜなら、現段階で主流となっている成膜
方法、有機系ガスをソースガスに使用したCVD 法では、
有機系ガス中の有機物の一部が分解されずに電荷を帯び
た状態で、形成中の膜に混入していたからである。この
ため、最終的に形成された半導体装置に電圧をかけた
際、この有機物がキャリアとして働き、電気的特性を低
下させていた。そこで従来は、(1)N2 雰囲気、又は(2)O
2 雰囲気で熱処理を行い、膜中の有機物を除去してい
た。
[0003] In the current mainstream of the film forming method, the CVD method using an organic gas as a source gas,
This is because a part of the organic substance in the organic gas was charged into the film being formed without being decomposed, and was mixed into the film being formed. For this reason, when a voltage is applied to the finally formed semiconductor device, the organic substance functions as a carrier, and the electrical characteristics are reduced. Therefore, conventionally, (1) N 2 atmosphere or (2) O
Heat treatment was performed in two atmospheres to remove organic substances in the film.

【0004】[0004]

【発明が解決しようとする課題】上述したように、BPSG
膜又はPSG 膜中の有機物を除去するにあたり、 (1) 従来の N2 雰囲気で熱処理を行う方法では、膜中の
有機物を除去するために、約900 ℃で30分程度の高温、
長時間の熱処理が必要であるが、不純物を導入した層を
有する半導体装置に適応した場合、不純物の拡散が進み
所望の電気的特性が得られなくなる問題を有していた。
特にShallow Junction 構造の半導体装置においては、
リーク電流を生じる深刻な問題となっていた。
As described above, BPSG
In removing organic substances in the film or PSG film, (1) In the conventional method of performing heat treatment in an N 2 atmosphere, in order to remove organic substances in the film, a high temperature of about 900 ° C. for about 30 minutes,
Although a long heat treatment is required, when applied to a semiconductor device having a layer into which an impurity is introduced, there is a problem that diffusion of the impurity progresses and desired electrical characteristics cannot be obtained.
Particularly in a semiconductor device having a Shallow Junction structure,
This is a serious problem that causes leakage current.

【0005】(2)O2 雰囲気(或は酸化性雰囲気)で熱
処理を行う方法では、膜中の有機物を除去するために、
約800 ℃で20分程度の熱処理が必要であるが、膜下に配
線層を有する半導体装置に適用した場合、配線層が酸化
されることから配線が細り抵抗が高くなる問題を有して
いた。
(2) In the method of performing heat treatment in an O 2 atmosphere (or an oxidizing atmosphere), in order to remove organic substances in a film,
A heat treatment of about 800 ° C. for about 20 minutes is required, but when applied to a semiconductor device having a wiring layer below the film, the wiring layer is oxidized, so that the wiring becomes thin and the resistance becomes high. .

【0006】そこで、本発明は、上記問題を解決し、最
終的に形成される半導体装置の電気的特性に悪影響を与
えずに、BPSG膜又はPSG 膜中の有機物を除去する事を目
的とする。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above problems and to remove organic substances in a BPSG film or a PSG film without adversely affecting the electrical characteristics of a finally formed semiconductor device. .

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体装置の製造方法では、半導体基板上
に有機系ソースガスを用いて絶縁膜を堆積する工程と、
前記絶縁膜を堆積した後、酸素分圧200 乃至400Torr 下
で熱処理を行なう工程とを具備することを特徴とする。
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: depositing an insulating film on a semiconductor substrate using an organic source gas;
Performing a heat treatment under an oxygen partial pressure of 200 to 400 Torr after depositing the insulating film.

【0008】尚、上記熱処理を400 ℃以上で行なうこと
を特徴とする。尚、上記熱処理時の雰囲気が、不活性ガ
スにより稀釈した酸化性雰囲気であることを特徴とす
る。
[0008] It is characterized in that the heat treatment is performed at 400 ° C or higher. Note that the atmosphere during the heat treatment is an oxidizing atmosphere diluted with an inert gas.

【0009】尚、上記有機系ソースガスは、テトラエト
キシシラン(TEOS;Si(C 2H 5 O) 4)、トリメチルボレ
ート(TMB ;B(CH3 ) 3 )、トリメチルフォスフェート
(TMP;PO(CH 3 O)3 ) のいずれかであることを特徴とす
る。尚、上記絶縁膜の下に、前記絶縁膜と接して素子分
離領域又は配線が存在する事を特徴とする。
The organic source gas is tetraethoxysilane (TEOS; Si (C 2 H 5 O) 4 ), trimethyl borate (TMB; B (CH 3 ) 3 ), trimethyl phosphate
(TMP; PO (CH 3 O) 3 ). Note that an element isolation region or a wiring is present below the insulating film in contact with the insulating film.

【0010】[0010]

【作用】有機ソースガスを用いて絶縁膜を形成した後、
760Torr 未満の酸素分圧で熱処理を行なう。この熱処理
をおこなうことにより、酸素分子が絶縁膜に侵入し、膜
中の有機物を二酸化炭素・水など揮発性物質に変化させ
て、絶縁膜中の有機物を除去すると考えられる。
After forming an insulating film using an organic source gas,
Heat treatment is performed at an oxygen partial pressure of less than 760 Torr. It is considered that by performing this heat treatment, oxygen molecules penetrate into the insulating film, convert organic substances in the film into volatile substances such as carbon dioxide and water, and remove organic substances in the insulating film.

【0011】さらに、絶縁膜の晒されている雰囲気は、
酸素分子数が少なく、熱処理により絶縁膜に侵入する酸
素分子数は、有機物の除去に最低限必要な分子数とな
る。このため、絶縁膜中または絶縁膜が覆った他の層の
構成分子と結合することなく、効率良く絶縁膜中の有機
物を除去を行なえる。
Further, the atmosphere to which the insulating film is exposed is:
The number of oxygen molecules is small, and the number of oxygen molecules that enter the insulating film by heat treatment is the minimum number of molecules necessary for removing organic substances. Therefore, organic substances in the insulating film can be efficiently removed without binding to constituent molecules in the insulating film or other layers covered by the insulating film.

【0012】[0012]

【実施例】以下、DRAMを例に、図面を参照して本発明の
半導体装置の製造方法を説明する。 P 型のSi基板1 上
にLOCOS 工程より素子分離領域を形成した後、所定位置
に熱酸化法によりゲート酸化膜2 を形成し、キャパシタ
部分に不純物を注入しSi基板表面にN 型層3 を作る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings, taking a DRAM as an example. After forming an element isolation region by a LOCOS process on a P-type Si substrate 1, a gate oxide film 2 is formed at a predetermined position by a thermal oxidation method, impurities are implanted into a capacitor portion, and an N-type layer 3 is formed on the surface of the Si substrate. create.

【0013】次に、全面に第一の多結晶Si層4aを形成
し、POCl3 拡散によってP を導入しN型化させた後パタ
ーニングしゲート電極を形成する。ここで第一の多結晶
Si層4aが除去された部分のゲート酸化膜2 は第一の多結
晶Si層4aのエッチングの際に損傷を受けているため、こ
のゲート酸化膜2 を除去し、Si層表面を露出させる。
Next, a first polycrystalline Si layer 4a is formed on the entire surface, P is introduced by POCl3 diffusion to make it N-type, and then patterned to form a gate electrode. Where the first polycrystalline
Since the portion of the gate oxide film 2 from which the Si layer 4a has been removed is damaged during the etching of the first polycrystalline Si layer 4a, the gate oxide film 2 is removed and the surface of the Si layer is exposed.

【0014】次に、Si層表面の露出した部分にセレクト
トランジスタ用のゲート酸化膜2 を成長させる。そし
て、これまでの工程を繰り返す(必要な部分にイオン注
入した後、第二の多結晶Si層4bを堆積させPOCl3 拡散し
た後、パターニングしゲート電極を形成する)。続い
て、層間絶縁膜としてBPSG膜5 をTEOS((C 2 H 5 O)4 S
i) 、ホスフィン(PH 3 ) 、TMB (B(CH3 ) 3 )、及びO
2 を使用したLP-CVD法によって、400nm 程度形成す
る。この時、ドーパントの濃度は[P]=7wt%、[B]=4wt%と
する。
Next, a gate oxide film 2 for a select transistor is grown on the exposed portion of the surface of the Si layer. Then, the steps up to this point are repeated (after ion implantation into necessary portions, the second polycrystalline Si layer 4b is deposited, POCl3 diffused, and then patterned to form a gate electrode). Subsequently, the BPSG film 5 was applied as an interlayer insulating film to TEOS ((C 2 H 5 O) 4 S
i), phosphine (PH 3 ), TMB (B (CH 3 ) 3 ), and O
2 is formed to a thickness of about 400 nm by the LP-CVD method. At this time, the concentration of the dopant is [P] = 7 wt% and [B] = 4 wt%.

【0015】次に、 O2 分圧300Torr 雰囲気中で、約80
0 ℃、20分間の熱処理を行なう( 図1 図示) 。図3に、
上述した半導体装置に酸化性雰囲気中で800 ℃、20分の
熱処理を行なった場合、その O2 分圧とBPSG膜5 中に残
留している炭素量、及び、BPSG膜5 下の多結晶Si層電極
上に形成された酸化膜厚との関係を示した。
Next, in an atmosphere of O 2 partial pressure of 300 Torr, about 80
A heat treatment is performed at 0 ° C. for 20 minutes (see FIG. 1). In FIG.
When the above-described semiconductor device is subjected to a heat treatment at 800 ° C. for 20 minutes in an oxidizing atmosphere, its O 2 partial pressure, the amount of carbon remaining in the BPSG film 5, and the polycrystalline Si under the BPSG film 5 The relationship with the oxide film thickness formed on the layer electrode was shown.

【0016】これまでの研究より、所望のデバイス特性
を得るためには絶縁膜中の電荷を帯びた有機物量は1021
atoms /cm3 程度まで低減させる必要があることがわか
っている。この点から図3を見ると、 O2 分圧は200Tor
r 以上が好ましい。さらに、O2 分圧を200Torr 以上に
上げても絶縁膜中の炭素量は大きく変化しない、すなわ
ち炭素除去の効率は変化しないことがわかる。
According to previous studies, in order to obtain desired device characteristics, the amount of charged organic substances in the insulating film must be 10 21
It is known that it is necessary to reduce to about atoms / cm 3 . Looking at Figure 3 from this point, the O 2 partial pressure is 200 Tor
r or more is preferable. Further, it can be seen that even if the O2 partial pressure is increased to 200 Torr or more, the amount of carbon in the insulating film does not change significantly, that is, the efficiency of carbon removal does not change.

【0017】次に、多結晶Si電極層における酸化量をみ
ると、 O2 分圧が高くなる程その酸化量が増加し、 O2
分圧200Torr 以下で多結晶Si電極層における酸化量の変
化が少なくなってきていることがわかる。
Next, looking at the oxidation amount in the polycrystalline Si electrode layer, the oxidation amount increases as the O 2 partial pressure increases, and the O 2 partial pressure increases.
It can be seen that at a partial pressure of 200 Torr or less, the change in the amount of oxidation in the polycrystalline Si electrode layer is reduced.

【0018】この二点から、 O2 分圧の最適値は200 乃
至400Torr 、好ましくは400Torr であることがわかる。
従って、上述したような O2 分圧300Torr 雰囲気中の熱
処理により、BPSG膜5下の電極の酸化量を最少に留め、
且つ絶縁膜中の炭素を除去し、このDRAMにおけるデバイ
ス特性の信頼性を向上することができる。
From these two points, it can be seen that the optimum value of the O 2 partial pressure is 200 to 400 Torr, preferably 400 Torr.
Therefore, the heat treatment in the O 2 partial pressure 300 Torr atmosphere as described above minimizes the oxidation amount of the electrode under the BPSG film 5,
In addition, carbon in the insulating film is removed, and the reliability of device characteristics in the DRAM can be improved.

【0019】そして、ビットライン用のコンタクトホー
ル6を開口した後、順に第三の多結晶Si層4c、金属シリ
サイド層7 を形成し、熱処理を行なう。次いで、第三の
多結晶Si層4c、金属シリサイド層7 をパターニングして
ビット線の配線とする。さらに、全面に上述したのと同
様に層間絶縁膜としてBPSG膜5 を形成し、 O2 分圧300T
orr 雰囲気中で、約800 ℃、20分間の熱処理を行なう。
After opening the contact hole 6 for the bit line, a third polycrystalline Si layer 4c and a metal silicide layer 7 are formed in this order, and a heat treatment is performed. Next, the third polycrystalline Si layer 4c and the metal silicide layer 7 are patterned to form bit line wiring. Further, a BPSG film 5 is formed on the entire surface as an interlayer insulating film in the same manner as described above, and an O 2 partial pressure of 300 T
Heat treatment at about 800 ° C for 20 minutes in orr atmosphere.

【0020】これにより、上述したものと同様の効果が
得られ、デバイス特性の低下を防止することができる。
続いて、所定部分を開口しAl層8 を堆積した後パターニ
ングしAl配線を形成し、保護膜として例えばプラズマSi
N 膜9 を形成し、Pad を開口してDRAMが製造される( 図
2図示)
As a result, the same effects as those described above can be obtained, and a decrease in device characteristics can be prevented.
Subsequently, a predetermined portion is opened, an Al layer 8 is deposited, and then patterned to form an Al wiring.
An N film 9 is formed, and a pad is opened to manufacture a DRAM (FIG. 2) .

【0021】尚、図4は素子分離領域で隔たれた二つの
N 型拡散層を有する半導体基板上に有機系ソースガスを
用いた形成したBPSG膜と、本実施例の熱処理後における
BPSG膜とにおいて、フィールド酸化膜下に反転層が形成
される際の印加電圧の関係を示した図である。また比較
のためシラン、ジボラン、酸素、ホスフィンで成膜した
BPSG膜と印加電圧の関係も示した。
FIG. 4 shows two elements separated by an element isolation region.
A BPSG film formed using an organic source gas on a semiconductor substrate having an N-type diffusion layer,
FIG. 6 is a diagram showing a relationship between applied voltages when an inversion layer is formed under a field oxide film with a BPSG film. For comparison, a film was formed with silane, diborane, oxygen, and phosphine.
The relationship between the BPSG film and the applied voltage is also shown.

【0022】これによれば、熱処理を行なうことによ
り、有機系ソースを用いず成膜した場合と同様の耐圧を
得られることがわかる。従って、このように製造したDR
AMは、層間絶縁膜中の電荷を帯びた有機物が減少してい
るため、素子分離領域と接して形成された層間絶縁膜に
電圧がかかった際、層間絶縁膜中をキャリア( 有機物が
電荷を帯びていることから生じた) が移動し、低い電圧
で分離されていた素子を導通する等のデバイス特性の低
下を防ぐことができる。特に、素子分離領域間が導通す
る電圧値が高い条件が望ましいフラッシュメモリーにお
いて、本発明の効果は大きい。
According to this, it is understood that the same breakdown voltage can be obtained by performing the heat treatment as in the case where the film is formed without using the organic source. Therefore, the DR manufactured in this way
In AM, the amount of charged organic substances in the interlayer insulating film is reduced, so that when a voltage is applied to the interlayer insulating film formed in contact with the element isolation region, carriers (organic substances transfer charges) in the interlayer insulating film. (Which is caused by being carried) can be prevented from deteriorating device characteristics such as conduction of an element which has been separated at a low voltage. In particular, the effect of the present invention is great in a flash memory in which a condition in which a voltage value for conducting between element isolation regions is high is desirable.

【0023】また、BPSG膜5 は吸湿性であるが、熱処理
により吸湿性が低下しBPSG膜5 の膜質を成膜時と同様に
保つ事ができる。さらに、層間絶縁膜の平坦化の面で
も、効果が望める。
Although the BPSG film 5 is hygroscopic, the heat treatment reduces the hygroscopicity, so that the film quality of the BPSG film 5 can be maintained in the same manner as when the film was formed. Further, the effect can be expected in terms of flattening the interlayer insulating film.

【0024】また、層間絶縁膜を形成した後、同じ装置
内において熱処理を行なえば、外気に晒されないので、
その膜質を低下させず、且つ処理時間を短くすることが
できる。
Further, if a heat treatment is performed in the same device after forming the interlayer insulating film, the film is not exposed to the outside air.
The processing time can be shortened without lowering the film quality.

【0025】尚、本発明は、上記実施例に限定されず、
例えば以下に示す様に、変更しても良い。層間絶縁膜の
種類、その形成方法及び形成した膜厚は、上記実施例に
限定されない。
The present invention is not limited to the above embodiment,
For example, it may be changed as shown below. The type of the interlayer insulating film, the method of forming the same, and the thickness of the formed film are not limited to those in the above embodiment.

【0026】また、層間絶縁膜の形成用の材料も上記実
施例に限定されず、トリメチルフォスフェート(PO(CH3
O)3 など有機系物質を含んでいれば良い。尚、絶縁膜
から有機物を除去するための熱処理時の雰囲気は、上記
実施例に限定されず、減圧下、不活性ガスにより稀釈し
た酸化性雰囲気、水蒸気雰囲気でも良い。但し、雰囲気
中に含まれる酸素の分圧が760Torr 未満、望ましくは20
0 乃至400Torr であれば良い。尚、DRAMを例に本発明を
説明したが、多層デバイス構造の半導体装置であれば本
発明を適用し、効果を上げることができる。
Further, the material for forming the interlayer insulating film is not limited to the above-described embodiment, but may be trimethyl phosphate (PO (CH 3
O) It is sufficient if organic substances such as 3 are included. The atmosphere at the time of the heat treatment for removing organic substances from the insulating film is not limited to the above embodiment, and may be an oxidizing atmosphere or a steam atmosphere diluted with an inert gas under reduced pressure. However, the partial pressure of oxygen contained in the atmosphere is less than 760 Torr, preferably 20
It may be 0 to 400 Torr. Although the present invention has been described by taking a DRAM as an example, the present invention can be applied to a semiconductor device having a multi-layer device structure, and the effect can be improved.

【0027】[0027]

【発明の効果】本発明は、上述のように構成されている
ので、多層デバイス構造の半導体装置のデバイス特性の
低下を防止できる。
Since the present invention is configured as described above, it is possible to prevent a decrease in device characteristics of a semiconductor device having a multilayer device structure.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の実施例の半導体装置の製造方法によ
る工程を示す断面図。
FIG. 1 is a cross-sectional view showing a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図2】 本発明の実施例の半導体装置の製造方法によ
る工程を示す断面図。
FIG. 2 is a cross-sectional view illustrating a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図3】 本発明の実施例において多結晶Si層の配線上
にBPSG膜を堆積した後行なった熱処理結果において、 O
2 分圧を変えた場合の多結晶Si層の配線における酸化量
及びBPSG膜中に含まれる有機物量の関係を示した図。
FIG. 3 shows a result of a heat treatment performed after depositing a BPSG film on the wiring of the polycrystalline Si layer in the embodiment of the present invention.
Diagram showing the relationship of the amount of organic matter contained in the oxidation amount and the BPSG film in the wiring of the polycrystalline Si layer in the case of changing the 2 partial pressure.

【図4】 素子分離領域で隔たれた二つのN 型拡散層を
有する半導体基板上に成膜時の条件が異なるBPSG膜にお
いて、フィールド酸化膜下に反転層が形成される際の印
加電圧の関係を示した図である。
FIG. 4 shows a relationship between applied voltages when an inversion layer is formed under a field oxide film in a BPSG film having different conditions at the time of film formation on a semiconductor substrate having two N-type diffusion layers separated by an element isolation region. FIG.

【符号の説明】[Explanation of symbols]

1 P 型Si基板 2 熱酸化膜 3 N 型拡散層 4a 第一の多結晶Si層 4b 第二の多結晶Si層 4c 第三の多結晶Si層 5 BPSG膜 6 コンタクトホール 7 タングステンシリサイド層 8 Al配線 9 プラズマSiN 層 1 P-type Si substrate 2 Thermal oxide film 3 N-type diffusion layer 4a First polycrystalline Si layer 4b Second polycrystalline Si layer 4c Third polycrystalline Si layer 5 BPSG film 6 Contact hole 7 Tungsten silicide layer 8 Al Wiring 9 Plasma SiN layer

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/312 - 21/318 H01L 21/31 ──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/312-21/318 H01L 21/31

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体基板上に有機系ソースガスを用い
て絶縁膜を堆積する工程と、前記絶縁膜を堆積した後、
酸素分圧200 乃至400Torr 下で熱処理を行なう工程とを
具備することを特徴とする半導体装置の製造方法。
A step of depositing an insulating film on a semiconductor substrate using an organic source gas; and
Performing a heat treatment under an oxygen partial pressure of 200 to 400 Torr.
【請求項2】 上記熱処理を400 ℃以上で行なうことを
特徴とする請求項1記載の半導体装置の製造方法。
2. The method according to claim 1, wherein said heat treatment is performed at 400 ° C. or higher.
【請求項3】 上記熱処理時の雰囲気が、不活性ガスに
より稀釈した酸化性雰囲気であることを特徴とする請求
項1記載の半導体装置の製造方法。
3. The method according to claim 1, wherein the atmosphere during the heat treatment is an oxidizing atmosphere diluted with an inert gas.
【請求項4】 上記有機系ソースガスは、テトラエトキ
シシラン(TEOS;Si(C 2H 5 O) 4)、トリメチルボレー
ト(TMB ;B(CH3 ) 3 )、トリメチルフォスフェート(T
MP;PO(CH 3 O)3 ) のいずれかであることを特徴とする
請求項1記載の半導体装置の製造方法。
4. The organic source gas includes tetraethoxysilane (TEOS; Si (C 2 H 5 O) 4 ), trimethyl borate (TMB; B (CH 3 ) 3 ), and trimethyl phosphate (T
2. The method for manufacturing a semiconductor device according to claim 1, wherein the method is any one of MP; PO (CH 3 O) 3 ).
【請求項5】 上記絶縁膜の下に、素子分離領域又は配
線が存在する事を特徴とする請求項1記載の半導体装置
の製造方法。
5. The method according to claim 1, wherein an element isolation region or a wiring exists under the insulating film.
JP14158195A 1995-06-08 1995-06-08 Method for manufacturing semiconductor device Expired - Fee Related JP3226251B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14158195A JP3226251B2 (en) 1995-06-08 1995-06-08 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14158195A JP3226251B2 (en) 1995-06-08 1995-06-08 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH08335577A JPH08335577A (en) 1996-12-17
JP3226251B2 true JP3226251B2 (en) 2001-11-05

Family

ID=15295329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14158195A Expired - Fee Related JP3226251B2 (en) 1995-06-08 1995-06-08 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3226251B2 (en)

Also Published As

Publication number Publication date
JPH08335577A (en) 1996-12-17

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