JP3225524B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a high-speed, high-integration semiconductor device composed of fine elements.

[0002]

2. Description of the Related Art Semiconductor integrated circuits (LSI = Large Scale)
Integration), the high integration of MO
It has been promoted by miniaturization of S transistors. In the case of a so-called deep submicron LSI in which the minimum dimension of the element is 0.5 μm or less, the breakdown voltage of the element decreases and the L
An increase in power consumed by the SI poses a problem. To solve such a problem, it is considered that reducing the operating power supply voltage as the element is miniaturized is an effective means.

As the power supply voltage of the current LSI is 5 V, the technology of mounting a voltage conversion circuit for reducing the external power supply voltage on an LSI chip as a means for forming an LSI with fine elements has been developed. EiEi Journal of Solid State Circuits, No. 2
Vol. 1, No. 5, pp. 605-611 (1986) (IEE
E Jounal of Solid-State Circuits, vol.21, No.5, p
605-611, October 1986).
In this case, the values of the external power supply voltage and the internal power supply voltage are 5 V and 3.5 V, respectively. As described above, the problem of power consumption is becoming apparent in a dynamic RAM (DRAM) having the highest integration among LSIs.

[0004]

However, on the other hand, it has been pointed out that the power supply voltage has a lower limit due to physical restrictions. Regarding this restriction, see the IEE Journal of Solid State Circuits, Vol. 9, No. 5, pages 256-267 (197).
4) (IEEE Jounal of Solid-State Circuits, vol.9, N
o.5, pp.256-267, October 1974). As shown therein, the low current characteristic of the MOS transistor has a so-called sub-threshold characteristic in which the drain current attenuates exponentially with respect to the gate voltage. This coefficient is called a subthreshold coefficient (tailing coefficient), and is a value of about 80 mV / 1 digit at room temperature. Therefore, if the gate threshold voltage is decreased in proportion to the decrease in the power supply voltage, a minute DC current flows even during the period when the transistor is cut off, and there is a problem that current consumption during standby increases. . For this reason, in the conventional CMOS circuit, when the power supply voltage is reduced, the threshold voltage cannot be reduced below a certain value. The lower practical limit is described in Procedures of Technical Papers, 1989.
・ International Symposium on VSI Technology System and Applications, 188-192 (1989) (Proceed)
edings of Technical Papers, 1989 International Symp
osium on VLSI Technology, Systems and Application
s, pp. 188-192, May 1989) and Proceedings
Of the symposium on low temperature electronics and high temparecia
Superconductors, pp. 55-69 (198
7) (Proceedings of the Symposium on Low Temperat
ure Electronics and High Temperature Superconducto
rs, pp. 55-69, Oct. 1987). Its value is about 0.35 to 0.55V. The lower limit of the power supply voltage at this time is practically about 1.5 V, and there is a problem that if the voltage is further reduced, the delay time is significantly increased.

An object of the present invention is to operate at a high speed even with a signal amplitude smaller than the power supply voltage, which has been conventionally set as the lower limit,
Another object of the present invention is to provide a semiconductor integrated circuit that does not increase current consumption during standby.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to make a plurality of signal amplitudes inside an integrated circuit, drive a main signal wiring with a small amplitude, and convert a small signal amplitude into a large signal amplitude with a small standby current. This can be achieved by providing an amplitude conversion circuit.

[0007]

The amplitude of the internal signal of various integrated circuits can be reduced, so that the charge / discharge current of the signal wiring (bus) can be reduced and the power consumption can be reduced. Further, since the peak current can be reduced, the reliability of the signal wiring can be improved and the noise can be reduced.
Further, the charge / discharge time of the signal wiring (bus) can be reduced, and the speed can be increased. As a result, low power consumption can be achieved without being bound by the lower limit of the power supply voltage, which is a problem in the conventional circuit system, and high integration, high speed, and low power consumption can be simultaneously achieved.

[0008]

FIG. 1 is an embodiment for explaining the basic concept of a CMOS integrated circuit according to the present invention. In FIG.
An integrated circuit is composed of a plurality of circuit blocks such as BLK1 and BLK2 and signal wiring for transmitting signals between them. In the example of this figure, the output of BLK1 is connected to the signal wiring SI.
G1 is transmitted to the input of BLK2. Each circuit block includes a signal receiving unit (for example, REC2 in the figure) which receives a signal having a small amplitude from another circuit block and converts the signal into a signal with a large amplitude, and a signal processing unit (for example, FIG. Drive circuits (for example, DRV in the figure) which output signals of small amplitude to signal wirings.
1).

Of these, the signal processing section is provided with a power supply voltage VC.
It operates by C and VSS, and its signal amplitude is (VCC-V
SS). The drive circuit DRV1 includes an N-channel MOS transistor TN2 and a P-channel MOS transistor T
P2. This drive circuit has a power supply voltage VCL
O and VSLO, and the signal line SIG1 has an amplitude (V
CLO-VSLO) signal. Note that between these power supply voltages, VCC>VCLO>VSLO> VSS
The following relationship holds. In this example, the back gate of TN2 is set to VSS, and the back gate of TP2 is set to VC.
C, each connected to VSLO, V
It may be connected to CLO.

The signal receiving unit REC2 includes an N-channel MOS transistor TN3 and a P-channel MOS transistor TP3 forming a transfer gate, and a pair of N-channel MOS transistors TN4 whose gates and drains are cross-connected.
And TN5 and P-channel MOS transistor pair TP4
And TP5.

A voltage V is applied to the gate of the transfer gate TN3.
CLI and a voltage VSLI are applied to the gate of TP3, respectively. The back gate of TN3 is VSS
The back gates of TP3 are connected to VCC, respectively, but they may be VSLO and VCLO, respectively. In this embodiment, the gate threshold voltage of the N-channel MOS transistor is about 0.5 V, and the gate threshold voltage of the P-channel MOS transistor is about -0.5.
V is set.

The operation of this circuit will be described with reference to FIG. In this example, VCC = 1.5V, VSS = 0V,
VCLO = 1V, VSLO = 0.5V, VCLI = 1.5
The case where V and VSLI = 0 V will be described. However, the present invention is not limited to these values, and an effect can be obtained as long as VCC>VCLO>VSLO> VSS and VCLI> VSLI are satisfied. Well, now,
The output N1 of the inverter INV1 in the circuit block BLK1
Changes from 1.5V to 0V at time t0 and from 0V to 1.5V at time t3.

Before time t0, that is, when the terminal N1 is 1.
During the period of 5 V, the gate-source voltage of the transistor TN2 becomes 1 V and the gate-source voltage of the transistor TP2 becomes 0.5 V. Therefore, TN2 becomes conductive and TP2 becomes nonconductive, and the output of the drive circuit, that is, the signal line VSLO = 0.5V is output to SIG1. At the same time, the voltage between the gate and source of the transfer gate TN3 constituting the receiving circuit REC2 is 1 V, and the voltage between the gate and source of the transistor TP3 is -0.5 V, so that TN3 is conductive and TP3 is nonconductive. The driving capability of the transistor TN3 is changed to TP4
The terminal N2 is set to 0.5 V, which is equal to the input SIG1, so that the transistor TP5 is conducting. On the other hand, the voltage of the terminal N3 is 0.5
Therefore, the transistor TN5 is turned off, and the terminal N4 is at 1.5V. Therefore, transistor TN4 is conducting and terminal N3 is consequently set to 0V. Among these transistors, the gate-source voltage of TP3 is -0.5 V, which is equal to the gate threshold voltage, so that a small current called a sub-threshold current flows. For example, the proportion occupied by this transistor is small, and its current is negligibly small. Now,
It is assumed that the terminal N1 changes from 1.5V to 0V at time t0. The gate-source voltage of the transistor TN2 is -0.5 V, and the gate-source voltage of the transistor TP2 is
Since the source-to-source voltage becomes -1 V, TN2 is turned off, and T
P2 becomes conductive, and the output of the drive circuit, that is, the signal line S
VCLO = 1V is output to IG1. At the same time, the gate-source voltage of the transfer gate TN3 constituting the receiving circuit REC2 is 0.5 V, and the gate-source voltage of the transistor TP3 is
Since the source-to-source voltage becomes -1 V, TN3 is turned off and T
P3 becomes conductive. Set the driving capability of transistor TP3 to TN
4, the terminal N3 becomes 1V equal to the input SIG1, and the transistor TN5
Becomes conductive. On the other hand, the voltage of the terminal N2 rises to about 1V. Accordingly, the transistor TP5 becomes non-conductive, and the terminal N4 becomes 0V. As a result, the transistor TP4 conducts, and the terminal N2 is pulled up to 1.5 V at the time t2.

Similarly, when the terminal N1 changes from 0 V to 1.5 V at time t3, the signal line SIG1
Changes from 1V to 0.5V, and the terminal N4 changes from 0V to 1.5V.

As described above, the 1.5V signal amplitude in the circuit block BLK1 is converted into a signal having an amplitude of 0.5V, and the signal is converted again into a 1.5V signal amplitude in the circuit block BLK2. be able to. In general,
Most of the power consumption of an integrated circuit is consumed by charging and discharging a signal line (bus) provided for transmitting and receiving signals between circuit blocks. Therefore, reducing the voltage amplitude of this signal line is extremely effective in reducing the power consumption of the entire integrated circuit. Further, by increasing the voltage amplitude in the integrated circuit block to be larger than the signal amplitude of the bus, the operating speed of the circuit group in the block is increased, and at the same time, the gate of the inverter circuit (driver) for driving the bus is set to the amplitude of the bus or more. And the switching speed of the bus can be improved. In this embodiment, the amount of charge required to charge and discharge the load capacitance CW of the signal line SIG1 once is calculated from CW (VCC-VSS) to CW (V
(CLO-VSLO) to about one third. As a result, current consumption and power consumption can be reduced to about one third. Also, when compared at the same operation speed, the peak current of the signal line and the power supply line generated due to the charging and discharging of the signal line capacity can be reduced to about one third, and the metal wiring constituting the signal line and the power supply line can be reduced. Reliability can be improved. Further, power supply noise generated due to the resistance of the power supply line can be reduced to about one third, and an integrated circuit with more stable operation can be provided. Thus, by reducing the signal amplitude of the main signal line, an integrated circuit with low power consumption and low noise can be realized while maintaining high speed.

In the above description, six power supply voltages VCC,
The case where a circuit is configured using VSS, VCLO, VSLO, VCLI, and VSLI has been described. Some of these voltages may be the same voltage as described in this embodiment. All of them may be supplied from the outside, or VCC and VSS may be supplied from the outside of the device, and VCLO, VSLO, VCLI, VSLI, etc. may be generated by a voltage conversion circuit provided inside the integrated circuit.

FIG. 3 shows another embodiment of a CMOS integrated circuit according to the present invention. In the present embodiment, in order to reduce the number of types of power supplies, a plurality of types of threshold voltages of MOS transistors of each conductivity type are used. In the figure, the difference from the embodiment of FIG. 1 is that the N-channel M
The absolute values of the gate threshold voltages of the OS transistor TN6 and the P-channel MOS transistor TP6, and the N-channel MOS transistor TN7 and the P-channel MOS transistor TP7 forming the transfer gate of the signal receiving unit REC4 are determined by the MOS transistors forming the other circuits. That is, it is lower than the absolute value of the gate threshold voltage. Thus, the power supply voltage of the drive circuit and the gate applied voltage of the transfer gate can be made equal to VCL and VSL. In addition,
The back gates of TN6 and TN7 are connected to VSS, TP6 and T
The back gates of P7 are connected to VCC, respectively, but they may be VSL and VCL, respectively. In the present embodiment, the gate threshold voltage of the N-channel MOS transistor is about 0.5 V for the higher one, about 0 V for the lower one, and the gate threshold voltage of the P-channel MOS transistor is about -V for the higher absolute value. 0.5V, and the lower absolute value is about 0V.

The operation of this circuit is similarly described with reference to the operation waveforms shown in FIG. Here, VCC = 1.5V, VSS
= 0V, VCL = 1V, VSL = 0.5V will be described, but it is obvious that the values are not limited to these values.

Before time t0, that is, when the terminal N5 is 1.
During the period of 5 V, the gate-source voltage of the transistor TN6 becomes 1 V and the gate-source voltage of the transistor TP6 becomes 0.5 V. Therefore, TN6 becomes conductive and TP6 becomes nonconductive, and the output of the drive circuit, that is, the signal line VSL = 0.5V is output to SIG2. At the same time, the receiving circuit R
Since the gate-source voltage of the transfer gate TN7 constituting the EC4 is 0.5 V and the gate-source voltage of the transistor TP7 is 0 V, TN7 is conductive and TP7
Becomes non-conductive. Set the driving capability of the transistor TN7 to TP
By designing the terminal N6 to be sufficiently larger than that of the terminal 8, the terminal N6 is set to 0.5 V which is equal to the input SIG2, and the transistor TP9 is conducting. On the other hand, since the voltage at the terminal N7 is lower than 0.5 V, the transistor TN9 is non-conductive and the terminal N8 is 1.5 V. Therefore, the transistor TN8 conducts and the terminal N
7 is consequently set to 0V. Among these transistors, the gate-source voltage of TP7 is 0V,
A small current called a sub-threshold current flows because it matches the gate threshold voltage. However, compared to the transistor of the entire integrated circuit, this transistor occupies a small proportion and its current is negligibly small.

The operation at other times is the same as in the example shown in FIG. As described above, by using MOS transistors having two types of gate threshold voltages for each conductivity type, the four power supply voltages VCC, VSS, VCL, and VSL are used.
Can form a circuit. All of these may be supplied from the outside, or VCC and VSS may be supplied from outside the device, and VC and VSS may be supplied by a voltage conversion circuit provided inside the integrated circuit.
L, VSL, etc. may be generated. In this embodiment, the same effects as those described in the previous embodiment can be obtained.

Next, the effect of the present invention will be specifically described with reference to FIG. 4 and 5 show load capacity (CL = 2p).
An example in which the drive circuit of F) is configured using the conventional technology and the present invention is shown. In each case, the amplitude (VCL
-VSL) signal and load is amplitude (VCL-V
SL). In a conventional CMOS integrated circuit, as shown in FIG. 4, a drive circuit is constituted by a plurality of stages of CMOS inverters. In a CMOS inverter, since the power supply voltage is equal to the signal amplitude as it is,
CL and VSL are operated as power supplies. On the other hand, in the present invention, as shown in FIG. 5, a level conversion circuit REC5 for amplifying the amplitude of an input signal and a CMOS inverter circuit DRV5 for driving a load are provided. REC5 is REC4 in FIG. 3, and DRV5 is DRV3 in FIG.
And are basically the same. Also, the gate threshold voltage of each transistor is the same as the value described in the description of FIG. MOS transistor has a gate oxide film thickness of 7 nm
(Nanometers), and the gate length L and gate width W of each transistor are as follows.

[0022] As a result, the power consumption of the conventional circuit and the circuit of the present invention during standby is substantially the same.

FIG. 6 shows input (IN) and output (OUT) waveforms. The time when the output reaches 10% to 90% is the output rise time tr, the time when the output reaches 90% to 10% is the output fall time tf, and the time from when the input rises to 50% to when the output rises to 50%. Is defined as a rising propagation delay time tpdr, and a time from when an input falls to 50% to when an output falls to 50% is defined as a falling propagation delay time tpdf.

FIG. 7 shows the signal amplitude (V) of the output rise time tr.
9 shows the results of computer analysis of (CL-VSL) dependence.
In a conventional driving circuit using a CMOS inverter, the rise time sharply increases when the signal amplitude is 1.5 V or less. The typical relationship between signal amplitude and rise time is shown below. Becomes Assuming that tr <2 ns is one standard in terms of speed performance, the minimum value of the signal amplitude is 1.5V. on the other hand,
In the present invention, the relationship between signal amplitude and rise time is Assuming that tr <2 ns is one standard, the minimum value of the signal amplitude is about 0.12 V. From this analysis result,
Considering the output rise time tr, according to the present invention,
The signal amplitude can be reduced by about one digit from the conventional 1.5V to about 0.12V. Although the analysis result of the output rise time tr is shown here, the same improvement effect can be obtained for the output fall time tf.

FIG. 8 shows the result of computer analysis of the signal amplitude (VCL-VSL) dependence of the rise propagation delay time tpdr. In a drive circuit using a conventional CMOS inverter, the rise propagation delay time sharply increases when the signal amplitude is 1.5 V or less, similarly to the rise time. The relationship between the signal amplitude and the rise propagation delay time is shown below for typical ones. Becomes Assuming that tpdr <3 ns is one standard in terms of speed performance, the minimum value of the signal amplitude is about 1.2 V. On the other hand, in the present invention, the relationship between the signal amplitude and the rise propagation delay time is Assuming that tpdr <3 ns is one standard, the minimum value of the signal amplitude is about 0.31 V. From this analysis result,
Considering the rising propagation delay time tpdr, according to the present invention, the signal amplitude can be reduced to about a quarter from the conventional about 1.2 V to about 0.31 V. Although the analysis result of the rising propagation delay time tr is shown here, a similar improvement effect can be obtained for the falling propagation delay time tf.

FIG. 9 shows another embodiment of a CMOS integrated circuit according to the present invention. In the embodiment of FIG. 1 or FIG. 3, when a signal transitions between a high level and a low level, a small DC current flows from the signal receiving unit to the signal line or from the signal line to the signal receiving unit. If the rise or fall time of the signal is long due to the parasitic resistance and parasitic capacitance of the signal line, or if many signal receiving circuits are connected to one signal line, the smaller this current is, the better. It is preferable in terms of circuit operation. FIG. 9 shows an example of a configuration for preventing the direct current from flowing. In this example, a signal receiving section for receiving a signal with a small amplitude from another circuit block and converting the signal into a signal with a large amplitude is constituted by a receiving circuit REC8A using a CMOS inverter and a level converting circuit REC8B. The inverter circuit of REC8A has VCL and VCL like the inverter circuit of drive circuit DRV7 in the figure.
It operates using SL as a power supply. Level conversion circuit REC8B
Is basically the same as REC4 in FIG. In the figure, an N channel MO constituting a drive circuit DRV7 is provided.
S transistor TN16 and P channel MOS transistor TP16, N forming an inverter of receiving circuit REC8A
Channel MOS transistor TN17 and P channel MOS transistor TP17, and level conversion circuit R
N-channel MOS transistor TN18 and P-channel MOS transistor TP forming a transfer gate of EC8B
The absolute value of the gate threshold voltage of the MOS transistor 18 is made lower than the absolute value of the gate threshold voltage of the MOS transistor constituting another circuit. Note that TN16, TN17 and TN
The back gate at 18 is connected to VSS, and the back gates at TP16, TP17 and TP18 are connected to VCC, respectively, but they can be VSL and VCL, respectively. As in the embodiment of FIG.
The gate threshold voltage of the OS transistor is about 0.5 V for the high side and about 0 V for the low side.
5V, the lower absolute value is about 0V.

The operation of this circuit will be described with reference to the operation waveforms shown in FIG. The difference from the example shown in FIG. 3 resides in that the input of the level conversion circuit REC8B is driven by an output inverted by an inverter instead of directly driven by a signal line. Therefore, in this embodiment, the signal at the terminal N10 is
, But the basic operation remains the same. Here, VCC = 1.5V, VSS = 0V, VC
The case where L = 1V and VSL = 0.5V will be described, but it is obvious that the values are not limited to these values. As described above, by configuring the signal receiving unit with the CMOS inverter and the level conversion circuit, it is possible to prevent the inflow of DC current from the signal line to the signal receiving unit or the outflow of DC current from the signal receiving unit to the signal line. Can be. Note that, in the CMOS inverter forming the receiving circuit, the power supply VCL
DC current flows through SL. However, since the number of elements and dimensions of the inverter are negligibly small relative to the number of elements and dimensions of the entire integrated circuit, this current does not significantly affect the current consumption of the integrated circuit.

FIG. 11 shows another embodiment of the CMOS integrated circuit according to the present invention. The present embodiment provides a signal receiving section which receives a plurality of signals having small amplitudes and converts the result of the logical operation into a large signal amplitude used inside the circuit block.

In this example, the signal receiving section comprises a receiving circuit REC11A using a NAND gate and a level converting circuit REC11B. REC11A NAND
The gate operates using VCL and VSL as power supplies, similarly to REC8A of FIG. The level conversion circuit REC11B
It is basically the same as REC4 in FIG. 3 and REC8B in FIG.

As in the case of the ordinary CMOS circuit, two series-connected N-channel MOS transistors TN3
2, TN33 and two parallel connected P-channel MOs
The S transistors TP32 and TP33 form a NAND gate. In addition, another circuit block BLK9
Signal SIG4 from BLK10 and signal SIG5 from BLK10.
And the NAND output is obtained at the terminal N15. N
The MOS transistors forming the AND gate are shown in FIG.
As in the case of REC8A in the middle, one having a low absolute value of the threshold voltage is used. With such a configuration, the result of the logical operation of a plurality of low-amplitude signals can be taken into the circuit block as a large signal. Here, as an example of the logical operation, the case of a two-input NAND has been described.
It is obvious that any logical operation such as NOR with two or more inputs and EOR (exclusive OR) can be similarly applied.

FIG. 12 shows an embodiment of a circuit configuration for generating power supply voltages VCL and VSL inside the chip based on external power supply voltages VCC and VSS.

In the figure, DIV has three resistors R1, R2, R
3, OP1 and OP2 are differential amplifier circuits, TP40 is a P-channel MOS transistor for driving VCL, and TN40 is an N-channel MOS for driving VSL.
Transistors, R4 and R5 are bias resistors, C1
C3 is a smoothing capacitor. With this circuit, VCL and V
In SL, VCL = (R2 + R3) × (VCC−VSS) / (R1
+ R2 + R3) VSL = R3 × (VCC−VSS) / (R1 + R2 + R
3) The following voltage is obtained. For example, VCC = 1.5V, VS
When S = 0V and R1 = R2 = R3, VCL = 1
V and VSL = 0.5V are obtained.

FIG. 13 shows another embodiment of the integrated circuit according to the present invention. In this embodiment, the common power supplies VCL, VSL
Is supplied to the signal line drive circuit, VCC, VS
S is supplied to reduce the signal amplitude for each drive circuit.

In FIG. 13, CHP5 is an integrated circuit chip, BLK12 and BLK13 are circuit blocks constituting the chip, SIG6 is a signal line for transmitting a signal of small amplitude from BLK12 to BLK13, DRV12 is a driving circuit for the signal line, The REC 13 is a signal receiving circuit. Except for the drive circuit DRV12, the basic configuration is the same as that shown in FIG.

The drive circuit DRV12 is an N-channel MOS.
Transistor TN40, P-channel MOS transistor TP40, NPN type bipolar transistor Q1, P
NP-type bipolar transistor Q2. The collector terminals of the two bipolar transistors are connected to power supplies VCC and VSS, respectively, and the emitter terminals are connected to a CMOS inverter. A DC voltage VCLB,
VSLB is applied. These values are respectively VCLB
= VCL + VBE VSLB = VSL-VBE. Here, VBE is a forward voltage drop between the base emitter of the bipolar transistor and about 0.7
5V. With such a connection, VCL is obtained at the terminal N20 and VSL is obtained at the terminal N21. According to this circuit system, the power supply such as VCL or VSL does not need to have a low impedance as in the example of FIG. Accordingly, the generation circuit shown in FIG. 12 does not need to have a large driving capability, and does not cause an increase in the area occupied by the generation circuit itself and an increase in power consumption. Similar effects can be obtained by using N-channel and P-channel MOS transistors instead of the NPN and PNP bipolar transistors used in this example.

FIG. 14 shows an embodiment of a circuit configuration for generating power supply voltages VCL, VSL and VCLB and VSLB inside the chip based on external power supply voltages VCC and VSS.

In the figure, the voltage dividing circuit includes resistors R10, R11, R
NPN type and PN connecting base 12, emitter and emitter
It is composed of P-type bipolar transistors Q3 and Q4. Q5 is an NPN bipolar transistor for driving VCL, Q6 is a PNP bipolar transistor for driving VSL, R13 is a resistor for bias, C10
C12 is a smoothing capacity. With this circuit, VCL
And VSL, VCL = ((R11 + R12) × VCC + (R10-R11-R12) × VBE) / (R10 +
VSL = (R12 x VCC + (R10 + R11-R12) x VBE) / (R10 + R11 + R1
2) The following voltage is obtained. However, it is assumed here that VSS = 0V. VBE is a forward voltage drop between the base and the emitter of the bipolar transistor, and is about 0.
It is about 75V. For example, VCC = 3V, 0.25 ×
When R11 = R10 = R12, VCL = 2V, VS
L = 1V is obtained.

FIG. 15 shows another embodiment of the integrated circuit according to the present invention. In this embodiment, the signal transmission between the integrated circuit chips is performed by a signal having a low amplitude.

In the figure, CHP6 and CHP7 are integrated circuit chips, SIG7 is a signal line for transmitting a signal of small amplitude from CHP6 to CHP7, DRV16 is a signal line driving circuit, and REC17 is a signal receiving circuit. The drive circuit DRV16 is connected to the DRV12 in FIG.
C17 is basically the same as that shown in REC13 in FIG.

With this configuration, it is possible to reduce the power required to drive a signal line between chips having a large capacity. Further, the peak current generated due to the charging and discharging of the signal line can be suppressed low, so that the reliability of the signal wiring and the noise of the power supply line can be reduced. Therefore, an integrated circuit having a large number of signal lines such as a microprocessor is particularly effective.

Also, in the conventional input circuit of the integrated circuit chip, the TTL level (for example, the LOW determination level maximum value V
IL _MAX = 0.8 V, HIGH judgment level minimum value VIH
_MIN = 2.4V), there is a problem that the through current flows through the CMOS inverter, so that the standby current cannot be reduced. However, if the receiving circuit of the present invention is used, the standby current can be reduced. Since it can be made extremely small, it is extremely effective in reducing the current consumption of the integrated circuit chip.

FIG. 16 shows another embodiment of the integrated circuit according to the present invention. In this embodiment, as in FIG. 15, the signal transmission between the integrated circuits is performed using a low-amplitude signal.

In the figure, CHP8 and CHP9 are integrated circuit chips, SIG8 is a signal line for transmitting a signal of small amplitude from CHP8 to CHP9, DRV18 is a signal line driving circuit, and REC19 is a signal receiving circuit. The driving circuit DRV18 is an NPN type bipolar transistor Q2.
It comprises a complementary inverter circuit comprising 0 and PNP type bipolar transistors Q21 and a CMOS inverter circuit provided to drive a base terminal which is an input thereof. VCLB and VSLB are applied to the power supply voltage of the CMOS inverter circuit, and VCL + VB is set to a high level at the input of the complementary inverter circuit.
E, VSL-VBE is obtained as a low level. Thus, the amplitude of the signal line is (VCL-VS
L) can be obtained.

With this configuration, it is possible to reduce the power required to drive a signal line between chips having a large capacity. Further, the peak current generated due to the charging and discharging of the signal line can be suppressed low, so that the reliability of the signal wiring and the noise of the power supply line can be reduced. In particular, since the output circuit is composed of only bipolar transistors, a large load driving capability can be obtained as compared with the example of FIG.

FIGS. 17 to 20 show a CMOS according to the present invention.
7 shows another embodiment of the integrated circuit. In these embodiments, another method of a signal receiving unit in which a plurality of small amplitude signals are input and the logical operation result is converted into a large signal amplitude used inside a circuit block is shown.

FIG. 17 shows an example of a circuit configuration of a signal receiving unit which outputs an operation result Q of an inverted logical product (NAND) of two inputs A and B. That is, when both the inputs A and B are at a high level, the output Q is at a low level, and at other times, the output Q is at a high level. The signal amplitudes of the inputs A and B and the inverted signal B-bar of the signal B are VSL at the low level and VCL at the high level, as in the embodiment of FIG. The inverted signal B-bar may be generated by a drive circuit, or may be generated from an input B by providing an inverter in a receiving unit. In this circuit, in REC4 in FIG. 3, a transfer gate is constituted by four transistors, TN70, TN71, TP70 and TP71, in order to make use of the level conversion function as it is and to have a new logical operation function. And a signal is applied to the gate terminal of the transfer gate instead of the DC voltage.

Next, the operation of this circuit will be described. When the input B is at a low level, that is, when the input B-bar is at a high level, the transistor TN70 is off, and TN7
1 becomes conductive and the terminal N40 becomes low level. Further, the transistor TP70 is turned off, the transistor TP71 is turned on, and the terminal N41 is also at a low level. Therefore, the output Q is at a high level regardless of the level of the input A. On the other hand, when the input B is at a high level, the transistor TN70 is turned on, the TN71 is turned off, and the terminal N40 is at a level equal to the input A. Further, the transistor TP70 is turned on, the TP71 is turned off, and the terminal N41 is at the same level as the input A. Therefore, an inverted output of the input A is obtained at the output Q. Thus, the output is low only when both inputs A and B are high, and the output is high in other combinations. That is, the operation result of the NAND of A and B is obtained at the output Q.

FIG. 18 shows an example of a circuit configuration of a signal receiving section which outputs an operation result Q of an inverted logical sum (NOR) of two inputs A and B. That is, when both the inputs A and B are at a low level, the output Q is at a high level, and at other times, the output Q is at a low level. When input B is high,
That is, when the input B-bar is at a low level, the transistor TN75 is turned on, the TN76 is turned off, and the terminal N45 is at a high level. Further, the transistor TP75 is turned on, the TP76 is turned off, and the terminal N46 is also at a high level. Therefore, the output Q is at a low level regardless of the level of the input A. On the other hand, input B
Is low, transistor TN75 is nonconductive, TN76 is conductive, and terminal N45 is connected to input A.
Level. Further, the transistor TP75 is turned off, the TP76 is turned on, and the terminal N46 is at the same level as the input A. Therefore, an inverted output of the input A is obtained at the output Q. From these, inputs A and B
Are high only when both are low, and the output is low in other combinations. That is, the operation result of the inverted logical sum (NOR) of A and B is output Q
Is obtained.

FIG. 19 shows an example of a circuit configuration of a signal receiving section which outputs an operation result Q of an inverted logical product (NAND) of three inputs A, B and C. As in the embodiment of FIG. 17, when the inputs A, B and C are all at a high level, the terminals N50 and N51 are at a high level. Thus, the output is low only when the inputs A, B and C are both high, and the output is high in other combinations. That is, the result of the operation of the inversion logical product (NAND) of A, B and C is obtained at the output Q.

FIG. 20 shows an example of a circuit configuration of a signal receiving section which outputs an operation result Q of exclusive OR (Exclusive-OR = EOR) of two inputs A and B. That is, when the inputs A and B are at the same level, the output Q is at a low level, and at other times, the output Q is at a high level. Input B
Is high, that is, when the input B-bar is low, the transistor TN85 is conducting and TN8
6 is turned off, and the terminal N55 is at the same level as the input A. Further, the transistor TP85 is turned on, and T
P86 is turned off, and the terminal N56 is at the same level as the input A. Therefore, the output Q has the inverted logic of the input A. On the other hand, when the input B is at a low level, the transistor TN85 is turned off, the TN86 is turned on, and the terminal N55 is at the same level as the input A-bar.
Further, the transistor TP85 is turned off, the TP86 is turned on, and the terminal N56 is at the same level as the input A-bar. Therefore, the output Q has the same logic as the input A. From these, exclusive OR (EOR) of inputs A and B
Is obtained at the output Q.

As shown in the above embodiments, according to the present invention, it is possible to perform a logical operation directly from a plurality of signals having small input amplitudes. The number of transistors used can be reduced as compared with the case where an operation is performed, and a highly integrated circuit can be formed. It is obvious that the present invention can be similarly applied to a larger number of inputs and any other logical operation in addition to the above-described embodiment.

FIGS. 21 to 23 show a CMOS according to the present invention.
7 shows another embodiment of the integrated circuit. In these embodiments, examples are shown in which the present invention is applied to an input circuit capable of accurately determining a logic level even with a small input signal amplitude. In general, signal levels for an interface of a CMOS integrated circuit are two levels, ie, a CMOS level and a TTL level.
Types are widely used. The minimum value VOHmin of the output high level (VOH) of each interface signal level
And the maximum value VOLmax of the output low level (VOL) is C
In the case of the MOS level, VOHmin = VCC-0.1 (V) VOLmax = 0.1 (V) In the case of the TTL level, a value of VOHmin = 2.4 (V) VOLmax = 0.4 (V) is generally used. is there. The smaller the amplitude of these signals, the higher the speed and the smaller the charge / discharge current of the load capacitance. However, on the other hand, there is a drawback that the noise margin of the signal receiving circuit is reduced. As an interface having a lower amplitude than these, an ECL interface used in a bipolar LSI or a biCMOS LSI is known. In this case, VOHmin ≒ -1.0 (V) VOLmax ≒ -1.6 (V), and the signal amplitude is as small as about 0.6V. As the number of signals (number of pins) per integrated circuit increases and the degree of integration of CMOS integrated circuits increases, there is a strong demand for higher speed and lower noise. However, the conventional ECL interface
Since the face is based on a bipolar transistor, it is difficult to realize with a CMOS circuit. Since a large bias current is required for an input circuit, power consumption (especially power consumption in a standby state) is large. There was a problem. There has been a demand for a low-amplitude interface that overcomes these problems, operates the noise margin widely and stably, and maintains the low power consumption performance characteristic of CMOS.
These new interfaces must satisfy the following conditions:

(1) The signal amplitude is about 1 V or less and has a sufficient noise margin.

(2) In the standby state (input is equal to or higher than VIHmin or equal to or lower than VILmax), almost no current is consumed.

In order to satisfy such conditions, an input circuit is required which can reliably detect a small input signal amplitude and does not consume current in a standby state. Examples of such an input circuit are shown in FIGS. 15 and 16, but other examples will be described below.

FIG. 21 shows an embodiment of an input circuit of a CMOS integrated circuit according to the present invention. In this embodiment, the two transfer gates in FIG. 15 or FIG. 16 are replaced by four transistors TN90, TN91, TP90 and TP91. Reference voltages VRN and VRP are applied to the gates of TN90 and TP91, respectively. VRN
And VRP, as shown on the right side of the figure, VRN = VIH + VTN + VTP VRP = VIL-VTN-VTP. Here, VIH and VIL
Is the high level and low level of the input signal, and VTN and VTP are N
This is the absolute value of the threshold voltage of the channel transistor and the P-channel transistor.

When the voltage of the input IN is lower than VIL, TN91 and TP91 are turned off, and TN90 and TP91 are turned off.
90 becomes conductive and the terminal N60 goes low. As a result, the output OUT becomes high level and the terminal N6
1 is low level. Conversely, when the voltage of the input IN is higher than VIH, TN91 and TP91 are conducting,
N90 and TP90 are turned off, and the terminal N61 goes high. As a result, the output OUT goes low and the terminal N60 goes high. In this manner, an input circuit that stably responds to a small input signal amplitude can be configured. Also, since there is no DC current path from VCC to VSS, the current in standby can be made almost zero.

FIG. 22 shows another embodiment of the input circuit of the CMOS integrated circuit according to the present invention. Here, VI
4 shows a configuration example of an input circuit when L = 0. In the figure, TN1
00 to TN103 are N-channel transistors, TP10
0 to TP102 are P-channel transistors. TN
A reference voltage VREF1 is applied to the gate of 101, and its source is a CMOS comprising TN100 and TP100.
Inverter is connected. The input is TN103
The output inverted by the inverter is applied to the TN 102. These TN102, TN103 and TP101,
The TP 102 forms a level conversion circuit. The value of the reference voltage VREF1 is VREF1 = VIH + VTN + V
The value is TP. Here, VIH is the high level of the input signal, VTN and VTP are the N-channel transistor and P
This is the absolute value of the threshold voltage of the channel transistor.

When the voltage of the input IN is 0 (V), the output N65 of the inverter is at a high level. Therefore,
The TN 103 is turned off and the TN 102 is turned on, so that the terminal N67 goes high and the terminal N66 goes low. As a result, the output OUT goes high. Conversely, when the voltage of the input IN is higher than VIH, the output N65 of the inverter goes low. Therefore, TN10
2 is in a non-conductive state, TN103 is in a conductive state, the terminal N66 is at a high level, and the terminal N67 is at a low level. As a result, the output OUT goes low. In this manner, an input circuit that stably responds to a small input signal amplitude can be configured. Also, since there is no DC current path from VCC to VSS, the current in standby can be made almost zero.

FIG. 23 shows another embodiment of the input circuit of the CMOS integrated circuit according to the present invention. Here, FIG.
As in the example shown in FIG. 2, a configuration example of the input circuit when VIL = 0 is shown. In the figure, TN110 to TN112 are N-channel transistors, and TP110 to TP113 are P-channel transistors. The reference voltage VREF2 is applied to the gate of TN111. Input is TN110 and TP1
10, the source of TP110 and the source of TN111.
Connected. Here, instead of creating an inverted input signal, the TN111 and TP110 implement complementary operation with the N-channel transistor, that is, an operation that conducts when the input is low and turns off when the input is high. are doing. These TN110, TN111 and TP110 are further combined with TP111 and TP112 to have a level conversion function. The value of the reference voltage VREF2 is VREF2 = VIH + VTN + VTP. Here, VIH is the high level of the input signal, and VTN and VTP are the absolute values of the threshold voltages of the N-channel transistor and the P-channel transistor.

When the voltage of the input IN is 0 (V), T
N110 is turned off, TN111 and TP110 are turned on, the terminal N70 goes low, and the output OUT goes high. Conversely, when the voltage of the input IN is higher than VIH, the TN 111 and the TP 110 are turned off,
N110 becomes conductive, the terminal N70 becomes high level,
The output OUT goes low. In this manner, an input circuit that stably responds to a small input signal amplitude can be configured. Also, since there is no DC current path from VCC to VSS, the current in standby can be made almost zero.

If the input circuit described above is used, the amplitude of the input signal can be reduced while maintaining a sufficient noise margin, so that signal transmission can be performed at high speed. Further, since a transient current due to switching can be reduced, fluctuations in the power supply voltage can be suppressed, and noise margin can be increased. Furthermore, since no DC current is consumed in the standby state, application to battery operation requiring low power consumption is also possible.

Although the present invention has been described in detail with reference to the embodiments, the scope of the present invention is not limited to these embodiments. For example, here, the case where an LSI is constituted by a CMOS transistor and a bipolar transistor has been mainly described, but an LSI using a junction type FET, and an LSI in which an element is formed on a substrate other than silicon, for example, gallium arsenide, etc. But it can be applied as it is.

[0064]

According to the present invention described above, since the signal amplitude can be reduced without reducing the power supply voltage itself, the power consumption, which is a problem with high integration, can be increased. Can provide no LSI. Further, according to the present invention, it is possible to provide an LSI in which the delay time does not increase. Further, according to the present invention, an LSI operating at high speed can be provided.

[Brief description of the drawings]

FIG. 1 is an embodiment illustrating the basic concept of the present invention.

FIG. 2 is a voltage waveform diagram in FIG.

FIG. 3 is an embodiment illustrating the basic concept of the present invention.

FIG. 4 is a conventional circuit.

FIG. 5 shows a circuit according to the invention for comparison with the circuit of FIG.

FIG. 6 Definition of input / output waveform

FIG. 7 is a characteristic comparison result between the circuits of FIGS. 4 and 5 to show the effect of the present invention.

FIG. 8 is a characteristic comparison result between the circuits of FIGS. 4 and 5 to show the effect of the present invention.

FIG. 9 is another embodiment illustrating the basic concept of the present invention.

FIG. 10 is a voltage waveform diagram in FIG.

FIG. 11 is a specific embodiment in which the present invention is applied to a NAND gate circuit.

FIG. 12 is a specific embodiment of a circuit for generating an internal power supply voltage according to the present invention;

FIG. 13 is another embodiment illustrating the basic concept of the present invention using a bipolar transistor.

FIG. 14 is an example of a VCL, VSL, VCLB, and VSLB generation circuit;

FIG. 15 shows another embodiment in which the present invention is used for signal transmission between chips.

FIG. 16 shows another embodiment in which the present invention is used for signal transmission between chips.

FIG. 17 shows another embodiment in which the present invention is applied to a logic circuit.

FIG. 18 shows another embodiment in which the present invention is applied to a logic circuit.

FIG. 19 shows another embodiment in which the present invention is applied to a logic circuit.

FIG. 20 shows another embodiment in which the present invention is applied to a logic circuit.

FIG. 21 shows another embodiment in which the present invention is applied to an input circuit.

FIG. 22 shows another embodiment in which the present invention is applied to an input circuit.

FIG. 23 shows another embodiment in which the present invention is applied to an input circuit.

[Explanation of symbols]

CHP1 to CHP9 ... integrated circuit chips, BLK1 to BL
K13: integrated circuit block, INV1 to INV19: inverter, DRV1 to DRV18: drive circuit, REC2
REC19: receiving circuit, R1 to R13: resistor, Q1
Q21: bipolar transistor, OP1, OP2: differential amplifier circuit, C1 to C12: smoothing capacity.

Continuation of the front page (56) References JP-A-64-19810 (JP, A) JP-A-2-140971 (JP, A) JP-A-63-174422 (JP, A) JP-A-63-107224 (JP) , A) Hikaru 2-53638 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 19/00 H03L 27/00

Claims (7)

(57) [Claims] A first internal circuit operating at a first amplitude; receiving a signal of the first amplitude output from the first internal circuit, and outputting a signal of a second amplitude smaller than the first amplitude; a second 1CMOS circuit block and a CMOS inverter circuit, a signal line having one end to an output of the CMOS inverter times <br/> path of the 1CMOS circuit block is connected, is connected to the other end of said signal line, said first A signal receiving unit for receiving the signal of the second amplitude output from the CMOS inverter circuit of one CMOS circuit block and outputting the signal of the first amplitude, and receiving the signal of the first amplitude output from the signal receiving unit A second CMOS circuit block having a second internal circuit operating at the first amplitude and a second CMOS circuit block on a single semiconductor substrate, wherein a high level and a low level of the second amplitude are equal to the first level.
At a potential between the high level and the low level of the amplitude, wherein the signal receiving unit is connected between an input of the signal receiving unit and a first node;
First MOS of first conductivity type having source / drain path
A transistor, a source connected to a first operating potential, and a
A gate connected to the output and the gate connected to the first node
Second MOS transistor of second conductivity type having drain
Data and the first node and the source connected to the first operating potential
Connected to the gate connected to the gate and the output of the signal receiving unit.
And a third MOS transistor of the second conductivity type
And register, connected between the input and the second node of the signal receiving section
Fourth MOS of second conductivity type having source / drain path
A transistor, a source connected to a second operating potential, and a
A gate connected to the output and a gate connected to the second node
Fifth MOS transistor of first conductivity type having drain and
Motor and said second node and said source connected to the second operating potential
Connected to the gate connected to the gate and the output of the signal receiving unit.
Sixth MOS transistor of the first conductivity type having
Wherein a and a register. 2. The device according to claim 1, wherein a gate of the first MOS transistor is connected to a third operating potential corresponding to a high level of the second amplitude, and a gate of the fourth MOS transistor is connected to a third operating potential of the second amplitude. A semiconductor device connected to a fourth operating potential corresponding to a low level. 3. The method according to claim 1, wherein the first operating potential corresponds to a high level of the first amplitude, and the second operating potential corresponds to a low level of the first amplitude. Characteristic semiconductor device. 4. The second conductivity type according to claim 1, wherein the CMOS inverter circuit has a source connected to a third operating potential that is lower than the first operating potential. 7th MOS
A transistor, a source connected to a fourth operating potential higher than the second operating potential, a gate connected to a gate of the seventh MOS transistor, and a drain connected to a drain of the seventh MOS transistor. And a first conductivity type eighth MOS transistor having the following structure. 5. The method according to claim 4, wherein the third operating potential corresponds to a high level of the second amplitude, and the fourth operating potential corresponds to a low level of the second amplitude. Semiconductor device. 6. The semiconductor device according to claim 1, wherein the magnitude of the second amplitude is less than 1V. 7. The semiconductor device according to claim 1, wherein said first conductivity type is an N-channel, and said second conductivity type is a P-channel.