JP3209140B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an image processing device for computer graphics.

[0002]

2. Description of the Related Art FIGS. 11 to 13 schematically show a conventional three-dimensional computer graphic system.
For convenience of explanation, a part including the main processor 11 and the main memory 12 is called a host system 101, and the image generation device 16
And a portion including the display device 17 will be referred to as an image display system 102.

In FIG. 11 to FIG. 13, a host system 101 and an image display system 102 are connected to a system bus 15.
To exchange data via In FIG. 11, a main processor 11, a main memory 12, and a bus controller 13 exchange data with each other via a processor bus 14. In FIG. 12, the main processor 11 and the path controller 13 are connected by a processor bus 14, and the main memory 12 and the bus controller 13 are connected by a memory bus 18. In FIG. 13, the main processor 11 is directly connected to the system bus 15, and is connected to the main memory 12 by a memory bus 18.

FIG. 14 shows a flow of configuration information data in the conventional three-dimensional computer graphic processing. In the conventional system, the configuration information of the three-dimensional video is taken into the main processor 11 along the route (1), the main processor 11 analyzes the configuration of the three-dimensional video, and the main processor 11 can understand the image generation device 16. Into the drawing commands
The main processor 11 has sent the drawing command to the image generation device 16 along the route (2). As described above, in the conventional system, the main processor 16 directly transmits the configuration information of the three-dimensional video.

In general, elements constituting a three-dimensional video are converted into data in a predetermined format and stored in the main memory 12.
For example, in order to compose a complicated three-dimensional scene in which two quadrangular pyramids are placed on a rectangular parallelepiped as shown in FIG. 8, a configuration information database combining element data as shown in FIG. Stored in memory.

FIG. 15 shows a three-dimensional image processing process of a conventional three-dimensional graphics system. The main processor 11 transmits the three-dimensional configuration information data (as shown in FIG.
This data is read from the data of the object 1, the data of the object 2, and the definition data of the configuration defining the configuration therebetween, processed, and sent to the image generation device 16. Further, the sub-processor 16a in the image generation device 16 sends the drawing commands to the drawing processor 16b as a list of drawing commands that the drawing processor 16b can understand. Drawing processor 16b
Processes the drawing commands and draws appropriately. And 17
The drawing result is output to the display device.

The main role of the sub-processor 16a is to perform geometric transformation processing. In other systems, the main processor 11 performs all the geometric transformation processing, and the sub-processor 16
In some systems, a does not exist.

A drawback of this conventional system is that the main processor 11 is always involved in the process of transmitting the configuration information of the three-dimensional image. For this reason, the load is concentrated on the main processor 11, and in the three-dimensional graphics representation that requires real-time processing such as a simulator, a substantial operation processing time for calculating a moving image scene such as moving an object is reduced. But could not secure enough.

[0009]

As described above, in the conventional three-dimensional graphics system, the main processor 11 directly transfers the configuration information of the three-dimensional video to the image generator 16. For this reason, the main processor 11 cannot spend the majority of the processing time in the data transfer processing, so that the capacity of the main processor 11 cannot be used for substantial arithmetic processing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and reduces the direct data transfer by the main processor and efficiently converts a three-dimensional image without impairing the performance of a recent high-performance main processor. Provide a means to generate.

Further, the configuration information of the three-dimensional video is stored in the memory, and the image generation device retrieves the configuration information from the memory, thereby obviating the need for the main processor to substantially transfer data to the image generation device.

[0012] Further, by making the above-mentioned configuration information into an adaptive data structure, optimal processing can be performed in the generation and efficiency of the configuration information data.

[0013]

An image processing apparatus according to the present invention comprises: an image generating apparatus for generating an image displayed on a display device; a main processor for analyzing a configuration of a three-dimensional image; A memory storing configuration data, data analyzed by the main processor, and data control information for performing information acquisition control of the image generation device;
Wherein the image generating apparatus has means for reading the configuration data and the analysis data from the memory according to the data control information stored in the memory, and generating the image. . The picture
The image generator consists of a data processor and a drawing processor.
Wherein the data processor is stored in the memory
The configuration from the memory according to the data control information
Read the data and the analysis data and draw a drawing command
Means for generating and supplying the same to the drawing processor.
The image generation device has a process in an image generation process .
Notify the processed data or the status of the image generation device
Means for writing data for use in the main memory. The memory of the present invention is a main memory of the main processor, and the image generating device has a unit for directly accessing the main memory. Further, the configuration data of the three-dimensional image includes a code for identifying an element of the data and a parameter. Further, the data is a code capable of identifying the word length of the data. Further, the configuration data of the three-dimensional image includes one or both of the first format data with high data efficiency and the second format data with high conversion efficiency. Further, the image generation device may include a unit that writes at least one of intermediate data, processed data, and data for notifying a state of the image generation device to the memory in an image generation process. Have. Further, the image generation apparatus includes an address translation mechanism corresponding to the virtual storage of the main processor.

In the image processing device according to the present invention, the image generation device accesses a main memory of the main processor.

[0015] In the image processing apparatus according to the present invention, the image generation apparatus may include intermediate data in an image generation process;
At least one of the processed data or the data for notifying the state of the image generating apparatus is written in the memory.

In the image processing device according to the present invention, the image generation device includes an address translation mechanism corresponding to virtual storage of the main processor.

This address translation mechanism is for considering the influence of the virtual memory of the main processor.

In the image processing device according to the present invention, the configuration information of the three-dimensional video includes data control information, and the image generation device interprets and executes the data control information. This enables processing that does not go through the main processor.

In the image processing apparatus according to the present invention, the configuration information of the three-dimensional video includes element data including a code for identifying a word length, and the word length of a data transfer path can be analyzed.

The element data is an element of the configuration information of the three-dimensional video. The element data defines a part or all of the structure in the three-dimensional space. For example, element codes indicating vertices, normals, and the like, vertex X, vertex Y, and vertex Z
And the parameter which is the information constituting the element.

In the image processing apparatus according to the present invention, the configuration information of the three-dimensional video includes one or both of first format data having high data efficiency and second format data having high conversion efficiency.

Good data efficiency means that the amount of data required to express the same configuration information is small, and good conversion efficiency means that the processing by the main processor or the image generating apparatus is easy. What you can do.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 of the Invention Hereinafter, an apparatus and a method according to Embodiment 1 of the present invention will be described.

FIG. 1 is a schematic functional block diagram of an image processing apparatus according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 1 denotes a central processing unit (CPU), which performs operations on an object in a virtual space, obtains information on the object, and performs various controls. 2 is a geometry processor (ge
and performs high-speed geometric transformation (vector calculation) such as coordinate transformation, clipping, and perspective transformation of polygons in three-dimensional computer graphics and luminance calculation. 2a is a polygon material light buffer RAM (polygon material light buffer RAM),
This buffer stores valid polygon data, material data, and write data for one frame when the geometry processor 2 performs processing. A polygon is a polyhedron that forms a solid in a virtual space. The details of the data stored in the buffer memory 2a are as follows.

Link information, coordinate information and other attribute information of polygons LINK X, LINK Y, X, Y, iz, Tx, Ty, Nx, Ny, Sign Nz,
Alpha, Light ID, Material ID, etc.

Material information Depth enable, Depth function, Depth density, Textr
e enable, Fog enable, translucensy enable, textre t
ype, texture function, offset x, y, size x, y, repea
tx, y, mirror x, y, color id, Sine, Material specul
ar, Material emission, Polygon color, Texture mod
e, blend mode, etc.

Light Information Light Position, Light Direction, Light Type, Atten
uation, Cutoff, Spotexp, Light Color, Light Ambient
And so on.

Reference numeral 3 denotes a fill processor for performing a hidden surface erasing process. The fill processor 3 paints the polygons in the area, and obtains information of the nearest polygon for each pixel.

4 is a texture processor (texture proc)
essor). The texture processor 4 pastes a texture on each pixel in the area. Texture mapping is a process of creating an image by pasting (mapping) a pattern (texture) defined separately from a shape on the surface of an object whose shape is defined. 4a is a texture memory (texture RAM) in which a texture map for processing by the texture processor 4 is stored.

5 is a shading processor (shading
processor). Shading is a method of expressing a shadow of an object constituted by polygons in consideration of the normal vector of the polygon, the position and color of the light source, the position of the viewpoint, the direction of the line of sight, and the like. Shading processor 5
Finds the brightness of each pixel in the region. 5a is a frame buffer (frame buffer) in which image data of one screen is stored.
ffer). Data is sequentially read from the frame buffer 5a, converted from digital data into an analog signal, and supplied to a display such as a CRT, a liquid crystal display, or a plasma display (not shown).

Reference numeral 6 denotes a program for the CPU 1 and commands to the graphic processor (a database of polygons,
Program work polygon buffer memory (display work list etc.)
r RAM). The buffer memory 6 is also a work memory of the CPU 1.

The fill processor 3, texture processor 4, and shading processor 5 perform so-called rendering for creating a picture using a model defined in virtual space coordinates. In rendering, each area is processed in order from the upper left of the screen. The rendering process is repeated for the number of regions.

Next, details of the image processing apparatus according to the first embodiment of the present invention will be described with reference to functional block diagrams of FIGS.

FIG. 2 is a functional block diagram of the geometry processor 2. In this figure, reference numeral 21 denotes a data dispatcher, which reads out and analyzes commands from the buffer memory 6, controls the vector engine 22 and the clipping engine 24 based on the analysis result, and sorts the processed data into a sort engine 27. Output to

Reference numeral 22 denotes a vector engine.
And performs a vector operation. The vector to be handled is stored in the vector register 23.

Reference numeral 23 denotes a vector register (vector register).
r), and stores vector data to be operated by the vector engine 22.

24 is a clipping engine (clipping e)
ngine) and performs clipping.

Reference numeral 25 denotes a Y-sort index (Y-sort IND).
EX), and stores the Y index used when performing Y sorting by the sort engine 27.

26 is an X-sort index (X-sort IND)
EX), and stores an X index used when performing X sorting by the sort engine 27.

Reference numeral 27 denotes a sort engine, which performs a X sorting and a Y sorting to search the buffer 6 for polygons that fall into a region of interest. The searched polygon is stored in the buffer memory 2a.
And sent to the fill processor 3 for rendering. The sort engine 27 also controls the polygon TAG 28 and the polygon cache 34.

Reference numeral 28 denotes a polygon TAG (polygon TAG), which is a buffer for storing the TAG of the polygon cache 34.

FIG. 3 is a functional block diagram of the geometry processor 2. In this figure, reference numeral 31 denotes a cache controller, which controls material caches 42, 45, 51b, 52a, 53a and a write cache 51a to be described later.

32 is a material TAG (material TAG)
And material caches 42, 45, and 51 described below.
b, 52a, 53a and TA of the write cache 51a
Save G.

Reference numeral 33 denotes a light TAG (light TAG), which is a buffer for storing a TAG of a write cache 51a described later.

Reference numeral 34 denotes a polygon cache (polygon cache).
e) is a cache memory for polygon data.

35 is an initial parameter calculator (initial pa
rameter calculator) to obtain the initial value of DDA.

Reference numeral 36 denotes a Z comparator array.
or array), Z comparison is performed between polygons for hidden surface removal processing, and polygon ID and internal division ratio t0,
Embed t1 and t2. Z comparator array 36 is 8
X8 = 64 Z comparators. Since these operate in parallel, it is possible to process 64 pixels at the same time. One Z comparator stores data on polygons. For example, polygon ID, iz, t0,
t1, t2, window, stencil, shadow, etc.

37 is a vertex parameter buffer (vertex p)
arameter buffer), which is a buffer that stores the parameters at the vertices of the polygon. It has a size of 64 polygons corresponding to the Z comparator array 36.

Reference numeral 38 denotes an interpolator.
Pixel parameters are interpolated and calculated based on the calculation results t0, t1, t2 and iz of the comparator array 36 and the contents of the vertex parameter buffer 37.

FIG. 4 is a functional block diagram of the texture processor 4. In this figure, 41 is a concentration calculator (de
nsity calculator), which calculates the blend ratio for fog or depth cuing.

Reference numeral 42 denotes a material cache (material c)
ache), and data related to depth information is stored.
For example, Depth enable, Depth function, Depth densit
y, Depth end z, Texture enable, Fog enable, etc.

Reference numeral 43 denotes a window register (window regis).
ter), which is a buffer for storing information about the window. For example, kz, cz, fog function, fog dens
ity, fog end z 44 is an address generator,
An address on the texture map is calculated from the texture coordinates Tx, Ty and LOD.

45 is a material cache (material c)
ache), and data on the material is stored. For example, translucensy enable, texture type, offset x, y,
size x, y, repeat x, y, mirror x, y, color id, etc.

Reference numeral 46 denotes a TLMMI calculator (TLMMI calculat) for performing trilinear mipmap interpolation as three-dimensional interpolation.
or, TLMMI: Tri Linear MIP Map Interpolation). The mipmap is a technique for anti-aliasing when performing texture mapping, that is, a technique for eliminating texture jaggies. This is based on the following principle. Originally, the color (luminance) of the object plane projected onto one pixel must be the average value of the colors of the corresponding mapping area. Otherwise the jaggies will be noticeable and the quality of the texture will be significantly reduced. On the other hand, if the processing for obtaining the average is performed each time, the calculation load becomes excessive, the processing takes time, and a high-speed processor is required. Mip maps are intended to solve this. In the mipmap, in order to simplify the calculation of the color (luminance) of the mapping area corresponding to one pixel,
A plurality of mapping data having a multiple width of 2 is prepared in advance. The size of all the mapping areas corresponding to one pixel will be between any two data of multiples of these two. The color of the corresponding mapping area is determined by comparing these two data. For example,
When there is a screen A of 1 time and a screen B of 1/2 time, 1 /
Pixels of screens A and B corresponding to each pixel of screen C of 1.5 times are obtained. At this time, the color of the pixel on the screen C is an intermediate color between the pixel on the screen A and the pixel on the screen B.

Reference numeral 47 denotes a color converter.
r), color conversion is performed at the time of 4-bit texel.

Reference numeral 48 denotes a color pallet, which stores color information at the time of 4-bit texels.
The color palette 48 stores colors used when writing graphics. 1 corresponding to the contents of the color palette 48
The colors that can be used for one pixel are determined.

FIG. 5 is a functional block diagram of the shading processor 5. In this drawing, reference numeral 51 denotes a luminance processor (intensity processor) which performs luminance calculation on a polygon after texture mapping.

Reference numeral 51a denotes a light cache (light cache).
e) to store the write information. For example, Light Pos
ition, Light Direction, Light Type, Attenuation, C
utoff, Spotexp, Light Color, Light Ambient, etc.

51b is a material cache (material cache)
cache), which stores information about the material. Sine,
Material specular, material emission, etc.

Reference numeral 51c denotes a window register (window reg)
ister) and stores information about the window. S
creen center, Focus, Scene ambient.

Reference numeral 52 denotes a modulate processor (modulate pro
cessor), which associates polygon colors with texture colors, performs luminance modulation, and performs fog processing.

[0062] 52a is a material cache (material cache).
cache), which stores information about the material. For example, Polygon color, Texture mode, etc.

Reference numeral 52b denotes a window register (window reg
is a buffer for storing information about the window. Fog color.

Reference numeral 53 denotes a blend processor (blend processo).
r), the data is blended with the data in the color buffer 54 and written into the color buffer 54. The blend processor 53 blends the current pixel color with the pixel color of the frame buffer based on the value of the blend rate register, and writes the blended pixel color to the frame buffer of the bank indicated by the write bank register. Blender 5
According to No. 3, afterimage processing can be performed.

Reference numeral 53a denotes a material cache (material cache)
cache), which stores information about the material. blend
mode.

A color buffer 54 is a color buffer having a size of 8 × 8. It has a double bank structure.

Reference numeral 55 denotes a plot processor.
And writes the data in the color buffer 54 into the frame buffer 5a.

Reference numeral 56 denotes a bitmap processor (bitmap processor).
ssor) and performs bitmap processing.

Reference numeral 57 denotes a display controller (display control)
roller), reads data from the frame buffer 5a, supplies the data to a DAC (Digital to Analog Converter), and displays the data on a display (not shown).

FIG. 6 shows Embodiment 1 of the invention shown in FIGS.
Is simplified for easy understanding. For convenience of explanation, a portion including the main processor 11 and the main memory 12 will be referred to as a host system 101, and a portion including the image generation device 16 and the display device 17 will be referred to as an image display system 102.

In FIG. 6, data is exchanged between the host system 101 and the image display system 102 via the system bus 15. Main processor 11, main memory 1
2. The bus controller 13 communicates with the processor bus 14
To exchange data.

In FIG. 6, the configuration information of the three-dimensional video is fetched into the main processor 11 along the route (1), and the main processor 11 analyzes the configuration of the three-dimensional video. Further, the image generating device 16 reads and writes the configuration information of the three-dimensional video with the main memory 12 along the route (3).

The features of the device according to the first embodiment of the present invention are as follows.
The route (3) is used by the image generation device 16. On the host system 101, the bus controller 1
3 appears to be accessing main memory 12,
It is the image generation device 16 that issues the instruction. That is, the image generation device 16 has the master right to the host system 101. Therefore,
The load on the main processor 11 is reduced, and the efficiency and speed of the processing can be improved by concentrating on the original processing.

Next, the processing of the three-dimensional graphic system will be described using the configuration of the three-dimensional video shown in FIG. 8 as an example. This example shows an object having two rectangular pyramids on a rectangular parallelepiped. This object is defined by being divided into a rectangular parallelepiped part and a quadrangular pyramid part. Each part of the object is
The object 1 and the object 2 are defined as a set of a plurality of elements (triangles). An element (triangle) is defined by three vertices, and the vertices are defined by coordinates (X, Y, Z).

FIG. 7 shows a three-dimensional image processing process of the three-dimensional graphics system according to the first embodiment of the present invention. In this system, the main processor 11 basically operates only on the matrix data defining the object.
To generate the scene, the data processor 16c in the image generating device 16 directly processes the configuration information data, generates a drawing command, and sends it directly to the drawing processor 16b. In this manner, drawing is not performed via the main processor 11.

In the conventional case, as shown in FIG.
Although the configuration definition data and the object definition data are linked, in the first embodiment of the present invention, as shown in FIG. 7, a code for controlling the data is incorporated in the configuration information data. In the example of FIG. 7, both are connected by "call" and "return". In the case of the matrix 1 in the configuration definition data, the object 2 is called. The elements in the definition data of the object 2 are accessed sequentially (triangles 7 to 18), and when the access ends, the process returns. Similarly, in either case of matrices 2 and 3, after the object 1 is called and the elements are accessed sequentially (triangles 1 to 6), it returns.

As shown in FIG. 9, in the element data of the configuration information of the system according to the first embodiment of the present invention, a code for identifying what kind of element the element data is embedded in the data. One-word type element data includes one element code, two-word type element data includes one element code and one parameter, and four-word type element data includes one element code and three parameters. The eight-word type element data includes one element code and seven parameters.

The elements are, for example, vertices, normals, and the like, and the parameters are vertices X, Y, and Z.
Is the information that makes up the element.

There are various types of elements, and the number of necessary parameters also varies. Therefore, the data length information including the parameter is included in the element code so that the data transfer path can know the data length independently.

FIG. 10 shows an example of surface data. The figure shows two configurations. FIG. 10A shows a combination type including normal word element data of four words and position element data of four words. FIG. 10B shows a pack type including four-word surface element data. In this type, one word includes two pieces of information, a normal line and a position.
Although the type of FIG. 10A has a long total data length,
It is easy for the main processor 11 to directly operate the parameters. On the other hand, in the type of FIG. 10B, the data length is short, but it is difficult for the main processor 11 to directly operate the parameters. Thus, each has its advantages and disadvantages. It is important to note that the system can take either form.
Users of the system can choose to take advantage of their strengths.

As described above, according to the first embodiment of the present invention, the following features are provided.

(1) The image generating apparatus can access the host system with the master right.

(2) The configuration information data of the three-dimensional video can be analyzed and processed by the image generating apparatus.

(3) The configuration information data of the three-dimensional video includes a code for controlling the data.

(4) The element data of the configuration information data of the three-dimensional video contains a code for identifying the word length.

(5) There are a plurality of configuration information data forms in which the processing results are the same.

With the above features, the following excellent effects can be obtained.

(1) The overhead due to the data transfer of the main processor is eliminated, and the main processor can concentrate on the substantial processing.

(2) A data buffer memory such as a FIFO or a buffer can be reduced or eliminated, and a system can be realized with no cost.

(3) The configuration information of the three-dimensional video can be defined in advance as fixed data. In particular, continuous frames can be generated with a minimum amount of information operation in moving image processing.

(4) Since data control information is provided in the configuration information itself of the three-dimensional video and the data is not controlled by the main processor but is controlled by the image generation device,
Scenes can be generated independently of the main processor operation.

(5) The configuration information of the three-dimensional video can be optimally dealt with when the efficiency of the data size is emphasized, when the efficiency of data generation is emphasized, or in an intermediate case.

As described above, in short, the optimum processing can be performed in the generation and efficiency of the configuration information data.

[0094]

As described above, according to the present invention, a main processor for analyzing the configuration of a three-dimensional video, a memory for storing configuration information of the three-dimensional video, and an image based on the configuration information of the three-dimensional video. Since the image generation device accesses the memory, there is no overhead due to data transfer, and the main processor can concentrate on substantial arithmetic processing. Therefore, optimal processing can be performed in the generation and efficiency of the configuration information data.

Further, according to the present invention, the configuration information of the three-dimensional video includes data control information, and the image generation device interprets and executes the data control information, thereby enabling processing not via the main processor. . Therefore, optimal processing can be performed in the generation and efficiency of the configuration information data.

Further, according to the present invention, since the configuration information of the three-dimensional video includes element data including a code for identifying a word length, the word length of the data transfer path can be analyzed. Even when there are various types of elements, it is possible to appropriately cope by knowing the data length on the data transfer path.

According to the present invention, the configuration information of the three-dimensional video includes one or both of the first format data having high data efficiency and the second format data having high conversion efficiency. The configuration information of the two-dimensional video can be optimally dealt with when importance is placed on the efficiency of the data size, when importance is placed on the efficiency of data generation, or when the efficiency is intermediate.

[Brief description of the drawings]

FIG. 1 is a schematic functional block diagram of an image processing apparatus according to Embodiment 1 of the present invention.

FIG. 2 is a functional block diagram of a geometry processor of the image processing device according to the first embodiment of the present invention.

FIG. 3 is a functional block diagram of a geometry processor of the image processing device according to the first embodiment of the present invention.

FIG. 4 is a functional block diagram of a texture processor of the image processing device according to the first embodiment of the present invention.

FIG. 5 is a functional block diagram of a shading processor of the image processing device according to the first embodiment of the present invention.

FIG. 6 is a block diagram schematically showing a three-dimensional computer graphic system according to the first embodiment of the present invention.

FIG. 7 is an explanatory diagram of a three-dimensional video processing process of the three-dimensional computer graphic system according to the first embodiment of the present invention.

FIG. 8 is an example of a configuration of a three-dimensional video.

FIG. 9 is an example of element data of configuration information of the system according to the first embodiment of the present invention.

FIG. 10 is a diagram showing an example of surface data according to the first embodiment of the present invention. FIG. 10A shows a combination type including normal word element data of four words and position element data of four words. FIG. 10B shows a pack type including four-word surface element data.

FIG. 11 schematically shows a conventional three-dimensional computer graphic system.

FIG. 12 schematically shows a conventional three-dimensional computer graphic system.

FIG. 13 schematically shows a conventional three-dimensional computer graphic system.

FIG. 14 is a diagram showing a flow of configuration information data in conventional three-dimensional computer graphic processing.

FIG. 15 shows a three-dimensional image processing process of a conventional three-dimensional graphics system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Geometry processor 2a Polygon material light buffer memory 3 Fill processor 4 Texture processor 4a Texture memory 5 Shading processor 5a Frame buffer 6 Program work polygon buffer memory 11 Main processor 12 Main memory 13 Bus controller 14 Processor bus 15 System bus 16 Image Generating Device 17 Display Device 18 Memory Bus 21 Data Dispatcher 22 Vector Engine 23 Vector Register 24 Clipping Engine 25 Y Sort Index 26 X Sort Index 27 Sort Engine 28 Polygon TAG 31 Cache Controller 32 Material TAG 33 Write TAG 34 Polygon Cache 35 Initial Parameter calculator 6 Z Comparator Array 37 Vertex Parameter Buffer 38 Interpolator 41 Density Calculator 42 Material Cache 43 Window Register 44 Address Generator 45 Material Cache 46 TLMMI Calculator 47 Color Comparator 48 Color Palette 51 Brightness Processor 51a Write Cache 51b Material Cache 51c Window Register 52 Modulator 52a Material cache 52b Window register 53 Blend processor 53a Material cache 54 Color buffer 55 Plot processor 56 Bitmap processor 57 Display controller 101 Host system 102 Image display system

Continuation of the front page (56) References JP-A-6-162214 (JP, A) JP-A-7-262387 (JP, A) JP-A-6-59651 (JP, A) JP-A-5-266201 (JP) JP-A 7-320070 (JP, A) JP-A 7-282273 (JP, A) JP-A 7-73333 (JP, A) JP-A 7-98766 (JP, A) 6-4488 (JP, A) JP-A-5-260476 (JP, A) U.S. Pat. No. 5,218,678 (US, A) "Library Reference Software Development Tool", Sony Computer Entertainment Inc., 1996 Published in June, full text "User's Guide Software Development Tool", Sony Computer Entertainment Inc., published in June 1996, full text (58) surveyed Field (Int.Cl. ^7, DB name) G06T 15/00 100 G06T 17/00 JICST file (JOIS) WPI (DIALOG)

Claims (4)

(57) [Claims] An image generation device that generates an image displayed on a display device; a main processor that analyzes a configuration of a three-dimensional image; configuration data of the three-dimensional image; data analyzed by the main processor; A main memory for storing data control information for performing information acquisition control of the image generation apparatus, wherein the main processor and the main memory form a host system, and the image generation apparatus The main memory can be accessed by instructing a bus controller with master right, and the image generation device is a data processor and a drawing processor.
Consists of a, the data processor, the said configuration data and reads the analysis data from the memory in accordance with the data control information stored in the memory, rendering co
Made this by generating a command comprises means for supplying to the drawing processor, the image generation apparatus Zhou of processed data or the image generating apparatus in the course of image generation
Means for writing data for notifying the status to the main memory, and wherein the configuration data of the three-dimensional image includes the data control information. 2. The image processing apparatus according to claim 1, wherein the configuration data of the three-dimensional image includes a code for identifying an element of the data and a parameter. 3. The image processing apparatus according to claim 2, wherein the data is a code capable of identifying a word length of the data. 4. The configuration data of the three-dimensional image includes one or both of first format data with high data efficiency and second format data with high conversion efficiency. Item 3. The image processing device according to item 1 or 2.