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JP3200270B2 - Surface conduction electron-emitting device, electron source, and method of manufacturing image forming apparatus - Google Patents

Surface conduction electron-emitting device, electron source, and method of manufacturing image forming apparatus

Info

Publication number
JP3200270B2
JP3200270B2 JP33110393A JP33110393A JP3200270B2 JP 3200270 B2 JP3200270 B2 JP 3200270B2 JP 33110393 A JP33110393 A JP 33110393A JP 33110393 A JP33110393 A JP 33110393A JP 3200270 B2 JP3200270 B2 JP 3200270B2
Authority
JP
Japan
Prior art keywords
electron
surface conduction
emitting device
emitting
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP33110393A
Other languages
Japanese (ja)
Other versions
JPH07192614A (en
Inventor
正人 山野辺
英俊 鱸
一郎 野村
武夫 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP33110393A priority Critical patent/JP3200270B2/en
Application filed by Canon Inc filed Critical Canon Inc
Priority to CA002299957A priority patent/CA2299957C/en
Priority to CA002126509A priority patent/CA2126509C/en
Priority to CA002418595A priority patent/CA2418595C/en
Priority to CA002540606A priority patent/CA2540606C/en
Priority to DE69435336T priority patent/DE69435336D1/en
Priority to AT99112412T priority patent/ATE501519T1/en
Priority to AT94109787T priority patent/ATE237185T1/en
Priority to EP94109787A priority patent/EP0660357B1/en
Priority to AU65922/94A priority patent/AU6592294A/en
Priority to US08/264,497 priority patent/US6169356B1/en
Priority to DE69432456T priority patent/DE69432456T2/en
Priority to EP99112412A priority patent/EP0942449B1/en
Priority to AT01104026T priority patent/ATE381109T1/en
Priority to AT07118989T priority patent/ATE523893T1/en
Priority to CNB2004100039544A priority patent/CN1306540C/en
Priority to CN94109010A priority patent/CN1086055C/en
Priority to EP01104026A priority patent/EP1124248B1/en
Priority to EP07118989A priority patent/EP1892743B1/en
Priority to DE69435051T priority patent/DE69435051T2/en
Priority to CNB200610100715XA priority patent/CN100438589C/en
Priority to KR1019940014559A priority patent/KR0154358B1/en
Publication of JPH07192614A publication Critical patent/JPH07192614A/en
Priority to KR1019980014201A priority patent/KR0170822B1/en
Priority to US09/332,101 priority patent/US6802752B1/en
Priority to US09/332,100 priority patent/US6384541B1/en
Priority to US09/513,841 priority patent/US6344711B1/en
Priority to CNB001083791A priority patent/CN1174460C/en
Priority to CNB001085654A priority patent/CN1174459C/en
Application granted granted Critical
Publication of JP3200270B2 publication Critical patent/JP3200270B2/en
Priority to US10/615,995 priority patent/US6908356B2/en
Priority to US10/776,171 priority patent/US6890231B2/en
Priority to US11/008,925 priority patent/US7348719B2/en
Priority to US12/037,684 priority patent/US7705527B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2201/00—Electrodes common to discharge tubes
    • H01J2201/30—Cold cathodes
    • H01J2201/316—Cold cathodes having an electric field parallel to the surface thereof, e.g. thin film cathodes
    • H01J2201/3165—Surface conduction emission type cathodes

Landscapes

  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
  • Cold Cathode And The Manufacture (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、表面伝導形電子放出素
子、電子源、及び、画像形成装置の製造方法に関する発
明である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface conduction electron-emitting device , an electron source , and a method of manufacturing an image forming apparatus.

【０００２】[0002]

【従来の技術】従来、電子放出素子として熱電子源と冷
陰極電子源の２種類が知られている。2. Description of the Related Art Conventionally, two types of electron emitting devices, a thermionic electron source and a cold cathode electron source, are known.

【０００３】そのうち、冷陰極電子源としては、電界放
出型（以下、ＦＥと略す）、金属／絶縁層／金属−型
（以下、ＭＩＭと略す）や表面伝導形電子放出素子等が
ある。The cold cathode electron sources include a field emission type (hereinafter abbreviated as FE), a metal / insulating layer / metal-type (hereinafter abbreviated as MIM), and a surface conduction electron-emitting device.

【０００４】上記ＦＥの例としては、W.P.Dyke & W.W.D
olan,"Fieldemission",Advance inElectron Physics,8,
89(1956) 、あるいは、C.A.Spindt,"Physical properti
esof thin-film field emission cathodes with Molybd
enium cones",J.Appl.Phys,47,5248(1976)などが知られ
ている。As an example of the above FE, WPDyke & WWD
olan, "Fieldemission", Advance inElectron Physics, 8,
89 (1956) or CASpindt, "Physical properti
esof thin-film field emission cathodes with Molybd
enium cones ", J. Appl. Phys., 47, 5248 (1976).

【０００５】上記ＭＩＭの例としては、C.A.Mead,"The
tunnel-emission amplifier", J.Appl. Phys,32,646(19
61) などが知られている。As an example of the above-mentioned MIM, CAMead, "The
tunnel-emission amplifier ", J. Appl. Phys, 32, 646 (19
61) are known.

【０００６】上記表面伝導形電子放出素子の例として
は、M.I.Elinson,Radio Eng.ElectronPhys.,10(1965)
などが知られている。As an example of the above surface conduction electron-emitting device, see MIElinson, Radio Eng. ElectronPhys., 10 (1965).
Etc. are known.

【０００７】ここで表面伝導形電子放出素子は、基板上
に形成された小面積の薄膜に、膜面に平行に電流を流す
ことにより、電子放出が生ずる現象を利用するものであ
る。この表面伝導形電子放出素子としては、前記エリン
ソン等によるＳｎＯ2 薄膜を用いたもののほかに、Ａｕ
薄膜によるもの［G.Dittmer:"Thin Solid Films",9,317
(1972)］、Ｉｎ2 Ｏ3 ／ＳｎＯ2 薄膜によるもの［M.Ha
rtwell and C.G.Fonstad:"IEEE Trans.ED Conf.",519(1
975)］、カーボン薄膜によるもの［荒木久 他：真空、
第２６巻、第１号、２２頁（１９８３）］等が報告され
ている。Here, the surface conduction electron-emitting device utilizes the phenomenon that electron emission occurs when a current flows in a small-area thin film formed on a substrate in parallel with the film surface. As this surface conduction electron-emitting device, in addition to the device using the SnO 2 thin film by Elinson et al.
By thin film [G. Dittmer: "Thin Solid Films", 9,317
(1972)], using an In 2 O 3 / SnO 2 thin film [M.Ha
rtwell and CGFonstad: "IEEE Trans.ED Conf.", 519 (1
975)], using a carbon thin film [Hisashi Araki et al .: Vacuum,
26, No. 1, p. 22 (1983)].

【０００８】これらの表面伝導形電子放出素子の典型的
な素子構成として前述のＭ．ハートウェルの素子構成を
図１６に示す。同図において４３１は絶縁性基板、４３
２は電子放出部形成用薄膜で、Ｈ型形状のパターンに、
スパッタで形成された金属酸化物薄膜等からなり、後述
のフォーミングと呼ばれる通電処理により電子放出部４
３３が形成される。尚、図１６中、素子の長さＬ１は約
０．５ｍｍ〜ｌｍｍ、素子の幅Ｗ１は約０．１ｍｍであ
る。また、４３４は電子放出部を含む薄膜と呼ぶ。As a typical device configuration of these surface conduction electron-emitting devices, the above-mentioned M.S. FIG. 16 shows an element configuration of the Hartwell. In the figure, reference numeral 431 denotes an insulating substrate;
Reference numeral 2 denotes a thin film for forming an electron-emitting portion, which has an H-shaped pattern,
The electron emission portion 4 is made of a metal oxide thin film or the like formed by sputtering.
33 are formed. In FIG. 16, the element length L1 is about 0.5 mm to 1 mm, and the element width W1 is about 0.1 mm. Reference numeral 434 denotes a thin film including an electron-emitting portion.

【０００９】従来、これらの表面伝導形電子放出素子に
おいては、電子放出を行う前に電子放出部形成用薄膜４
３２を予めフォーミングと呼ばれる通電処理によって電
子放出部４３３を形成するのが一般的であった。即ち、
フォーミングとは前記電子放出部形成用薄膜４３２の両
端に電圧印加し通電処理することで、電子放出部形成用
薄膜を局所的に破壊、変形もしくは変質せしめ、電気的
に高抵抗な状態にした電子放出部４３３を形成すること
である。このようにフォ−ミング処理を施した表面伝導
形電子放出素子は、上記電子放出部を含む薄膜４３４に
電圧を印加し、素子に電流を流すことにより、上記電子
放出部４３３より電子を放出せしめるものである。Conventionally, in these surface conduction electron-emitting devices, the electron-emitting portion forming thin film
In general, the electron emission portion 433 is generally formed by applying an energization process called “forming” beforehand. That is,
Forming is a process in which a voltage is applied to both ends of the thin film 432 for forming an electron emission portion and a current is applied to the thin film 432 for forming an electron emission portion to locally destroy, deform or alter the thin film for forming the electron emission portion, thereby forming an electron with a high resistance state. That is, forming the emission part 433. In the surface conduction type electron-emitting device subjected to the forming process as described above, a voltage is applied to the thin film 434 including the electron-emitting portion and a current flows through the device, so that the electron-emitting portion 433 emits electrons. Things.

【００１０】[0010]

【発明が解決しようとする課題】しかしながら、上述の
フォ−ミング処理は、本質的に通電によるジュ−ル熱に
よる薄膜の部分的な破壊または変質を起こさせる工程で
あり、以下のような問題点があった。 １）フォ−ミング時に薄膜の適度な破壊または変質に必
要な電力以上の過電力投入による、該薄膜への極度のダ
メ−ジ、電子放出特性への悪影響、または電極の破壊を
生じる。 ２）フォ−ミング電圧が素子抵抗に依存するため、素子
抵抗のバラツキによる過電力投入をもたらす。However, the above-mentioned forming process is essentially a step of causing partial destruction or deterioration of the thin film by Joule heat due to energization, and has the following problems. was there. 1) Excessive power supply beyond the power required for proper destruction or alteration of the thin film during forming causes extreme damage to the thin film, adverse effects on the electron emission characteristics, or destruction of the electrode. 2) Since the forming voltage depends on the element resistance, an over-power is supplied due to the variation of the element resistance.

【００１１】以上のような問題を回避するために、本出
願人は特開平４−２８１３９号公報に記載の通り、パル
ス電圧によるフォ−ミングの実施を提案した。しかしな
がら、より一層の電子放出特性の均一化を図るためには
更なる改善が要求される。In order to avoid the above-mentioned problems, the present applicant has proposed forming with a pulse voltage as described in Japanese Patent Application Laid-Open No. 4-28139. However, further improvement is required to further uniform the electron emission characteristics.

【００１２】そこで本発明の目的は、表面伝導形電子放
出素子の製造工程における、素子劣化や電子放出特性の
バラツキを低減させ、均一な電子放出特性を有する表面
伝導形電子放出素子の提供とその製造方法を提供するこ
とである。SUMMARY OF THE INVENTION An object of the present invention is to provide a surface conduction electron-emitting device having uniform electron emission characteristics by reducing device deterioration and variations in electron emission characteristics in the process of manufacturing the surface conduction electron-emitting device, and providing the same. It is to provide a manufacturing method.

【００１３】更に本発明は、上記均一な電子放出特性を
有する表面伝導形電子放出素子を用い、輝度むらの少な
い高品位の画像を形成し得る電子源及び画像形成装置を
提供することを目的とする。A further object of the present invention is to provide an electron source and an image forming apparatus capable of forming a high-quality image with less uneven brightness by using the above-mentioned surface conduction electron-emitting device having uniform electron emission characteristics. I do.

【００１４】[0014]

【課題を解決する為の手段】以上の目的を達成する本発
明は、電極間に、電子放出部を含む薄膜を有する表面伝
導形電子放出素子の製造方法において、該電子放出部の
形成工程が、該電極間に、波高値をステップ状に増加さ
せた複数のパルス電圧を印加するとともに該複数のパル
ス電圧の間に素子電流を測定するための電圧を印加する
工程を有することを特徴とする表面伝導形電子放出素子
の製造方法である。According to the present invention, which achieves the above objects, there is provided a method of manufacturing a surface conduction electron-emitting device having a thin film including an electron-emitting portion between electrodes. Between the electrodes, the peak value is increased stepwise.
The plurality of pulse applied with a plurality of pulse voltages was
Is a manufacturing method of the surface conduction electron-emitting device characterized by having a more <br/> Engineering for applying a voltage for measuring the device current between the scan voltage.

【００１５】更に本発明は、表面伝導形電子放出素子を
有し、入力信号に応じて電子を放出する電子源の製造方
法において、該表面伝導形電子放出素子が、上記本発明
の製造方法にて製造されることを特徴とする電子源の製
造方法、及び、表面伝導形電子放出素子と画像形成部材
とを有し、入力信号に応じて画像を形成する画像形成装
置の製造方法において、該表面伝導形電子放出素子が、
上記本発明の製造方法にて製造されることを特徴とする
画像形成装置の製造方法である。The present invention further provides a surface conduction electron-emitting device.
Method of manufacturing an electron source that emits electrons in response to an input signal
In the method, the surface conduction electron-emitting device may be the same as that of the present invention.
Production of an electron source characterized by being produced by the production method of
Fabrication method, surface conduction electron-emitting device and image forming member
And an image forming apparatus for forming an image in accordance with an input signal.
In the method of manufacturing a device, the surface conduction electron-emitting device may be:
It is manufactured by the manufacturing method of the present invention.
4 is a method for manufacturing an image forming apparatus .

【００１６】以下に本発明の好ましい態様について詳述
する。Hereinafter, preferred embodiments of the present invention will be described in detail.

【００１７】本発明に係る、とりわけ好ましい表面伝導
形電子放出素子の構成及び製造方法の基本的な特徴とし
ては、次の様なものが挙げられる。 （１）フォーミングとよばれる通電処理の前の電子放出
部形成用薄膜は、微粒子分散体を分散し形成された微粒
子からなる薄膜、あるいは、有機金属等を加熱焼成し形
成された微粒子からなる薄膜等の、基本的には、微粒子
より構成される。 （２）フォーミングとよばれる通電処理の後の電子放出
部を含む薄膜は、電子放出部、電子放出部を含む薄膜と
もに、基本的には、微粒子より構成される。The basic features of the structure and manufacturing method of a particularly preferred surface conduction electron-emitting device according to the present invention include the following. (1) The thin film for forming the electron-emitting portion before the energization treatment called forming is a thin film composed of fine particles formed by dispersing a fine particle dispersion, or a thin film formed by heating and firing an organic metal or the like. Basically, it is composed of fine particles. (2) The thin film including the electron emitting portion after the energization process called forming is basically composed of fine particles together with the electron emitting portion and the thin film including the electron emitting portion.

【００１８】まず、本発明の表面伝導形電子放出素子の
製造方法について、その好ましい態様例を挙げ、以下
に、図２及び図４を用いて順を追って説明する。 １）基板１を洗剤、純水および有機溶剤により十分に洗
浄後、真空蒸着法、スパッタ法等により素子電極材料を
堆積後、フォトリソグラフィー技術により該基板１の面
上に素子電極５、６を形成する（図２の（ａ））。 ２）基板１上に設けられた素子電極５と素子電極６との
間の基板１上に、有機金属溶液を塗布して放置すること
により、有機金属薄膜を形成する。First, a method of manufacturing a surface conduction electron-emitting device according to the present invention will be described with reference to FIG. 2 and FIG. 1) After sufficiently washing the substrate 1 with a detergent, pure water and an organic solvent, depositing element electrode materials by vacuum evaporation, sputtering, or the like, and then depositing the element electrodes 5 and 6 on the surface of the substrate 1 by photolithography. (FIG. 2A). 2) An organic metal solution is applied on the substrate 1 between the element electrodes 5 and 6 provided on the substrate 1 and left to form an organic metal thin film.

【００１９】尚、有機金属溶液とはＰｄ、Ｒｕ、Ａｇ、
Ａｕ、Ｔｉ、Ｉｎ、Ｃｕ、Ｃｒ、Ｆｅ、Ｚｎ、Ｓｎ、Ｔ
ａ、Ｗ、Ｐｂ等の金属を主元素とする有機化合物の溶液
である。The organic metal solution is Pd, Ru, Ag,
Au, Ti, In, Cu, Cr, Fe, Zn, Sn, T
This is a solution of an organic compound containing a metal such as a, W, and Pb as a main element.

【００２０】この後、有機金属薄膜を加熱焼成処理し、
リフトオフ、エッチング等によりパターニングし、電子
放出部形成用薄膜２を形成する（図２の（ｂ））。Thereafter, the organic metal thin film is heated and baked,
Patterning is performed by lift-off, etching, or the like to form the electron-emitting-portion-forming thin film 2 (FIG. 2B).

【００２１】尚、ここでは有機金属溶液の塗布法により
説明したが、これに限る物でなく、真空蒸着法、スパッ
タ法、化学的気相堆積法、分散塗布法、ディッピング
法、スピンナー法等によって形成される場合もある。 ３）次に、フォーミングと呼ばれる通電処理を、素子電
極５、６間に電圧を不図示の電源により、パルス電圧に
よって行うと、電子放出部形成用薄膜２の部位に構造の
変化した電子放出部３が形成される（図２の（ｃ））。Although the description has been given of the method of applying an organic metal solution here, the present invention is not limited to this, but may be applied by a vacuum deposition method, a sputtering method, a chemical vapor deposition method, a dispersion coating method, a dipping method, a spinner method, or the like. It may be formed. 3) Next, an energization process called forming is performed by applying a voltage between the device electrodes 5 and 6 with a power supply (not shown) by a pulse voltage. 3 is formed (FIG. 2C).

【００２２】この通電処理により電子放出部形成用薄膜
２を局所的に破壊、変形もしくは変質せしめ、構造の変
化した部位を電子放出部３と呼ぶ。The electron-emitting portion forming thin film 2 is locally destroyed, deformed or deteriorated by the energization process, and a portion having a changed structure is called an electron-emitting portion 3.

【００２３】ここで、本発明の製造方法を特徴付ける、
上記フォ−ミング処理におけるパルス電圧の印加は、パ
ルス波高値を増加させながら行われる。Here, the manufacturing method of the present invention is characterized.
The application of the pulse voltage in the forming process is performed while increasing the pulse peak value.

【００２４】図４に、本発明に係る上記フォーミング処
理の電圧波形の一例を示す。FIG. 4 shows an example of a voltage waveform of the forming process according to the present invention.

【００２５】図４中、Ｔ１及びＴ２は電圧波形のパルス
幅とパルス間隔であり、Ｔ１を１マイクロ秒〜１０ミリ
秒、Ｔ２を１０マイクロ秒〜１００ミリ秒とし、三角波
の波高値（フォーミング時のピーク電圧）は、例えば、
０．１Ｖステップ程度づつ増加させながら、１０のマイ
ナス５乗程度の真空雰囲気下で、該パルス電圧の印加が
行われる。In FIG. 4, T1 and T2 are the pulse width and pulse interval of the voltage waveform, T1 is 1 microsecond to 10 milliseconds, T2 is 10 microseconds to 100 milliseconds, and the peak value of the triangular wave (at the time of forming). Peak voltage) is, for example,
The pulse voltage is applied in a vacuum atmosphere of about 10 to the fifth power while increasing in steps of about 0.1 V.

【００２６】また、本発明に係る上記フォ−ミング処理
は、好ましくは、上記パルス間隔Ｔ２の間に、電子放出
部形成用薄膜２を局所的に破壊、変形しない程度の電
圧、例えば、０．１Ｖ程度の電圧を素子電極５、６間に
不図示の電源により印加し、該素子に流れる電流（素子
電流）を測定して、該素子の抵抗値（素子抵抗）を求
め、この抵抗値が、例えば、１Ｍオ−ム以上の抵抗値を
示した時に、上記フォ−ミング処理を終了させる工程を
有する。尚、この時の電圧を、以下、フォ−ミング電圧
ＶＦと呼ぶ事とする。The forming process according to the present invention is preferably such that a voltage which does not locally damage or deform the electron-emitting-portion-forming thin film 2 during the pulse interval T 2, for example, a voltage of 0. A voltage of about 1 V is applied between the device electrodes 5 and 6 by a power supply (not shown), and a current flowing through the device (device current) is measured to determine a resistance value (device resistance) of the device. For example, a step of terminating the forming process when a resistance value of 1 M ohm or more is indicated. The voltage at this time is hereinafter referred to as a forming voltage VF.

【００２７】また、以上の説明においては、電子放出部
を形成する際に、素子の電極間に三角波パルスを印加し
てフォーミング処理を行っているが、本発明の製造方法
においては、素子の電極間に印加する波形は三角波に限
定することはなく、矩形波など所望の波形を用いても良
く、その波高値及びパルス幅、パルス間隔等についても
上述の値に限ることなく、電子放出部が良好に形成され
るように、電子放出素子の抵抗値等に合わせて、所望の
値を選択することが出来る。In the above description, the forming process is performed by applying a triangular wave pulse between the electrodes of the device when forming the electron-emitting portion. The waveform to be applied in between is not limited to a triangular wave, and a desired waveform such as a rectangular wave may be used. The peak value, pulse width, pulse interval, and the like are not limited to the above-described values, and the electron emitting portion may be used. A desired value can be selected in accordance with the resistance value of the electron-emitting device or the like so as to be formed well.

【００２８】次に、以上述べた本発明の製造方法にて製
造される表面伝導形電子放出素子の、とりわけ好ましい
基本構成について説明する。Next, a particularly preferred basic configuration of the surface conduction electron-emitting device manufactured by the above-described manufacturing method of the present invention will be described.

【００２９】本発明に係る表面伝導形電子放出素子の基
本的な構成は、以下に述べるような、平面型及び垂直型
の２つの構成が挙げられる。The basic structure of the surface conduction electron-emitting device according to the present invention includes the following two structures of a flat type and a vertical type.

【００３０】まず、以下に、平面型表面伝導形電子放出
素子について説明する。First, a flat surface conduction electron-emitting device will be described below.

【００３１】図１の（ａ）、（ｂ）は、それぞれ、本発
明に係る基本的な表面伝導形電子放出素子の構成を示す
平面図及び断面図である。この図１を用いて、本発明に
係る表面伝導形電子放出素子の基本的な構成を説明す
る。FIGS. 1A and 1B are a plan view and a sectional view, respectively, showing the configuration of a basic surface conduction electron-emitting device according to the present invention. The basic configuration of the surface conduction electron-emitting device according to the present invention will be described with reference to FIG.

【００３２】図１において、１は基板、５と６は素子電
極、４は電子放出部を含む薄膜、３は電子放出部であ
る。In FIG. 1, 1 is a substrate, 5 and 6 are device electrodes, 4 is a thin film including an electron emitting portion, and 3 is an electron emitting portion.

【００３３】前記基板１としては、石英ガラス、Ｎａ等
の不純物含有量を減少したガラス、青板ガラス、青板ガ
ラスにスパッタ法等により形成したＳｉＯ2 を積層した
ガラス基板等、あるいは、アルミナ等のセラミックス等
のとりわけ、絶縁性基板が好適に用いられる。Examples of the substrate 1 include quartz glass, glass having a reduced content of impurities such as Na, blue plate glass, a glass substrate obtained by laminating SiO 2 formed on blue plate glass by sputtering or the like, or ceramic such as alumina. In particular, an insulating substrate is suitably used.

【００３４】また、対向する前記素子電極５、６の材料
としては、導電性を有するものであればどのようなもの
であっても構わないが、例えば、Ｎｉ、Ｃｒ、Ａｕ、Ｍ
ｏ、Ｗ、Ｐｔ、Ｔｉ、Ａｌ、Ｃｕ、Ｐｄ等の金属、或は
合金及びＰｄ、Ａｇ、Ａｕ、ＲｕＯ2 、Ｐｄ- Ａｇ等の
金属、或は金属酸化物とガラス等から構成される印刷導
体、Ｉｎ2 Ｏ3 −ＳｎＯ2 等の透明導電体及びポリシリ
コン等の半導体材料等が挙げられる。The material of the opposing element electrodes 5 and 6 may be any material as long as it has conductivity. For example, Ni, Cr, Au, M
Printing composed of metals such as o, W, Pt, Ti, Al, Cu, Pd, or alloys and metals such as Pd, Ag, Au, RuO 2 , Pd-Ag, or metal oxides and glass Examples of the material include a conductor, a transparent conductor such as In 2 O 3 —SnO 2 , and a semiconductor material such as polysilicon.

【００３５】素子電極間隔Ｌ１は、数百オングストロー
ムから数百マイクロメートルであり、素子電極の製法の
基本となるフォトリソグラフィー技術、即ち、露光機の
性能とエッチング方法等、及び、素子電極間に印加する
電圧と電子放出し得る電界強度等により設定されるが、
好ましくは、数マイクロメートルから数十マイクロメー
トルである。The element electrode interval L1 is from several hundred angstroms to several hundred micrometers, and the photolithography technique which is the basis of the element electrode manufacturing method, that is, the performance of the exposure machine and the etching method, etc. Voltage and the electric field strength that can emit electrons.
Preferably, it is several micrometers to several tens of micrometers.

【００３６】素子電極長さＷ１及び素子電極５、６の膜
厚ｄは、電極の抵抗値、多数個の電子放出素子が配置さ
れる場合の電子放出素子の配線及び配置上の問題より適
宜設計され、通常は、素子電極長さＷ１は、数マイクロ
メートルから数百マイクロメートルであり、素子電極
５、６の膜厚ｄは、数百オングストロームから数マイク
ロメ−トルである。The length W1 of the device electrode and the thickness d of the device electrodes 5 and 6 are appropriately designed depending on the resistance of the electrodes, wiring and arrangement of the electron-emitting devices when a large number of electron-emitting devices are arranged. Usually, the element electrode length W1 is several micrometers to several hundred micrometers, and the film thickness d of the device electrodes 5 and 6 is several hundred angstroms to several micrometers.

【００３７】基板１上に設けられた対向する素子電極５
及び素子電極６間と、素子電極５、６上に設置された、
電子放出部を含む薄膜４は、電子放出部３を含むが、図
１の（ｂ）に示された形態だけでなく、素子電極５、６
上には設置されない形態もある。即ち、基板１上に、電
子放出部形成用薄膜２、対向する素子電極５、６の順に
積層構成した形態もある。また、製法によっては、対向
する素子電極５と素子電極６の間全てが電子放出部とし
て機能する場合もある。この電子放出部を含む薄膜４の
膜厚は、好ましくは、数オングストロームから数千オン
グストロームで、特に好ましくは、１０オングストロ−
ムから５００オングストロ−ムであり、素子電極５、６
へのステップカバレージ、電子放出部３と素子電極５、
６間の抵抗値、電子放出部３の導電性微粒子の粒径、さ
らには、前述した通電処理条件等によって適宜設定され
る。また、その抵抗値は、１０の３乗から１０の７乗オ
ーム/ □のシート抵抗値を示す。The opposing element electrodes 5 provided on the substrate 1
And between the device electrodes 6 and on the device electrodes 5 and 6,
Although the thin film 4 including the electron-emitting portion includes the electron-emitting portion 3, the thin film 4 includes not only the form shown in FIG.
There is also a form that is not installed above. That is, there is also an embodiment in which the thin film 2 for forming an electron emission portion and the device electrodes 5 and 6 facing each other are laminated on the substrate 1 in this order. Further, depending on the manufacturing method, the entire space between the opposing element electrodes 5 and 6 may function as an electron emission portion. The thickness of the thin film 4 including the electron-emitting portion is preferably several angstroms to several thousand angstroms, and particularly preferably 10 angstroms.
To 500 Å, and the device electrodes 5, 6
Step coverage, electron emission part 3 and device electrode 5,
The resistance is set appropriately according to the resistance value between the six, the particle size of the conductive fine particles of the electron emission portion 3, and the above-described energization processing conditions. Further, the resistance value indicates a sheet resistance value of 10 3 to 10 7 ohm / □.

【００３８】電子放出部を含む薄膜４を構成する材料の
具体例を挙げるならば、Ｐｄ、Ｎｂ、Ｍｏ、Ｒｈ、Ｈ
ｆ、Ｒｅ、Ｉｒ、Ｐｔ、Ａｌ、Ｃｏ、Ｎｉ、Ｃｓ、Ｂ
ａ、Ｒｕ、Ａｇ、Ａｕ、Ｔｉ、Ｉｎ、Ｃｕ、Ｃｒ、Ｆ
ｅ、Ｚｎ、Ｓｎ、Ｔａ、Ｗ、Ｐｂ等の金属、ＰｄＯ、Ｓ
ｎＯ2 、Ｉｎ2 Ｏ3 、ＰｂＯ、Ｓｂ2 Ｏ3 、ＢａＯ、Ｍ
ｇＯ等の酸化物、ＨｆＢ2 、ＺｒＢ2 、ＬａＢ6 、Ｃｅ
Ｂ6 、ＹＢ4 、ＧｄＢ4 等の硼化物、ＴｉＣ、ＺｒＣ、
ＨｆＣ、ＴａＣ、ＳｉＣ、ＷＣ等の炭化物、ＴｉＮ、Ｚ
ｒＮ、ＨｆＮ等の窒化物、Ｓｉ、Ｇｅ等の半導体、カー
ボン等であり、微粒子からなる。Specific examples of the material constituting the thin film 4 including the electron-emitting portion include Pd, Nb, Mo, Rh, and H.
f, Re, Ir, Pt, Al, Co, Ni, Cs, B
a, Ru, Ag, Au, Ti, In, Cu, Cr, F
e, metal such as Zn, Sn, Ta, W, Pb, PdO, S
nO 2 , In 2 O 3 , PbO, Sb 2 O 3 , BaO, M
oxides such as gO, HfB 2 , ZrB 2 , LaB 6 , Ce
Borides such as B 6 , YB 4 and GdB 4 , TiC, ZrC,
Carbides such as HfC, TaC, SiC, WC, TiN, Z
It is a nitride such as rN or HfN, a semiconductor such as Si or Ge, carbon or the like, and is made of fine particles.

【００３９】尚、ここで述べる微粒子膜とは、複数の微
粒子が集合した膜であり、その微細構造として、微粒子
が個々に分散配置した状態のみならず、微粒子が互いに
隣接、あるいは重なり合った状態（島状も含む）の膜を
さす。The fine particle film described here is a film in which a plurality of fine particles are gathered, and has a fine structure not only in a state where the fine particles are individually dispersed and arranged, but also in a state where the fine particles are adjacent to each other or overlap each other ( (Including islands).

【００４０】また、電子放出部３は、好ましくは、数オ
ングストロームから数百オングストローム、特に好まし
くは、１０オングストロ−ムから５００オングストロ−
ムの粒径の導電性微粒子多数個からなり、電子放出部を
含む薄膜４の膜厚及び前述した通電処理条件等の製法に
依存しており、適宜設定される。また、電子放出部３を
構成する材料は、電子放出部を含む薄膜４を構成する材
料の元素の一部あるいは全てを有する材料である。The electron-emitting portion 3 is preferably a few angstroms to a few hundreds of angstroms, and particularly preferably a 10 angstroms to a 500 angstroms.
It is composed of a number of conductive fine particles having a particle size of a film and depends on the manufacturing method such as the film thickness of the thin film 4 including the electron-emitting portion and the above-described energization processing conditions, and is appropriately set. The material forming the electron-emitting portion 3 is a material having some or all of the elements of the material forming the thin film 4 including the electron-emitting portion.

【００４１】次に本発明に係わる別な構成の表面伝導形
電子放出素子である垂直型表面伝導形電子放出素子につ
いて説明する。Next, a vertical surface conduction electron-emitting device which is another surface conduction electron-emitting device according to the present invention will be described.

【００４２】図６は、本発明に係る基本的な垂直型表面
伝導形電子放出素子の構成を示す図である。FIG. 6 is a diagram showing the configuration of a basic vertical surface conduction electron-emitting device according to the present invention.

【００４３】図６中、１は基板、５と６は素子電極、４
は電子放出部を含む薄膜、３は電子放出部、６７は段差
形成部である。ここで、基板１、素子電極５と６、電子
放出部を含む薄膜４、電子放出部３は、前述した平面型
表面伝導形電子放出素子と同様の材料で構成されたもの
であり、垂直型表面伝導形電子放出素子を特徴付ける段
差形成部６７、電子放出部を含む薄膜４について詳述す
る。In FIG. 6, 1 is a substrate, 5 and 6 are device electrodes,
Denotes a thin film including an electron emitting portion, 3 denotes an electron emitting portion, and 67 denotes a step forming portion. Here, the substrate 1, the device electrodes 5 and 6, the thin film 4 including the electron-emitting portion, and the electron-emitting portion 3 are made of the same material as that of the above-mentioned flat surface-conduction type electron-emitting device. The step forming portion 67 which characterizes the surface conduction electron-emitting device and the thin film 4 including the electron-emitting portion will be described in detail.

【００４４】段差形成部６７は、真空蒸着法、印刷法、
スパッタ法等で形成されたＳｉＯ2等の絶縁性材料で構
成され、段差形成部６７の厚さは、先に述べた平面型表
面伝導形電子放出素子の素子電極間隔Ｌ１に対応し、数
百オングストロームから数十マイクロメートルであり、
段差形成部の製法、及び、素子電極間に印加する電圧と
電子放出し得る電界強度により設定されるが、好ましく
は、数千オングストロームから数マイクロメートルであ
る。The step forming section 67 is formed by a vacuum deposition method, a printing method,
The stepped portion 67 is made of an insulating material such as SiO 2 formed by a sputtering method or the like. The thickness of the step forming portion 67 corresponds to the device electrode interval L1 of the above-mentioned flat surface conduction electron-emitting device, and is several hundreds. Tens of micrometers from Angstroms,
It is set by the manufacturing method of the step forming portion, the voltage applied between the device electrodes, and the electric field intensity capable of emitting electrons, and is preferably from several thousand angstroms to several micrometers.

【００４５】電子放出部を含む薄膜４は、素子電極５、
６と段差形成部６７作成後に形成するため、素子電極
５、６の上に積層され、場合によっては、素子電極５、
６との電気的接続をする重なりをもった所望の形状にさ
れる。また、電子放出部を含む薄膜４の膜厚は、その製
法に依存しており、段差部での膜厚と素子電極５、６の
上に積層された部分の膜厚では、異なる場合が多く、一
般に段差部分の膜厚は薄い傾向にある。また、電子放出
部３は、薄膜４のいずれかの位置に形成されるものであ
って、図６に示された位置に形成されるとは限らない。The thin film 4 including the electron-emitting portion has a device electrode 5,
6 are formed on the device electrodes 5 and 6 so as to be formed after the formation of the step forming portion 67.
6 is formed in a desired shape with an overlap for making an electrical connection with the same. In addition, the thickness of the thin film 4 including the electron-emitting portion depends on the manufacturing method, and the thickness at the step portion and the thickness of the portion stacked on the device electrodes 5 and 6 often differ. Generally, the film thickness of the stepped portion tends to be thin. Further, the electron-emitting portion 3 is formed at any position of the thin film 4, and is not necessarily formed at the position shown in FIG.

【００４６】上述のような製造方法によって製造され、
また、上述のような素子構成を有する本発明に係る表面
伝導形電子放出素子の基本特性について、図３、図５を
用いて説明する。It is manufactured by the manufacturing method as described above,
Further, basic characteristics of the surface conduction electron-emitting device according to the present invention having the above-described device configuration will be described with reference to FIGS.

【００４７】図３は、図１で示した構成を有する素子の
電子放出特性を測定するための測定評価装置の概略構成
図である。FIG. 3 is a schematic configuration diagram of a measurement evaluation device for measuring the electron emission characteristics of the device having the configuration shown in FIG.

【００４８】図３において、１は基板、５及び６は素子
電極、４は電子放出部を含む薄膜、３は電子放出部を示
す。また、３１は素子に素子電圧Ｖｆを印加するための
電源、３０は素子電極５、６間の電子放出部を含む薄膜
４を流れる素子電流Ｉｆを測定するための電流計、３４
は素子の電子放出部より放出される放出電流Ｉｅを捕捉
するためのアノード電極、３３はアノード電極３４に電
圧を印加するための高圧電源、３２は素子の電子放出部
３より放出される放出電流Ｉｅを測定するための電流計
である。In FIG. 3, 1 is a substrate, 5 and 6 are device electrodes, 4 is a thin film including an electron emitting portion, and 3 is an electron emitting portion. Reference numeral 31 denotes a power supply for applying a device voltage Vf to the device, reference numeral 30 denotes an ammeter for measuring a device current If flowing through the thin film 4 including an electron-emitting portion between the device electrodes 5 and 6, and 34.
Is an anode electrode for capturing an emission current Ie emitted from the electron emission portion of the device, 33 is a high voltage power supply for applying a voltage to the anode electrode 34, and 32 is an emission current emitted from the electron emission portion 3 of the device. It is an ammeter for measuring Ie.

【００４９】電子放出素子の上記素子電流Ｉｆ、放出電
流Ｉｅの測定にあたっては、素子電極５、６に電源３１
と電流計３０とを接続し、該電子放出素子の上方に電源
３３と電流計３２とを接続したアノード電極３４を配置
している。また、電子放出素子及びアノード電極３４は
真空装置内に設置され、その真空装置には不図示の排気
ポンプ及び真空計等の真空装置に必要な機器が具備され
ており、所望の真空下で本素子の測定評価を行えるよう
になっている。また、アノード電極の電圧は１ｋＶ〜１
０ｋＶ、アノード電極と電子放出素子との距離Ｈは２ｍ
ｍ〜８ｍｍの範囲で測定した。In measuring the device current If and the emission current Ie of the electron-emitting device, the power source 31 is connected to the device electrodes 5 and 6.
And an ammeter 30, and an anode 34 connected to a power supply 33 and an ammeter 32 is disposed above the electron-emitting device. The electron-emitting device and the anode electrode 34 are installed in a vacuum device, and the vacuum device is provided with equipment necessary for a vacuum device such as an exhaust pump (not shown) and a vacuum gauge. The device can be measured and evaluated. The voltage of the anode electrode is 1 kV to 1 kV.
0 kV, the distance H between the anode electrode and the electron-emitting device is 2 m
It was measured in the range of m to 8 mm.

【００５０】図３に示した測定評価装置により測定され
た本発明に係る電子放出素子の放出電流Ｉｅおよび素子
電流Ｉｆと、素子電圧Ｖｆの関係の典型的な例を図５に
示す。FIG. 5 shows a typical example of the relationship between the emission current Ie and the device current If of the electron-emitting device according to the present invention measured by the measurement and evaluation apparatus shown in FIG. 3, and the device voltage Vf.

【００５１】尚、図５は、放出電流Ｉｅが素子電流Ｉｆ
に比べて著しく小さいので、任意単位で示されている。FIG. 5 shows that the emission current Ie is equal to the device current If.
Since it is significantly smaller than, it is shown in arbitrary units.

【００５２】この図５からも明らかなように、本発明に
係る表面伝導形電子放出素子は放出電流Ｉｅに対する三
つの特性を有する。As apparent from FIG. 5, the surface conduction electron-emitting device according to the present invention has three characteristics with respect to the emission current Ie.

【００５３】まず第一に、本電子放出素子はある電圧
（これを、閾値電圧と呼び、図５中にはＶｔｈで示して
ある）以上の素子電圧を印加すると急激に放出電流Ｉｅ
が増加し、一方、閾値電圧Ｖｔｈ以下では放出電流Ｉｅ
がほとんど検出されない。First, when an element voltage higher than a certain voltage (this is called a threshold voltage and is indicated by Vth in FIG. 5) is applied to the electron-emitting device, the emission current Ie suddenly increases.
On the other hand, the emission current Ie below the threshold voltage Vth
Is hardly detected.

【００５４】即ち、本電子放出素子は、放出電流Ｉｅに
対する明確な閾値電圧Ｖｔｈを持った非線形素子であ
る。That is, the electron-emitting device is a non-linear device having a clear threshold voltage Vth with respect to the emission current Ie.

【００５５】第二に、放出電流Ｉｅが素子電圧Ｖｆに依
存するため、放出電流Ｉｅは素子電圧Ｖｆで制御でき
る。Second, since the emission current Ie depends on the device voltage Vf, the emission current Ie can be controlled by the device voltage Vf.

【００５６】第三に、アノード電極３４に捕捉される放
出電荷は、素子電圧Ｖｆを印加する時間に依存する。Third, the amount of charge discharged to the anode electrode 34 depends on the time during which the device voltage Vf is applied.

【００５７】即ち、アノード電極３４に捕捉される電荷
量は、素子電圧Ｖｆを印加する時間により制御できる。That is, the amount of charge captured by the anode electrode 34 can be controlled by the time during which the device voltage Vf is applied.

【００５８】以上のような特性を有するため、本発明に
係る表面伝導形電子放出素子は、多方面への応用が期待
できる。Because of the above characteristics, the surface conduction electron-emitting device according to the present invention can be expected to be applied to various fields.

【００５９】一方、素子電流Ｉｆは素子電圧Ｖｆに対し
て、単調増加する特性（ＭＩ特性と呼ぶ）の例を図５に
示したが、この他にも、素子電流Ｉｆが素子電圧Ｖｆに
対して電圧制御型負性抵抗特性（ＶＣＮＲ特性と呼ぶ）
を示す場合もある。尚、この場合も本電子放出素子は上
述した三つの特性上の特徴を有する。On the other hand, FIG. 5 shows an example in which the element current If monotonically increases with respect to the element voltage Vf (referred to as MI characteristic). In addition, the element current If changes with respect to the element voltage Vf. Voltage control type negative resistance characteristics (referred to as VCNR characteristics)
May be indicated. In this case, the electron-emitting device also has the above-described three characteristics.

【００６０】以上、本発明の製造方法及び表面伝導形電
子放出素子の構成について説明したが、本発明の製造方
法は、上述の基本的な製造方法に限らず、その一部を変
更しても良い。また、本発明の製造方法にて製造される
表面伝導形電子放出素子は、上述の構成に限らず、ま
た、上述の三つの特性を有すれば、後述の電子源、画像
形成装置に好適に用いられる。Although the manufacturing method and the structure of the surface conduction electron-emitting device of the present invention have been described above, the manufacturing method of the present invention is not limited to the basic manufacturing method described above, and may be partially modified. good. Moreover, Ru is manufactured by the manufacturing method of the present invention
The surface conduction electron-emitting device is not limited to the above-described configuration, and if it has the above-mentioned three characteristics, it is suitably used for an electron source and an image forming apparatus described later.

【００６１】次に、本発明の製造方法にて製造された表
面伝導形電子放出素子を用いた電子源及び画像形成装置
について述べる。Next, an electron source and an image forming apparatus using the surface conduction electron-emitting device manufactured by the manufacturing method of the present invention will be described.

【００６２】前述した本発明に係る表面伝導形電子放出
素子の３つの基本的特性の特徴によれば、表面伝導形電
子放出素子からの放出電子は、閾値電圧以上では、対向
する素子電極間に印加するパルス状電圧の波高値と巾で
制御される。一方、閾値電圧以下では、殆ど放出されな
い。この特性によれば、多数の電子放出素子を配置した
場合においても、個々の表面伝導形電子放出素子に、上
記パルス状電圧を適宜印加すれば、入力信号に応じて、
任意の表面伝導型電子放出素子を選択し、その電子放出
量が制御出来るという作用効果を奏する事となる。According to the characteristics of the three basic characteristics of the surface conduction electron-emitting device according to the present invention described above, the electrons emitted from the surface conduction electron-emitting device can be disposed between the opposing device electrodes at a threshold voltage or higher. It is controlled by the peak value and the width of the applied pulse voltage. On the other hand, below the threshold voltage, almost no emission occurs. According to this characteristic, even when a large number of electron-emitting devices are arranged, if the pulse-like voltage is appropriately applied to each surface conduction electron-emitting device,
This has the effect of selecting an arbitrary surface conduction electron-emitting device and controlling the amount of electron emission.

【００６３】以下で、この原理に基づき構成した電子源
基板の構成について、図７を用いて説明する。The configuration of the electron source substrate based on this principle will be described below with reference to FIG.

【００６４】図７において、１は基板、７２はＸ方向配
線、７３はＹ方向配線、７４は上述した表面伝導形電子
放出素子、７５は結線である。尚、表面伝導形電子放出
素子は、上述の平面型あるいは垂直型のどちらであって
もよい。In FIG. 7, 1 is a substrate, 72 is an X-direction wiring, 73 is a Y-direction wiring, 74 is the above-mentioned surface conduction electron-emitting device, and 75 is a connection. The surface conduction electron-emitting device may be either of the above-mentioned flat type or vertical type.

【００６５】ここで、基板１は前述したガラス基板等の
絶縁性基板であり、その大きさ及びその厚みは、基板１
に設置される表面伝導形電子放出素子の個数及び個々の
素子の設計上の形状、及び電子源の使用時容器の一部を
構成する場合にはその容器を真空に保持するための条件
等に依存して適宜設定される。Here, the substrate 1 is an insulating substrate such as the above-mentioned glass substrate, and its size and thickness are
The number of surface-conduction electron-emitting devices to be installed in the device, the design shape of each device, and the conditions for maintaining the container in a vacuum when using a part of the container when the electron source is used. It is set appropriately depending on it.

【００６６】ｍ本のＸ方向配線７２は、ＤＸ1 、ＤＸ2
、．．、ＤＸｍからなり、基板１上に、真空蒸着法、
印刷法、スパッタ法等で形成し、所望のパーターンとし
た導電性金属等からなり、多数の表面伝導形電子放出素
子にほぼ均等な電圧が供給される様に、その材料、膜
厚、配線幅が設定される。The m X-direction wirings 72 are DX1, DX2
,. . , DXm, on the substrate 1, a vacuum deposition method,
It is made of a conductive metal or the like that is formed by a printing method, a sputtering method, etc. and has a desired pattern, and its material, film thickness, and wiring width are set so that a substantially uniform voltage is supplied to a large number of surface conduction electron-emitting devices. Is set.

【００６７】また、Ｙ方向配線７３は、ＤＹ１、ＤＹ
２、．．、ＤＹｎのｎ本の配線よりなり、Ｘ方向配線７
２と同様に、真空蒸着法、印刷法、スパッタ法等で形成
し、所望のパーターンとした導電性金属等からなり、多
数の表面伝導形電子放出素子にほぼ均等な電圧が供給さ
れる様に、その材料、膜厚、配線幅等が設定される。The Y-direction wiring 73 is connected to DY1, DY
2,. . , DYn, and the X-direction wiring 7
In the same manner as in 2, the conductive pattern is formed by a vacuum evaporation method, a printing method, a sputtering method, or the like, and is made of a conductive metal having a desired pattern so that a substantially uniform voltage is supplied to a large number of surface conduction electron-emitting devices. , Its material, film thickness, wiring width, etc. are set.

【００６８】これらｍ本のＸ方向配線７２とｎ本のＹ方
向配線７３との間には、不図示の層間絶縁層が設置さ
れ、電気的に分離されて、マトリックス配線を構成す
る。尚、ここでｍ、ｎは、共に正の整数である。An interlayer insulating layer (not shown) is provided between the m X-directional wirings 72 and the n Y-directional wirings 73, and is electrically separated to form a matrix wiring. Here, both m and n are positive integers.

【００６９】不図示の層間絶縁層は、真空蒸着法、印刷
法、スパッタ法等で形成されたＳｉＯ2 等であり、Ｘ方
向配線７２を形成した基板１の全面或は一部に所望の形
状で形成され、特に、Ｘ方向配線７２とＹ方向配線７３
の交差部の電位差に耐え得る様に、その膜厚、材料、製
法が適宜設定され、Ｘ方向配線７２とＹ方向配線７３の
交差部のみに設置される場合もあり、このときは、結線
７５とＸ方向配線７２あるいはＹ方向配線７３との電気
的接続は、コンタクトホールを介さず行なう事ができ
る。また、Ｘ方向配線７２とＹ方向配線７３は、それぞ
れ外部端子として引き出されている。The interlayer insulating layer (not shown) is, for example, SiO 2 formed by a vacuum deposition method, a printing method, a sputtering method, or the like, and has a desired shape on the entire surface or a part of the substrate 1 on which the X-directional wiring 72 is formed. In particular, the X direction wiring 72 and the Y direction wiring 73
The thickness, the material, and the manufacturing method are appropriately set so as to withstand the potential difference at the intersection of the X-direction wiring 72 and the Y-direction wiring 73. And the X-direction wiring 72 or the Y-direction wiring 73 can be electrically connected without using a contact hole. Further, the X-direction wiring 72 and the Y-direction wiring 73 are respectively drawn as external terminals.

【００７０】尚、ｍ本のＸ方向配線７２の上に、ｎ本の
Ｙ方向配線７３を層間絶縁層を介して設置した例で説明
したが、ｎ本のＹ方向配線７３の上に、ｍ本のＸ方向配
線７２を層間絶縁層を介して設置する場合もある。In the above description, an example in which n Y-directional wirings 73 are provided on m X-directional wirings 72 via an interlayer insulating layer has been described. In some cases, the X-directional wiring 72 is provided via an interlayer insulating layer.

【００７１】更に、前述と同様にして、表面伝導形電子
放出素子７４の対向する素子電極（不図示）は、ｍ本の
Ｘ方向配線（ＤＸ1 、ＤＸ2 、．．、ＤＸｍ）７２及び
ｎ本のＹ方向配線（ＤＹ１、ＤＹ２、．．、ＤＹｎ）７
３と、真空蒸着法、印刷法、スパッタ法等で形成された
導電性金属等からなる結線７５によって電気的に接続さ
れている。Further, in the same manner as described above, the opposing device electrodes (not shown) of the surface conduction electron-emitting device 74 are composed of m X-directional wirings (DX1, DX2,..., DXm) 72 and n Y-direction wiring (DY1, DY2,... DYn) 7
3 are electrically connected to each other by a connection 75 made of a conductive metal or the like formed by a vacuum deposition method, a printing method, a sputtering method, or the like.

【００７２】ここで、ｍ本のＸ方向配線７２、ｎ本のＹ
方向配線７３、結線７５、及び対向する素子電極を構成
する導電性金属は、その構成元素の一部あるいは全部が
同一であっても、またそれぞれ異なっていてもよく、例
えば、Ｎｉ、Ｃｒ、Ａｕ、Ｍｏ、Ｗ、Ｐｔ、Ｔｉ、Ａ
ｌ、Ｃｕ、Ｐｄ等の金属或は合金及びＰｄ、Ａｇ、Ａ
ｕ、ＲｕＯ2 、Ｐｄ- Ａｇ等の金属或は金属酸化物とガ
ラス等から構成される印刷導体、Ｉｎ2 Ｏ3 −ＳｎＯ2
等の透明導体及びポリシリコン等の半導体材料等より適
宜選択される。また、表面伝導形電子放出素子は、基板
１あるいは、不図示の層間絶縁層上どちらに形成しても
よい。Here, m X-directional wires 72 and n Y wires
Some or all of the constituent elements of the directional wiring 73, the connection 75, and the conductive metal constituting the opposing element electrode may be the same or different, and for example, Ni, Cr, Au , Mo, W, Pt, Ti, A
metals or alloys such as l, Cu, Pd and Pd, Ag, A
a printed conductor composed of a metal such as u, RuO 2 , Pd-Ag, or a metal oxide and glass; In 2 O 3 —SnO 2
And the like and a semiconductor material such as polysilicon. Further, the surface conduction electron-emitting device may be formed on either the substrate 1 or an interlayer insulating layer (not shown).

【００７３】また、後に詳述するが、前記Ｘ方向配線７
２には、Ｘ方向に配列する表面伝導形電子放出素子７４
の行を入力信号に応じて走査するために、Ｘ方向配線７
２に走査信号を印加するための不図示の走査信号印加手
段が電気的に接続されている。一方、Ｙ方向配線７３に
は、Ｙ方向に配列する表面伝導形電子放出素子７４の列
の各列を入力信号に応じて変調するために、Ｙ方向配線
７３に変調信号を印加するための不図示の変調信号発生
手段が電気的に接続されている。更に、複数の表面伝導
形電子放出素子の各素子に印加される駆動電圧は、当該
素子に印加される走査信号と変調信号との差電圧として
供給されるものである。As will be described in detail later, the X-direction wiring 7
2 includes a surface conduction electron-emitting device 74 arranged in the X direction.
In order to scan the row according to the input signal, the X-direction wiring 7
2, a scanning signal applying unit (not shown) for applying a scanning signal is electrically connected. On the other hand, in order to modulate each of the rows of the surface conduction electron-emitting devices 74 arranged in the Y direction in accordance with an input signal, the Y-direction wiring 73 has an unnecessity for applying a modulation signal to the Y-direction wiring 73. The illustrated modulation signal generating means is electrically connected. Further, the driving voltage applied to each of the plurality of surface conduction electron-emitting devices is supplied as a difference voltage between a scanning signal applied to the device and a modulation signal.

【００７４】次に、以上のようにして作成した電子源基
板を用いた、電子源と表示等に用いる画像形成装置につ
いて、図８と図９を用いて説明する。尚、図８は画像形
成装置の基本構成図であり、図９は蛍光膜を示す図であ
る。Next, an electron source and an image forming apparatus used for display and the like using the electron source substrate prepared as described above will be described with reference to FIGS. 8 and 9. FIG. FIG. 8 is a basic configuration diagram of the image forming apparatus, and FIG. 9 is a diagram illustrating a fluorescent film.

【００７５】図８において、１は、上述のようにして電
子放出素子を作製した電子源基板、８１は電子源基板１
を固定したリアプレート、８６はガラス基板８３の内面
に蛍光膜８４とメタルバック８５等が形成されたフェー
スプレート、８２は支持枠であり、これらリアプレート
８１、支持枠８２及びフェースプレート８６を、それら
の接合面にフリットガラス等を塗布し、大気中あるいは
窒素中で、４００〜５００℃、１０分以上の条件で焼成
することにより封着して、外囲器８８を構成する。尚、
図８において、７４は、図１における電子放出部３に相
当し、また、７２、７３は表面伝導形電子放出素子の一
対の素子電極と接続されたＸ方向配線及びＹ方向配線で
ある。ここで、これら素子電極と接続された配線は、素
子電極と同一の材料よりなる場合には、素子電極と呼ぶ
こともある。In FIG. 8, reference numeral 1 denotes an electron source substrate on which an electron-emitting device is manufactured as described above, and 81 denotes an electron source substrate.
Are fixed, 86 is a face plate having a fluorescent film 84 and a metal back 85 formed on the inner surface of a glass substrate 83, 82 is a support frame, and these rear plate 81, support frame 82 and face plate 86 are A frit glass or the like is applied to these joint surfaces and sealed by baking in air or nitrogen at 400 to 500 ° C. for 10 minutes or more to form an envelope 88. still,
8, reference numeral 74 corresponds to the electron-emitting portion 3 in FIG. 1, and reference numerals 72 and 73 denote X-direction wiring and Y-direction wiring connected to a pair of device electrodes of the surface conduction electron-emitting device. Here, the wirings connected to these device electrodes may be referred to as device electrodes when they are made of the same material as the device electrodes.

【００７６】また、前記外囲器８８は、上述の如く、フ
ェースープレート８６、支持枠８２、リアプレート８１
で構成したが、リアプレート８１は主に基板１の強度を
補強する目的で設けられるため、基板１自体で十分な強
度を持つ場合は別体のリアプレート８１は不要であり、
基板１に直接支持枠８２を封着し、フェースプレート８
６、支持枠８２、基板１にて外囲器８８を構成しても良
い。The envelope 88 includes a face plate 86, a support frame 82, and a rear plate 81 as described above.
However, since the rear plate 81 is provided mainly for the purpose of reinforcing the strength of the substrate 1, if the substrate 1 itself has sufficient strength, the separate rear plate 81 is unnecessary,
The support frame 82 is directly sealed to the substrate 1 and the face plate 8
6. The envelope 88 may be composed of the support frame 82 and the substrate 1.

【００７７】次に、図９は蛍光膜を示す図であるが、図
８の蛍光膜８４は、モノクロームの場合は蛍光体のみか
ら成るが、カラーの蛍光膜の場合は、蛍光体の配列によ
りブラックストライプあるいはブラックマトリクスなど
と呼ばれる黒色導伝材９１と蛍光体９２とで構成され
る。Next, FIG. 9 is a view showing a fluorescent film. The fluorescent film 84 shown in FIG. 8 is composed of only a fluorescent substance in the case of a monochrome image, but differs depending on the arrangement of the fluorescent substance in the case of a color fluorescent film. It is composed of a black conductive material 91 called a black stripe or a black matrix and a phosphor 92.

【００７８】このようなブラックストライプあるいはブ
ラックマトリクスが設けられる目的は、カラー表示の場
合必要となる三原色蛍光体の、各蛍光体９２間の塗り分
け部を黒くすることで混色等を目立たなくすることと、
蛍光膜８４における外光反射によるコントラストの低下
を抑制することである。The purpose of providing such a black stripe or a black matrix is to make the color separation between the phosphors 92 of the three primary color phosphors necessary for color display black so that color mixing and the like become inconspicuous. When,
The purpose is to suppress a decrease in contrast due to reflection of external light on the fluorescent film 84.

【００７９】また、ブラックストライプの材料として
は、通常良く用いられている黒鉛を主成分とする材料だ
けでなく、導電性があり、光の透過及び反射が少ない材
料であればこれに限るものではない。The material of the black stripe is not limited to the commonly used material containing graphite as a main component, as long as it is conductive and has little light transmission and reflection. Absent.

【００８０】尚、ガラス基板８３に蛍光体を塗布する方
法はモノクローム、カラーによらず、沈澱法や印刷法が
用いられる。また、蛍光膜８４の内面側には通常メタル
バック８５が設けられるが、メタルバックの目的は、蛍
光体の発光のうち内面側への光をフェースプレート８６
側へ鏡面反射することにより輝度を向上すること、電子
ビーム加速電圧を印加するための電極として作用するこ
と、外囲器内で発生した負イオンの衝突によるダメ−ジ
からの蛍光体の保護等である。メタルバックは、蛍光膜
作製後、蛍光膜の内面側表面の平滑化処理（通常、フィ
ルミングと呼ばれる）を行い、その後Ａｌを真空蒸着等
で堆積することで作製できる。The method of applying the fluorescent substance to the glass substrate 83 is not limited to monochrome or color, but a precipitation method or a printing method is used. A metal back 85 is usually provided on the inner surface side of the fluorescent film 84. The purpose of the metal back is to convert the light emitted from the phosphor toward the inner surface side into the face plate 86.
Improve brightness by specular reflection to the side, act as an electrode for applying electron beam acceleration voltage, protect phosphor from damage due to collision of negative ions generated in the envelope, etc. It is. The metal back can be manufactured by performing a smoothing treatment (usually called filming) on the inner surface of the fluorescent film after manufacturing the fluorescent film, and then depositing Al by vacuum evaporation or the like.

【００８１】また、フェースプレート８６には、更に、
蛍光膜８４の導伝性を高めるため、蛍光膜８４の外面側
に透明電極（不図示）を設けてもよい。The face plate 86 further includes:
In order to increase the conductivity of the fluorescent film 84, a transparent electrode (not shown) may be provided on the outer surface side of the fluorescent film 84.

【００８２】尚、前述の封着を行う際、カラーの場合は
各色蛍光体と電子放出素子とを対応させなくてはいけな
いため、十分な位置合わせを行なう必要がある。When the above-mentioned sealing is performed, in the case of color, the phosphors of each color must correspond to the electron-emitting devices, so that it is necessary to perform sufficient alignment.

【００８３】外囲器８８は、不図示の排気管を通じ、１
０のマイナス６乗トール程度の真空度にされ、外囲器８
８の封止がおこなわれる。尚、この時、不図示の排気管
を通じ、１０のマイナス６乗ト−ル程度の真空中で、容
器外端子Ｄo ｘ１〜Ｄo ｘｍとＤo ｙ１〜Ｄo ｙｎを通
じて、素子電極間に、上述の本発明の製造方法に係るパ
ルス電圧を印加し、フォ−ミング処理を行い、各電子放
出素子に電子放出部を形成して、基板上に複数の表面伝
導形電子放出素子を配設した電子源を作成する。The envelope 88 is connected to an exhaust pipe (not shown) to
The degree of vacuum is reduced to about 0 to the sixth power of Torr, and the envelope 8
8 is performed. At this time, the above-mentioned book is connected between the device electrodes through the external terminals Dox1 to Doxm and Doy1 to Doyn through an exhaust pipe (not shown) in a vacuum of about 10 minus 6 torr. According to the manufacturing method of the present invention, a pulse voltage is applied, a forming process is performed, an electron emission portion is formed in each electron emission device, and an electron source having a plurality of surface conduction electron emission devices disposed on a substrate is provided. create.

【００８４】また、外囲器８８の封止後の真空度を維持
するために、ゲッター処理を行なう場合もある。これ
は、外囲器８８の封止を行う直前あるいは封止後に、抵
抗加熱あるいは高周波加熱等の加熱法により、外囲器８
８内の所定の位置（不図示）に配置されたゲッターを加
熱し、蒸着膜を形成する処理である。ゲッターは通常Ｂ
ａ等が主成分であり、該蒸着膜の吸着作用により、たと
えば１×１０マイナス５乗〜１×１０マイナス７乗ト−
ルの真空度を維持するものである。In some cases, a getter process is performed to maintain the degree of vacuum after the envelope 88 is sealed. This is because immediately before or after sealing of the envelope 88, the envelope 8 is heated by a heating method such as resistance heating or high-frequency heating.
This is a process of heating a getter disposed at a predetermined position (not shown) in the step 8 to form a vapor deposition film. Getter is usually B
a is a main component, and for example, 1 × 10−5 to 1 × 10−7 due to the adsorption action of the deposited film.
This is to maintain the vacuum of the vacuum.

【００８５】以上のように完成した画像形成装置におい
て、各表面伝導形電子放出素子には、容器外端子Ｄo ｘ
１〜Ｄo ｘｍ、Ｄo ｙ１〜Ｄo ｙｎを通じ、電圧を印加
することにより電子放出させ、高圧端子Ｈｖを通じ、メ
タルバック８５あるいは透明電極（不図示）に数ｋＶ以
上の高圧を印加し、電子ビームを加速し、蛍光膜８４に
衝突させ、励起・発光させることで画像を表示するもの
である。[0085] In images forming apparatus completed as described above, each surface conduction electron-emitting devices, vessel terminals Do x
Electrons are emitted by applying a voltage through 1 to Doxm and Doy1 to Doyn, and a high voltage of several kV or more is applied to a metal back 85 or a transparent electrode (not shown) through a high voltage terminal Hv, and an electron beam is applied. The image is displayed by accelerating, colliding with the fluorescent film 84, exciting and emitting light.

【００８６】以上述べた構成は、表示等に用いられる好
適な画像形成装置を作製する上で必要な概略構成であ
り、例えば各部材の材料等、詳細な部分は上述内容に限
られるものではなく、画像形成装置の用途に適するよう
適宜選択する。The configuration described above is a schematic configuration necessary for producing a suitable image forming apparatus used for display and the like. For example, detailed portions such as materials of each member are not limited to the above-described contents. Is appropriately selected so as to be suitable for the use of the image forming apparatus.

【００８７】[0087]

【実施例】以下に、実施例を挙げて、本発明をより具体
的に説明する。The present invention will be described more specifically below with reference to examples.

【００８８】（実施例１）本実施例の表面伝導形電子放
出素子として、上述の図１の（ａ）、（ｂ）に示される
素子を製造した。Example 1 As the surface conduction electron-emitting device of this example, the above-described devices shown in FIGS. 1A and 1B were manufactured.

【００８９】以下に、順を追って本実施例の製造方法に
ついて詳述する。Hereinafter, the manufacturing method of this embodiment will be described in detail step by step.

【００９０】まず、基板１として絶縁性の石英基板を用
い、これを有機溶媒にて充分洗浄後、該基板１面上に、
Ｎｉからなる素子電極５、６を形成した（図２の
（ａ））。この時、素子電極間隔Ｌ１は３マイクロメ−
タとし、素子電極の幅Ｗ１を５００マイクロメ−タ、そ
の厚さｄを１０００オングストロ−ムとした。First, an insulative quartz substrate was used as the substrate 1, and this was sufficiently washed with an organic solvent.
The device electrodes 5 and 6 made of Ni were formed (FIG. 2A). At this time, the element electrode interval L1 was 3 micrometer.
The device electrode had a width W1 of 500 micrometers and a thickness d of 1000 angstroms.

【００９１】次に、有機金属化合物として、０．１モル
（２２．４９ｇ）の酢酸パラジウムと０．２モル（２
０．２４ｇ）のジｎ−プロピルアミンの混合物をスピナ
−塗布（８００ｒｐｍ、３０ｓｅｃ）した後、クリ−ン
オ−ブンにて、３００℃、１２ｍｉｎの条件で焼成を行
い、ＰｄＯ微粒子膜からなる電子放出部形成用薄膜２を
形成した（図２の（ｂ））。尚、ここで述べる微粒子膜
とは、複数の微粒子が集合した膜のことであって、その
微細構造は、微粒子が個々に分散配置した状態のみなら
ず、微粒子が互いに隣接、あるいは、重なり合った状態
（島状も含む）の膜を意味する。本実施例では、上記塗
布／焼成を２回繰り返すことにより、２×１０4 〜５×
１０4 オ−ム／□の膜抵抗を得た。Next, 0.1 mol (22.49 g) of palladium acetate and 0.2 mol (2
0.24 g) of a mixture of di-n-propylamine was applied by spinner (800 rpm, 30 sec), and then baked in a clean oven at 300 ° C. for 12 minutes to emit electrons of a PdO fine particle film. A thin film 2 for forming a portion was formed (FIG. 2B). Note that the fine particle film described here is a film in which a plurality of fine particles are aggregated, and the fine structure thereof is not only a state in which the fine particles are individually dispersed and arranged, but also a state in which the fine particles are adjacent to each other or overlap each other. (Including island-shaped) film. In this embodiment, the above-mentioned coating / firing is repeated twice to obtain 2 × 10 4 to 5 ×
A film resistance of 10 4 ohm / □ was obtained.

【００９２】次に、タ−ボポンプとロ−タリ−ポンプ
で、１０-6Ｔｏｒｒまで排気した真空容器内で、素子電
極５、６間に、図４に示される三角波のパルス電圧を印
加し、電子放出部形成用薄膜２を通電処理（フォ−ミン
グ処理）した（図２の（ｃ））。ここで、図４におい
て、Ｔ１及びＴ２はそれぞれ電圧波形のパルス幅とパル
ス間隔であり、本実施例では、Ｔ１を１ミリ秒、Ｔ２を
１０ミリ秒とし、三角波の波高値（フォ−ミング時のピ
−ク電圧）は、０．２Ｖ／ｍｉｎで昇圧した。また、本
実施例においては、パルス電圧印加時に、素子に流れる
電流をモニタ−して、この電流が急激に減少した時点、
即ち、素子抵抗が急激に増加した時点で該電圧の印加を
終了した。Next, a triangular pulse voltage shown in FIG. 4 is applied between the device electrodes 5 and 6 in a vacuum vessel evacuated to 10 -6 Torr by a turbo pump and a rotary pump. The thin film 2 for forming the electron-emitting portion was subjected to an energization process (forming process) (FIG. 2C). Here, in FIG. 4, T1 and T2 are the pulse width and pulse interval of the voltage waveform, respectively. In this embodiment, T1 is 1 millisecond, T2 is 10 milliseconds, and the peak value of the triangular wave (at the time of forming). Peak voltage) was increased at 0.2 V / min. Further, in this embodiment, when a pulse voltage is applied, the current flowing through the element is monitored, and when this current sharply decreases,
That is, the application of the voltage was terminated when the element resistance sharply increased.

【００９３】図１０に、典型的な素子抵抗とパルス電圧
の波高値との関係を示す。FIG. 10 shows a typical relationship between the element resistance and the peak value of the pulse voltage.

【００９４】図１０から明らかであるように、パルス電
圧の低い領域では、素子抵抗はほぼ一定であるが、電圧
の増加とともに素子抵抗は急激な増加を示す。電圧印加
を終了した時点での三角波の波高値は、素子抵抗のバラ
ツキに対応して４〜６Ｖまで変化した。As is clear from FIG. 10, the element resistance is almost constant in the region where the pulse voltage is low, but the element resistance shows a sharp increase with an increase in the voltage. The peak value of the triangular wave at the end of the voltage application changed from 4 to 6 V corresponding to the variation of the element resistance.

【００９５】以上のように作成された、本実施例の表面
伝導形電子放出素子について、その電子放出特性の評価
を、上述の図３に示した測定評価装置を用いて行った。The electron emission characteristics of the surface conduction electron-emitting device of the present embodiment prepared as described above were evaluated using the above-described measurement and evaluation apparatus shown in FIG.

【００９６】尚、測定条件は、アノード電極と電子放出
素子間の距離を４ｍｍ、アノード電極の電位を１ｋＶ、
電子放出特性測定時の真空装置内の真空度を１×１０マ
イナス６乗ト−ルとした。The measurement conditions were as follows: the distance between the anode and the electron-emitting device was 4 mm; the potential of the anode was 1 kV;
The degree of vacuum in the vacuum apparatus at the time of measuring the electron emission characteristics was set to 1 × 10 minus 6 torr.

【００９７】本実施例の製造方法にて作成された表面伝
導形電子放出素子の電極５及び６の間に素子電圧Ｖｆを
印加し、その時に流れる素子電流Ｉｆ及び放出電流Ｉｅ
を測定したところ、図１１に示したような電流−電圧特
性が得られた。即ち、本実施例の製造方法にて作成され
る素子の平均的な特性は、素子電圧８Ｖ程度から急激に
放出電流Ｉｅが増加し、素子電圧１４Ｖでは素子電流Ｉ
ｆが２．２ｍＡ、放出電流Ｉｅが１．１マイクロＡとな
り、電子放出効率η＝Ｉｅ／Ｉｆ×１００（％）は０．
０５％であり、上記フォ−ミング電圧に依らずほぼ均一
な特性の素子が得られた。The device voltage Vf is applied between the electrodes 5 and 6 of the surface conduction electron-emitting device manufactured by the manufacturing method of this embodiment, and the device current If and the emission current Ie flowing at that time are applied.
Was measured, a current-voltage characteristic as shown in FIG. 11 was obtained. That is, the average characteristic of the device manufactured by the manufacturing method of this embodiment is that the emission current Ie sharply increases from the device voltage of about 8 V, and the device current Ie increases at the device voltage of 14 V.
f is 2.2 mA, the emission current Ie is 1.1 microA, and the electron emission efficiency η = Ie / If × 100 (%) is 0.2.
It was 0.5%, and an element having substantially uniform characteristics was obtained irrespective of the above-mentioned forming voltage.

【００９８】（実施例２）本実施例は、多数の表面伝導
形電子放出素子を単純マトリクス配置した電子源を用い
た画像形成装置の例を示すものである。(Embodiment 2) This embodiment shows an example of an image forming apparatus using an electron source in which many surface conduction electron-emitting devices are arranged in a simple matrix.

【００９９】電子源の一部の平面図を図１２に示す。ま
た、図中のＡ−Ａ’断面図を図１３に示す。ここで１は
基板、９２は、図８のＤＸｍに対応するＸ方向配線（下
配線とも呼ぶ）、９３は、図８のＤＹｎに対応するＹ方
向配線（上配線とも呼ぶ）、９４は電子放出部を含む薄
膜、９５、９６は素子電極、１４１は層間絶縁層、１４
２は、素子電極９５と下配線９２との電気的接続のため
のコンタクトホールである。FIG. 12 is a plan view of a part of the electron source. FIG. 13 is a sectional view taken along the line AA ′ in the figure. Here, 1 is a substrate, 92 is an X-direction wiring (also called lower wiring) corresponding to DXm in FIG. 8, 93 is a Y-direction wiring (also called upper wiring) corresponding to DYn in FIG. 8, and 94 is electron emission. Thin film including a part, 95 and 96 are device electrodes, 141 is an interlayer insulating layer, 14
Reference numeral 2 denotes a contact hole for electrical connection between the element electrode 95 and the lower wiring 92.

【０１００】以上の電子源の製造方法及びその電子源を
用いた画像形成装置について、図１４及び、上述の図
８、図９を用いて以下に具体的に説明する。The above-described method of manufacturing an electron source and an image forming apparatus using the electron source will be specifically described below with reference to FIGS. 14 and 8 and 9 described above.

【０１０１】工程−ａ：清浄化した青板ガラス上に厚さ
０．５ミクロンのシリコン酸化膜をスパッタ法で形成し
た基板１上に、真空蒸着により厚さ５０オングストロ−
ムのＣｒ、厚さ６０００オングストロ−ムのＡｕを順次
積層した後、ホトレジスト（ＡＺ１３７０ ヘキスト社
製）をスピンナーにより回転塗布、ベークした後、ホト
マスク像を露光、現像して、下配線９２のレジストパタ
ーンを形成し、Ａｕ／Ｃｒ堆積膜をウエットエッチング
して、所望の形状の下配線９２を形成する（図１４の
（ａ））。Step-a: A 50 .ANG.-thick silicon oxide film having a thickness of 0.5 .mu.m was formed on a cleaned blue plate glass by a sputtering method.
After sequentially laminating Cr and Au having a thickness of 6000 angstroms, a photoresist (manufactured by AZ1370 Hoechst) is spin-coated with a spinner and baked, and then a photomask image is exposed and developed to form a resist pattern of the lower wiring 92. Is formed, and the Au / Cr deposited film is wet-etched to form a lower wiring 92 having a desired shape (FIG. 14A).

【０１０２】工程−ｂ：次に、厚さ１．０ミクロンのシ
リコン酸化膜からなる層間絶縁層１４１をＲＦスパッタ
法により堆積する（図１４の（ｂ））。Step-b: Next, an interlayer insulating layer 141 made of a silicon oxide film having a thickness of 1.0 μm is deposited by RF sputtering (FIG. 14B).

【０１０３】工程−ｃ：前記工程ｂで堆積したシリコン
酸化膜にコンタクトホール１４２を形成するためのホト
レジストパターンを作り、これをマスクとして層間絶縁
層１４１をエッチングして、コンタクトホール１４２を
形成する（図１４の（ｃ））。Step-c: A photoresist pattern for forming the contact hole 142 is formed in the silicon oxide film deposited in the step b, and the interlayer insulating layer 141 is etched using the photoresist pattern as a mask to form the contact hole 142 ( FIG. 14 (c)).

【０１０４】尚、エッチングはＣＦ4 とＨ2 ガスを用い
たＲＩＥ（Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎ
ｇ）法によった。The etching is performed by RIE (Reactive Ion Etching) using CF 4 and H 2 gas.
g) The method was used.

【０１０５】工程−ｄ：その後、素子電極９５と、素子
電極間ギャップＧとなるべきパターンをホトレジスト
（ＲＤ−２０００Ｎ−４１ 日立化成社製）を形成し、
真空蒸着法により、厚さ５０オングストロ−ムのＴｉ、
厚さ１０００オングストロ−ムのＮｉを順次堆積した。
ホトレジストパターンを有機溶剤で溶解し、Ｎｉ／Ｔｉ
堆積膜をリフトオフし、素子電極間隔Ｇは３ミクロンと
し、素子電極の幅Ｗ１が３００ミクロンとなるように素
子電極９５、９６を形成した（図１４の（ｄ））。Step-d: Thereafter, a photoresist (RD-2000N-41 manufactured by Hitachi Chemical Co., Ltd.) is formed on the device electrode 95 and a pattern to be a gap G between the device electrodes.
50 angstrom thick Ti,
Ni having a thickness of 1000 angstroms was sequentially deposited.
Dissolve the photoresist pattern with an organic solvent and use Ni / Ti
The deposited film was lifted off, and the device electrodes 95 and 96 were formed so that the device electrode interval G was 3 μm and the device electrode width W1 was 300 μm (FIG. 14D).

【０１０６】工程−ｅ：素子電極９５、９６の上に上配
線９３のホトレジストパターンを形成した後、厚さ５０
オングストロ−ムのＴｉ、厚さ５０００オングストロ−
ムのＡｕを順次、真空蒸着により堆積し、リフトオフに
より不要の部分を除去して、所望の形状の上配線９３を
形成した（図１５の（ｅ））。Step-e: After forming a photoresist pattern of the upper wiring 93 on the device electrodes 95 and 96,
Angstrom Ti, 5000 Angstrom thickness
Au was sequentially deposited by vacuum evaporation, and unnecessary portions were removed by lift-off to form an upper wiring 93 having a desired shape (FIG. 15E).

【０１０７】工程−ｆ：膜厚１０００オングストロ−ム
のＣｒ膜１５１を真空蒸着により堆積・パターニング
し、その上に有機Ｐｄ（ｃｃｐ４２３０奥野製薬（株）
社製）をスピンナーにより回転塗布、３００℃で１０分
間の加熱焼成処理をした（図１５の（ｆ））。Step-f: A Cr film 151 having a thickness of 1000 angstroms is deposited and patterned by vacuum evaporation, and an organic Pd (ccp4230 Okuno Pharmaceutical Co., Ltd.) is formed thereon.
Was spin-coated with a spinner and heated and baked at 300 ° C. for 10 minutes (FIG. 15 (f)).

【０１０８】また、こうして形成された、主元素として
Ｐｄよりなる微粒子からなる電子放出部形成用薄膜１０
０の膜厚は１００オングストローム、シート抵抗値は５
×１０の４乗Ω／□であった。なお、ここで述べる微粒
子膜とは、上述したように、複数の微粒子が集合した膜
であり、その微細構造として、微粒子が個々に分散配置
した状態のみならず、微粒子が互いに隣接、あるいは、
重なり合った状態（島状も含む）の膜をさし、その粒径
とは、前記状態で粒子形状が認識可能な微粒子について
の径をいう。Further, the thus formed thin film 10 for forming an electron emitting portion, which is composed of fine particles of Pd as a main element, is formed.
A film thickness of 0 is 100 angstroms, and a sheet resistance value is 5
× 10 4 Ω / □. The fine particle film described here is, as described above, a film in which a plurality of fine particles are aggregated, and as a fine structure, not only a state in which the fine particles are individually dispersed and arranged, but also the fine particles are adjacent to each other, or
A film in an overlapped state (including an island shape) is referred to, and the particle size refers to the diameter of fine particles whose particle shape can be recognized in the above state.

【０１０９】工程−ｇ：Ｃｒ膜１５１および焼成後の電
子放出部形成用薄膜１００を酸エッチャントによりエッ
チングして所望のパターンを形成した（図１５の
（ｇ））。Step-g: A desired pattern was formed by etching the Cr film 151 and the fired electron emitting portion forming thin film 100 with an acid etchant (FIG. 15 (g)).

【０１１０】工程−ｈ：コンタクトホール１４２部分以
外にレジストを塗布するようなパターンを形成し、真空
蒸着により厚さ５０オングストロ−ムのＴｉ、厚さ５０
００オングストロ−ムのＡｕを順次堆積した。リフトオ
フにより不要の部分を除去することにより、コンタクト
ホール１４２を埋め込んだ（図１５の（ｈ））。Step-h: A pattern is formed such that a resist is applied to portions other than the contact hole 142, and a thickness of 50 angstroms of Ti and a thickness of 50 are formed by vacuum evaporation.
00 Å of Au was sequentially deposited. Unnecessary portions were removed by lift-off to bury the contact holes 142 (FIG. 15H).

【０１１１】以上の工程により絶縁性基板１上に下配線
９２、層間絶縁層１４１、上配線９３、素子電極９５、
９６、電子放出部形成用薄膜１００を形成した。Through the above steps, the lower wiring 92, the interlayer insulating layer 141, the upper wiring 93, the device electrode 95,
96, an electron emitting portion forming thin film 100 was formed.

【０１１２】次に、以上のようにして作成した電子源基
板を用いて、電子源及び該電子源を用いた画像表示装置
を構成した例を、図８と図９を用いて説明する。Next, an example in which an electron source and an image display apparatus using the electron source are configured by using the electron source substrate prepared as described above will be described with reference to FIGS. 8 and 9. FIG.

【０１１３】上述のようにして多数の電子放出素子を作
製した基板１を、リアプレート８１上に固定した後、基
板１の５ｍｍ上方に、フェースプレート８６（ガラス基
板８３の内面に蛍光膜８４とメタルバック８５が形成さ
れて構成される）を支持枠８２を介し配置し、フェース
プレート８６、支持枠８２、リアプレート８１の接合部
にフリットガラスを塗布し、大気中あるいは窒素雰囲気
中で４００℃〜５００℃で１０分以上焼成することで封
着した（図８）。After the substrate 1 on which a large number of electron-emitting devices have been manufactured as described above is fixed on the rear plate 81, a face plate 86 (with the fluorescent film 84 on the inner surface of the glass substrate 83) is placed 5 mm above the substrate 1. A metal back 85 is formed via a support frame 82, and frit glass is applied to the joint between the face plate 86, the support frame 82 and the rear plate 81, and is heated to 400 ° C. in the air or a nitrogen atmosphere. Sealing was performed by firing at 500 ° C. for 10 minutes or more (FIG. 8).

【０１１４】また、リアプレート８１への基板１の固定
もフリットガラスで行った。The fixing of the substrate 1 to the rear plate 81 was also performed using frit glass.

【０１１５】蛍光膜８４は、モノクロームの場合は蛍光
体のみから成るが、本実施例では、蛍光体はストライプ
形状を採用し、先にブラックストライプを形成し、その
間隙部に各色蛍光体を塗布し、蛍光膜８４を作製した。
ここで、ブラックストライプの材料としては、通常良く
用いられている黒鉛を主成分とする材料を用いた。尚、
ガラス基板８３に蛍光体を塗布する方法はスラリー法を
用いた。The fluorescent film 84 is composed of only a phosphor in the case of monochrome, but in the present embodiment, the phosphor is formed in a stripe shape, a black stripe is formed first, and each color phosphor is applied to the gap. Thus, a fluorescent film 84 was manufactured.
Here, as a material for the black stripe, a material mainly containing graphite, which is usually used, was used. still,
A slurry method was used to apply the phosphor onto the glass substrate 83.

【０１１６】また、蛍光膜８４の内面側には通常メタル
バック８５を設けた。このメタルバックは、蛍光膜作製
後、蛍光膜の内面側表面の平滑化処理（通常フィルミン
グと呼ばれる）を行い、その後、Ａｌを真空蒸着するこ
とで作製した。A metal back 85 is usually provided on the inner side of the fluorescent film 84. This metal back was produced by performing a smoothing treatment (usually called filming) on the inner surface of the phosphor film after producing the phosphor film, and then vacuum-depositing Al.

【０１１７】フェースプレート８６には、更に、蛍光膜
８４の導伝性を高めるため、蛍光膜８４の外面側に透明
電極（不図示）が設けられる場合もあるが、本実施例で
は、メタルバックのみで十分な導伝性が得られたので省
略した。In the face plate 86, a transparent electrode (not shown) may be provided on the outer surface side of the fluorescent film 84 in order to further enhance the conductivity of the fluorescent film 84. In this embodiment, a metal back is used. Was omitted because only sufficient conductivity was obtained.

【０１１８】また、前述の封着を行う際、カラーの場合
は各色蛍光体と電子放出素子とを対応させなくてはいけ
ないため、十分な位置合わせを行った。When the above-mentioned sealing is performed, in the case of color, the phosphors of each color must correspond to the electron-emitting devices, so that sufficient alignment is performed.

【０１１９】以上のようにして完成したガラス容器内の
雰囲気を排気管（図示せず）を通じ、真空ポンプにて排
気し、十分な真空度に達した後、容器外端子Ｄｘo １〜
ＤoｘｍとＤo ｙ１〜Ｄo ｙｎを通じ電子放出素子７４
の素子電極間に電圧を印加し、電子放出部３を、電子放
出部形成用薄膜を通電処理（フォーミング処理）するこ
とにより作成した。このときの、フォーミング処理の電
圧波形は、図４と同様であり、本実施例のフォ−ミング
も上述の実施例１と同様に行った。The atmosphere in the glass container completed as described above is evacuated by a vacuum pump through an exhaust pipe (not shown) to reach a sufficient degree of vacuum.
Electron emission device 74 through Doxm and Doy1 to Doyn
A voltage was applied between the device electrodes of No. 1 and the electron-emitting portion 3 was formed by applying a current to the thin film for forming an electron-emitting portion (forming process). At this time, the voltage waveform of the forming process is the same as that of FIG. 4, and the forming of this embodiment was also performed in the same manner as in the first embodiment.

【０１２０】以上のフォ−ミング処理により、電子放出
部３を形成し、複数の表面伝導形電子放出素子が基板１
上に配置された電子源を製造した。By the above-described forming process, the electron-emitting portion 3 is formed, and a plurality of surface conduction electron-emitting devices are mounted on the substrate 1.
The electron source placed above was manufactured.

【０１２１】次に１０のマイナス６乗トール程度の真空
度で、不図示の排気管をガスバーナーで熱することで溶
着し外囲器の封止を行った。Next, the exhaust pipe (not shown) was heated with a gas burner at a degree of vacuum of about 10 −6 Torr to weld and seal the envelope.

【０１２２】最後に封止後の真空度を維持するために、
高周波加熱法でゲッター処理を行った。Finally, to maintain the degree of vacuum after sealing,
Getter treatment was performed by a high-frequency heating method.

【０１２３】以上のように完成した本実施例の画像表示
装置において、各表面伝導形電子放出素子には、容器外
端子Ｄｘ１〜Ｄｘｍ、Ｄｙ１〜Ｄｙｎを通じ、走査信号
及び変調信号を不図示の信号発生手段よりそれぞれ印加
することにより、電子放出させ、高圧端子Ｈｖを通じ、
メタルバック８５に、数ｋＶ以上の高圧を印加し、電子
ビームを加速し、蛍光膜８４に衝突させ、励起・発光さ
せることで画像を表示した。In the image display device of the present embodiment completed as described above, the scanning signal and the modulation signal are supplied to the respective surface conduction electron-emitting devices through the external terminals Dx1 to Dxm and Dy1 to Dyn. By applying each from the generating means, electrons are emitted, and through the high voltage terminal Hv,
An image was displayed by applying a high voltage of several kV or more to the metal back 85, accelerating the electron beam, colliding with the fluorescent film 84, exciting and emitting light.

【０１２４】尚、以上の実施例２においては、表面伝導
形電子放出素子の単純マトリクス配置を例に挙げ説明し
たが、他の配置の例として、多数の表面伝導形電子放出
素子を並列に配置し、個々の素子の両端を配線にて結線
した、電子放出素子の行を多数行配列し（行方向と呼
ぶ）、この行方向と直交する方向（列方向と呼ぶ）で、
該多数の電子放出素子の上方の空間に設置された制御電
極により、電子を制御駆動する配置法によっても、上記
画像表示装置を構成することは可能である。In the second embodiment described above, the simple matrix arrangement of the surface conduction electron-emitting devices has been described as an example. However, as another arrangement, a large number of surface conduction electron-emitting devices are arranged in parallel. A large number of rows of electron-emitting devices in which both ends of each element are connected by wiring are arranged in rows (referred to as row direction), and in a direction orthogonal to the row direction (referred to as column direction),
The image display device can also be configured by an arrangement method in which electrons are controlled and driven by control electrodes provided in a space above the many electron-emitting devices.

【０１２５】また、本発明によれば、表示に用いられる
画像形成装置に限るものでなく、感光性ドラムと発光ダ
イオード等で構成された光プリンターの発光ダイオード
等の代替の発光源として、上述の画像形成装置を用いる
こともできる。この際、上述のｍ本の行方向配線とｎ本
の列方向配線を、適宜選択することで、ライン状発光源
だけでなく、2 次元状の発光源としても応用できる。Further, according to the present invention, the present invention is not limited to the image forming apparatus used for display, but may be used as an alternative light source such as a light emitting diode of an optical printer including a photosensitive drum and a light emitting diode. An image forming apparatus can also be used. In this case, by appropriately selecting the above-mentioned m row-directional wirings and n column-directional wirings, the present invention can be applied not only to a linear light emitting source but also to a two-dimensional light emitting source.

【０１２６】[0126]

【発明の効果】以上述べた本発明によれば、表面伝導形
電子放出素子の、とりわけフォ−ミング工程において、
電極間に、波高値をステップ状に増加させた複数のパル
ス電圧を印加するとともに該複数のパルス電圧の間に素
子電流を測定するための電圧を印加することにより、薄
膜を破壊または変質させるのに必要な電力以上の、過電
力投入による電子放出特性の劣化を回避でき、また、素
子抵抗のバラツキが電子放出特性に与える影響を低減で
き、均一な電子放出特性を有する表面伝導形電子放出素
子の製造が可能となった。更には、電子源として上記本
発明に係る表面伝導形電子放出素子を用いた画像表示装
置などの画像形成装置においては、とりわけ、表示画像
の輝度むらが低減される。According to the present invention described above, the surface conduction type electron-emitting device, particularly in the forming step, can be used.
A plurality of pallets with a step-like increase in the peak value between the electrodes
And applying a pulse voltage between the plurality of pulse voltages.
By applying a voltage to measure the electron current, it is possible to avoid deterioration of the electron emission characteristics due to over-power input that exceeds the power required to destroy or alter the thin film, and the variation in the element resistance causes electron emission. The influence on the characteristics can be reduced, and a surface conduction electron-emitting device having uniform electron emission characteristics can be manufactured. Further, in an image forming apparatus such as an image display apparatus using the surface conduction electron-emitting device according to the present invention as an electron source, uneven brightness of a displayed image is reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明に係る表面伝導形電子放出素子の基本構
成図。（ａ）は平面図。（ｂ）は断面図。FIG. 1 is a basic configuration diagram of a surface conduction electron-emitting device according to the present invention. (A) is a plan view. (B) is sectional drawing.

【図２】本発明の表面伝導形電子放出素子の製造方法を
説明するための断面図。FIG. 2 is a cross-sectional view for explaining a method for manufacturing a surface conduction electron-emitting device according to the present invention.

【図３】本発明に係る表面伝導形電子放出素子の特性評
価を行うための測定評価装置の概略図。FIG. 3 is a schematic diagram of a measurement and evaluation device for evaluating characteristics of the surface conduction electron-emitting device according to the present invention.

【図４】本発明の表面伝導形電子放出素子の製造方法に
係る通電処理時の電圧波形の例を示す図。FIG. 4 is a diagram showing an example of a voltage waveform at the time of energization processing according to the method for manufacturing a surface conduction electron-emitting device of the present invention.

【図５】本発明に係る表面伝導形電子放出素子の基本的
な特性を示す図。FIG. 5 is a view showing basic characteristics of a surface conduction electron-emitting device according to the present invention.

【図６】本発明に係る表面伝導形電子放出素子の他の態
様を示す斜視図。FIG. 6 is a perspective view showing another embodiment of the surface conduction electron-emitting device according to the present invention.

【図７】本発明に係る電子源の構成を示す概略図。FIG. 7 is a schematic diagram showing a configuration of an electron source according to the present invention.

【図８】本発明に係る画像形成装置の構成を示す図。FIG. 8 is a diagram showing a configuration of an image forming apparatus according to the present invention.

【図９】本発明に係る画像形成装置に用いられる蛍光膜
の説明図。FIG. 9 is an explanatory diagram of a fluorescent film used in the image forming apparatus according to the present invention.

【図１０】実施例１におけるフォ−ミング時のパルス電
圧の波高値と素子抵抗との関係を示す図。FIG. 10 is a diagram showing a relationship between a peak value of a pulse voltage and element resistance at the time of forming in the first embodiment.

【図１１】実施例１における表面伝導形電子放出素子の
特性を示す図。FIG. 11 is a diagram showing characteristics of the surface conduction electron-emitting device according to the first embodiment.

【図１２】実施例２の電子源の平面図。FIG. 12 is a plan view of the electron source according to the second embodiment.

【図１３】実施例２の電子源の部分断面図。FIG. 13 is a partial cross-sectional view of the electron source according to the second embodiment.

【図１４】実施例２の電子源の製造方法を説明するため
の断面図。FIG. 14 is a cross-sectional view for explaining the method for manufacturing the electron source according to the second embodiment.

【図１５】実施例２の電子源の製造方法を説明するため
の断面図。FIG. 15 is a cross-sectional view for explaining the method of manufacturing the electron source according to the second embodiment.

【図１６】従来の表面伝導形電子放出素子の構成を示す
概略図。FIG. 16 is a schematic view showing a configuration of a conventional surface conduction electron-emitting device.

【符号の説明】[Explanation of symbols]

１ 基板 ２，１００ 電子放出部形成用薄膜 ３，４３３ 電子放出部 ４，９４，４３４ 電子放出部を含む薄膜 ５，６，９５，９６ 素子電極 ３１，３３ 電源 ３０，３２ 電流計 ３４ アノード電極 ６７ 段差形成部 ７４，９９ 表面伝導形電子放出素子 ７２，９２ Ｘ方向配線 ７３，９３ Ｙ方向配線 ７５ 結線 ８１ リアプレート ８３ ガラス基板 ８４ 蛍光膜 ８５ メタルバック ８６ フェースプレート ８８ 外周器 ９１ 黒色伝導材 ９２ 蛍光体 １４１ 層間絶縁層 １４２ コンタクトホール DESCRIPTION OF SYMBOLS 1 Substrate 2, 100 Electron emission part forming thin film 3, 433 Electron emission part 4, 94, 434 Thin film including electron emission part 5, 6, 95, 96 Element electrode 31, 33 Power supply 30, 32 Ammeter 34 Anode electrode 67 Step forming part 74,99 Surface conduction type electron-emitting device 72,92 X-direction wiring 73,93 Y-direction wiring 75 Connection 81 Rear plate 83 Glass substrate 84 Fluorescent film 85 Metal back 86 Face plate 88 Peripheral device 91 Black conductive material 92 Fluorescent Body 141 interlayer insulating layer 142 contact hole

───────────────────────────────────────────────────── フロントページの続き (72)発明者 小野 武夫 東京都大田区下丸子３丁目30番２号キヤ ノン株式会社内 (56)参考文献 特開 平４−28139（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01J 9/02 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Takeo Ono 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (56) References JP-A-4-28139 (JP, A) (58) Survey Field (Int.Cl. 7 , DB name) H01J 9/02

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 電極間に、電子放出部を含む薄膜を有す
る表面伝導形電子放出素子の製造方法において、該電子
放出部の形成工程が、該電極間に、波高値をステップ状
に増加させた複数のパルス電圧を印加するとともに該複
数のパルス電圧の間に素子電流を測定するための電圧を
印加する工程を有することを特徴とする表面伝導形電子
放出素子の製造方法。1. A method of manufacturing a surface conduction electron-emitting device having a thin film including an electron-emitting portion between electrodes, wherein the step of forming the electron-emitting portion includes a step-like process in which a peak value is applied between the electrodes.
Plurality applied with a plurality of the pulse voltage was increased to
Voltage to measure the device current between several pulse voltages.
Method of manufacturing a surface conduction electron-emitting device characterized by having a more Engineering applied. 【請求項２】 前記パルス電圧の波高値のステップ状の
増加は、該増加速度を一定にして行われる請求項１に記
載の表面伝導形電子放出素子の製造方法。2. A stepwise <br/> increase in peak value of the pulse voltage, the manufacturing method of the surface conduction electron-emitting device according to 請 Motomeko 1 Ru done with a bulking acceleration constant. 【請求項３】 前記パルス電圧の波形が、三角波または
矩形波である請求項１に記載の表面伝導形電子放出素子
の製造方法。3. The method according to claim 1, wherein the waveform of the pulse voltage is a triangular wave or a rectangular wave. 【請求項４】 前記電子放出部を含む薄膜が導電性微粒
子で構成されている請求項１に記載の表面伝導形電子放
出素子の製造方法。4. The method of manufacturing a surface conduction electron-emitting device according to claim 1, wherein the thin film including the electron-emitting portion is made of conductive fine particles. 【請求項５】 表面伝導形電子放出素子を有し、入力信
号に応じて電子を放出する電子源の製造方法において、
該表面伝導形電子放出素子が、請求項１〜４のいずれか
に記載の製造方法にて製造されることを特徴とする電子
源の製造方法。5. A method of manufacturing an electron source having a surface conduction electron-emitting device and emitting electrons in response to an input signal,
Method of manufacturing an electron source in which the surface conduction electron-emitting device, characterized in that it is produced by the production method according to any one of claims 1-4. 【請求項６】 表面伝導形電子放出素子と画像形成部材
とを有し、入力信号に応じて画像を形成する画像形成装
置の製造方法において、該表面伝導形電子放出素子が、
請求項１〜４のいずれかに記載の製造方法にて製造され
ることを特徴とする画像形成装置の製造方法。6. and a surface conduction electron emitting device and an image forming member, in the manufacturing method of an image forming apparatus for forming an image according to the input signal, the surface conduction type electron-emitting device,
Produced by the production method according to any one of claims 1-4
Method of manufacturing an image forming apparatus characterized by that.
JP33110393A 1993-12-27 1993-12-27 Surface conduction electron-emitting device, electron source, and method of manufacturing image forming apparatus Expired - Fee Related JP3200270B2 (en)

Priority Applications (32)

Application Number Priority Date Filing Date Title
JP33110393A JP3200270B2 (en) 1993-12-27 1993-12-27 Surface conduction electron-emitting device, electron source, and method of manufacturing image forming apparatus
CA002126509A CA2126509C (en) 1993-12-27 1994-06-22 Electron-emitting device and method of manufacturing the same as well as electron source and image-forming apparatus
CA002418595A CA2418595C (en) 1993-12-27 1994-06-22 Electron-emitting device and method of manufacturing the same as well as electron source and image-forming apparatus
CA002540606A CA2540606C (en) 1993-12-27 1994-06-22 Electron-emitting device and method of manufacturing the same as well as electron source and image-forming apparatus
CA002299957A CA2299957C (en) 1993-12-27 1994-06-22 Electron-emitting device and method of manufacturing the same as well as electron source and image-forming apparatus
AT99112412T ATE501519T1 (en) 1993-12-27 1994-06-23 PRODUCTION METHOD OF AN ELECTRON EMITTING DEVICE
AT94109787T ATE237185T1 (en) 1993-12-27 1994-06-23 ELECTRON EMITTING DEVICES
EP94109787A EP0660357B1 (en) 1993-12-27 1994-06-23 Electron-emitting devices
AU65922/94A AU6592294A (en) 1993-12-27 1994-06-23 Electron-emitting device and method of manufacturing the same as well as electron source and image-forming apparatus
US08/264,497 US6169356B1 (en) 1993-12-27 1994-06-23 Electron-emitting device, electron source and image-forming apparatus
DE69432456T DE69432456T2 (en) 1993-12-27 1994-06-23 Electron-emitting devices
EP99112412A EP0942449B1 (en) 1993-12-27 1994-06-23 Method of manufacturing an electron-emitting device
DE69435336T DE69435336D1 (en) 1993-12-27 1994-06-23 Manufacturing method of an electron-emitting device
AT07118989T ATE523893T1 (en) 1993-12-27 1994-06-24 IMAGE PRODUCING DEVICE
CNB2004100039544A CN1306540C (en) 1993-12-27 1994-06-24 Method for producing electronic transmitting device
CN94109010A CN1086055C (en) 1993-12-27 1994-06-24 Electron-emitting device and method of manufacturing the same as well as electron source and image-forming apparatus
AT01104026T ATE381109T1 (en) 1993-12-27 1994-06-24 ELECTRON SOURCE AND IMAGE PRODUCING DEVICE
EP01104026A EP1124248B1 (en) 1993-12-27 1994-06-24 Electron source and image forming apparatus
EP07118989A EP1892743B1 (en) 1993-12-27 1994-06-24 Image forming apparatus
DE69435051T DE69435051T2 (en) 1993-12-27 1994-06-24 Electron source and imaging device
CNB200610100715XA CN100438589C (en) 1993-12-27 1994-06-24 TV set and image display device
KR1019940014559A KR0154358B1 (en) 1993-12-27 1994-06-24 Electron-emitting device
KR1019980014201A KR0170822B1 (en) 1993-12-27 1998-04-21 Electron emission device, method of manufacturing the same, electron source, and image forming apparatus
US09/332,101 US6802752B1 (en) 1993-12-27 1999-06-14 Method of manufacturing electron emitting device
US09/332,100 US6384541B1 (en) 1993-12-27 1999-06-14 Electron-emitting device, electron source, and image-forming apparatus
US09/513,841 US6344711B1 (en) 1993-12-27 2000-02-25 Electron-emitting device
CNB001083791A CN1174460C (en) 1993-12-27 2000-05-11 Electron-emitting device manufacturing method
CNB001085654A CN1174459C (en) 1993-12-27 2000-05-18 Electron source, image forming device
US10/615,995 US6908356B2 (en) 1993-12-27 2003-07-10 Electron-emitting device, electron source, and image-forming apparatus
US10/776,171 US6890231B2 (en) 1993-12-27 2004-02-12 Electron-emitting device, electron source, and image forming apparatus
US11/008,925 US7348719B2 (en) 1993-12-27 2004-12-13 Electron-emitting devices provided with a deposit between electroconductive films made of a material different from that of the electroconductive films
US12/037,684 US7705527B2 (en) 1993-12-27 2008-02-26 Electron-emitting device, electron source, and image-forming apparatus

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