JP3285855B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, LOCOS has been widely used for isolation between elements of a semiconductor integrated circuit. But LOC
Since the OS involves a bird's beak problem, it is not suitable for element separation of a VLSI. An STI (Shallow Trench Isolation) structure has been proposed as an element division structure replacing the LOCOS. The STI structure has a relatively shallow trench (depth: 0.2 to 0.6 μm) in an isolation region of a silicon substrate.
m), and the trench is filled with a SiO ₂ film.

[0003] The STI structure is an isolation technique that replaces LOCOS when the area of the source / drain region is small, in other words, when the distance between the edge of the gate and the edge of the element region is small. Therefore, adoption of the STI structure
This has great significance as a technology for separating a semiconductor device in which minute transistors whose distance between the edge of the gate and the edge of the element region is, for example, about 0.7 μm or less are integrated.

Referring to FIGS. 1 (a) to 1 (d), ST
A method for manufacturing a conventional semiconductor device having an I structure will be described.

First, a structure shown in FIG. 1A is manufactured.
This structure includes a trench 10 formed in an isolation region of a silicon substrate 1 and an SiO ₂ film 1 filling the trench 10.
1 and the trench 10 and the SiO ₂ film 11
Forms an STI structure.

[0006] A region surrounded by the isolation region functions as an element region or an active region. 1A includes a gate insulating film 2 formed in an element region, a gate electrode 3 formed on the gate insulating film 2, and a source / drain region 4 formed on the surface of the silicon substrate 1. ing. These are components of a MOS transistor. FIG.
In (a), an SiO ₂ film 5a is deposited so as to cover both the element region and the isolation region.

[0007] Next, as shown in FIG. 1 (b), SiO ₂
By etching back the film 5a, the SiO ₂ film 5 is formed.
a is left on the side surface of the gate electrode 3, thereby forming the sidewall spacer 5b. Thereafter, an ion implantation step is performed using the gate electrode 3 and the side wall spacers 5b as a mask to form a high concentration portion of the source / drain region 4. Side wall spacer 5
The low concentration portion of the source / drain region 4 located below b functions as an LDD.

At the time of etching the SiO ₂ film 5a, the uppermost portion of the STI structure, ie, S
The uppermost part of the iO ₂ film 11 is also etched. As a result, a step (level difference) occurs between the upper surface of the element region and the upper surface of the SiO ₂ film 11. This step is 20 to
It is considered to have a size of about 100 nm.

Next, as shown in FIG. 1C, after these structures are covered with an interlayer insulating film 6, a predetermined portion of the interlayer insulating film 6 is etched, and a contact hole 12 is formed in that portion. At the time of this etching, the upper part of the SiO ₂ film 11 is etched, and the step is further increased. The size of the step at this time reaches about 50 to 200 nm.

In recent years, the junction depth of the source / drain regions 4 has tended to become increasingly shallow. In the case of a semiconductor device having a degree of integration that is meaningful to employ the STI structure, the junction depth of the source / drain region 4 is about 30 to 150 nm. This is smaller than the size of the step. Therefore, in the process step shown in FIG. 1C, the pn junction of the source / drain region 4 is exposed on the side surface of the step.

Next, as shown in FIG. 1D, the contact holes 12 in the interlayer insulating film 6 are filled with metal plugs 13 such as tungsten. This metal plug 1
Reference numeral 3 plays a role of realizing electrical conduction between an upper wiring (not shown) formed on the interlayer insulating film 6 and the source / drain region 4.

[0012]

A part of the pn junction of the source / drain region 4 is in direct contact with the metal plug 13 as shown in FIG. For this reason, a large current leak occurs through a path schematically indicated by an arrow.

FIGS. 2A and 2B show a state in which a relatively narrow contact hole is formed on a source / drain region having a relatively large area, and the contact hole is filled with a metal plug 13. Is shown. Such a configuration can be employed in a semiconductor device with a low degree of integration. In this case, the metal plug 13
Is in contact with the upper surface of the source / drain region 4 and is not in contact with the pn junction of the source / drain region 4. Therefore, no current leaks through the metal plug 13. When the distance Z shown in FIG. 2B is about 0.8 μm or more, it is possible to form the metal plug 13 so as not to protrude above the separation region.
If the degree of integration is improved so as to be less than about 8 μm, it becomes difficult to form the metal plug 13 so as not to protrude above the isolation region.

In the case of the structure shown in FIGS. 2A and 2B, the SiO ₂ film 11 in the trench is not etched by the etching for forming the contact hole. Furthermore, conventionally, the source / drain region 4
Of the element region 20 was also relatively large.
Level difference Y between the upper surface of the upper surface and the SiO ₂ film 11 is smaller than the junction depth X of the source / drain regions 4. For this reason, conventionally, even if the position of the contact hole is shifted and thereby the metal plug 13 crosses the boundary between the element region and the isolation region, the pn junction of the source / drain region 4 contacts the metal plug 13. No leak path was formed as shown in FIG. 1 (d).

However, as device dimensions have been miniaturized and the manufacturing method shown in FIGS. 1A to 1D has been adopted, current leakage occurs along a path which has not been a problem in the past. I understood.

The present invention has been made in view of the above points, and a main object of the present invention is to form a contact hole for connecting a source / drain region and a wiring at a boundary portion between the source / drain region and the STI structure. It is an object of the present invention to provide a semiconductor device in which current leakage due to a step at a boundary portion thereof is suppressed when the semiconductor device is formed so as to straddle the semiconductor device, and a method for manufacturing the same.

[0017]

A semiconductor device according to the present invention comprises a semiconductor substrate having an element region and an isolation region, a gate electrode structure formed on the element region, and a half of the element region.
A trench isolation structure including a source / drain region formed in a conductive substrate, a trench formed in an isolation region, and an insulator embedded in the trench, and a gate electrode structure
Of element regions where source and drain regions are formed
Formed on the isolation region where the trench isolation structure is formed
Oxide film and the side of the gate electrode structure where the oxide film is formed
Insulating sidewall spacers formed on the wall and oxidation
Silicon nitride film formed on the film and silicon
Interlayer insulation film formed on nitride film and interlayer insulation
Etch film, silicon nitride film and oxide film
And reach the source / drain regions.
A first opening, a second opening, and a first opening and a second opening.
And an electrode buried in the second opening and in contact with the source / drain region, respectively, and the first opening and the second opening are formed with a part of each region of the corresponding source / drain region. It is formed on a region that straddles each part of the trench isolation structure adjacent to a part thereof.

[0018]

In a preferred embodiment, the insulating sidewall
The aluminum spacer is formed from a silicon nitride film.

Also, in a preferred embodiment, the first opening
The mouth and the second opening are insulative sidewall spaces.
It is formed by further removing a part of the semiconductor.

In a preferred embodiment, the oxide film
The film thickness is 20 to 50 nm.

The method for manufacturing a semiconductor device according to the present invention comprises:
A trench isolation structure including a trench formed in an isolation region of a semiconductor substrate and an insulator embedded in the trench, and a gate electrode structure of a MOS transistor formed in an element region of the semiconductor substrate surrounded by the trench isolation structure (A), a step (b) of depositing an oxide film on the isolation region and the element region after the step (a), and an insulating sidewall on the side wall of the gate electrode structure after the step (b). A step (c) of forming a spacer, a step (d) of depositing a silicon nitride film serving as an etch stop layer on the oxide film and the insulating sidewall spacer after the step (c), and a step of forming a silicon nitride film and (e) forming an interlayer insulating film on the silicon nitride film as an etch stop layer, source of the MOS transistor in the interlayer insulating film The first opening and the first opening are formed in the interlayer insulating film by etching the upper portion of the region over each of a part of each region of the drain / drain region and a part of the trench isolation structure adjacent to the part. and forming a second opening (f), exposed at the bottom of the first opening and the second opening formed in the interlayer insulating film Shirikon'na
Etch nitride film, silicon nitride film
(G) exposing an oxide film located underneath ;
First opening and second opening formed in interlayer insulating film
Selectively etch the oxide film exposed at the bottom of the part
To expose a part of the surface of the source / drain region
(H), the surface of the source / drain region is formed via the first opening and the second opening formed in the interlayer insulating film .
( I ) forming an electrode that comes into contact with a part thereof.

[0023]

In a preferred embodiment, the insulating sidewall
The aluminum spacer is formed from a silicon nitride film.

In a preferred embodiment, the step
(G), a first opening formed in the interlayer insulating film;
And an insulating die located at the bottom in the second opening.
The wall spacer is removed .

In a preferred embodiment, the oxide film
The film thickness is 20 to 50 nm.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) A method of manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. 3 (a) to 3 (c) and FIGS. 4 (a) and 4 (b).

First, the structure shown in FIG. 3A is manufactured through the known process described with reference to FIGS. 1A and 1B. This structure includes a trench 40 having a depth of about 0.2 to 0.6 μm formed in an isolation region of a p-type silicon substrate 31 and an SiO ₂ film 4 filling the trench 40.
1 and the trench 40 and the SiO ₂ film 41
Forms an STI structure.

The region surrounded by the trench 40 is an element region
(Or active region). Structure of FIG.
Indicates the gate insulating film 32 formed in the element region,
A gate electrode (gate length: 0.1) formed on the edge film 32
3 to 0.25 μm, gate width: about 2.0 μm) 33,
And source / drain regions formed on the surface of the element region
An area 34 is provided. The source / drain regions 34
On the other hand, it consists of a part with low impurity concentration and a part with high impurity concentration.
ing. Further, both side surfaces of the gate electrode 33 are made of _TwoMembrane
Covered by the sidewall spacer 35b formed from
Have been done. These are the components of MOS transistors
It is.

In the structure of FIG. 3A, a step is formed between the upper surface of the element region and the upper surface of the SiO ₂ film 41. In the case of the present embodiment, the size of the step in the process step shown in FIG. 3A is about 20 to 100 nm.
The size of the step is 50 nm depending on the manufacturing process conditions.
It fluctuates within a range. In the present embodiment, the size of the source / drain region 34 in the channel length direction (the size corresponding to the distance Z in FIG. 2B) is about 0.1 to 0.7 μm, and the junction depth is 30 to 150 nm. It is about.

Next, as shown in FIG. 3B, these structures are covered with an insulating film (thickness: 50 nm) 45 made of silicon nitride or the like, and then, as shown in FIG. An interlayer insulating film (thickness: 0.5 to 1.0) is formed on the film 45.
μm) 36 is deposited by a CVD method or the like. The upper surface of the interlayer insulating film 36 is preferably planarized by a CMP (chemical mechanical polishing) method.

The insulating film 45 is formed of a material different from the material of the interlayer insulating film 36. More specifically, the interlayer insulating film 3
When etching 6, the insulating film 45 is preferably formed from a material that functions as an etch stop layer. A silicon oxide film or a low dielectric constant organic film as the interlayer insulating film 36;
Alternatively, when a multilayer film is used, the insulating film 45 is preferably formed from a silicon nitride film. This is because it is easy to sufficiently increase the etching selectivity. Since the insulating film 45 is preferably a film having good coverage, it is preferably deposited by a CVD method.

The insulating film 45 is formed in the source / drain region 34
To achieve the electrical insulation between the metal plug and the metal plug. If the thickness of the insulating film 45 is too thin, this function is deteriorated. Therefore, it is considered that the thickness of the insulating film 45 needs to be at least 20 nm. On the other hand, if the insulating film 45 is too thick, the time for over-etching increases, and
Since the adverse effect that the sag of the SiO ₂ film 41 becomes large may occur, the thickness of the insulating film 45 is 100 nm.
The following is preferred. After all, the preferable range of the thickness of the insulating film 45 is 20 to 100 nm.

Next, using a known lithography technique,
As shown in FIG. 3C, a resist mask 46 having an opening 47 for defining the position and shape of the contact hole is formed on the interlayer insulating film 36. Thereafter, the interlayer insulating film 36 is etched using an SiO ₂ etching gas such as CF ₄ under the etching conditions of 3 Pa and RF power of 500 W as shown in FIG.
Thus, a contact hole 48 is formed in the interlayer insulating film 36. This contact etching is performed until the surface of the insulating film 45 is exposed. Insulating film 45 of the present embodiment
Is formed of silicon nitride, the etching of the insulating film 45 hardly occurs by the contact etching, and the insulating film 45 functions as an etch stop layer. A time sufficiently exceeding the etching time required to etch the interlayer insulating film 36 by the thickness thereof,
Contact etching is performed (over-etching is performed), and the insulating film 4 exposed at the bottom of the contact hole 48 is formed.
The silicon oxide film can hardly be left on 5.

In this embodiment, the size of the contact hole 48 is, for example, 0.16 to 0.3 μm. This size is about 50% to 100% of the size of the source / drain region 34 in the channel length direction (the size corresponding to the distance Z in FIG. 2B).

Next, the insulating film 45 is etched with strong anisotropy. As shown in FIG. 4A, most of the insulating film 45 located at the bottom of the contact hole 48 is removed by this etching, but the portion located near the step remains as a sidewall spacer 45b. Cover the side of the step. The thickness of the sidewall spacer 45b formed from the insulating film 45 is 20 to 100.
nm.

In the anisotropic etching, for example, Cl ₂ +
Pressure 5P using SiN etching gas such as CHF ₃
Since the RF power is set to 250 W under a,
The SiO ₂ film 41 in the trench 40 is hardly etched. For this reason, the size of the step shown in FIG. 3A does not increase by the etching process shown in FIG.

Next, as shown in FIG. 4B, the inside of the contact hole 48 is filled with a conductive plug 49 such as tungsten. The conductive plug 49 plays a role as a drain electrode for realizing electrical conduction between an upper wiring (not shown) formed on the interlayer insulating film 36 and the source / drain region 34. The conductive plug 49 is formed by depositing a tungsten film by sputtering, for example,
It can be formed by removing unnecessary portions using a flattening technique such as a (chemical mechanical polishing) method. Alternatively, the conductive plug 49 may be formed by a selective growth method. In any case, the conductive plug 49 is in contact with the upper surface of the source / drain region 34, where electrical contact is realized.

As described above, according to the present embodiment, the source /
Since the portion of the pn junction of the drain region 34 located on the side surface of the step is covered with the sidewall spacer 45b, the pn junction of the source / drain region 34 is not in contact with the conductive plug 49. Since the side wall spacer 45b has an insulating property, FIG.
No current leak occurs along the path schematically shown by the arrow (d).

(Second Embodiment) A method of manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS.

First, the structure shown in FIG. 5A is manufactured through the known process described with reference to FIGS. 1A to 1C. This structure is basically the same as the structure shown in FIG. 3A, except that the interlayer insulating film 36 covers the upper surface of the substrate 31 and an opening 47 is provided on the interlayer insulating film 36. The difference is that a resist mask 46 is formed. The resist mask 46 is formed by a usual lithography technique, and the opening 47 defines a position and a shape of a contact hole to be formed in the interlayer insulating film 36.

Next, the RF power was increased to 500 W under a pressure of 3 Pa using an SiO ₂ etching gas such as CF _4.
Under such etching conditions, the interlayer insulating film 36 is etched as shown in FIG. 5B, thereby forming a contact hole 48 in the interlayer insulating film 36. This contact etching is performed on the surface (source / source) of the silicon substrate 31.
The process is performed until the drain region 34) is exposed. By this contact etching, the SiO ₂ film 4 in the STI structure is formed.
1 occurs, and the size of the step is 50 to 200 n.
m.

After removing the resist mask 46, FIG.
As shown in (c), an insulating sidewall spacer 50 is formed on the inner wall of the contact hole 48 and the side surface of the step. This insulating sidewall spacer 50 is formed of an insulating film (thickness: 10 to 10) made of silicon nitride or the like.
After covering the structure of FIG. 5B with 50 nm), the insulating film is formed by performing strong anisotropic etching.

Next, as shown in FIG. 5D, the inside of the contact hole 48 is filled with a conductive plug 49 of tungsten or the like.
Embed by The conductive plug 49 is used for the interlayer insulating film 36.
It functions as a drain electrode for realizing electrical conduction between an upper layer wiring (not shown) formed above and the source / drain region 34. The conductive plug 49 can be formed, for example, by depositing a tungsten film by a sputtering method and then removing an unnecessary portion by using a planarization technique such as a CMP (chemical mechanical polishing) method. Alternatively, the conductive plug 49 may be formed by a selective growth method. Also in this embodiment, the conductive plug 49 is in contact with the upper surface of the source / drain region 34, and an electrical contact is realized there.

As described above, also in the present embodiment, the portion of the pn junction of the source / drain region 34 located on the side surface of the step is covered with the insulating sidewall spacer 50, so that the source / drain region 34 is formed. P
The n-junction is not in contact with the conductive plug 49. As a result, current leakage does not occur in the path schematically shown by the arrow in FIG.

An example of a planar layout of the semiconductor device of the present invention will be described with reference to FIG. As can be seen from FIG. 6, the island-shaped element region 60 is surrounded by the isolation region, and the trench 41 for the STI structure is formed in the isolation region. For simplicity, FIG. 6 shows only a single element region 60, but in reality many element regions 60 are arranged on the surface of the silicon substrate. The gate electrode 33 has a wiring shape and crosses the element region 60. The contact hole 48 is patterned so as to cross the boundary between the element region 60 and the trench 41. Electrical contact between the electrode and the source / drain region is achieved in a region where the device region 60 and the contact hole 48 overlap (actual contact region). The area of this actual contact region is smaller than the cross-sectional area of the contact hole. If the contact hole 48 is formed so as not to protrude from the element region 60 into the trench 41, the contact hole 48 is patterned so as to overlap the gate electrode 33, or less than about half the size shown in the figure. It is formed to be reduced in size. Since it is difficult to further reduce the size of the contact hole 48, as shown in FIG. 6, the contact hole 48 is arranged on a relatively wide region crossing the boundary between the element region 60 and the isolation region. Is preferred.

(Third Embodiment) Next, FIGS.
Another embodiment of the semiconductor device according to the present invention will be described with reference to (c) and FIGS. 8 (a) to (c).

First, a structure shown in FIG.
This structure has a trench (depth: 0.4 μm) formed in an isolation region of a silicon substrate 71 and an SiO ₂ film 72 filling the trench.
The STI structure is formed by the O ₂ film 72. The region surrounded by the isolation region functions as an element region or an active region. 7A includes a gate insulating film 73 formed in an element region, a gate electrode 74 formed on the gate insulating film 73, and an insulating film 7 provided on the gate electrode 74.
5 and a source / drain region 76 formed in the silicon substrate 71. These are components of a MOS transistor. Further, an SiO ₂ film (thickness: 0.1 μm) is formed so as to cover both the element region and the isolation region.
m) 77 is formed, and a silicon nitride film (thickness: 0.5 μm) 78 is deposited on the SiO ₂ film 77. SiO ₂ film 77 and silicon nitride film 78
It is, for example, be formed by a CVD method or the like, SiO ₂
The film 77 can also be formed by a thermal oxidation method.

Next, as shown in FIG. 7B, the silicon nitride film 78 is etched with high anisotropy to remove most of the silicon nitride film 78 and to remove the silicon nitride film 78. Is formed on the side wall of the gate electrode structure. The etching conditions are, for example, RF using a SiN etching gas such as Cl ₂ + CHF ₃ under a pressure of 5 Pa.
The power is 250W. The size of the sidewall spacer 78b measured along the channel length direction is 10 to
It becomes 50 nm. Under these etching conditions, the SiO ₂ film 77 located under the silicon nitride film 78 is hardly etched.

Next, as shown in FIG. 7C, FIG.
After depositing a second silicon nitride film (thickness: 0.05 μm) 82 covering the structure of (b) by the CVD method, an interlayer insulating film (thickness: 1 μm) 79 is formed thereon by CVD.
Deposited by the method. Next, a contact hole 80 is formed in the interlayer insulating film 79 by using a lithography technique and an etching technique. The contact hole 80 is formed at the position shown in FIG. 6 on the layout, but the actual planar shape may be a circle or an oval instead of a rectangle. The etching of the interlayer insulating film 79 for forming the contact hole 80 is performed by using an SiO ₂ etching gas such as CF ₄ and applying an RF power of 5 under a pressure of 3 Pa.
It is performed under the etching condition of 00W. For this reason,
The underlying silicon nitride film 82 of the interlayer insulating film 79 is
It is hardly etched and functions as an etch stop film. When the etching of the interlayer insulating film 79 is completed,
A silicon nitride film 82 exists on the bottom of the contact hole 80.

Next, the contact hole 8 is formed under conditions of high anisotropy for selectively etching silicon nitride.
The silicon nitride film 82 existing at the bottom in
Then, the sidewall spacer 78b is removed from the inside of the contact hole 80 (FIG. 8A). By this etching, the SiO ₂ film 7 is formed on the bottom of the contact hole 80.
7 appears.

Next, as shown in FIG. 8B, the SiO ₂ film 77 located at the bottom of the contact hole 80 is selectively etched to expose the surface of the source / drain region 76. Since the SiO ₂ film 77 is formed as thin as 0.1 μm, it is almost completely removed from the source / drain region 76 in a relatively short time. For this reason,
By etching the SiO ₂ film 77, the S
The iO ₂ film 72 is not dug deep. Therefore, the upper surface of the source / drain region 76 and the Si
No large step is formed between the upper surface of the O ₂ film 72 and the pn junction of the source / drain region 76 does not appear on the side surface of the step. In other words, the source / drain regions 7
The pn junction of No. 6 is completely covered by the SiO ₂ film 72 in the trench.

Next, as shown in FIG. 8C, a metal plug 81 is buried in the contact hole to achieve contact between the metal plug 81 functioning as an electrode and the source / drain region 76. As can be seen from FIG.
No current leak path is formed between the source / drain region 76 and the substrate 71 via the metal plug 81.

The preferable thickness range of the SiO ₂ film 77 is 20 to 50 nm. The preferable thickness range of the second silicon nitride film 82 is 20 to 50 nm.

(Fourth Embodiment) Next, still another embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 9 (a) and 9 (b).

FIG. 9A shows a cross section of a semiconductor device in which source / drain regions are formed in a silicon layer epitaxially grown on a silicon substrate.

In this semiconductor device, the MO formed in the element region of the p-type
The semiconductor device includes an S-type transistor and a trench isolation structure 92 formed in an isolation region. The feature of this embodiment is that the silicon layer 97 epitaxially grown on the element region of the silicon substrate 91 has
7 functions as a source / drain region of a MOS transistor.

The gate structure of the MOS transistor includes a gate insulating film 93 formed on a silicon substrate 91, a gate electrode 94 formed on the gate insulating film 93, and an insulating layer 95 formed on the gate electrode 94. And
The side surface of this gate structure is covered with a sidewall insulating film 96. The MOS transistor and the trench isolation structure have a relatively thin silicon nitride film 9.
9 and a relatively thick interlayer insulating film 100. An opening is formed in the interlayer insulating film 99, and the opening reaches a part of the source / drain impurity diffusion layer of the MOS transistor and a part of the trench isolation structure.
An electrode plug 101 is provided in the opening of the interlayer insulating film 100, and this electrode plug 101 is in contact with the source / drain impurity diffusion region.

In the structure of FIG. 9A, the n-type impurity doped in the silicon layer 97 diffuses shallowly from the surface of the silicon substrate 91 to the inside of the substrate, and the n-type impurity layer for the source / drain region and the silicon A pn junction 98 is formed with the substrate 91.

Also in this embodiment, a step is formed between the upper surface of the element region and the upper surface of the trench isolation structure.
At least one of the source / drain impurity diffusion layers reaches the side surface of the step, and an insulating sidewall spacer 99b is inserted between the side surface of the step and the electrode 101. The insulating side wall spacers 99b are shown in FIGS.
It is manufactured by a method similar to the method described with reference to FIG.

FIG. 9B is a device obtained by modifying the semiconductor device of FIG. 9A. The difference between the device shown in FIG. 9B and the device shown in FIG. 9A is the following two points.

First, in the device of FIG. 9A, the impurity diffusion layer for the source / drain region has reached the silicon substrate 91, but in the device of FIG. Impurity diffusion layer exists inside the silicon layer 97.

Next, in the device of FIG. 9A, the insulating side wall spacer 99b was not present on the inner side surface of the contact hole, but in the device of FIG. 102 is present on the inner surface of the contact hole. Such an insulating side wall spacer 102 can be formed by the method described with reference to FIG.

According to the semiconductor device of FIG. 9B, since the source / drain region is formed inside the silicon layer 97, the channel formed below the gate electrode 94 and the source / drain region are not formed. A relatively large offset area can be formed between them.

(Fifth Embodiment) Hereinafter, FIG.
Another embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. Although a single N-channel MOS transistor is shown in the figure, many transistors are actually integrated on the same substrate.

First, as shown in FIG. 10A, after an STI structure 202 is formed in a selected region of a P-type silicon substrate 201 by a known manufacturing process, a gate oxide film (thickness: 3 to 8 nm) is formed. 203 is formed. STI structure 2
02 is formed in an isolation region (field region) on the main surface of the silicon substrate 201. Silicon substrate 201
Of the main surface where the STI structure 202 is not formed is used for the active region of the transistor. After forming the gate insulating film 203 using a known method, the lower N-type polycrystalline silicon layer (thickness: 100 to 300 nm) 2
04 and upper cap layer (thickness: 50 to 200 nm)
A gate structure including 205 is formed on the gate oxide film 203. This gate structure is formed through a thin film deposition process, a lithography process, and an etching process. The size of the gate structure measured along the channel length direction, that is, the gate length L is set to, for example, 0.1 to 0.2 μm,
The gate width W (channel width) can be set to, for example, 1 to 10 μm. Note that the cap layer 205 of this embodiment is formed of silicon dioxide (SiO ₂ ). The cap layer 205 may be formed from silicon nitride (such as Si ₃ N ₄ ) or another insulating material.

After the entire top surface of the structure shown in FIG. 10A is covered with a nitride film (not shown) (thickness: 30 to 100 nm), unnecessary portions of the nitride film are removed by anisotropic dry etching. Thus, as shown in FIG. 10B, the sidewall protective layer 206 formed of a nitride film is disposed on the side surface of the gate structure. The thickness of the sidewall protective layer 206 can be adjusted with high accuracy by the thickness of the nitride film to be deposited and the conditions of anisotropic dry etching.

Next, as shown in FIG. 10C, a P-type layer having a thickness of about 50 nm is formed by using a selective epitaxial growth technique.
A type single crystal silicon layer 207 is grown on the silicon substrate 201. This selective growth is performed, for example, by using disilane gas (3
sccm), diborane gas (0.01 sccm), and chlorine gas (0.02 sccm).
The temperature can be performed at 630 ° C. At this temperature, disilane gas is thermally decomposed, and epitaxial growth of silicon proceeds on exposed silicon. Chlorine gas is introduced to remove an amorphous silicon layer which is simultaneously grown on an oxide film or a nitride film. Note that a silane gas or another silicon compound gas may be used instead of the disilane gas. In addition, borane or another boron compound gas may be used instead of diborane as the P-type dopant gas. Further, another chlorine compound gas may be used instead of the chlorine gas.

Next, as shown in FIG. 10D, sidewall spacers 208 made of silicon nitride are formed.
Cover the step side with. The sidewall spacer 208
For example, after depositing a silicon nitride film by a CVD method or the like, the silicon nitride film is formed on the side wall of the gate electrode structure and the side wall of the P-type single crystal silicon layer 207 by performing anisotropic etching on the film.

Next, as shown in FIG. 10E, a single-crystal silicon layer 209 having a thickness of about 100 nm is formed using a selective epitaxial growth technique.
Grow on. This selective growth is performed by, for example, disilane gas (10 sccm) and chlorine gas (0.04 scc).
m) The raw material gas was used, and the temperature was 630 ° C.
Regarding the type of source gas, the P-type single crystal silicon layer 20
What is said about 7 applies. For the sake of simplicity, the multilayer film formed by the above two types of selective growth steps will be referred to as a “laminated structure”. In this embodiment,
The height of the stacked structure is set to be substantially equal to the height of the gate structure. Therefore, as shown in FIG. 10E, the upper surfaces of the stacked structure, the gate structure, and the sidewall spacers are located at substantially the same level, thereby improving the flatness of the transistor. Therefore, there is an advantage that after the transistor is covered with the interlayer insulating film, the transistor is easily planarized by chemical mechanical polishing (CMP).

With respect to this “laminated structure”, a dose amount of 2 ×
After implanting 10 ¹⁵ cm ^-2 arsenic (As) ions at an energy of 40 keV, a heat treatment is performed at, for example, about 950 ° C for 30 seconds. As a result, source / drain diffusion layers are formed in the “stacked structure”. Note that other N-type impurity ions such as phosphorus may be used instead of arsenic ions. The source / drain diffusion layers extend from the upper surface of the “stacked structure” to the lower layer of the “stacked structure”, that is, the inside of the single-crystal silicon layer 207. In other words, the N-type dopant introduced into the stacked structure by the above-described ion implantation diffuses throughout the single crystal silicon layer 209 and also diffuses into the upper portion of the single crystal silicon layer 207. Therefore, the P-type single-crystal silicon layer 2 immediately after the epitaxial growth
07 is made N-type, and a PN junction is formed inside single crystal silicon layer 207. In the present embodiment, the source /
Part of the P-type single-crystal silicon layer 207 exists between the drain diffusion layer 209 and the channel region as P-type. In other words, the source / drain diffusion layers are offset from the channel region.

A titanium film having a thickness of about 50 nm is formed as shown in FIG.
After depositing on the structure of (e), a titanium silicide film may be formed on the “laminated structure” by a heat treatment at 650 ° C. for 60 seconds. In this case, after removing unreacted titanium with sulfuric acid and hydrogen peroxide, heat treatment is performed at 900 ° C. for 10 seconds, thereby reducing the resistance of the titanium silicide film.

Next, as shown in FIG. 10F, after an interlayer insulating film 210 is deposited on the silicon substrate 201, a contact hole 211 is provided in the interlayer insulating film 210. The contact hole 211 is formed so as to cross the boundary between the element region and the isolation region, and exposes the side surface of the “laminated structure” and the surface of the STI structure.

Next, as shown in FIG. 10 (g), a conductive plug (source / drain electrode) 212 that contacts the source / drain region via the contact hole 211 is formed. Thereafter, a multilayer wiring is further formed through a normal manufacturing process.

According to the manufacturing method of this embodiment, the source /
In the “laminated structure” in which the drain region is formed, the side surface of the P-type single-crystal silicon layer 207 where the pn junction is located is covered with an insulating sidewall spacer 208. Therefore, the pn junction of the source / drain region does not come into contact with the conductive plug 212, and no current leaks along a path schematically shown by an arrow in FIG.

Further, according to this manufacturing method, the structure for the stacked source / drain is formed by a two-stage epitaxial growth process as shown in FIGS. 10 (c) and 10 (e). First single crystal silicon layer 207
In the growth of, the growth rate is as low as about 10 nm / min due to the small amount of supply gas, and a processing time of about 5 minutes is required. Although the growth rate is low, the crystallinity of the grown film is good and it can be formed almost without defects. Therefore, if the junction surface of the source / drain diffusion layer is formed in single-crystal silicon layer 207, junction leakage due to crystal defects does not increase.

In the second silicon layer growth, since the amount of the supplied gas is relatively large, the growth rate can be increased to about 20 nm / min, and the growth can be completed in about 5 minutes. Fast growth (2 of the first growth rate)
On the other hand, the crystallinity is relatively poor, and relatively many defects are generated. However, since the pn junction is not located in this crystal layer, there is no influence on the junction leak.

In order to epitaxially grow the silicon layer for the stacked source / drain to the same thickness as in the above embodiment, according to the conventional one-step growth,
It takes about 15 minutes. In this embodiment, the time required for the growth of the corresponding silicon layer is about 2/3 of that of the prior art.
(About 10 minutes).

As described above, according to the manufacturing method of this embodiment,
By performing the growth under the two-stage condition with the gas flow rate changed, the growth time of the silicon layer of the stacked source / drain portion can be reduced to about ／ and the increase in the junction leak current can be prevented.

In the present embodiment, the upper layer portion of the “stacked structure” is formed of an epitaxially grown silicon layer, but an epitaxially grown SiGe layer may be used instead.

[0082]

According to the present invention, a contact hole for connecting a source / drain region and a wiring is formed in a source / drain region.
When formed so as to straddle the boundary between the drain region and the STI structure, even if a step is formed at the boundary, generation of current leak due to the step can be suppressed.

Further, according to the present invention, even when the contact hole for connecting the source / drain region and the wiring is formed so as to straddle the boundary between the source / drain region and the STI structure, the boundary is formed. The occurrence of a step in the portion itself can be prevented.

[Brief description of the drawings]

FIGS. 1A to 1D are process cross-sectional views illustrating a method for manufacturing a conventional semiconductor device having an STI structure.

FIG. 2 (a) shows a source / source having a relatively large area.
FIG. 4B is a cross-sectional view showing a state in which a relatively narrow contact hole is formed on the drain region and the inside of the contact hole is filled with a metal plug 13. FIG.

FIGS. 3A to 3C are process cross-sectional views showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIGS. 4A and 4B are process cross-sectional views showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIGS. 5A to 5D are process cross-sectional views showing a second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 6 illustrates a planar layout example of a semiconductor device according to the present invention.

FIGS. 7A to 7C are process cross-sectional views illustrating a third embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIGS. 8A to 8C are cross-sectional views showing a process in a third embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIGS. 9A and 9B are cross-sectional views showing other embodiments of the semiconductor device according to the present invention.

FIGS. 10A to 10G are process cross-sectional views showing a fourth embodiment of the method for manufacturing a semiconductor device according to the present invention.

[Explanation of symbols]

Reference Signs List 31 p-type silicon substrate 32 gate insulating film 33 gate electrode 34 source / drain region 35 b SiO ₂ sidewall spacer 36 interlayer insulating film 40 trench 41 SiO ₂ film in trench 45 insulating film 46 resist mask 47 resist opening 48 contact hole 50 insulating sidewall spacers 71 silicon substrate 72 trench SiO ₂ film 73 gate insulating film 74 gate electrode 75 insulating film 76 source / drain regions 77 SiO ₂ film 78 a silicon nitride film 78b sidewall spacer 79 interlayer insulating film 80 contact hole Reference Signs List 81 metal plug 82 second silicon nitride film 91 p-type silicon substrate 92 trench isolation structure 93 gate insulating film 94 gate electrode 95 insulating layer 96 sidewall insulating film 97 epi Axially grown silicon layer 99b insulating side wall spacer 100 interlayer insulating film 101 electrode plug

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Ichiro Nakao 1006 Kazuma Kadoma, Kazuma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-2000-174137 (JP, A) JP-A-10-312975 (JP, A) JP-A-9-69627 (JP, A) JP-A-9-293865 (JP, A) JP-A-8-330588 (JP, A) (58) Fields investigated (Int. Cl. ⁷⁾ H01L 29/78 H01L 21/336 H01L 21/28 H01L 21/768

Claims (8)

(57) [Claims] A semiconductor substrate having an element region and an isolation region ; a gate electrode structure formed on the element region ; and a source / drain formed on the semiconductor substrate in the element region.
A rain region, a trench isolation structure including a trench formed in the isolation region and an insulator embedded in the trench, and a trench isolation structure including the gate electrode structure and the source / drain region.
Of the formed element region and the trench isolation structure
An oxide film formed on the formed isolation region and a sidewall formed on the gate electrode structure on which the oxide film is formed;
An insulating sidewall spacer formed, a silicon nitride film formed on the oxide film, and an interlayer insulating film formed on the silicon nitride film
And the interlayer insulating film, the silicon nitride film, and
The source / drain is formed by etching the oxide film.
A first opening reaching each region of the
An opening , embedded in the first opening and the second opening;
An electrode respectively in contact with the source / drain region, wherein the first opening and the second opening are a part of a corresponding region of the source / drain region and the trench adjacent to the part. A semiconductor device formed on a region that straddles each of a part of an isolation structure. 2. The insulating side wall spacer according to claim 1 ,
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed of a silicon nitride film. 3. The semiconductor device according to claim 1, wherein the first opening and the second opening are formed by further removing a part of the insulating sidewall spacer. 4. An oxide film having a thickness of 20 to 50 nm.
The semiconductor according to any one of claims 1 to 3.
apparatus. 5. A trench isolation structure comprising a trench formed in an isolation region of a semiconductor substrate and an insulator buried in the trench, and a MOS type device region in the semiconductor substrate surrounded by the trench isolation structure. Transistor game
A step of forming a gate electrode structure (a), after the step (a), the step (b) of depositing an oxide film on the isolation region and the device region, after the step (b), the Perfect on the side wall of the gate electrode structure
A step of forming a rim sidewall spacers (c), after step (c), the etch stop layer on the oxide film and the insulating support <br/> Id wall spacer sheet
Depositing a silicon nitride film and (d), and (e) forming an interlayer insulating film on the silicon nitride film, the silicon nitride film as an etch stop layer, wherein in the interlayer insulating film By etching an upper portion of a region that straddles a part of each of the source / drain regions of the MOS transistor and a part of the trench isolation structure adjacent to the part, the interlayer insulating film is etched. first the opening and a second step of forming an opening (f), the silicon Knight line exposed at the bottom of the interlayer insulating film on the first opening formed and the second opening
Etching the nitride film, and under the silicon nitride film.
(G) exposing the oxide film located on the first and second openings formed in the interlayer insulating film;
The oxide film exposed at the bottom in the opening 2 is selectively etched.
A part of the surface of the source / drain region
(H) exposing a surface of the source / drain region through the first opening and the second opening formed in the interlayer insulating film .
Forming a contacting electrode partly ( i ). 6. The insulating side wall spacer ,
6. The method for manufacturing a semiconductor device according to claim 5, wherein the method is formed from a silicon nitride film. 7. In the step (g), the interlayer insulating film is formed.
In the first opening and the second opening formed in the film
The insulating sidewall scan pacer that are present in the bottom of the
The method for manufacturing a semiconductor device according to claim 5 , wherein the semiconductor device is removed . 8. An oxide film having a thickness of 20 to 50 nm.
The semiconductor according to any one of claims 5 to 7.
Device manufacturing method.