JP3261785B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used as a driving element of an image sensor or a liquid crystal display (LCD), and more particularly to a mask alignment for determining the length of an offset region adjacent to a source region and a drain region. The present invention relates to a method for manufacturing a thin film transistor that can increase tolerance and improve characteristics.

[0002]

2. Description of the Related Art A thin film transistor (TFT) using a polycrystalline silicon (poly-Si) thin film as a semiconductor active layer.
Since it is easy to form a large amount and uniformly on an inexpensive glass substrate, it is used as a driving element of an image sensor or a liquid crystal display. Also, poly-S
Since the iTFT has a high current driving capability, it can be applied to a peripheral driving circuit, and has an advantage that an image sensor or an LCD can be formed at low cost.

As a thin film transistor provided with a gate offset region having a low impurity concentration in a semiconductor active layer adjacent to a channel region in order to reduce a leakage current in a poly-Si TFT, as shown in FIGS. There was a structure. FIG. 14A is an explanatory plan view of a conventional thin film transistor having a gate offset structure, and FIG. 14B is an explanatory sectional view taken along the line DD ′ of FIG. 14A.

A poly-Si TFT having a gate offset structure
As shown in FIGS. 14A and 14B, a semiconductor active layer 2 made of polycrystalline silicon (poly-Si), a gate insulating layer 3, and a tantalum (Ta) are formed on an insulating substrate 1. It has a structure in which a gate electrode 4 and an interlayer insulating layer 5 are sequentially laminated, and further has a source electrode 6 connected to a source region 2a through an opening provided in the interlayer insulating layer 5, and a drain region 2b Is provided between the channel region 2c and the source region 2a immediately below the gate electrode 4, and an offset region 2d having a low impurity concentration (or containing no impurity) is provided. The structure is such that an offset region 2e is provided between the region 2c and the drain region 2b. The offset regions 2d and 2e having a low impurity concentration have a length (OS) of L1,
L2, which is formed by providing a resist mask 8 'on the upper portion when ions are implanted into the source region 2a and the drain region 2b (JP-A-2-7407).
No. 7).

Here, the operation of the thin film transistor having the above configuration will be described with reference to FIG. FIG. 15 is a schematic explanatory view showing the operation of an n-channel transistor in which an n-type impurity (for example, phosphorus) is implanted into the source region 2a and the drain region 2b. As shown in FIG.
Is connected to a reference potential (earth), the drain electrode 7 is connected to a positive power supply, and the gate voltage can be freely changed.

When a positive voltage is applied to the gate electrode 4,
Side (upper side) of channel region 2c in contact with gate insulating layer 3
Then, a channel (n − channel) having a high electron concentration is formed, and the diffusion region of the source region 2a and the diffusion region of the drain region 2b are connected to each other, so that electrons move and a drain current Id flows, and the transistor is turned on. State.

On the other hand, when a negative voltage is applied to gate electrode 4, holes are induced on the side of channel region 2c in contact with gate insulating layer 3 to form ap @-channel, and n-type diffusion region of drain region 2b is formed. And a pn junction in a reverse bias state is formed between them, so that the drain current hardly flows and the pn junction is turned off.

At this time, since a strong electric field is applied to the pn junction in the reverse bias state, a leak current flows even in the OFF state. Therefore, in order to reduce the leakage current, an offset region 2e having a high resistance is provided between the channel region 2c and the drain region 2e.

A case where the thin film transistor having the above configuration is applied as a driving element of a liquid crystal display (LCD) will be described with reference to a partial circuit diagram of FIG. As shown in FIG. 16, a pixel of the LCD is composed of a liquid crystal cell (Li, j) and a thin film transistor (Ti, j), and the liquid crystal cell of each pixel has one of the source and drain electrodes of the corresponding thin film transistor. It is connected to the. The other electrode of the source / drain of each thin film transistor is connected to a data line for transmitting a data signal, and each data line is connected to a data driver 15. The gate electrode of the thin film transistor is connected to a gate line for controlling ON / OFF of the gate, and the gate line is connected to a gate driver 16. The data line is common to each column and the gate line is common to each row, forming an active matrix circuit.

It is necessary to store both positive and negative charges in the liquid crystal capacitance of the cell. Since both positive and negative voltages are applied from the data line, the source and drain regions are reversed. 2a shown in FIG.
May be a drain region and 2b may be a source region.
Therefore, as shown in FIG. 14, the offset region 2d is required also on the source region 2a side.

Next, a method for manufacturing the above-mentioned conventional thin film transistor will be described with reference to a process sectional view of FIG. First, polycrystalline silicon (poly-Si) as a semiconductor active layer 2 is formed in an island shape on an insulating substrate 1,
A gate oxide layer 3 is formed by depositing a silicon oxide (SiO ₂ ) layer so as to cover the oly-Si layer (FIG. 17A).
reference).

Next, tantalum (Ta) is deposited, a gate electrode 4 is formed at a predetermined position on the gate insulating layer 3 by photolithography and etching, and the offset region is made a region with a low impurity concentration. For example, ion implantation of low concentration phosphorus (P) over the entire surface (first ion implantation)
(See FIG. 17B).

Then, a resist mask 8 'is formed in portions corresponding to the offset regions 2d and 2e by photolithography (see FIG. 14), and high-concentration phosphorus (P) is ion-implanted (second ion implantation). Then, a source region 2a and a drain region 2b are formed (see FIG. 17C).

After stripping the resist, an SiO ₂ layer is deposited, patterned to form an interlayer insulating layer 5, and electrodes 6, 7 and other wirings are formed to form a thin film transistor having a gate offset structure. (See FIG. 17D).

In the thin film transistor having the gate offset structure, the length L1 of the offset region 2d, the length L2 of the offset region 2e, and the important parameters which determine the characteristics of the TFT are determined by the impurity concentration of the offset regions 2d and 2e. Has become. The values of L1 and L2 are determined by the alignment accuracy of the photolithography twice when the gate electrode 4 is formed and when the resist mask 8 'is formed in the second ion implantation step.
Since d and 2e are located on opposite sides of the gate electrode 4, even if the mask alignment is slightly shifted, L1 and L2
2 is not equal. For example, when the alignment for forming the resist mask 8 'is shifted to the left by 0.5 μm,
L1 is 1 μm longer than L2.

Here, the case where the lengths of the offset regions 2d and 2e are not equal will be described with reference to the schematic explanatory diagram of FIG. 18 and the Vg-Id characteristic diagram of the TFT of FIG. Here, the length (L1) of the offset area 2d
Is larger than the length (L2) of the offset area 2e (L1> L2). FIG.
(A) is a schematic description of a case where positive charges are accumulated in the liquid crystal capacitor CLC ((+) writing), and (b) is a schematic description of a case where negative charges are accumulated in the liquid crystal capacitance CLC ((−) writing). FIG.

As shown in FIG. 18A, in the case of (+) write, 2a is a drain, 2b is a source, and O
The N current becomes ION1 flowing from the drain to the source. On the other hand, in the case of the (-) write shown in (b), since 2a acts as a source and 2b acts as a drain, the ON current becomes I
ON2.

FIG. 19 shows the offset region 2 as described above.
Vg-Id characteristic diagram showing the relationship between the gate voltage (Vg) and the drain current (Id) when the source and drain electrodes of the thin film transistor are inverted when the lengths of d and 2e satisfy L1> L2. It is. In FIG. 19, Id is represented by a logarithm. As shown in FIG. 19, the gate voltage Vg
The drain currents ION1 and ION2 both increase with an increase in the current, but ION1 <ION2 always holds. this is,
This is because the longer the length of the offset region on the drain side, the higher the resistance and the more difficult the ON current to flow, and L1> L
In the case of 2, when compared at the same Vg, ION1 when the long offset region 2d is on the drain side is smaller than ION2 when the short offset region 2e is on the drain side. In other words, if the lengths of the offset regions are not equal, the Vg-Id characteristics when the source and the drain are inverted are not equal to those before the inversion, and the characteristics are asymmetric.

[0019]

However, according to the above-mentioned conventional thin film transistor and the method of manufacturing the same, since the offset regions 2d and 2e are formed on opposite sides of the gate electrode, the length of the offset regions 2d and 2e can be reduced. L1,
L2 greatly depends on the accuracy of mask alignment (mask alignment) twice when the gate electrode 4 is formed and when the resist mask 8 'is formed in the second ion implantation step. One of the length of the region 2d and the length of the drain-side offset region 2e is longer and the other is shorter.
Differences occur in the lengths of d and 2e, and the Vg-Id characteristics when the source and drain electrodes are inverted are no longer the same as before the inversion. When such a thin film transistor is applied to driving a liquid crystal display (LCD), There is a problem that the actually stored charges differ between the case of storing the positive charges and the case of storing the negative charges, and display quality is impaired.

The present invention has been made in view of the above circumstances, and has a large tolerance for mask misalignment in photolithography in an ion implantation process. Each of the masks formed between a channel region and a source region and a drain region is formed. It is an object of the present invention to provide a thin film transistor in which the lengths of the offset regions can be made equal and the characteristics of the thin film transistor are symmetric with respect to the inversion of the source and the drain, and a manufacturing method thereof.

[0021]

[MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
The method for manufacturing a thin film transistor according to the present invention includes the steps of:
The opposite end of the U-shape on two opposite sides
Semiconductor active layers serving as source and drain regions, respectively
Forming an insulating layer covering the semiconductor active layer
Forming a semiconductor active layer on the insulating layer.
Forming a gate electrode across two opposing sides
And the semi-conductor is connected to the U-shaped terminal side of the semiconductor active layer.
Adjacent to the channel region below the gate electrode in the active layer
To cover the top of the offset area
Pattern on two opposite sides of the semiconductor active layer.
Forming on the insulating layer, the resist pattern
Impurity is implanted as a mask, and the source region and the
Forming a rain region, the semiconductor active layer
Before the resist pattern on the two sides facing each other
The sides on the source region and drain region side are
A side of the gate electrode on the side of the source region and the drain region.
It is characterized by being on the same parallel straight line .

[0022]

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

According to the present invention, a method of manufacturing a thin film transistor
In the above, two offset regions are formed in the same direction with respect to the gate electrode, and even if a slight misalignment occurs when a resist pattern serving as a mask for impurity implantation is formed, the lengths of the two offset regions are made equal. The characteristics can be improved by making the characteristics of the thin film transistor symmetric with respect to the inversion of the source and the drain.

[0031]

An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an explanatory plan view of a thin film transistor according to one embodiment of the present invention, and FIG.
It is sectional explanatory drawing of a part. Parts having the same configuration as in FIG. 14 will be described with the same reference numerals. As shown in FIG. 1, the thin film transistor of this embodiment includes a semiconductor active layer 2 made of polycrystalline silicon (poly-Si) patterned in a U-shape on an insulating substrate 1 such as glass.
A gate insulating layer 3 made of silicon oxide (SiO ₂ ) is sequentially laminated, and a gate electrode 4 made of tantalum (Ta) is formed so as to cross the upper and lower sides of the U-shape of poly-Si in FIG. A source electrode 6 and a drain electrode 7 are formed on the left side of the gate electrode 4 in FIG.

In the semiconductor active layer 2, a portion immediately below the gate electrode 4 is a channel region 2 containing no impurities.
c, 2c ', the portion where the source electrode 6 and the drain electrode 7 are connected is the source region 2a and the drain region 2b, and the portion between the channel regions 2c, 2c' and the source region 2a and the drain region 2b has the impurity concentration. The low offset regions 2d and 2e provide a dual gate thin film transistor having a gate offset structure.

Next, each part of the thin film transistor according to the present embodiment will be specifically described with reference to FIGS. The characteristic part of the thin film transistor of this embodiment is that the source region 2a is formed at both ends of the terminal of the semiconductor active layer 2 formed in a U-shape.
And the drain region 2b are formed, the source region 2a and the drain region 2b are provided on the same side (the left side in FIG. 1) with respect to the gate electrode 4, and the offset regions 2d and 2e are similarly formed on the same side with respect to the gate electrode 4. (The left side in FIG. 1).

The U-shaped semiconductor active layer 2 has an upper side (the
1 semiconductor active layer) 12 and the lower side (second semiconductor active layer)
Layer 13 ) and a bridging portion (conductive layer) 11 connecting them. The upper side portion 12 of the semiconductor active layer 2 has a source electrode 2a, an offset region 2d,
Channel region 2c, low resistance region 2 on the right side of gate electrode 4
f, and only one TFT is provided on the upper side 12 alone.
Act as

In addition, the bottom portion 13 includes the drain region 2b,
An offset region 2e, a channel region 2c ', and a low-resistance region 2g are provided.
It acts as an FT. Therefore, the thin film transistor of the present embodiment is equivalent to a configuration in which two thin film transistors formed on the upper side portion 12 and the lower side portion 13 are connected by the bridge portion 11.

The bridging portion 11 is a low-resistance region made of poly-Si into which impurity ions are implanted at a high concentration, and connects the low-resistance region 2f of the upper side portion 12 and the low-resistance region 2g of the bottom side portion 13. It is formed by patterning integrally in the same step as the low-resistance regions 2f and 2g, and by ion-implanting integrally.

In the semiconductor active layer 2, no impurity ions are implanted into the channel regions 2c and 2c 'immediately below the gate electrode 4, and desired characteristics can be obtained in the offset regions 2d and 2e. Impurity ions are implanted at a low concentration set in the above. Other areas, namely
Source region 2a, drain region 2b, low resistance region 2
f, 2g, the impurity ions are implanted into the bridge portion 11 at a high concentration to form a low resistance region.

By forming semiconductor active layer 2 as described above, offset region 2d in contact with source region 2a is formed.
And the offset region 2e in contact with the drain region 2b is formed on the same side (the left side in FIG. 1) with respect to the gate electrode 4, so that the length L1 of the offset region 2d, which greatly affects the TFT characteristics, The length L2 of the offset region 2e can be made equal.

That is, in the step of forming the thin film transistor, after the gate electrode 4 is formed, the offset region 2 is formed.
A first ion implantation with a low impurity concentration for forming d and 2e is performed, and then a resist mask 8 is formed so as to partially overlap the upper portion of the gate electrode 4 to form a second ion implantation with a high impurity concentration.
Is performed to form offset regions 2d and 2e into which high-concentration impurities are not implanted.

Here, the lengths L 1 and L 2 of the offset regions 2 d and 2 e are determined by the length of the portion OS of the resist mask 8 excluding the gate electrode 4. 4 is formed in the same direction as that of the resist mask 8, even if the mask alignment is deviated in the photolithography process for forming the resist mask 8, one of L1 and L2 does not become longer and the other becomes shorter. L2 is shifted in the same way.
1, L2 can be made equal in length.

Next, a method of manufacturing the thin film transistor according to the present embodiment will be described with reference to FIGS. 3 (c), 4 (e), 5 (g), 6
(I) and FIG. 7 (k) are process plan explanatory views, and FIG.
(A), (b), FIG. 4 (d), FIG. 5 (f), FIG.
(H) and FIG. 7 (j) show corresponding plan views A
It is sectional drawing of -A 'part.

First, LP is placed on an insulating substrate 1 such as glass.
Amorphous silicon (a-Si) is deposited to a thickness of about 100 nm by a CVD method, the substrate 1 is annealed by an infrared lamp heater or a laser beam, and a-Si is grown on polycrystalline silicon (poly-Si). A poly-Si layer is formed as the active layer 2 (see FIG. 3A).

Next, a semiconductor active layer 2 is formed by patterning the poly-Si layer in a U-shape by photolithography and etching, and then a SiO ₂ layer is deposited to a thickness of about 100 nm by plasma CVD. Then, a gate insulating layer 3 is formed. Tantalum (Ta) is deposited thereon to a thickness of about 200 nm by a sputtering method, and patterned by photolithography and etching in a band shape so as to cross the upper side 12 and the bottom side 13 of the U-shape of the semiconductor active layer 2. To form a gate electrode 4 (FIG. 3B)
(C)).

Then, phosphorus (P) as a low concentration impurity ion is implanted into the entire surface of the substrate using the gate electrode 4 as a mask (first ion implantation). The impurity concentration at this time is
A low impurity concentration is used for the offset regions 2d and 2e (see FIGS. 4D and 4E). The offset area 2
If d and 2e do not contain any impurities, the first ion implantation may be omitted.

Next, the offset region 2 having a desired length OS is formed on the left side of the gate electrode 4 by photolithography.
A resist mask 8 is formed so as to be d and 2e, and high-concentration impurity ions are implanted (second ion implantation).
By the second ion implantation, high-concentration impurities are implanted into the source region 2a and the drain region 2b, the low-resistance regions 2f and 2g, and the bridging portion 11, and the region becomes a low-resistance region. The portion below 8 is not doped with impurities by the second ion implantation, and becomes offset regions 2d and 2e having a low impurity concentration (FIG. 5F).
(G)).

At this time, since the offset regions 2d and 2e are both formed on the left side of the gate electrode 4, the length of the offset regions 2d and 2e can be maintained even if the mask alignment when forming the resist mask 8 is slightly shifted. L1 and L2 can be formed equally.

Then, a silicon oxide (SiO ₂ ) layer is deposited to a thickness of 1 μm on the entire surface of the substrate by a plasma CVD method, and via contacts are opened in the interlayer insulating layer 5 and the gate insulating layer 3 by photolithography and etching. ,
An interlayer insulating layer 5 is formed (see FIGS. 6H and 6I).

Then, aluminum (Al) is deposited to a thickness of about 1 μm by a sputtering method, and is patterned by photolithography and etching to form a source electrode 6, a drain electrode 7, and each wiring layer 10 (FIG. 7). (See (j) (k)). Thus, the thin film transistor of the present embodiment is formed.

Next, the characteristics of the thin film transistor of this embodiment will be described with reference to the schematic explanatory diagram of FIG. 8 and the Vg-Id characteristic diagram of FIG. FIG. 9 shows the relationship between the gate voltage (Vg) and the drain current (Id) when the source and the drain are inverted with respect to the thin film transistor of this embodiment.
FIG. 14 is a graph showing the -Id characteristic. Note that Id in FIG. 9 is represented by a logarithm. As shown in FIG. 8, if the ON current at the time of (+) writing in which positive charges are accumulated in the liquid crystal cell is ION1 and the ON current at the time of (−) writing in which negative charges are accumulated is ION2, (+) In the case of ()) writing, 2a acts as a source and 2b acts as a drain. In the case of (-) writing, 2a acts as a drain and 2b acts as a source.

As shown in FIG. 9, in the thin film transistor of this embodiment, since the lengths L1 and L2 of the offset regions 2d and 2e having high resistance are formed to be equal, the charge written in the liquid crystal cell depends on the sign. Source region 2a
And the drain region 2b is inverted, and 2a is the drain, 2b
Is the source, the Vg-Id characteristics are completely equal. Therefore, when the thin film transistor of this embodiment is used for a liquid crystal display (LCD), (+)
Writing and (−) writing are completely equivalent, and the image quality of the LCD can be improved.

According to the thin film transistor of this embodiment and the method of manufacturing the same, the semiconductor active layer 2 is formed in a U-shape, and the gate electrode 4 is formed so as to cross the upper side 12 and the lower side 13 of the semiconductor active layer 2. Then, the source / drain region and the offset regions 2d, 2e in the same direction with respect to the gate electrode 4.
Can be formed, even if the mask alignment when forming the resist mask 8 is slightly shifted, the lengths L1 and L2 of the offset regions 2d and 2e are only shifted by the same width.
As a result, the lengths of L1 and L2 are made equal, and there is an effect that the characteristics can be made symmetric with respect to the inversion of the source / drain during the operation of the thin film transistor.

When the thin film transistor of this embodiment is used as a driving element of a liquid crystal display (LCD),
Since (+) writing and (-) writing are equal,
There is an effect that the image quality of the LCD can be improved.

Next, a thin film transistor according to a second embodiment of the present invention will be described with reference to FIG. FIG.
10A is an explanatory plan view of a thin film transistor according to a second embodiment, and FIG. 10B is an explanatory sectional view taken along the line BB ′ of FIG. 10A. The thin film transistor of the second embodiment has substantially the same structure as that of the first embodiment, has a U-shaped semiconductor active layer 2, and is provided above the offset regions 2d 'and 2e' on the interlayer insulating layer 5. The dual gate TFT has a second gate electrode 14 made of aluminum (Al) at a corresponding position.

U-shaped upper side 1 of semiconductor active layer 2
2, a left-side source region 2 a and a right-side low-resistance region 2 f, a left-side drain region 2 b and a right-side low-resistance region 2 g on a bottom portion 13, and a bridge portion 1 connecting an upper side portion 12 and a bottom side portion 13.
Impurities 1 are implanted at a high concentration to form a low resistance region. Further, no impurity is implanted into the channel regions 2c and 2c 'corresponding to the lower portion of the gate electrode 4 and the offset regions 2d' and 2e '.

The second gate electrode 14 is formed on the interlayer insulating layer 9 so as to cover the offset regions 2d 'and 2e', and applies a voltage of several volts to several tens of volts to form the second gate electrode 14. It controls the current flowing through the semiconductor active layer 2 below the gate 14. As a method of controlling the current in the semiconductor active layer 2, it is more preferable to control the current by adjusting the voltage applied to the second gate electrode 14 than to control the amount of impurity ions doped into the offset regions 2d 'and 2e'. It is easy, and by providing the second gate electrode 14,
Low-concentration ion implantation (first ion implantation) into the offset regions 2d 'and 2e' can be omitted.

Next, a method of manufacturing the thin film transistor according to the second embodiment will be described in detail with reference to FIGS. 11A to 11D. First, a semiconductor active layer 2 is formed on an insulating substrate 1 such as glass by LPCVD.
A-Si is deposited to a thickness of about 100 nm, a polycrystalline silicon (poly-Si) layer is formed by annealing, and the poly-Si layer is patterned in a U-shape by photolithography and etching to form a semiconductor active layer. A second pattern is formed (see FIG. 11A).

Next, an SiO ₂ layer is deposited to a thickness of about 100 nm by a plasma CVD method to form a gate insulating layer 3, on which tantalum (T) is deposited by a sputtering method.
a) is deposited to a thickness of about 200 nm, and patterned by photolithography and etching in a shape crossing the U-shaped upper side 12 and bottom side 13 of the semiconductor active layer 2 to form the gate electrode 4. (See FIG. 11B).

Next, a resist mask 8 is formed by photolithography so as to be shifted from the gate electrode 4 by a desired length OS of the offset regions 2d 'and 2e', and impurity ions are implanted at a high concentration. By this ion implantation, a high-concentration impurity is implanted into the source region 2a and the drain region 2b, the low-resistance regions 2f and 2g, and the bridge portion 11 to form a low-resistance region. Implantation is not performed, resulting in offset regions 2d 'and 2e' containing no impurities (see FIG. 11C). That is, in the method of manufacturing a thin film transistor according to the second embodiment, the ion implantation process is performed only once for high-concentration implantation, and low-concentration ion implantation is not performed.

Then, a silicon oxide (SiO ₂ ) layer having a thickness of 1 μm is deposited on the entire surface of the substrate by a plasma CVD method, and via contacts are opened in the interlayer insulating layer 5 and the gate insulating layer 3 by photolithography and etching. ,
An interlayer insulating layer 5 is formed. Next, aluminum (Al) is deposited to a thickness of about 1 μm by a sputtering method, and patterned by photolithography and etching to form a source electrode 6, a drain electrode 7, a second gate electrode 14, and each wiring layer 10. (See FIG. 11D). Since the second gate electrode 14 can be formed in the same step as other electrodes, wirings, and the like, it is not necessary to add a new step. Thus, the thin film transistor of the second embodiment is formed.

According to the thin film transistor and the method of manufacturing the same according to the second embodiment, since both the offset regions 2d 'and 2e' are formed on the left side with respect to the gate electrode 4, alignment in forming the resist mask 8 is performed. Even when a shift occurs, the lengths of the offset regions 2d 'and 2e' can be made equal, and when the source / drain is inverted, the TFTs can be formed.
The characteristics can be made symmetrical, and the second gate electrode 14 can be formed without adding a new manufacturing process.
By adjusting the voltage applied to the gate electrode 14, the current flowing through the semiconductor active layer 2 can be controlled, and the step of implanting low-concentration ions in the offset regions 2d 'and 2e' can be omitted to simplify the process. There is an effect that can be. Further, when the thin film transistor of the second embodiment is used for an LCD, there is an effect that the image quality of the LCD can be improved.

Next, a thin film transistor according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 12A is an explanatory plan view of a thin film transistor according to the third embodiment, and FIG.
It is sectional explanatory drawing of CC 'part of (a). The thin film transistor according to the third embodiment is formed by forming an island-shaped patterned polycrystalline silicon (poly-S) on an insulating substrate 1 such as glass.
i)) and a gate insulating layer 3 made of silicon oxide (SiO ₂ ) are sequentially stacked, and the semiconductor active layers 2 and 2 ′ are made of tantalum (Ta) so as to cross the semiconductor active layer 2 and the semiconductor active layer 2 ′. And a source electrode 6 connected to the semiconductor active layer 2 on the left side of the gate electrode 4 through an opening in the interlayer insulating layer 5, and a semiconductor active layer 2 'on the left side of the gate electrode 4. A drain electrode 7 connected to the semiconductor active layer 2 and the semiconductor active layer 2 ′ on the right side of the gate electrode 4 through the opening of the interlayer insulating layer 5. 1
1 'is formed.

In the thin-film transistor of the third embodiment, the thin-film transistor T1 having the semiconductor active layer 2 and the thin-film transistor T2 having the semiconductor active layer 2 'are connected to the right side of the common gate electrode 4 via the Al wiring of the bridge portion 11'. And are connected in series. The entire structure is equivalent to a dual gate thin film transistor. Channel regions 2c and 2c 'are formed below gate electrode 4, and source region 2a and drain region 2b are formed as gate electrode 4c.
And the offset regions 2d and 2e are also formed on the left side of the gate electrode 4. That is,
The offset regions 2d and 2e are located on the left side of the channel regions 2c and 2c 'in FIG.
A drain region 2b is formed.

Next, a method of manufacturing the thin film transistor according to the third embodiment will be specifically described with reference to FIGS. 13A to 13D. First, an a-Si layer as a semiconductor active layer 2 or 2 'is deposited to a thickness of about 100 nm on an insulating substrate 1 made of glass or the like by LPCVD, and annealed by polycrystalline silicon (poly-Si). Layers and
The poly-Si layer is patterned into an island shape by photolithography and etching to form semiconductor active layers 2 and 2 '(see FIG. 13A).

Next, an SiO ₂ layer is deposited to a thickness of about 100 nm by a plasma CVD method to form a gate insulating layer 3 on which tantalum (Ta) is formed by a sputtering method.
Is deposited to a thickness of about 200 nm, and patterned by photolithography and etching so as to cross the semiconductor active layers 2 and 2 ′ to form a common gate electrode 4. Then, ion implantation is performed at the impurity concentration for the offset regions 2d and 2e (first ion implantation) (FIG. 13).
(B)).

Next, a resist mask 8 is formed by photolithography so as to be displaced from the gate electrode 4 by a desired length OS of the offset regions 2d and 2e, and impurity ions are implanted at a high concentration. The drain region 2b and the low-resistance regions 2f and 2g are formed (second ion implantation) (see FIG. 13C).

Then, a silicon oxide (SiO ₂ ) layer is deposited to a thickness of 1 μm on the entire surface of the substrate by a plasma CVD method, and via contacts are opened in the interlayer insulating layer 5 and the gate insulating layer 3 by photolithography and etching. ,
The shape of the interlayer insulating layer 5 is formed, aluminum (Al) is deposited to a thickness of about 1 μm by a sputtering method, and patterned by photolithography and etching to form a source electrode 6, a drain electrode 7, a bridge portion 11 ′, Each wiring layer is formed (see FIG. 13D). Bridge 1
Since 1 'can be formed by the same manufacturing process as other electrodes, wirings, etc., it is not necessary to add a new process. Thus, the thin film transistor of the third embodiment is formed.

According to the third embodiment, the gate electrodes 4 of the thin film transistors T1 and T2 having a semiconductor active layer having the same shape as the conventional thin film transistor are made common, and the right side of the gate electrode 4 is connected in series by the bridge portion 11 '. Connected, making it equivalent to a dual gate thin film transistor as a whole,
Since both the offset regions 2d and 2e are formed on the left side of the gate electrode 4, even if the mask alignment when forming the resist mask 8 is slightly shifted, the offset regions 2d and 2e are formed.
The lengths of d and 2e can be made equal, and there is an effect that the characteristics of the thin film transistor at the time of source / drain inversion can be made symmetric. Further, when the thin film transistor of the third embodiment is used for an LCD, there is an effect that the image quality of the LCD can be improved.

[0068]

[0069]

[0070]

[0071]

[0072]

According to the present invention, there is provided a method for manufacturing a thin film transistor.
In the fabrication method, two offset regions are formed in the same direction with respect to the gate electrode, and even if a slight misalignment occurs when a resist pattern serving as a mask for impurity implantation is formed, the length of the two offset regions is reduced. They can be formed equally,
A method of manufacturing a highly reliable thin film transistor that can be improved in characteristics by being symmetrical with respect to the inversion of the drain.
Obtainable.

[Brief description of the drawings]

FIG. 1 is an explanatory plan view of a thin film transistor according to one embodiment of the present invention.

FIG. 2 is an explanatory cross-sectional view taken along the line AA ′ of FIG. 1;

FIG. 3 is a process explanatory view showing a method for manufacturing a thin film transistor according to the present embodiment.

FIG. 4 is a process explanatory view showing a method for manufacturing a thin film transistor according to the present embodiment.

FIG. 5 is a process explanatory view showing a method for manufacturing a thin film transistor according to the present embodiment.

FIG. 6 is a process explanatory view showing a method for manufacturing a thin film transistor according to the present embodiment.

FIG. 7 is a process explanatory view showing a method for manufacturing a thin film transistor according to the present embodiment.

FIG. 8 is a schematic explanatory view in the case where the thin film transistor of this example is used as a driving element of a liquid crystal display.

FIG. 9 is a Vg-Id characteristic diagram of the thin film transistor of the present example.

FIG. 10A is a plan view of a thin film transistor according to a second embodiment of the present invention, and FIG.
It is sectional drawing of -B 'part.

FIGS. 11A to 11D are process cross-sectional views illustrating a method for manufacturing a thin film transistor according to a second embodiment.

12A is a plan view of a thin film transistor according to a third embodiment of the present invention, and FIG. 12B is a plan view of C in FIG.
It is sectional drawing of -C 'part.

FIGS. 13A to 13D are process cross-sectional views illustrating a method for manufacturing a thin film transistor according to a third embodiment.

FIG. 14A is a plan view illustrating a conventional thin film transistor, and FIG. 14B is a cross-sectional view taken along the line DD ′ in FIG. 14A.

FIG. 15 is a schematic explanatory view showing the operation of an n-channel thin film transistor.

FIG. 16 is a partial circuit diagram of a liquid crystal display using a thin film transistor.

FIG. 17 is a process cross-sectional view illustrating a method for manufacturing a conventional thin film transistor having a gate offset structure.

FIG. 18 is a schematic explanatory view when a conventional thin film transistor is used as a driving element of a liquid crystal display.

FIG. 19 is a Vg-Id characteristic diagram of a conventional thin film transistor.

[Explanation of symbols]

1 ... substrate, 2 ... semiconductor active layer, 3 ... gate insulating layer,
4 gate electrode, 5 interlayer insulating layer, 6 source electrode, 7 drain electrode, 8 8 ′ resist mask, 10 wiring layer, 11 11 ′ cross-linked portion, 12
... top side, 13 ... bottom side, 14 ... second gate electrode,
15: Data driver, 16: Gate driver

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Takeshi Nakamura 2274 Hongo, Ebina-shi, Kanagawa Fuji Xerox Co., Ltd. (56) References JP-A-63-151083 (JP, A) JP-A-58-115864 ( JP, A) JP-A-64-89464 (JP, A) JP-A-63-204769 (JP, A) JP-A-2-34970 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , (DB name) H01L 29/786 H01L 21/336 G02F 1/1368

Claims (1)

(57) [Claims] 1. On a substrateU-shaped, in front of two opposing sides
The U-shaped ends are the source area and the drain, respectively.
Semiconductor active layer to beForming and the semiconductor
Forming an insulating layer covering the body active layer;
Across the two opposite sides of the semiconductor active layer on the layer
Forming a gate electrode on the semiconductor active layer;
The semiconductor active layer on the terminal side of the
A portion that becomes an offset region adjacent to the lower channel region
Resist pattern covering the top of the minuteThe semiconductor activity
On two opposite sides of the layerForming on the insulating layer
Implanting impurities using the resist pattern as a mask
AndThe source region and the drain regionForming the
WithAnd The register on two opposite sides of the semiconductor active layer
Of the source pattern and the drain region of the
A side is the source region and the drain of the gate electrode.
On the same straight line parallel to the side of the Characterized by
Manufacturing method of a thin film transistor.