JP3258040B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

 [Object of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a parallel test mode.

[0002]

2. Description of the Related Art As DRAMs become more highly integrated, the time required to test whether or not memory cells operate normally increases, and test costs tend to increase. As a measure against this, 1
Since the MbDRAM, various techniques for reducing test costs have been proposed. The basic concept of these methods is mainly based on the following two concepts. (1) Shortening test time (2) Easy test method

[0003] Of these, reduction of test time is realized by parallelization of tests. That is, writing is performed simultaneously on a plurality of memory cells in the chip, then reading is performed simultaneously, and the result of the match / mismatch detection is output to the outside. This method uses 1M
It has been standardized since bDRAM. However, the bit length that can be tested in parallel differs for each generation, and is 4 bits for the 1Mb generation, 8 bits for the 4Mb generation, and 16 bits for the 16Mb generation, which is twice as large for each generation.

On the other hand, the simplification of the test method refers to how simple a test is performed on a chip. For example, a built-in self test (BIS)
T) technology. BIST technology is a high-density DRA
For example, there is an example mounted on M as an experimental trial (for example, JSSC, Vol, SC-22. No. 5, Oc
t. 1987 P663-668 or JSS
C, Vol. 25, no. 4, Aug. 1990 P9
03-911), not yet standardized.

[0005] As described above, to date, the technique of shortening the test time is the only technique used for reducing the test cost, and this tendency is considered to continue for a while.

The simplest parallel test method is to write the same data to a plurality of memory cells connected to a word line activated in the same RAS cycle and then read a plurality of bits of data. This is a method of detecting the match or mismatch. For example, when a match or mismatch of 16-bit memory cell data is detected, as shown in FIG. 10, the match detection circuit includes a two-input exclusive OR circuit (EXOR logic) and a multi-input OR. It is configured by combining a NOT circuit (NOR logic). However, in this configuration, considering the actual chip layout, if the match detection circuit is arranged near the output pad,
It is necessary to route these bus lines in the chip, which may increase the chip size. This will become more serious as the integration becomes more advanced in the future and the bit length tested in parallel becomes larger.

As a countermeasure, it is conceivable to adopt a configuration as shown in FIG. 11 in a test data reading system. When the memory cell array is divided into, for example, four cell array blocks, match detection circuits 21 to 24 are provided for detecting the match or mismatch of a plurality of bits of memory cell data for each cell array block. The configuration principle of these coincidence detecting circuits 21 to 24 is the same as that of FIG. Then, the detection results of the coincidence detection circuits 21 to 25 are guided to near the output pad of the chip, and an AND circuit 25 for obtaining a logical product (AND logic) of the detection results from each block is provided here. With such a configuration, the coincidence detection circuit is arranged for each cell array block.
The bus lines can be greatly reduced as compared with the above method, and an increase in the chip area can be minimized.

By the way, when the method of FIG. 11 is adopted,
The following problem of a decrease in the efficiency of mismatch detection occurs. Plural memory cell data (4 bits in FIG. 11) input from the same cell array block to the match detection circuit
Is generally a plurality of bits connected to the same word line, depending on how addresses are allocated to the memory matrix plane. In this case, when the word line does not operate for any reason, the read data of a plurality of bits may be fixed at logical "1" or "0". In this case, no defect is detected. A failure mode in which all of a plurality of cell data in the same cell array block is inverted is a word line failure (ie, R
This is extremely likely to occur when OW failure occurs.

[0009]

[Configuration of the invention]

[0010]

A semiconductor memory device according to the present invention, as a coincidence detecting circuit for a parallel test, detects coincidence or non-coincidence of a plurality of bits of memory cell data in each cell array block. A plurality of first match detection circuits provided adjacent to each other;
A second match detection circuit for detecting the match or mismatch of the representative values with an arbitrary 1-bit data in each cell array block as a representative value of the block;
And a third match detection circuit arranged near the output pad of the chip for detecting the match or mismatch of the output of the second match detection circuit.

[0011]

The semiconductor memory device according to the present invention is based on the configuration shown in FIG. 11 and additionally detects any one-bit data from each memory array block as a representative value, and detects a match or mismatch between the representative values. It can be said that a coincidence detection circuit is also provided. This makes it possible to detect a defect even when all the memory cell data in a specific cell array block is inverted. Therefore, it is possible to realize a semiconductor memory device having a parallel test mode in which the number of bus lines routed in the chip is small and high detection efficiency can be obtained.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a DRAM having a parallel test mode system according to one embodiment of the present invention. In the embodiment, a 16 Mb DRAM is assumed, and therefore, the parallel test mode shows a case of 16-bit parallel. 1
A memory array mat having a capacity of 6 Mb has four cell array blocks 1 (11, 1) of 4 Mb each as shown in the figure.
2, 13 and 14). A first match detection circuit 2 is adjacent to each cell array block 1.
(21,22,23,24) are provided. In the parallel test mode, the 4-bit memory cells M connected to the same word line WL from each cell array block 1
The data of C is read. The read 4-bit data in each cell array block 1 is connected to a data line 3
The signals are input to the first coincidence detection circuit 2 via (31, 32, 33, 34).

On the other hand, an arbitrary 1-bit data read from each of the four cell array blocks 1 is used as a representative value representing each cell array block 1, and a second for detecting coincidence or non-coincidence of these representative values. A coincidence detection circuit 4 is provided. That is, 1-bit data lines 5 (51, 52,.
53, 54) are branched and connected to the second coincidence detecting circuit 4.

A third coincidence detecting circuit 6 is provided near the output pad of the chip. The third match detection circuit 6 has output data lines 71,.
72, 73, 74 and 5-bit data on the output data line 75 of the second coincidence detecting circuit 4 are inputted, and coincidence or non-coincidence of all the data is detected. The output data line 9 of the third coincidence detection circuit 6 is connected to an output drive circuit 8, and the output drive circuit 8 outputs a parallel test result to an output pad.

In this embodiment, as described above, the second match detection circuit 4 for detecting the match or mismatch of one bit of the representative value read from each cell array block is newly provided. Therefore, a defect can be detected even when all four bits of memory cell data of a certain cell array block are inverted, and the detection efficiency is greatly improved as compared with the conventional case. The increase in the number of data buses due to the introduction of the second coincidence detection circuit 4 for detecting coincidence or non-coincidence of the representative values is only one compared with the conventional system of FIG. This is negligible even if the integration advances in the future, the bit length of the parallel test increases, and the number of data buses increases.

FIG. 2 shows a specific configuration of the first match detection circuit 2 and the second match detection circuit 4 shown in FIG.
As shown, a two-input exclusive OR (EXOR) circuit 3
And a three-input NOR circuit (NOR).

FIG. 3 shows a specific configuration of the third coincidence detecting circuit 6 shown in FIG. When the circuit shown in FIG. 2 is used as the first and second coincidence detecting circuits 2 and 4, the third coincidence detecting circuit simply performs the logical AND (AN
D) It can be composed of a circuit. By combining the above two types of match detection circuits, 16-bit data can be converted to 1-bit match / mismatch data.

By the way, even if the switching speed of a MOS transistor is improved by miniaturization according to the scaling law with the high integration of the DRAM, the realization of the high speed of the DRAM is actually restricted by the wiring resistance of the signal line. It's getting harder. As a countermeasure, it has been proposed to use a small-amplitude differential signal in which the signal amplitude is limited to a value smaller than the power supply voltage in a read data transfer system (for example, ISSCC '91, digest of tec).
h. papers P.S. 56-57, or ISSC
C'91, digest of tech. pape
rsP. 114-115). A method for realizing the parallel test mode when such a small-amplitude differential signal is used in the read data transfer system will be described below.

In general, when considering a plurality of differential signal input logics, the EXOR circuit can be relatively easily realized, but the NOR circuit and the AND circuit are not controlled if the following two points are realized. It becomes complicated and the operation becomes unstable. (a) When the differential input voltage is OV even in one of a plurality of input pairs, the potential difference between the output line pairs is always OV. (b) The potential difference between the output line pair is always OV even when the voltages at the signal amplitude centers of the plurality of inputs are different from each other.

Therefore, in the embodiment of the present invention, the first and second coincidence detecting circuits 2 and 4 of FIG. 1 are configured by using an EXOR circuit having a built-in level conversion function, and a differential signal data transfer system and a parallel test are performed. Mode compatible. At this time, the data lines 3 from each cell array block 1 to the first match detection circuit 2 and the data lines 5 from the second match detection circuit 4 in FIG. 1 have small amplitudes as shown in FIG. These output data lines 7 are of a full amplitude differential signal data transfer system as shown in FIG. 4 (b).

FIG. 5 shows an embodiment of a two-input EXOR circuit having a built-in level conversion circuit for obtaining a full-amplitude differential signal from a small-amplitude differential signal as described above. The EXOR circuit includes first and second current mirror type differential logic circuits 111 and 112 to which a small amplitude differential signal is input, and a current control for inverting these outputs to obtain a full amplitude differential signal. It is constituted by first and second inverters 121 and 122 having a type load.

First current mirror type differential logic circuit 11
Reference numeral 1 denotes a pair of n-channel MOS transistors Q11 and Q11 whose inputs IN2 and / IN2 enter their gates and whose sources are commonly connected.
12, n-channel MOS transistor pairs Q13, Q14 and Q15, Q16, which are vertically stacked on these transistors Q11, Q12, respectively, and whose inputs IN1, / IN1 enter their gates.
And p-channel MOS constituting current mirror circuit
It has transistors Q17 and Q18. The common source of the n-channel MOS transistors Q11 and Q12 is controlled by an activation n-channel MOS transistor Q19 driven by a control signal TEST which goes to "H" level during a parallel test and a control signal VCM of an intermediate potential. It is grounded via a constant current source n-channel MOS transistor Q20 that operates as an arc tube. The second current mirror type differential logic circuit 112 is also configured symmetrically with the first differential logic circuit 111.

The first inverter 121 has a p-channel MOS transistor Q31 as a driver controlled by the potential of the output node N1 of the first differential logic circuit 111.
And an n-channel MOS transistor Q32 as a load. n channel MOS transistor Q
32 is a gate whose constant current source MO of the differential logic circuit 111 is
The current control type load is controlled by the same control signal VCM as the S transistor Q20 and operates as a pentode. Similarly, the second inverter 122 also has the second differential logic circuit 1
P channel MOS receiving output of output node N2 of 11
It comprises a transistor Q41 and an n-channel MOS transistor Q42 constituting a current control type load.

The p-channel MOS transistors Q51 and Q52 provided at the output nodes N1 and N2 of the differential logic circuits 111 and 112 are for precharging. These MOs
The S transistors Q51 and Q52 are controlled by the control signal TEST and turned on except during the parallel test (TEST = "L"), whereby the output nodes N1 and N2 are precharged to "H" level.

This EXOR circuit outputs an output of OUT = "H" and / OUT = "L" when the two inputs match. The general operation will be described.
Are at the "H" level, the first differential logic circuit 111
In this case, the n-channel MOS transistors Q11 and Q13 are turned on, and the output node N1 drops in potential, whereby the first inverter 121 outputs OUT = "H".
When both inputs IN1 and IN2 are at "L" level, / IN
1 and / IN2 are both at the "H" level, so that the n-channel MOS transistors Q12 and Q15 are turned on in the first differential logic circuit 111, the output node N1 is also lowered in potential, and the first inverter 121 Output OUT = “H”. If the two inputs are different, the output node N1 of the first differential logic circuit 111 outputs an "H" level, and the first inverter 121 outputs OUT = "L".

The operations of the second differential logic circuit 112 and the second inverter 122 are the same, and the first differential logic circuit 111 and the first inverter 121 output complementary outputs / OUT. .

In modes other than the parallel test mode, that is, when the control signal TEST is at "L" level, the nodes N1 and N2 are both precharged to "H" level (= Vcc), and the outputs OUT and / OUT is at the “L” level.

The above is a brief description of the operation.
In order to actually convert the level of a small-amplitude differential signal into a full-amplitude differential signal in the OR circuit operation, the first and second inverters 121 and 122 must have a current control type load. This is an important point, and the dimensions of each element need to be set optimally. Such conditions will be specifically described below.

FIG. 6 (a) shows an output node N1 side of the first differential logic circuit 111 and a portion of the first inverter 121 in the EXOR circuit shown in FIG. 11 1 side is an n-channel driver MOS transistor Q
1 and a p-channel load MOS transistor Q2. Here, the driver MOS transistor Q1
Means that the two differential inputs do not match, namely IN1, IN2
One is at the “H” level, (for example, (）) (Vcc + Δ
V)) and the other is at the “L” level (for example, (（) (V
5), or when there is no differential input, that is, when both IN1 and IN2 are, for example, (1/2) Vcc, the driver MOS transistors Q11 and Q11 in FIG.
13, driver MOS transistors Q15 and Q12 provided in parallel to these, and further MOS transistors Q11 and Q12
Including the activation MOS transistor Q19 and the current source MOS transistor Q20 provided in the common source of
This is represented as one equivalent MOS transistor.

At this time, the potential of the node N1 is as shown in FIG.
As shown, the characteristic curve of the MOS transistor Q1 and M
This is the potential at the intersection A of the characteristic curve of the OS transistor Q2. The load curve of the p-channel MOS transistor Q2 to which the gate and the drain are connected has a diode characteristic as shown in the figure, where the threshold voltage of the p-channel MOS transistor Q2 is Vtp. Since the gate of the n-channel MOS transistor Q1 is controlled by the control signal VCM set to the intermediate potential and operates as a pentode, the curve becomes Q1 in the figure. The intersection A of these curves is the "H" level potential of the node N1.

At this time, if the potential of the node N1 is an intermediate potential that causes the p-channel MOS transistor Q31 of the inverter 121 to operate as a pentode, the MOS transistor Q31
Is as shown by the solid line Q31 in FIG. 6 (b). To achieve this, it is necessary that the gate width W4 of the MOS transistor Q31 is set to be larger than the gate width W2 of the MOS transistor Q2. In the n-channel MOS transistor Q32 of the inverter 121, the gate width W3 is also set to be larger than the gate width W1 of the equivalent MOS transistor Q1, so that FIG.
The curve of Q32 shown in (b) is obtained. Therefore, at this time, the output Vout of the inverter 121 becomes the intersection B of the curves Q31 and Q32, and this is the "L" level output Vout. That is, if the element dimensions are designed such that W4> W2 and W3> W1, an "L" level output close to 0 V can be obtained.

On the other hand, when the two differential inputs match, the equivalent MO
When the current of the S transistor Q1 increases and the potential of the node N1 decreases, the p-channel
The current of the S transistor Q31 increases as shown by the dashed line in FIG. Therefore, the output Vout of the inverter 121 becomes the intersection C of the Q31 curve and the Q32 curve, and becomes a sufficient "H" level close to the power supply potential Vcc.

Incidentally, when a normal diode-connected load MOS transistor is used or when a resistive load is used, such a level conversion function cannot be obtained. FIG.
Is an ordinary n-channel MO in the inverter 121 of FIG.
FIG. 8 shows a case where a load composed of an S transistor Q3 is used and its characteristic diagram, and FIG. 8 shows a case where a resistive load R is used for the inverter 121 and its characteristic diagram, corresponding to FIG. As is clear from FIG. 7B, an inverter using a normal load MOS transistor cannot output sufficient "H" level output and "L" level output. In the case of a resistive load, as shown in FIG.
If the level output is to be made sufficiently low, an "H" level output will not be produced. Conversely, if the load resistance is made sufficiently high to produce a sufficient "H" level output, a low "L" level output will not be obtained. .

FIG. 9 shows an embodiment of the 4-bit coincidence detecting circuit constituted by using the EXOR circuit shown in FIG. 5 as a basic element, that is, the coincidence detecting circuits 2 and 4 shown in FIG.
Each of the three EXOR circuits 13 (131, 132, 133) has the configuration shown in FIG. When the 4-bit data matches, the output OUT of the EXOR circuit 13 becomes “H”,
OUT attains an “L” level.
The OR gate 14 outputs an "H" level output, and the NAND gate 15 outputs an "L" level output. From the output of the NOR gate 14 and the output of the NAND gate 15, the output circuit 17 outputs
As a result, / AGREE = "L" is obtained. If the 4-bit data does not match, AGREE = "L", / A
GREE = “H”. When the input of the differential signal is OV, the output of the EXOR circuit 13 is at the “L” level for both OUT and / OUT, and both the output circuits 16 and 17 are in a high impedance state. In the case of the embodiment shown in the figure, a precharge MOS transistor controlled by a control signal / PRE is provided at the output terminals of the output circuits 16 and 17, and is precharged to Vcc when there is no signal.

Although each circuit of the embodiment is shown in the simplest form, the present invention is not limited to the above-described embodiment, and can be freely modified without departing from the gist thereof. Further, although the embodiment has been described assuming a 16-bit parallel test, this can be applied even if the test bit length increases with the increase in the degree of integration of the RAM. Furthermore, although the embodiment has described the DRAM, other RAMs having the parallel test mode, such as SRAM, VRAM, PSRAM, etc., as well as the EPR
The present invention is also applicable to non-volatile memories such as OM and EEPROM.

[0037]

As described above, according to the present invention, the coincidence detection circuit is newly added without significantly increasing the number of data lines, thereby improving the defect detection efficiency in the parallel test. A semiconductor memory device can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a DRAM configuration according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of first and second coincidence detection circuits 2 and 4 of FIG. 1;

FIG. 3 is a diagram showing a configuration of a third coincidence detection circuit 6 in FIG. 1;

FIG. 4 is a diagram showing a small-amplitude differential signal and a full-amplitude differential signal.

FIG. 5 is a diagram showing an embodiment of an EXOR circuit having a level conversion function.

FIG. 6 is a diagram for explaining a level conversion function in the EXOR circuit of FIG. 5;

FIG. 7 is a view showing a comparative example of FIG. 6;

FIG. 8 is a view showing a comparative example of FIG. 6;

9 is a diagram showing a configuration of a 4-bit match detection circuit using the EXOR circuit of FIG. 5;

FIG. 10 is a diagram showing a configuration example of a conventional match detection circuit.

FIG. 11 is a diagram showing another configuration example of a conventional match detection circuit.

[Explanation of symbols]

 1 (11 to 14) ... cell array block, 2 (21 to 24) ... first match detection circuit, 3 (31 to 34) ... data line, 4 ... second match detection circuit, 5 (51 to 54) ... Data line, 6: Third match detection circuit, 7 (71 to 74): Data line, 8: Output drive circuit, 9: Data line, 111, 112: Current mirror type differential logic circuit, 121, 122: Current Control load type inverter.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-58375 (JP, A) JP-A-2-3199 (JP, A) JP-A-2-283000 (JP, A) JP-A-1- 253900 (JP, A) JP-A-64-76598 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 29/00 G11C 11/401 H01L 27/10 G01R 31/28

Claims (3)

(57) [Claims] In a semiconductor memory device having a memory cell divided into a plurality of cell array blocks and having a parallel test mode for writing and reading a plurality of bits at a time, a plurality of bits in each cell array block are provided. A plurality of first match detection circuits provided adjacent to each of the cell array blocks for detecting a match or mismatch of the memory cell data of each of the memory cell data; A second match detection circuit for detecting a match or mismatch between the representative values, and a match between the outputs of the first match detection circuit and the second match detection circuit arranged near the output pad of the chip. Alternatively, a semiconductor memory device comprising: a third match detection circuit for detecting a mismatch. 2. A data transfer system from the cell array block to the first match detection circuit and the second match detection circuit uses a small-amplitude differential signal having a signal amplitude smaller than a power supply voltage. 2. The semiconductor memory device according to claim 1, wherein a full-amplitude differential signal is used for an output data transfer system of the first match detection circuit and the second match detection circuit. 3. An exclusive OR circuit having a built-in level conversion circuit for obtaining a full-amplitude differential signal from a small-amplitude differential signal, said first coincidence detection circuit and said second coincidence detection circuit. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is configured by using the semiconductor memory device.