JP3249470B2 - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a memory cell using a ferroelectric capacitor and storing data in a nonvolatile manner by spontaneous polarization of a ferroelectric film, and a method of manufacturing the same. About.

[0002]

2. Description of the Related Art In recent years, non-volatile semiconductor memory devices using ferroelectric capacitors (hereinafter referred to as ferroelectric memories) have been actively studied. A ferroelectric capacitor has a laminated structure of a lower electrode, a ferroelectric film, and an upper electrode. As the ferroelectric film, typically, lead zirconate titanate (PZT) having a perovskite crystal structure is used. A ferroelectric memory enables data to be stored in a non-volatile manner by spontaneous polarization (remanent polarization) of a ferroelectric substance. The feature is that high-speed writing and reading are possible.

As an example in which a ferroelectric memory is constituted by a memory cell of one transistor / one capacitor similar to a DRAM, a method of using a ferroelectric capacitor for both a memory cell and a dummy cell for generating a reference potential (for example, Japanese Patent Application Laid-Open No.
198161), a method using a ferroelectric capacitor for a memory cell and a paraelectric capacitor for a dummy cell (for example, JP-A-5-325572) has been proposed.

Further, as an example of forming a ferroelectric memory by a memory cell system different from that of a DRAM, a system using two capacitors connected in series, a ferroelectric capacitor and a paraelectric capacitor, has been proposed ( JP-A-6
No. 119773). In this case, the connection node of the two capacitors becomes a storage node, and a MOS transistor having a gate connected to the storage node is required to detect the potential of the storage node. Therefore, an actual memory cell is a 1-transistor / 2-capacitor ( Or two transistors / two capacitors). The dummy cell has the same configuration.

[0005]

In the above-mentioned ferroelectric memory, a ferroelectric capacitor is used for a memory cell and a reference capacitor using a paraelectric film is used for a dummy cell. Assuming that a silicon oxide film or the like is used as the dielectric film, for example, as in a normal DRAM, the area occupied by the dummy cell is required to generate an intermediate reference potential with respect to the output potential of data "1" and "0". It will be much larger than the memory cell. In order to solve this difficulty, it is preferable to use a paraelectric film of the reference capacitor having a dielectric constant similar to that of the ferroelectric film of the ferroelectric capacitor. This is also suggested in the above-mentioned JP-A-5-325572 and JP-A-6-119773. However, Japanese Patent Application Laid-Open No. 5-325572 discloses that it is preferable to use a perovskite oxide as the paraelectric film. However, if the ferroelectric film and the paraelectric film are different materials, the same is true. A dielectric constant cannot be obtained, and the manufacturing process becomes complicated. Japanese Patent Application Laid-Open No. HEI 6-119773 describes that a paraelectric film is basically formed by the same process as a ferroelectric film. The specific reason for the dielectric is not disclosed.

On the other hand, the applicant of the present invention has made a technique of making a ferroelectric film in a memory cell and a paraelectric film in a dummy cell by making the epitaxial growth conditions of a dielectric film different between a memory cell and a dummy cell depending on a base electrode. Has been proposed (see JP-A-9-162362).

According to the results of the inventor's intensive research, the ferroelectric film is subjected to a certain treatment after the film formation, whereby the macro crystal structure identified by X-ray diffraction is reduced to the original ferroelectric film. It has been found that the ferroelectric film has the same ferroelectric property as the film, but can be modified into a paraelectric film having a relative dielectric constant substantially equal to that of the original ferroelectric film.

The present invention has been made on the basis of the above findings. The ferroelectric capacitor of the memory cell and the paraelectric film of the reference capacitor of the dummy cell have the same crystal structure, and have a small area by a simple manufacturing process. It is an object of the present invention to provide a ferroelectric memory capable of forming a cell array and a method of manufacturing the same.

[0009]

According to the present invention, a memory cell having a ferroelectric capacitor for storing data in a nonvolatile manner by spontaneous polarization of a ferroelectric film and a dummy cell having a reference capacitor for generating a reference potential are provided. In the nonvolatile semiconductor memory device having
A lower electrode, a ferroelectric film formed on the first lower electrode, and a first upper electrode formed on the ferroelectric film. And a paraelectric film formed on the second lower electrode and identified by X-ray diffraction as having the same crystal structure as the ferroelectric film, and a paraelectric film formed on the paraelectric film. And a second upper electrode.

Specifically, for example, the first lower electrode and the second lower electrode are formed of the same material film, and at least the interface portions in contact with the ferroelectric film and the paraelectric film have the same crystal structure. In addition, the paraelectric film of the reference capacitor is formed of the same material as the ferroelectric film of the ferroelectric capacitor, and is subjected to a modification process for deteriorating ferroelectricity.

Alternatively, the first lower electrode and the second lower electrode are formed of the same material film, and at least the interface portions respectively in contact with the ferroelectric film and the paraelectric film have the same crystal structure. The upper electrode and the second upper electrode are formed of different material films, and the paraelectric film of the reference capacitor is formed of the same material film as the ferroelectric film of the ferroelectric capacitor, thereby providing ferroelectricity. It is assumed that a reforming process that causes deterioration is performed.

Alternatively, the first lower electrode and the second lower electrode are formed of the same material film, and at least the interface portions in contact with the ferroelectric film and the paraelectric film have the same crystal structure. The first upper electrode and the second upper electrode are formed of the same material film, and the paraelectric film of the reference capacitor is formed of the same material film as the ferroelectric film of the ferroelectric capacitor, thereby providing ferroelectricity. It is assumed that a reforming process that causes deterioration is performed.

[0013] A method of manufacturing a nonvolatile semiconductor memory device according to the present invention comprises the steps of: forming transistors for memory cells and dummy cells on a semiconductor substrate; forming an interlayer insulating film covering the transistors; A step of integrally forming a capacitor for a memory cell and a dummy cell having a laminated structure of a lower electrode, a ferroelectric film and an upper electrode on the film; and for the capacitor for the dummy cell among the capacitors for the memory cell and the dummy cell, Before or after the formation of the upper electrode, a film modifying step of deteriorating the ferroelectricity of the ferroelectric film and modifying the ferroelectric film to a paraelectric film.

The film reforming step includes, for example, (a) a method of diffusing a specific metal element contained in the upper electrode of the capacitor for the dummy cell into the ferroelectric film by annealing, and (b) an upper electrode of the capacitor for the dummy cell. Before the formation, a method of annealing the exposed ferroelectric film in an atmosphere containing hydrogen, (c) a method of irradiating the ferroelectric film in the capacitor region for the dummy cell with an energy beam, and the like are used.

According to the present invention, the same material film is used for the ferroelectric film of the memory cell and the paraelectric film of the dummy cell, and the ferroelectric film having the dummy cell side as the paraelectric film by the modification treatment after the film formation. Memory is obtained. The modification of the ferroelectric film
It has been confirmed that diffusion of a metal element such as a transition metal into the ferroelectric film, annealing of the ferroelectric film in an atmosphere containing hydrogen, irradiation of the ferroelectric film with an energy beam, and the like are possible. When the conditions of the film modification process are selected, the dielectric film on the reference capacitor side of the dummy cell has the same macrocrystalline structure as the ferroelectric film of the memory cell, and X
Ferroelectricity is lost due to the introduction of minute defects that cannot be analyzed by line diffraction, and a paraelectric film having substantially the same relative dielectric constant can be obtained. As a result, the dummy cell can be formed to be as small as the memory cell, and a preferable reference potential can be generated for the read data "1" and "0" of the memory cell. Further, in the present invention, the modification of the ferroelectric film to the paraelectric film can be realized by a simple process.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1 to 6 are sectional views showing the steps of manufacturing a ferroelectric memory according to the first embodiment of the present invention, focusing on one memory cell MC and one dummy cell DC of a cell array. FIG. 1 shows a p-type (100) silicon substrate 1 (or a p-type well of an n-type silicon substrate)
After the element isolation insulating film 3 is buried, a MOS transistor QM for a memory cell and a MOS transistor QD for a dummy cell are formed in each element region.

The element isolation step is as follows. First, an element isolation groove 2 having a depth of about 0.3 μm is formed in a silicon substrate 1. Next, an SiO2 film of about 1.5 .mu.m is deposited on the entire surface of the substrate by a vapor phase growth method using a mixed gas of TEOS gas and ozone (O3) gas. Thereafter, the SiO2 is polished flat using a chemical mechanical polishing (CMP) method. As a result, Si
An element isolation insulating film 3 made of O2 is buried, and an element formation region surrounded by the element isolation insulating film 3 is obtained.

Thereafter, a gate electrode 5 of a polycrystalline silicon / WSi laminated film is formed via the gate insulating film 4,
MOS transistors QM and QD are formed by forming n + type diffusion layers 8 and 9 serving as a source and a drain. More specifically, a 10-nm gate insulating film and a 150-nm
Phosphorus doped polycrystalline silicon film, 150 nm WSi2
A 200 nm-thick Si3 N4 film 6 is deposited, and a gate electrode 5 having a width of 0.25 .mu.m is formed by a known photolithography method.
A pattern is formed while being covered with the N4 film 6. After this 3
After depositing a 0 nm SiO2 film on the entire surface, the entire surface is etched back by reactive ion etching (RIE) to form a sidewall SiO2 film 7 on the side of the gate electrode 5. Thereafter, n + is added to the silicon substrate 1 by ion implantation.
Forming diffusion layers 8 and 9 are formed. The gate electrodes 5 in the memory cell MC area and the dummy cell DC area are continuously arranged in a direction perpendicular to the plane of the drawing to become word lines and dummy word lines, respectively.

Next, as shown in FIG. 2, a first interlayer insulating film 10 is deposited on the entire surface, and the substrate surface is flattened by the CMP method.
/ Pt film 11, 200 nm thick PZ as ferroelectric film
T film 12 and Pt film 1 as an upper electrode film of the capacitor
3 are sequentially deposited. The PZT film 12 is crystallized by annealing after the film is deposited (or after the Pt film 13 is deposited thereon). Since the electrode portion in contact with the PZT film 12 is Pt, the PZT film 12 becomes a ferroelectric material having the same crystallinity including the Pt electrode portions in contact with the upper and lower portions thereof by annealing.

Thereafter, an upper electrode 13M is formed by using a well-known photolithography method, leaving a Pt electrode film only in a region of the memory cell MC region where a ferroelectric capacitor is to be formed. The Pt electrode on the area where the reference capacitor is to be formed in the dummy cell DC area is removed, and processing is performed so that the PZT film 12 is exposed. Next, PZT is added to each capacitor area.
The film 12 and the Ti / Pt film 11 are patterned using a reactive ion etching (RIE). This allows
As shown in FIG. 3, in the memory cell MC region, a ferroelectric capacitor CM having a laminated structure of a first lower electrode 11M, a PZT film 12, and a first upper electrode 13M is obtained. In the area of the capacitor CD, the second
The lower electrode 11D and the ferroelectric PZT film 12 are laminated to obtain an unfinished capacitor structure without an upper electrode. Each of the lower electrodes 11M and 11D is continuously arranged in a direction perpendicular to the plane of the drawing, and serves as a common drive line for a plurality of memory cells and a plurality of dummy cells.

At this stage, the first lower electrode 11M on the memory cell MC side and the second lower electrode 11M on the dummy cell DC side
D is the same Pt material film and has the same crystal structure, and the PZT film 12 thereon is also a polycrystalline film having the same crystal structure.

Next, as shown in FIG. 4, a second interlayer insulating film 14 is deposited on the entire surface, the surface is flattened by using the CMP method, and then the n + type diffusion of each of the MOS transistors QM and QD is performed. Buried contact layer 1 connected to layers 8 and 9 respectively
5 and 16 are formed. Buried contact layers 15, 16
Is an impurity-doped polysilicon for connecting the source and drain of the MOS transistor to the bit line and the capacitor node, respectively.

Thereafter, as shown in FIG. 5, contact holes 17 and 18 are formed in the region of the ferroelectric capacitor CM and the region of the reference capacitor CD, respectively. The contact hole 17 on the ferroelectric capacitor CM side has a size necessary to make an ohmic contact with the upper electrode 13M, and the contact hole 18 on the reference capacitor CD side is exposed so that the PZT film 12 is exposed as large as possible. First, the diameter is larger than that of the contact hole 17. An upper electrode 13M is provided at the bottom of the contact hole 17.
Is exposed, but PZT
The film 12 is exposed.

Thereafter, Ti / Ti is used as an upper electrode wiring layer.
An N / Al laminated film is deposited on the entire surface of the substrate, and desired wirings 19, 20, and 21 are formed by patterning using RIE. In the memory cell MC region, the Al laminated wiring 19 is a wiring only for connecting the buried contact layer 16 and the upper electrode 13M of the ferroelectric capacitor CM.
The Al laminated wiring 20 in the dummy cell DC region also serves as an upper electrode of the reference capacitor CD and connects the contact layer 16 and the reference capacitor CD. Further, the Al laminated wiring 21 connected to the remaining contact layers 15 is actually a bit line that is long disposed in the cell array region in the in-plane direction of the drawing.

In the steps up to this point, the ferroelectric capacitor CM of the memory cell MC and the reference capacitor CD of the dummy cell DC are formed in such a manner that only their upper electrodes are different. After that, 400 under nitrogen atmosphere.
Heat treatment is performed at 30 ° C. for 30 minutes. By this step, in the reference capacitor CD on the dummy cell DC side, Ti diffuses from the Al laminated wiring (also serving as upper electrode) 20 into the PZT film 12. As a result, the PZT film 12 of the reference capacitor CD is modified to lose ferroelectricity, and the paraelectric P
It becomes a ZT film. Since the ferroelectric capacitor CM on the memory cell MC side is protected by the upper electrode 13M,
no change.

According to the analysis of the inventor, the ferroelectric capacitor CM and the reference capacitor CD obtained in the above-described steps are obtained.
The PZT film 12 of (a) has the same spectrum by X-ray diffraction and is a polycrystal having the same macrocrystalline structure. (B) The PZT film 12 on the reference capacitor CD side is modified by Ti diffusion. Although the ferroelectricity is lost,
It was confirmed that it had a large relative permittivity (approximately 1000, almost the same as a PZT film that maintains ferroelectricity) determined by the macro crystal structure.

By using this embodiment, a paraelectric capacitor having a high dielectric constant can be realized by a simple process while maintaining the same crystal structure as the dielectric material constituting the ferroelectric capacitor. Therefore, the area occupied by the reference paraelectric capacitor can be reduced to the same extent as the ferroelectric capacitor, and the size of the ferroelectric memory can be reduced.

FIG. 7 is a cross-sectional view of a manufacturing process according to a second embodiment of the present invention, corresponding to FIG. 5 of the previous embodiment.
Parts corresponding to those in the previous embodiment are denoted by the same reference numerals as in the previous embodiment. 7 differs from that of FIG. 5 only in that only the contact hole 18 on the dummy cell DC side is opened and the ferroelectric capacitor CM on the memory cell MC side.
The point is that no contact hole is opened on the side.

In this embodiment, in the state shown in FIG. 7, the substrate is annealed at 150 ° C. for 30 minutes in a nitrogen atmosphere containing 3% of hydrogen. As a result, it has been confirmed that the PZT film 12 exposed at the bottom of the contact hole 18 loses ferroelectricity due to the introduction of vacancies due to oxygen defects as a result of the reducing action by hydrogen, and becomes a paraelectric PZT film. . Also in this example, the crystallinity of the paraelectric PZT film was the same as that of the ferroelectric PZT film, and the relative dielectric constant was about 1000, as in the previous example. Further, it was confirmed that the PZT film 12 in the memory cell MC region exhibited good ferroelectric characteristics.

Thereafter, although not shown, a contact hole is opened on the ferroelectric capacitor CM in the memory cell MC region, and a wiring layer is formed in the same manner as in the previous embodiment to form an element.

In this embodiment, the condition of annealing in a nitrogen atmosphere containing hydrogen is such that the hydrogen concentration is at least 0.
It has been confirmed that a similar effect can be obtained if the annealing temperature is 5% or more and the annealing temperature is 100 ° C. or more. Particularly preferable conditions are that the hydrogen concentration in the atmosphere is 1% or more and the annealing temperature is 1%.
It is 50 ° C. or more and 450 ° C. or less. Hydrogen may be contained in the atmosphere in any state of H2, OH group, H radical and the like.

According to this embodiment, similarly to the previous embodiment, a fine element can be realized by a simple method. 8 to 1
FIG. 1 is a sectional view showing a manufacturing process according to a third embodiment of the present invention.
Also in this embodiment, parts corresponding to those in the previous embodiment are denoted by the same reference numerals as in the previous embodiment, and detailed description is omitted. The steps up to the step of FIG. 2 are the same as in the first embodiment. Then, Ti / TiN
/ Pt film 11, PZT film 12, and Pt film 13 are simultaneously patterned to form a ferroelectric capacitor CM and a reference capacitor CD in a memory cell MC region and a dummy cell DC region, respectively, as shown in FIG. Form. The first lower electrode 11M of the ferroelectric capacitor CM and the second lower electrode 11D of the reference capacitor CM are the same material film, and the first upper electrode 13M of the ferroelectric capacitor CM and the first lower electrode 11M of the reference capacitor CM are formed. 2 upper electrode 13D
Is also the same material film. Therefore, at this stage, the reference capacitor CM is the same ferroelectric capacitor as the memory cell MC side.

Thereafter, as shown in FIG. 9, a second interlayer insulating film 14 is deposited on the entire surface, the surface of the substrate is flattened by using the CMP method, and buried contact layers 15 and 16 are formed. . Subsequently, as shown in FIG. 10, contact holes 17 and 18 are opened in each capacitor region. The conditions of the contact holes 17 and 18 are the same as in the first embodiment. Next, as shown in FIG. 11, a photoresist 23 is applied on the substrate, and the resist 23 is patterned so as to have an opening only in the area of the reference capacitor CD.

Thereafter, the entire surface of the substrate is irradiated with an ion beam. Specifically, in this example, H ⁺ ions were accelerated to 5 keV and implanted at a dose of 5E15 cm ² . As a result, it was confirmed that although the upper electrode was already formed in the reference capacitor CD, the PZT film 12 was reformed and did not lose ferroelectricity and became a paraelectric film. Also in the case of this embodiment, the paraelectric PZT film has the same macro crystal structure as the ferroelectric PZT and a relative dielectric constant of about 1,000.
Further, it was confirmed that the ferroelectric characteristics of the PZT film 12 did not deteriorate in the memory cell MC region.

The ion beam used in this embodiment is:
Inert gas ions or active gas ions may be used, but ions containing hydrogen are most effective, and those obtained by plasma discharge of hydrogen gas or those obtained by accelerating hydrogen ions with an accelerator and implanting them into a substrate, Good results were obtained using plasma discharge of carbon-hydrogen gas. Further, by applying another appropriate energy beam such as a photon beam such as an X-ray or an ultraviolet ray in addition to the ion beam, the PZT film can be similarly modified through the upper electrode.

In the case of the method of this embodiment, by making the diameter of the contact hole 18 substantially the same as that of the upper electrode 13D, a film reforming effect can be obtained with a low ion beam irradiation amount.
Thereafter, although not shown, a wiring for connecting each capacitor to the MOS transistor and other wirings are formed to complete the element structure.

In the embodiments described above, the lower electrode of the capacitor is used as a drive line commonly for a plurality of memory cells and dummy cells, and the upper electrode is used as an independent memory node for each memory cell and dummy cell. On the other hand, the lower electrode can be a memory node. FIG. 12 shows such a configuration example corresponding to FIG. 6 according to the first embodiment. The manufacturing process is basically the same as in the first embodiment. Immediately above the contact layer 16 buried in the first interlayer insulating film 10 and connected to the n + type diffusion layer 9, a ferroelectric capacitor CM of the memory cell MC and a reference capacitor CD of the dummy cell DC are arranged. Electrode 11M, 1
1D is connected to the contact layer 16. The upper electrode 13M of the ferroelectric capacitor CM is separated for each memory cell in order to separate the PZT film 12 for each memory cell.
Therefore, the upper electrode 13M is commonly connected by the Al laminated wiring 19 provided on the second interlayer insulating film 14 to form a drive line. The same applies to the dummy cell DC side, and the Al laminated wiring 20 also serving as the upper electrode is provided as a drive line.

The Al laminated wiring 21 connected to the contact layer 15 (15a, 15b) connected to the other n + type diffusion layer 8 of the MOS transistor is a relay electrode provided for each memory cell and each dummy cell. This is further connected to the uppermost bit line 27 via a third interlayer insulating film 25.

FIG. 13 shows an example in which the vertical relationship between the capacitors CM and CD and the bit line 27 is reversed with respect to the configuration shown in FIG. The bit line 27 is buried and disposed on the second interlayer insulating film 14 by, for example, a damascene method. A relay electrode 29 for connecting a capacitor to the contact layer 16 embedded in the first interlayer insulating film 10 is embedded in the second interlayer insulating film 14. And the bit line 27
The capacitors CM and CD are arranged on the second interlayer insulating film 14 in which is embedded by the same process as that of FIG.

When a ferroelectric capacitor and a reference capacitor are manufactured by the methods of the second and third embodiments, a laminated structure as shown in FIG. 12 or FIG. 13 can be used.
The memory cell system of the ferroelectric memory to which the present invention is applied may be of any type. For example, FIG. 14 or FIG.
The method shown in FIG.

The cell array 101 shown in FIG.
This is an example in which one dummy cell DC is arranged for a plurality of memory cells MC in a one-transistor / one-capacitor configuration like AM. In the figure, the bit line pair BLa,
A plurality of memory cells MC and another BL
b, one dummy cell DC is arranged. However, actually, in order to balance the bit line pair BLa, BLb,
A plurality of memory cells are also connected to Lb, and a dummy cell is also connected to BLa.

A sense amplifier 104 is connected to the bit line pair BLa, BLb. The gates of the MOS transistors of the memory cell MC and the dummy cell DC are connected to a word line WL and a dummy word line DWL, and are driven by a word line driving circuit 102 and a dummy word line driving circuit 103, respectively. The capacitor terminals of the memory cell MC and the dummy cell DC are connected to the drive line DL and the dummy drive line DD.
L, and driven by a drive line drive circuit 105 and a dummy drive line drive circuit 106, respectively.

The cell array 201 shown in FIG. 15 is an application example of a known two-transistor / 2-capacitor ferroelectric memory. In the ferroelectric memory, the spontaneous polarization is inverted every time data is read, which is a serious problem in reliability. In particular, if one dummy cell is arranged for a plurality of memory cells as a one-transistor / one-capacitor method similar to that of a DRAM, the operation of the dummy cells becomes more frequent than that of the memory cells, and as a result, the reliability deteriorates. The two-transistor / 2-capacitor memory cell system is preferable as it can solve such a problem of reliability.

In the example of FIG. 15, a plurality of memory cells MC each having a ferroelectric capacitor CM are connected to a bit line BLa, and a reference capacitor CD D is connected to a pair of bit lines BLb.
And a plurality of dummy cells DC having
1 are arranged in correspondence with 1. Pair of memory cells MC
And the capacitor terminals of the dummy cells DC are connected to a common drive line DL and are driven by a drive line drive circuit 204. Similarly, a pair of memory cell MC and dummy cell DC
Are commonly connected to a word line WL and are driven by a word line drive circuit 202. A sense amplifier 203 is connected to the pair of bit lines BLa and BLb.
Is connected.

The detailed description of the read and rewrite operations of the cell array system shown in FIGS. 14 and 15 will be omitted, but the principle of operation will be briefly described with reference to FIG. The ferroelectric capacitor CM of the memory cell MC changes the Q
-V shows hysteresis characteristics. The positive and negative spontaneous polarizations Qr1 and Qr2 of this hysteresis are stored in a nonvolatile manner as data “0” and “1”, respectively.
The reference capacitor CD of the dummy cell DC does not exhibit ferroelectricity in this embodiment, and has a relative dielectric constant similar to that of the ferroelectric capacitor. Therefore, a substantially linear history as shown in FIG.

At the time of data reading, as shown by the broken line in FIG.
The data does not cause a polarization reversal. At this time, the relationship between the read charge amounts of the memory cell MC and the dummy cell DC is as follows.
As shown in FIG. 16B, the charge amount difference Δ from the dummy cell
Based on Q1 and ΔQ2, “1” or “0” is determined. In data rewriting, as shown by the broken line in FIG. 16C, the data "1" whose polarization has been inverted by reading is again subjected to polarization inversion to return to the original spontaneous polarization Qr1 state. The non-inverted data "0" is the original spontaneous polarization Qr1
Return to

The present invention is not limited to the above embodiment. For example, as a ferroelectric material, not only PZT but also a layered ferroelectric (SrBi2 Ta2 O9, etc.) containing Sr, Bi, Ta, O as a main component, or Ba, Ti, O or Ba, Sr, Ti, O, etc. Similar effects can be obtained even when a ferroelectric material (BaTiO3, (Ba, Sr) TiO3, etc.) as a main component is used. That is, the present invention is effective in any case where an oxide ferroelectric having ionic bonding properties is used. As a material for the upper and lower electrodes sandwiching the ferroelectric film, a transition metal such as Ir or Ru, or a conductive oxide such as IrOx or RuOx can be used in addition to Pt. The metal element used when the metal element is diffused as a method of modifying the ferroelectric film is not limited to Ti, and other metal elements can be used.

[0048]

As described above, according to the present invention, the ferroelectric film modified by using the same material film as the ferroelectric film used for the ferroelectric capacitor is used as the reference capacitor of the dummy cell. A paraelectric film having the same crystal structure as that of the above and having a large relative dielectric constant is used. Therefore, it is possible to make the dummy cell have a large charge storage capacity with a small occupation area. Further, since the reference capacitor can be formed of the same material as the ferroelectric capacitor, the number of steps can be reduced and the cost can be reduced, and a highly reliable ferroelectric memory can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a step of forming a MOS transistor of a ferroelectric memory according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a capacitor forming step in the embodiment.

FIG. 3 is a cross-sectional view showing a patterning step of the capacitor in the embodiment.

FIG. 4 is a cross-sectional view showing a step of depositing a second interlayer insulating film in the same example.

FIG. 5 is a cross-sectional view showing a step of forming a contact hole for a capacitor in the example.

FIG. 6 is a cross-sectional view showing a process of modifying a ferroelectric film of a capacitor and a process of forming an upper electrode in the same example.

FIG. 7 is a cross-sectional view showing a process of modifying a ferroelectric film of a ferroelectric memory according to a second embodiment.

FIG. 8 is a sectional view showing a step of forming a capacitor of the ferroelectric memory according to the third embodiment.

FIG. 9 is a cross-sectional view showing a step of depositing a second interlayer insulating film in the example.

FIG. 10 is a cross-sectional view showing a step of forming a contact hole for the capacitor in the example.

FIG. 11 is a cross-sectional view showing a process of modifying a ferroelectric film in the example.

FIG. 12 is a cross-sectional view showing a memory cell and a dummy cell structure according to another embodiment.

FIG. 13 is a cross-sectional view showing a memory cell and a dummy cell structure according to another embodiment.

FIG. 14 shows an example of a cell array configuration of a ferroelectric memory to which the present invention is applied.

FIG. 15 shows another example of a cell array configuration of a ferroelectric memory to which the present invention is applied.

FIG. 16 is a diagram for explaining the operation principle of reading and rewriting of the ferroelectric memory.

[Explanation of symbols]

MC: memory cell, DC: dummy cell, CM: ferroelectric capacitor, CD: reference capacitor, 1 ... silicon substrate, 4 ... gate insulating film, 5 ... gate electrode, 8, 9 ... n +
-Type diffusion layers, 10, 14 ... interlayer insulating films, 11M, 11D ...
Lower electrode, 12: PZT film, 13M, 13D: Upper electrode, 20: Al laminated wiring (upper electrode).

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/105 H01L 21/8242 H01L 27/10 481 H01L 27/108

Claims (6)

(57) [Claims] 1. A nonvolatile semiconductor memory device comprising: a memory cell having a ferroelectric capacitor for storing data in a nonvolatile manner by spontaneous polarization of a ferroelectric film; and a dummy cell having a reference capacitor for generating a reference potential. the ferroelectric capacitor comprises a first lower electrode, and the first lower ferroelectric formed on the electrode film, and a first upper electrode formed on the ferroelectric film The said
The upper electrode is covered with an interlayer insulating film, and the reference capacitor includes a second lower electrode and a second lower electrode.
A paraelectric film which is formed on the lower electrode and is identified by X-ray diffraction to have the same crystal structure as the ferroelectric film .
The paraelectric film is covered with the interlayer insulating film.
And through the opening formed in the interlayer insulating film, the ferroelectric
A wiring layer in contact with a first upper electrode of the body capacitor;
A second upper part of the reference capacitor which is in contact with the paraelectric film
A nonvolatile semiconductor memory device, wherein a wiring layer also serving as an electrode is formed of the same material . 2. The method according to claim 1, wherein the first lower electrode and the second lower electrode are formed of the same material film, and at least the interface portions in contact with the ferroelectric film and the paraelectric film have the same crystal structure, and The paraelectric film of the reference capacitor is formed of the same material as the ferroelectric film of the ferroelectric capacitor, and has been subjected to a modification process for deteriorating ferroelectricity. 2. The nonvolatile semiconductor memory device according to 1. 3. have a first of the lower electrode and the second lower electrode is formed of the same material film at least a ferroelectric film and a respective contact surface portion paraelectric film is the same crystal structure, and The paraelectric film of the reference capacitor is formed of the same material film as the ferroelectric film of the ferroelectric capacitor, and is subjected to a modification process of deteriorating ferroelectricity by element diffusion from the wiring layer. 2. The non-volatile semiconductor storage device according to claim 1, wherein: 4. have a first of the lower electrode and the second lower electrode is formed of the same material film at least a ferroelectric film and a respective contact surface portion paraelectric film is the same crystal structure, and The paraelectric film of the reference capacitor is formed of the same material film as the ferroelectric film of the ferroelectric capacitor, and has been subjected to a modification process of deteriorating ferroelectricity by ion irradiation. The nonvolatile semiconductor memory device according to claim 1, wherein 5. A process for integrally forming transistors for memory cells and dummy cells on a semiconductor substrate; a process for forming a first interlayer insulating film covering the transistors; and a memory cell on the first interlayer insulating film. Capacitor area
The stacked structure of the lower electrode, ferroelectric film and upper electrode
And a lower voltage in the area of the dummy cell capacitor.
Patterning a laminated structure of a pole and a ferroelectric film, and forming a second interlayer insulating film covering the laminated structure
And the memory cell capacitor and the second interlayer insulating film.
Of opening the area of the capacitor for the dummy cell
And forming a dummy cell capacitor on the second interlayer insulating film.
For the memory cell, the upper electrode also serves as the upper electrode.
Form wiring layers for capacitors and capacitors for dummy cells
And annealing, to induce the dummy cell capacitor.
A method in which a specific element contained in the wiring layer is diffused into an electric film to deteriorate ferroelectricity and modify the film to a paraelectric film. . 6. A process for integrally forming transistors for memory cells and dummy cells on a semiconductor substrate; a process for forming an interlayer insulating film covering the transistors; and a lower electrode, a ferroelectric film, and a ferroelectric film on the interlayer insulating film. A step of integrally forming a capacitor for a memory cell and a capacitor for a dummy cell having a laminated structure of an upper electrode; and a ferroelectric material for the capacitor for the dummy cell.
A film modification step of irradiating the film with an ion beam to deteriorate ferroelectricity to modify the film into a paraelectric film.