JP3242132B2 - Semiconductor memory and semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a system using the same. It is related to technology that is effective when used for such things.

[0002]

2. Description of the Related Art A dynamic RAM in which a plurality of dummy cells are provided, the amount of information stored is monitored by monitoring the storage information level of the dummy cells, and an automatic refresh circuit is activated before the information is lost.
Has been proposed in JP-A-60-83293.

[0003]

In the above automatic refresh method, it is necessary to monitor the information storage amount of the dummy cell similar to the memory cell. However, in practice, when a dummy cell similar to a memory cell is used, the information storage capacitor has a smaller capacitance value than an input capacitance or a wiring capacitance of a comparator or the like for monitoring the same. Therefore, it is extremely difficult to make the information storage amount of the dummy cell monitored under the influence of the input capacitance and the wiring capacitance accurately correspond to the information storage amount of the actual memory cell. In particular, in a dynamic RAM in which elements are miniaturized, such as about 4 Mbits or about 16 Mbits, the capacitance value of the information storage capacitor tends to become smaller and smaller. It is no exaggeration to say that a refreshing operation with a certain nature cannot be expected.

[0004] Further, it is conceivable to perform a battery backup in order to make the storage information of the dynamic RAM nonvolatile in response to a power interruption or the like. In the case where such a battery backup is performed at a low voltage, problems such as insufficient levels and insufficient operation of the circuit may occur in a conventional booster circuit such as a word line or a substrate voltage generating circuit according to the present invention. Was clarified by the study of the elderly. An object of the present invention is to provide a semiconductor memory device having a self-refresh function with low power consumption and a system using the same. Another object of the present invention is to provide a semiconductor memory device provided with a variable booster circuit capable of obtaining an optimum boosted voltage corresponding to a power supply voltage or a boosted output. Another object of the present invention is to provide a semiconductor memory device provided with a substrate voltage generating circuit capable of forming a substrate bias voltage that follows power supply fluctuation while reducing power consumption. Still another object of the present invention is to provide a semiconductor memory device having a RAM circuit using dynamic memory cells and capable of battery backup at low voltage. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. In other words, the self-refresh operation around the RAM using the dynamic memory cell is performed based on a periodic pulse formed by an oscillation circuit that has substantially no temperature dependency,
The self-refresh cycle is controlled by a timer circuit using a time constant circuit corresponding to the temperature dependency of information retention in the memory cell. The operating voltage or boosted output voltage is monitored, and the boosted voltage is doubled,
A circuit operation for forming a plurality of types of boosted voltages that sequentially increase like double is switched. MOSFE provided between a substrate and a ground potential point of the circuit by a dummy substrate voltage generation circuit having a leakage current path that changes following a change in power supply voltage
Form the control voltage supplied to the gate of T.

[0006]

According to the above-described means, a self-refresh operation with low power consumption suitable for the information storage amount of the memory cell can be realized by the timer using the time constant circuit. The operation margin can be expanded by generating a variable boost corresponding to the fluctuation of the operation voltage. The substrate voltage can be changed following the power supply voltage without increasing the substrate leakage current by the MOSFET controlled by the dummy substrate voltage generation circuit.

[0007]

FIG. 1 shows an embodiment of a computer system using a memory device including a semiconductor memory RAM to which the present invention is applied. The memory device M
The EC is, for example, a memory card, and among the circuit blocks included in the memory card, each of the circuit blocks except for the battery is configured by a CMOS integrated circuit device including one chip. Although not particularly limited, the plurality of semiconductor chips are integrally housed together with the battery in a card-shaped package.

The semiconductor memory RAM is composed of a plurality of 1 to N, and each of the semiconductor memory RAMs
It has a control terminal CT, a data terminal DT, and an address terminal AT. Each of the control buses CB2 and CB3, the data bus DB2 and the address bus AB2 is composed of a plurality of signals. The control terminals CT, data terminals DT, address terminals AT, and terminals T5 to T8 are provided corresponding to the number of signal lines of the control bus CB, the data bus DB, and the address bus AB. By using the N semiconductor memory RAMs, the storage capacity of the memory card is set to N times the storage capacity of one RAM.

Although not particularly limited, a semiconductor memory RAM
Uses a dynamic memory cell composed of an address selection MOSFET and an information storage capacitor as described later,
Pseudo-static type R made compatible with AM
AM (hereinafter, may be simply referred to as PSRAM). By using a dynamic memory cell as the memory cell as described above, a relatively large storage capacity can be realized even in a limited mounting space such as a memory card.

The control circuit CONT selects one or a plurality of the semiconductor memory RAMs and controls the operation mode. That is, the control circuit CONT
Is connected to a terminal T1 of the microcomputer system MCS through a control signal dedicated terminal T5. The control circuit CONT includes a microprocessor MPU
Receiving the control signal output from the control bus CB1 and the terminal T1 to decode the system address of the higher-order bit to obtain one of N semiconductor memory RAMs.
, A write enable signal WEB for read / write control, an output enable signal OEB, and the like. Here, a signal suffixed with B at the end of the character string, such as the signals WEB and CEB, means that the low level is the active level. However, in the drawings, in order to facilitate understanding of the present invention, signals for which the low level is the active level are overbard according to a general logical notation.

The data terminal DT of the semiconductor memory RAM
Is connected to a data bus terminal T6.
Connected to. An address bus AB2 connected to an address terminal AT of the semiconductor memory RAM is connected to an address dedicated terminal T7.

The power supply control circuit PWR includes a memory card ME
The battery voltage of the battery (lithium) mounted inside C,
A power supply voltage supplied from the microcomputer system MCSK power supply circuit PCKT is received via the power supply voltage terminal T8, and the voltage is switched according to the operation mode to switch the internal semiconductor memory RAM or the control circuit CO
Supply to NT. For example, when the semiconductor memory RAM is in a data holding state, the power supply control circuit PWR supplies a voltage of a battery mounted inside the memory card MEC. On the other hand, the memory card MEC of this embodiment is connected to the microcomputer system MCS to
When a write operation is performed, the power supply voltage is switched to a power supply voltage for operating the microcomputer system MCS. In this case, the microcomputer system MCS constitutes a portable microcomputer system such as a laptop type, a notebook type or a palm top type, and various personal computers.

Each circuit block of the microcomputer system MCS (excluding the battery and the display mounted on the power supply circuit) is constituted by a semiconductor integrated circuit consisting of one chip. Microcomputer system M
The CS has a program memory PMEM in which instructions for execution by the microprocessor MPU are written, and a data memory DMEM for storing data to be processed by the microprocessor MPU in accordance with instructions from the program memory PMEM or processed data. . The level conversion circuit LC converts the signal level of the data stored in the data memory DMEM for display display, for example.

The microprocessor MPU, the program memory PMEM, the data memory DMEM, and the level conversion circuit LC include a control bus CB1, a data bus DB1.
And an address bus AB1. Also,
Microprocessor MPU, program memory PME
M, each circuit of the data memory DMEM is a power supply circuit PCK
A power supply voltage for operation is supplied from T.

For example, as the semiconductor memory RAM, 1
A memory card MEC is constituted by using four pieces each having a data retention current of 5 μA per unit, and has a nominal capacity of 250 mAh and a CR24 only in the data retention state.
If a 30-type lithium battery is used, it is not necessary to replace the battery for as long as about 520 days.

At present, the types of batteries mainly used in small electronic devices are lithium batteries, nickel-cadmium batteries and lead batteries as described above. The voltages generated by these batteries are 2.8 V to 3.6 V for lithium batteries, 1.2 V for NiCd batteries, and 2 V for lead batteries. Of these, NiCd batteries are often marketed with multiple directly connected,
For example, the output voltages are set to 2.4V and 3.6V.

The circuit elements constituting the semiconductor memory RAM and the control circuit CONT are not particularly limited. However, the maximum voltage is based on a battery voltage of 3.6 V. Considering that the current required for the operation of the CMOS circuit can be obtained up to about 1.6 V in a discharged state, the gate insulating film is formed as thin as possible and the channel length is shortened. 3.6 V to 1.6 V using
The operation at the battery voltage in the range up to is guaranteed. This makes it possible to obtain a memory card that can operate with any of three types of small batteries: a 3.6 V lithium battery, two 2.4 V nickel-cadmium batteries connected in series, and a 2 V lead battery.

In this case, the control circuit CONT and the power supply control circuit PWR are provided with a
74HC series and / or 74AC of OS logic IC
It is configured using a circuit corresponding to the series or its standard IC. The input / output interface of the semiconductor memory RAM is also designed to be compatible with the 74HC series and / or 74AC series.

As international interface specifications of CMOS circuits in consideration of operation by a low-voltage battery voltage or the like, LVCMOS (Low Voltage CMOS) and LVBO (Lo) described in JEDEC STANDARD No. 8 in 1984.
w Voltage Battery Operated CMOS), and the above RAM interface specifications are used to satisfy these requirements. In order to support the above interface specifications,
The interface specifications of the RAM of this embodiment are shown in Table 1 below.
It is decided as follows. Here, VCC is the power supply voltage, V _{IH (min)} is the minimum value of the input high level, V _{IL (max)}
Is the maximum value of the input low level, _{VIH (max)} is the maximum value of the input high level, and _{VIL (min)} is the minimum value of the input low level.

In the standard interface specifications as described above, the lower limit operating voltage VCC (min) is 74
HC series and LVBO both up to 2V, LV
CMOS is only up to 3V. In this embodiment, the lower limit operating voltage VCC (m
in) is set to 1.6V. However, in the standard interface, the power supply voltage VCC is 0.75
Or, set the voltage obtained by multiplying 0.7 to V _{IH (min),} and set the voltage obtained by multiplying the power supply voltage VCC by 0.15 or 0.2 to V _{IH (min).
Since IL (max)} is set, the interface specification at the lower limit operating voltage in this embodiment is set so as to conform to the above strict conditions.

[0021]

[Table 1]

Input circuits such as an address buffer and a data input buffer of a semiconductor memory RAM, and a P-channel MOSFET and an N-channel MO constituting an output buffer so as to satisfy the interface specifications shown in Table 1 above.
The conductance of the SFET and its conductance ratio are set.

As described above, the operation assurance voltage is 1.6 V which is lower than the lowest voltage of 2 V of the lead battery.
In the case of setting to, the current capacity of the lead battery can be used to the last minute, and the following advantages occur.
For example, when a lead-acid battery is used as a built-in battery and it is used for a data retention operation of a semiconductor memory RAM, in other words, when it is used for battery backup for nonvolatile storage information, the memory card MEC operates with a lithium battery. When connected to the microcomputer system MCS to be operated, it is necessary to provide a backflow prevention diode in order to prevent backflow from occurring in the built-in lead battery. When such a backflow prevention diode is connected, a voltage loss occurs by the forward voltage. For this reason,
If the lower limit voltage is set to the lead voltage of 2 V, the above lead battery cannot be used for battery backup. On the other hand, when the lower limit voltage is guaranteed to be lower than the lead voltage, such as 1.6 V, as in this embodiment, the lead battery can be used for the battery backup as described above. In this case, a diode having a small forward voltage such as a Schottky diode may be used.

FIG. 2 is a general layout diagram showing an embodiment of a selection circuit, a timing generation circuit, and a voltage generation circuit of a pseudo static RAM used in the memory card MEC and the like. Each of these circuits is divided into circuit blocks 1 to 4 in view of the size of the drawings, and specific circuits of each embodiment are shown in FIGS.

FIG. 7 shows the pseudo static RAM.
1 is an overall layout diagram of an embodiment of a memory array and its peripheral circuits. These circuits are divided into circuit blocks 1 to 4 in view of the size of the drawing, and details of each circuit are shown in FIGS. Is shown in FIG. 7 shows the relationship between the overall arrangements of FIGS. 8 to 11. FIG. 12 shows the pseudo static RA
FIG. 1 shows an overall layout of M data input / output circuits. These circuits are divided into circuit blocks 1 and 2 in view of the size of the drawing.
3 and FIG.

The circuit elements formed in each circuit block and the circuit elements of each circuit shown in FIGS. 2 to 14 are not particularly limited. Formed on a single semiconductor substrate. 3 to 6,
In FIGS. 8 to 11, 13 and 14, and the following circuit diagrams, signal lines for input or output signals and the like are shown starting from bonding pads formed on the surface of the semiconductor substrate.

Pseudo-static RAM of this embodiment
Has a dynamic RAM as a basic configuration as described above, and its memory cells are constituted by so-called one-dynamic MOSFET dynamic memory cells, thereby achieving high integration and low power consumption of the circuit. ing. Further, X address signals X0 to X10 and Y address signals Y11 to Y18 are input via separate address input terminals A0 to A10 and A11 to A18, respectively,
Further, as a control signal, a chip enable signal CEB,
Write enable signal WEB and output enable signal O
By providing the EB, a normal static RAM
It has an input / output interface compatible with

Further, the pseudo-static RAM has a refresh counter R containing a refresh address.
An auto-refresh mode in which a refresh operation is performed spontaneously while being designated by FC, a refresh counter RFC and a built-in refresh timer circuit TMR
And a refresh timer counter circuit SRC,
A self-refresh mode in which refresh operations for all word lines are performed autonomously and intermittently at a predetermined cycle.

In this embodiment, the output enable signal OEB is not particularly limited, but is also used as a refresh control signal RFSHB. The operation mode of the pseudo static RAM is selectively selected by the output enable signal OEB and the write enable signal WEB. Is set.

In FIG. 2 and FIGS. 3 to 6, a chip enable signal CE supplied from the outside as a start control signal is provided.
B, the write enable signal WEB and the output enable signal OEB, ie, the refresh control signal RFSHB,
Corresponding input buffers CEIB, WEIB and OEIB
Is supplied to the timing generation circuit TG. Also, the refresh address counter RFC is input buffer C
Upon receiving signals from EIB and OEIB, the refresh signal φ _SRF is supplied to the timing generation circuit TG. The timing generation circuit TG includes 3-bit non-inverted address signals BX0, BX1 and BX10 and inverted address signals BX0B, BX1B and B from the X address buffer XAB.
An internal complementary address signal composed of X10B is supplied.
The timing generator TG, said chip enable signal CEB, based write enable signal WEB and the output enable signal OEB and the refresh signal phi _SRF and the above-described complementary internal address signals BX0, BX1 and BX10 and BX0B, on whether BX1B and BX10B, pseudo Various timing signals necessary for the operation of each circuit block of the static RAM are formed.

Externally corresponding address input terminals A0 to A0
The 11-bit X address signals X0 to X10 supplied through A10 are supplied to, but not limited to, input terminals of an X address buffer XAB. The 8-bit Y address signals Y11 to Y18 are supplied to the Y address buffer YAB. Supplied. The X address buffer XAB has an inverted timing signal φrefB from the timing generation circuit TG.
And φxlB are supplied, and the inverted timing signal φylB is supplied to the Y address buffer YAB. Here, the inversion timing signal φrefB is, as described later, when the pseudo static RAM is selected in the auto-refresh or self-refresh mode.
When the pseudo static RAM is selected, the levels of the X address signals X0 to X10, the refresh address signals AR0 to AR10, and the Y address signals Y11 to Y18 are determined. At this point, it is selectively set to the low level.

When the pseudo-static RAM is selected in the normal write or read mode and the inversion timing signal φrefB is at a high level, the X address buffer XAB is supplied with an X address signal X0 supplied via an external terminal. X10 is fetched in accordance with the inversion timing signal φxlB and held. The X address buffer XAB further stores these X address signals X0 to X10
Based on the complementary internal address signals BX0 to BX10, B
X0B to BX10B are formed. Among them, the lower 2 bits of complementary internal address signals BX0-BX1, BX0B-
BX1B and the most significant 1-bit complementary internal address signal BX
10, BX10B are supplied to the timing generation circuit TG as described above, and are supplied to the 3-bit complementary internal address signal BX.
2, BX3, BX10 and BX2B, BX3B and BX
10B is supplied to the word line selection drive signal generation circuit PWD. The remaining 6 bits of complementary internal address signals BX4 to
BX9 and BX4B to BX9B are X predecoders PX
D. Complementary internal address signals BX2 to BX9
And BX2B to BX9B are also supplied to the X-system redundant circuit XR.

Each memory array of the pseudo static RAM is provided with four redundant word lines and eight sets of redundant complementary data lines. X-system redundant circuit XR (XRU, XRD)
Is a defective address assigned to each redundant word line, and a complementary internal address signal B supplied via the X address buffer XAB at the time of memory access.
X2 to BX9 and BX2B to BX9B are compared and collated bit by bit. As a result, when these addresses match all the bits, the corresponding inverted redundant word line select signal XR
0B to XR3B are selectively set to a low level. The inverted redundant word line selection signals XR0B to XR3B are supplied to a redundant word line selection drive signal generation circuit PRWD.

The word line selection drive signal generation circuit PWD
The complementary internal address signals BX2, BX3 and BX10
Based on the word line drive signals φx supplied from the BX2B, BX3B and BX10B and the timing generation circuit TG, the word line select drive signals X00U to X11U and X00D to X11D are selectively formed. The redundant word line selection drive signal generation circuit PRWD includes the word line drive signal φx, the inverted redundant word line selection signals XR0B to XR3B, and the complementary internal address signal BX.
10, BX10B, the corresponding redundant word line selection drive signals XR0U to XR3U or XR0D to XR3
D is selectively formed.

The boosting circuit VCHG performs a variable boosting operation based on a sensor output that detects a change in the operating voltage, as described later, and forms a predetermined boosted voltage VCH exceeding the power supply voltage of the circuit. The boosted voltage VCH is applied to the word line selection drive signals X00U to X11U (X00D
To X11D) and the redundant word line selection drive signal X
Used for selection levels of R0U to XR3U (XR0D to XR3D). By generating such a boosted voltage VCH, by operating at a low voltage as described above, it is possible to perform full writing of information storage charges to the information storage capacitor of the memory cell, which is necessarily reduced. It is to be.

The X predecoder PXD decodes the complementary internal address signals BX4 to BX9 and BX4B to BX9B by sequentially combining them two bits at a time, thereby forming the corresponding predecode signals AX450 to AX453 and AX670 to AX670.
AX673 and AX890 to AX893 are alternatively formed. These predecode signals are
It is supplied commonly to the decoder.

Similarly, when the pseudo static RAM is selected in the normal write or read mode, the Y address buffer YAB changes the Y address signals Y11 to Y18 supplied via the external terminals into the inverted timing signal φylB. And retain it. Further, based on these Y address signals, complementary internal address signals AY11 to AY18 and AY11B to AY18B are formed. These complementary internal address signals AY11-AY
Y18, AY11B to AY18B are Y predecoders P
It is supplied to YD and Y-system redundant circuit YRAC.

The Y-system redundant circuit YRAC includes a defective address assigned to each redundant data line and complementary internal address signals AY11-AY18, AY11B supplied via the Y address buffer YAB at the time of memory access.
AY18B is compared with bits. As a result, when these addresses match all the bits, the corresponding redundant data line selection signals YR0 to YR7 are selectively set to the high level. The redundant data line selection signals YR0 to YR7 are supplied to each Y decoder via a Y predecoder PYD.

The Y predecoder PYD decodes the complementary internal address signals AY11 to AY18 and AY11B to AY18B by sequentially combining them two bits at a time, so that the corresponding predecode signals AY120 to AY123, AY
340 to AY343, AY560 to AY563 and AY780 to AY783 are formed alternatively.
These predecode signals are commonly supplied to the respective Y decoders via corresponding signal lines. In this embodiment, the signal lines for transmitting the predecode signals AY560 to AY563 and AY780 to AY783 to the respective Y decoders are the redundant data line selection signals YR0 to YR.
7 is commonly used as a signal line for transmitting. Therefore, the Y predecoder PYD selectively selects the predecode signals AY560 to AY563 and AY780 to AY783 or the redundant data line selection signals YR0 to YR7 in accordance with the complementary internal control signals φyr and φyrB supplied from the Y redundant circuit YRAC. Also has a function of transmitting to the signal line.

As shown in FIG. 6, a substrate back bias voltage generating circuit VBBG for forming a negative potential substrate back bias voltage VBB based on a circuit power supply voltage, and a voltage approximately one half of the circuit power supply voltage. Internal voltage HVC
And a voltage generation circuit HVC that forms

Referring to FIGS. 7 to 11, this pseudo-static RAM includes eight memory arrays MARY0L and MARY8 which are substantially divided in the data line extending direction.
RY0R to MARY3L and MARY3R are provided. These memory arrays have corresponding sense amplifiers S
A0L and SA0R to SA3L and SA3R and column switches CS0L and CS0R to CS3L
And the corresponding Y address decoder Y along with CS3R
D0 to YD3 are arranged symmetrically.
Further, the sense amplifiers, column switches, and Y decoders corresponding to these memory arrays are arranged vertically above and below the corresponding X address decoders XD0L and XD0R to XD3L and XD3R, and correspond to the arrangement positions. (U) or (D). In the following description, the symbols (U) and (D) are omitted unless otherwise necessary to avoid complication. Further, of the memory arrays, those arranged above the X decoder (left side in the figure) are collectively referred to as an upper side array, and those arranged below (the right side in the figure) are referred to as a lower side array.

Memory arrays MARY0L to MARY3L
MARY0R to MARY3R are selectively put into an operation state when a designated word line is put into a selected state. In this embodiment, when the pseudo static RAM is set to the normal write or read mode or the auto refresh mode, the eight memory arrays are MARY0L and MARY2L (or MARY0R and MARY2R) or MARY1L.
And MARY3L (or MARY1R and MARY3
R) are simultaneously activated two by two in combination of R).
At this time, in each memory array, the upper-side array or the lower-side array is set to the complementary internal address signal BX1 of the most significant bit.
0, BX10B, and four sets of data lines are simultaneously selected from the two memory arrays to be operated, and the corresponding main amplifiers MALL and MALR or MALL and MARR or write circuits DILL and DILR or DIRL and DIRR are connected to corresponding unit circuits. as a result,
This pseudo-static RAM is a so-called × 8-bit RAM for simultaneously inputting and outputting 8-bit storage data.
It is said.

When the pseudo-static RAM is set to the self-refresh mode, there is no particular limitation, but the eight memory arrays are simultaneously operated. At this time, in each memory array, the upper-side array or the lower-side array indicates the complementary internal address signals BX10, BX of the most significant bit.
X10B is selectively operated, and refresh operations for a total of eight word lines that are selectively selected in these memory arrays are simultaneously executed. These refresh operations are executed autonomously and periodically at a cycle four times the normal refresh cycle, and the refresh address counter RFC is sequentially updated each time. As a result, the number of refreshes per unit time in the self-refresh mode is substantially a quarter, and the average current consumption of the memory array is correspondingly reduced. Such a self-refresh operation will be described later in detail. In FIG. 11, the memory array MARY
0L (U) shows one memory cell coupled to word line W and data line D.

As shown in FIGS. 12 to 14, the pseudo-static RAM has eight data input / output terminals IO0 to IO0 provided corresponding to 8-bit input or output data.
IO7 is provided. A data input buffer DIB and a data output buffer DOB each including eight unit circuits are provided corresponding to these data input / output terminals. The data input / output terminals IO0 to IO7 are coupled to the input terminals of the corresponding unit circuits of the data input buffer DIB and to the output terminals of the corresponding unit circuits of the data output buffer DOB. Data input buffer DI
B has a timing signal φ from the timing generation circuit TG.
dic is supplied, and the timing signal φdoc is supplied to the data output buffer DOB. Here, although the timing signal φdic is not particularly limited, when the pseudo static RAM is selected in the normal write mode, the level of input data supplied via the data input / output terminals IO0 to IO7 is determined. At some point, it is selectively set to high level. Also, the timing signal φdoc
Is set to a high level when the level of the read signal of the selected eight memory cells is determined when the pseudo static RAM is selected in the normal read mode.

The output terminals of the lower four unit circuits of the data input buffer DIB are connected to the write circuits DILL and DIR.
L are respectively coupled to the input terminals of the corresponding unit circuits,
Output terminals of the upper four unit circuits of the data input buffer DIB are respectively coupled to input terminals of the corresponding unit circuits of the write circuits DILR and DIRR. Similarly, the input terminals of the lower four unit circuits of the data output buffer DOB are respectively coupled to the output terminals of the corresponding unit circuits of the main amplifiers MALL and MARL, and the input terminals of the upper four unit circuits of the data output buffer DOB are connected. The terminals are respectively coupled to output terminals of the corresponding unit circuits of the main amplifiers MALR and MARR. A timing signal φma0 is supplied from the timing generation circuit TG to the main amplifiers MALL and MALR.
ARR is supplied with the timing signal φma1.

When the pseudo-static RAM is selected in the write-system operation cycle, the data input buffer DIB receives the input data supplied through the data input / output terminals IO0 to IO7 to the timing signal φdi.
c, and is written to eight memory cells that are simultaneously selected through the corresponding unit circuits of the write circuits DILL to DIRR. The data output buffer DOB is amplified by the main amplifiers MALL to MARR when the quasi-static RAM is selected in the operation cycle of the read system.
The bit read signal is converted to the timing signal φdoc.
According to the data input / output terminals IO0
It is sent to the outside via IO7. Timing signal φdo
When c is at a low level, data output buffer DO
The output of B is in a high impedance state.

Pseudo-static RAM of this embodiment
Uses the non-address multiplex system as described above, and has a total of 19 address input terminals A0 to A18. Further, a total of 16 memory arrays are formed, each of which is paired and divided into upper and lower parts, and each memory array is selectively selected and divided into groups of four as described later. Group, a total of 256 word lines,
A total of 1024 that are selectively selected at the same time for each four sets
Each set includes complementary data lines. As a result, each memory array has substantially 262144, so-called 2
It has an address space of 56 kilobits, so that the pseudo-static RAM has a so-called 4-megabit storage capacity.

When the pseudo-static RAM is set to the selected state in the normal operation mode, the 16 memory arrays are so-called pair-selected substantially at a time, two at a time. A total of eight memory cells are selected from the two memory arrays that are simultaneously operated, that is, four, and connected to the corresponding common I / O line. These memory cells are further connected to a corresponding unit circuit of the data input buffer DIB or the data output buffer DOB via a corresponding write circuit or main amplifier.

A memory array pair is selected by the address signals A0 and A1, and an upper or lower array is selected by the address signal A10. This allows
Sixteen memory arrays are selected by one eighth, and two memory arrays are simultaneously activated. As described above, when the pseudo-static RAM is set to the self-refresh mode, the address signals A0 and A1 have no meaning.
The upper or lower array is simultaneously activated.

6-bit address signals A4 to A9
Are supplied to the X predecoder PXD, and are combined and decoded by two bits each. As a result, the corresponding predecodes AX450 to AX453 to AX8
90 to AX893 are alternatively set to the high level. These predecode signals are supplied to the X decoder, and are supplied for alternatively selecting a word line group of each memory array. 2-bit address signals A2 and A3
Is supplied to the word line selection drive signal generation circuit PWD,
By being combined with the word line drive signal φx output from the word line drive signal generation circuit φXG, the word line drive signal X00, X01, X10, and X11 are supplied to selectively form. As described above, the word line selection drive signals X00 to X11 are set to the boosted voltage VCH exceeding the power supply voltage of the circuit. As a result, one of the 256 word lines constituting the two memory arrays specified by the address signals A0 and A1 and A10 according to the address signals A2 to A9 of 8 bits.
The book is alternatively selected.

Similarly, address input terminals A11 to A18
8-bit address signals A11 to A input through
Reference numeral 18 denotes a Y address signal, which is supplied to a Y predecoder PYD for selecting a data line, and A11 and A1
2, A13 and A14, A15 and A16 and A1
7 and A18 are decoded by 2 bits each. As a result, the corresponding predecode signal A
Y120 to AY123, AY340 to AY343, AY
560 to AY563 and AY780 to AY783
Is alternatively set to a high level. These predecode signals are further combined by the decoder tree of the Y decoder, and as a result, a total of eight sets of complementary data lines are selected from the two memory arrays which are brought into the operating state, and a corresponding common I line is selected. / O line. As a result, eight memory cells are selected from so-called 4-megabit memory cells, and data input / output terminals IO0 to IO are selected.
The operation of inputting / outputting 8-bit storage data via the CPU 7 is performed.

FIG. 15 shows the pseudo static RA
FIG. 16 shows an overall layout diagram of one embodiment on an M semiconductor substrate, which is divided into circuit blocks 1 to 3 according to the size of the drawing, and the detailed layout diagram of each is shown in FIG. 18 to FIG. That is, FIGS.
FIG. 15 shows the relationship between the geometrical overall arrangements. The basic layout of one embodiment of the pseudo-static RAM of this embodiment will be described with reference to FIGS. 16 to 18, the left side of the semiconductor substrate in the drawings is referred to as the upper side of the semiconductor substrate surface.

As described above, the pseudo static RAM
Are eight (substantially sixteen) memory arrays MARY0L to MARY3 each of which is divided into an upper side and a lower side.
L and MARY0R to MARY3R, and an X address decoder X provided corresponding to these memory arrays.
D0L to XD3L and XD0R to XD3R and four Y address decoders YD0 to YD provided corresponding to the two memory arrays and divided into upper and lower sides, respectively.
D3.

At the center of the semiconductor substrate surface, X address decoders XD0L to XD3L and XD0R to XD3R are arranged.
D) and WD0RU to WD3RU (WD0RD to W
D3RD). And these X
Corresponding to memory array MA so as to sandwich the system selection circuit.
RY0L to MARY3L and MARY0R to MARY3
R is arranged in a so-called vertical manner so as to sandwich the corresponding Y decoders YD0 to YD3 and extend the word lines in the vertical direction. Although not shown, a corresponding sense amplifier S is provided in the vicinity of the Y address decoders YD0 to YD3.
A0L to SA3L and SA0R to SA3R and column switches CS0L to CS3L and CS0R to CS3R
Are respectively arranged.

Memory arrays MARY0L to MARY3L
A pre-Y address decoder PYD and a Y address redundancy control circuit YR are provided above MARY0R to MARY3R.
AC and the like are arranged. Below these memory arrays, main amplifiers MALL to MARR and write circuits DILL to DIRR are arranged.

Bonding pads are arranged on each side of the semiconductor substrate surface so as to avoid positions near each corner of the semiconductor substrate surface and positions near the center of the left and right sides. In addition, adjacent unit circuits of the X address buffer XAB and the Y address buffer YAB and the data input buffer DIB and the data output buffer DOB are arranged close to these pads.

FIG. 40 is a block diagram showing one embodiment of the refresh counter RFC according to the present invention. The refresh counter RFC has a logic circuit LO
G1, G2, G3, an oscillation circuit OC, a low temperature limiter circuit LC and a timer circuit TC. Detailed description of each operation of the oscillation circuit OC, the low temperature limiter circuit LC, and the timer circuit TC will be given later with reference to the drawings.

The logic circuit LOG1 includes inverter circuits INV1 and INV2, NAND circuits NAND1 to NAND3, and a NOR circuit NOR1. The inverter circuit INV1 is
An output signal OE0 of the input buffer OEIB is supplied.
The NAND circuit NAND1 is supplied with the inverted output signal CE0B of the input buffer CEIB and the output signal of the inverter circuit INV1. The AND circuits NAND2 and NAND3 take a flip-flop form, and the output signal of the NAND circuit NAND1 is supplied as one input of the NAND circuit NAND2,
An output signal of the NAND circuit NAND3 is supplied as the other input. The output signal of the NAND circuit NAND2 is supplied as one input of the NAND circuit NAND3, and the inverted signal CE0B of the input buffer CEIB is supplied as the other input.
Is supplied. The inverter circuit INV2 receives an output signal of the NAND circuit NAND2. The output signal of the inverter circuit INV1 is supplied as one input of the NOR circuit NOR1, and the output signal of the inverter circuit INV2 is supplied as the other input. The NOR circuit NOR1 receives the signal RF
Outputs 1.

The oscillation circuit OC is supplied with the signal RF1 from the logic circuit LOG1, and outputs a timing signal φ _SRF1 B. The logic circuit LOG2 includes an inverter circuit IN
V3 and an output signal φ _SRF1 from the oscillation circuit OC.
B is inverted and output to the low temperature limiter circuit LC and the logic circuit LOG3. Low temperature limiter circuit LC
The output signal RF1 of the logic circuit LOG1, the output signal φ _SRF1 of the logic circuit LOG2 and the timer circuit TC
Is supplied.

The timer circuit TC is supplied with the output signal LENB of the low temperature limiter circuit LC and outputs a signal LMT. The logic circuit LOG3 is an AND circuit AND
1, the output signal φ _SRF1 of the logic circuit LOG2 is supplied as one input of the AND circuit AND1,
The output signal LENB of the low temperature limiter circuit LC is supplied as the other input. And the AND circuit AND1
_Forms and outputs a signal φ _SRF2 .

FIG. 19 shows the pseudo static RA
A timing diagram of one embodiment for explaining the self-refresh operation of M is shown. In this embodiment, as described above, a total of eight word lines are simultaneously selected in one operation, and 8,192 memory cells are refreshed. Therefore, since the RAM has a storage capacity of about 4 Mbits as a whole, one round of self-refresh operation consists of 1 to 512 512 cycles. In this embodiment, a pulse formed by a temperature-compensated oscillating circuit as described below is independent of temperature changes, in other words,
The self-refresh operation of one turn is continuously performed by the self-refresh time T1 irrespective of the information holding characteristic of the memory cell. Then, a pause time T2 set by a timer circuit using a time constant circuit corresponding to the information holding characteristic of the memory cell as described later is provided.
Therefore, the substantial refresh period T of this embodiment is
Is determined by the time T1 + T2. After the elapse of the pause time T2, the next refresh cycle is started, and the self-refresh operation (T1) from the first cycle to the 512th cycle is started again. When the self-refresh operation ends, the pause time T2 is entered. Hereinafter, the self-refresh operation is performed by similar repetition. In the self-refresh mode, in a state where the chip enable signal CEB is fixed at a high level, the output enable signal OEB is fixed at a low level continuously for a predetermined time (t _FAS ) or more to distinguish it from the auto-refresh mode. It is started on condition.

FIG. 20 is a circuit diagram of an embodiment of the timer circuit TC for setting the pause time T2. In this embodiment, a dummy cell formed under the same conditions (same process) as the memory cell is used in order to obtain a time constant circuit corresponding to the information storage charge amount of the memory cell. However, in the dummy cell, unlike the memory cell, only the address selection MOSFET Qm is used as a time constant circuit. Although not particularly limited, 1000 memory cells
Of the dummy cells corresponding to the number of cells, M for address selection is used.
OSFETs Qm are connected in a parallel configuration. That is, the gate electrode corresponding to the word line is commonly connected to the ground potential point of the circuit, and the drain corresponding to the data line is connected to the plate voltage VPL. The source to which the information storage capacitor is connected has a separately provided capacitor Cs
Connect.

Although not particularly limited, the capacitor Cs has a capacitance value corresponding to a combined capacitance value of about 100 information storage capacitors. As described above, the number of address selection MOSFETs Qm is about 100 memory cells connected in parallel, whereas the capacitance value of the capacitor Cs is about one digit smaller than that of about 100 memory cells. The capacitance value of the information storage capacitor is set for the following reason.
Of the memory cells formed in the memory array MARY,
The information storage time of the worst case memory cell is about one order of magnitude worse than the information storage time of the average memory cell. About 10
Address selection MOS corresponding to 00 memory cells
When FETs Qm are connected in parallel, the sum of the leakage currents through the sources or the channels is averaged. For such a leakage current, about 1
By connecting a capacitor Cs of an order of magnitude smaller, a time constant circuit corresponding to the information holding characteristic of the worst case memory cell can be equivalently obtained.

Further, by connecting the address selection MOSFETs Qm corresponding to as many as 1000 memory cells in parallel as described above, an average leakage current of the address selection MOSFETs Qm can be formed with respect to process variations. Together with about 10
Since as many as 0 capacitors Cs are used, the capacitance value can be made large enough to ignore the input capacitance and the wiring capacitance of the voltage comparison circuit that monitors the voltage level. In this manner, a time constant circuit having a discharge time constant similar to the worst case memory cell formed in the memory array MARY can be obtained.

The precharge circuit for the capacitor Cs is not particularly limited, but its source and drain are not formed on a semiconductor substrate, but are formed on a polysilicon layer formed on a relatively thick field insulating film. Are used as a source and a drain. This is because, when the source and drain of the precharge MOSFET Q3 are constituted by diffusion layers, the leakage current affects the time constant set as described above.

The MOSFET Q3 is an N-channel MOSF
In the case of ET, the gate voltage is equal to the power supply voltage V
The boosted voltage VCH is used instead of CC. Thus, the power supply voltage VC formed by the inverter circuit N8
The capacitor Cs can be precharged by a high level such as C. If the inverter circuit N8 is set to a low level such as the ground potential of the circuit when the MOSFET Q3 is in the off state, the holding voltage of the capacitor Cs is applied between the source and the drain of the MOSFET Q3, thereby increasing the leakage current flowing between the channels. I do.
Therefore, in this embodiment, the plate voltage VPL is used as the low-level operation voltage of the inverter circuit N8.
Since the plate voltage VPL is set to VCC / 2, the leakage current between channels of the MOSFET Q3 can be reduced by 3 to 5 digits. As a result, a leak current in the precharge MOSFET can be substantially ignored, so that a highly accurate time constant can be obtained.

Control signal LENB is a precharge control signal. MOSFETs Q1 and Q3 receive inverter circuits N1 and N2 and their complementary output signals, and latch-type inverter circuits N3 and N4 operated by boosted voltage VCH. Constitutes a level conversion circuit, and converts the precharge control signal LENB at the VCC level to the boosted voltage VC
The signal is converted into a signal having a level corresponding to H. These converted signals are supplied as gate control signals for the precharge MOSFET Q3 through inverter circuits N5 and N6. Then, the output signal of the inverter circuit N6 is output as a precharge voltage through the inverter circuits N7 and N8.

The MOSFETs Q4 and Q5 are connected to a differential amplifier MO.
The gate of the MOSFET Q4 is supplied with the voltage VP of the time constant circuit, and the gate of the MOSFET Q5 is supplied with a plate voltage. In this example,
In order to reduce the power consumption of the comparator, the differential MO
Provided at the common source of SFETs Q4 and Q5,
An N-channel MOSFET QN that forms an operating current forms a small operating current. In order to operate this differential amplifier circuit only in the above-described self-refresh mode, the gate is supplied with a control voltage VNNT that causes a small current to flow through the MOSFET QN in the self-refresh mode. The above differential MOSFET
The drains of Q4 and Q5 have a current mirror P
Channel MOSFETs Q6 and Q7 are provided as loads.

As described above, the gain of the differential amplifier circuit is reduced to reduce power consumption. Therefore, the output signal of the differential amplifier circuit is amplified by the inverter circuits N10 to N12 arranged in cascade. In these inverter circuits N10 to N12 as well, the N-channel MOSFET QN as a constant current source as described above is provided with the inverter circuits N10 and N1 for level adjustment and low power consumption.
2 and a similar P-channel MOSFET QP is provided in the inverter circuits N11 and N12. And
The output signal of the inverter circuit N12 is
N-channel MOSFET Q9 and P-channel MOSFET constituting a CMOS output circuit via N13 and N14
It is transmitted to the gate of Q8. N-channel MOSFET
The inverter circuit N13 forming the drive signal of Q9 includes:
A constant current source MOSFET QP is provided on the power supply voltage VCC side, and a constant current source QN is provided in parallel on the ground potential side of the inverter circuit N14 which forms a drive signal for the P-channel MOSFET Q8.

The inverter circuits N10 to N1 as described above
N-channel MOS provided at 4 and constituting a constant current source
The gates of the FETs QN and QP have these MOSFETs QN and MOSFET in the self-refresh mode, in other words, when the timer circuit is operated.
Control voltages VNNT and VPPT for turning on the QP are supplied.

FIG. 21 shows a pattern diagram of one embodiment of the dummy cell used in the timer circuit TC. Although not particularly limited, in this embodiment, N dummy cells are arranged in the vertical direction of the drawing and M dummy cells are arranged in the horizontal direction.
× N dummy cells are arranged. The pattern of the memory cells formed in the memory array is such that word lines composed of diffusion layers (source and drain) and the first polysilicon layer 8 are arranged in a zigzag manner in order to arrange the memory cells with high density. However, in the timer circuit, at most 100
Since it is sufficient to form dummy cells of about 0, the dummy cells are formed by linear sources, drains (diffusion layers 4) and word lines as shown in FIG. MOSFET Qm for address selection
Is connected to the ground potential point of the circuit by the word line (first polysilicon layer) 8 connected to the gate of the first common polysilicon layer 8 provided on the right side.

The drain of the address selection MOSFET Qm is connected by a contact 13 to a first line indicated by a broken line in FIG.
It is commonly connected to the aluminum layer 11 of the layer. This aluminum layer 11 is connected to plate voltage VPL. The information storage capacitor of the dummy cell is formed in a region sandwiched between two word lines, one electrode of which is a second polysilicon layer 9 shown by a dashed line in FIG. It is composed of a polysilicon layer 10.
The capacitor of the memory cell formed in the memory array is
The second polysilicon layer 9 is formed of individual address selecting Ms.
Although formed short-circuited by the contact 12 on the source side of the OSFET Qm, in this embodiment, since a separately provided capacitor is used, the OSFET Qm is formed by one common electrode. Then, the second polysilicon layer 9 is formed.
Is short-circuited to the diffusion layer through the contact 12 on the lower side of FIG. Further, it is extracted to the aluminum layer 11 through the contact 13. This aluminum layer 1
1, the third polysilicon layer 10 is short-circuited by the contact layer CN, and the address selecting MOSFET
It is used as a common source electrode for TQm. The above-mentioned capacitor Cs separately provided is connected to such a source electrode side.

FIG. 22 shows a memory cell MC having an STC structure.
And N-channel MOSFET Q forming a CMOS circuit
An element structure sectional view of one embodiment of the N and P channel MOSFET QP is shown. In the memory cell, two memory cells are arranged symmetrically about the n ⁺ layer constituting the MOSFET Qm for address selection, and two MOs for address selection using the first polysilicon layer 8 as a word line.
The SFET Qm is formed. The second side polysilicon layer 9 constituting the information storage capacitor is connected to the source side. A word line (first polysilicon layer 8) of a memory cell adjacent to the memory cell runs in parallel on a thick field insulating film which divides an element formation region. The drain shared by the two address selection MOSFETs Qm is connected to a first aluminum layer 11 constituting a data line. Further, an N-channel MOSFET QN and a P-channel MOSFET QP constituting a CMOS circuit are
Although not particularly limited, the first-layer polysilicon is used as a gate electrode, and the drain output is shared by the first-layer aluminum layer 11.

In the dummy cell used in the timer circuit TC as described above, a short circuit between the second polysilicon layer 9 and the third polysilicon layer 10 or a dielectric film of a capacitor may be formed. Omitted so that no capacitor is formed. The first aluminum layer 11 is supplied with the plate voltage VPL to be applied to the third polysilicon layer 10, and the first polysilicon layer 8 serving as a word line is shared. In that the memory is connected to the ground potential point of the circuit, and the second and third polysilicon layers 9 and 10 forming the capacitor are used as wiring for sharing the source of the address selection MOSFET Qm. This is different from the cell MC.

In the timer circuit TC as described above, the MOSFET Qm for address selection has a capacity of about 1000
A leak current of the number is supplied. In this case, even if one or two leakage currents are one order of magnitude larger due to process variation, the leakage current is only a few percent increase from the viewpoint of the entire leakage current, so that the average leakage current is obtained. By setting the capacitance value of the capacitor Cs to about 100, a time constant corresponding to the worst-case memory cell can be obtained. Therefore, by comparing the voltage VP precharged to the capacitor Cs by the comparator, the information holding amount of the memory cell can be indirectly monitored. This makes it possible to set the refresh cycle T corresponding to the process variation and the temperature dependency of the worst case memory cell having a short information retention time among the actual memory cells.

FIG. 23 is a circuit diagram of an embodiment of the oscillation circuit OC for determining the self refresh time T1. Although the circuit symbols given to the respective circuit elements in the figure partially overlap those shown in FIG. 20, it should be understood that they are different from each other. This is the same in the following circuit diagrams.

The oscillating circuit OC of this embodiment uses a high resistance R to generate an operating current for low power consumption and temperature compensation. That is, the power supply voltage Vcc and the circuit ground potential Vss
P-channel MOSFET Q in diode form between
The N-channel MOSFET Q3 is connected in the form of a diode with a high resistance R and a diode as described above. Thus, a small constant current i can be caused to flow through the high resistance R. The N-channel MOSFET Q3 is provided with an N-channel MOSFET Q4 in the form of a current mirror, and the capacitor C is discharged by its drain current (mirror output current) i.

Here, it is assumed that MOSFETs Q3 and Q4 have the same size. The above capacitor C
Has a diode-type P-channel MOSFET Q5
And a charging path including a P-channel type switch MOSFET Q6. P-channel MOSFET Q8
Is provided between the connection point of P-channel MOSFETs Q5 and Q6 and the power supply voltage Vcc. This MOSFET
The gate of Q8 is supplied with the signal RF1 formed by the logic circuit LOG1 described with reference to FIG.
The holding voltage VC of the capacitor C is the MOSFET Q7
Is supplied to the gate. The drain of the MOSFET Q7 is connected to the P-channel MOSFET Q1 and a P-channel load MOSFET Q2 in the form of a current mirror.
Is provided. The drain output of the MOSFET Q7 is supplied to the gate of the P-channel MOSFET Q6 via the delay circuit DELAY and the inverter circuit N1. Although not particularly limited, the inverter circuit N1
Is a periodic pulse from the output terminal OUT (oscillation signal φ
_SRF1 B) is sent out.

In the circuit of this embodiment, except for a short time during which the MOSFET Q7 is turned off, only a current proportional to the minute constant current i formed by the high resistance R flows, resulting in extremely low power consumption and temperature dependency. No stable oscillation operation. Then, in order not to be affected by the fluctuation of the power supply or the large fluctuation of the ground potential, an element structure as shown in FIG. 24 is adopted. For example, the resistor R is formed from the first polysilicon layer 8 formed in the same step as the gate electrode G or the like of the MOSFET Q3. In order to reduce the resistance value of the resistor R, there is no particular limitation.
There is also a method in which an impurity for increasing conductivity is not introduced like the gate electrode G of ETQ3. This resistor R is formed on the field insulating film 7 having a large thickness.

On the surface of the semiconductor substrate under the field insulating film 7, an N-type well region 2 divided into two approximately at the center of the polysilicon layer constituting the resistor R is provided, although not particularly limited. Can be P channel M of the resistor R
The power supply voltage Vcc is supplied to the well region corresponding to the left half side connected to the OSFET Q1 via the n ⁺ type diffusion layer region 4 formed in the same process as the source S and the drain D such as the MOSFET Q3. In the well region corresponding to the right half side connected to the N-channel MOSFET Q3 side of the resistor R, an n ⁺ type diffusion layer region 4 formed by the same process as the source S and drain D of the MOSFET Q3
, The ground potential Vss of the circuit is supplied. Reference numeral 5 denotes a thin gate insulating film for forming a MOSFET.

In FIG. 23, the upper half of the resistor R forms a parasitic capacitance with the power supply voltage Vcc, and the lower half of the resistor R forms a parasitic capacitance with the ground potential Vss of the circuit. For this reason, for example, when a power supply fluctuation occurs and the power supply voltage Vcc drops sharply, the potential VPP of the resistor R on the P-channel MOSFET Q1 side drops sharply following the parasitic capacitance. Therefore, P-channel MOSFET Q
1 maintains the ON state. As a result, the oscillation circuit can continue the stable oscillation operation without being affected by the power supply fluctuation.

Even if the ground potential Vss suddenly increases for some reason, the N-channel MOSF
The potential VNN on the ETQ3 side also rises sharply following this. Therefore, N-channel MOSFET Q1 maintains the ON state. As a result, the oscillation circuit can continue the oscillation operation without receiving a sudden change in the ground potential. Thus, the oscillation circuit can perform a stable operation without being affected by the fluctuation of the power supply voltage or the fluctuation of the ground potential. Therefore, the time required for the refresh cycle can be set as the oscillation frequency without considering the power supply fluctuation, temperature change, and the like.

By the combination of such a stable oscillation circuit OC and the above-described timer circuit TC having temperature dependency, it is possible to perform a self-refresh operation at an optimum long cycle according to the ability of the memory cell. As a result, power consumption during standby can be significantly reduced. As a result, when a battery is backed up by a small battery as described above, the battery life can be extended.

FIG. 25 shows a low temperature limiter circuit LC.
The circuit diagram of one embodiment is shown. In the self-refresh system of the above embodiment, in the timer circuit TC as shown in FIG. 20, the timer time is extremely lengthened correspondingly at a low temperature. On the other hand, in the memory cell, the leak current of the address selection MOSFET Qm decreases in response to the temperature drop, but the leak current as a whole does not decrease so much due to other leak current paths.
For this reason, if the refresh cycle T is determined only by the timer circuit as described above, the temperature dependency of the timer circuit and the temperature dependency of the memory cell cannot correspond one-to-one, and the refresh cycle T becomes too long. There is a possibility that the information stored in the memory cell may be lost.

Therefore, a low temperature limiter circuit LC as shown in FIG. 25 is provided. The counter circuit is CT0-C
It consists of a 13-bit binary counter consisting of T12. An oscillation pulse φ _srf of an oscillation circuit for self refresh and a self refresh signal RF1 are supplied to this counter. The output signal CA8 of CT8 of the counter circuit is used to detect the end of the self-refresh time T1 consisting of 1 to 512 cycles. That is, CA8 goes high in the 256th cycle and is held in the flip-flop circuit FF1, and when CA8 goes low in the 513th cycle,
The flip-flop circuit FF2 is set, and the precharge signal LENB of the timer circuit TC is generated.
This precharge operation is performed until CA8 becomes high level again, and the timer circuit TC is substantially started.

In the normal operation, an output signal LTM is formed from the timer circuit TM, and a signal LLOAD for clearing the counter circuit is generated through the gate circuits G6 and G7, the inverter circuit N4 and the delay stage D, and the self-refresh operation is performed. enter. At low temperatures, the output signal LTM from the timer circuit TC is greatly delayed. If the output signal CA12 of the final stage CT12 is set to a high level before that, the gate circuits G5 and G7 and the inverter circuit N4
In addition, a signal LLOAD for clearing the counter circuit is generated through the delay stage D. Thus, at a low temperature, the upper limit cycle of the refresh cycle T is determined by the low temperature limiter, so that the refresh can be performed before the information of the memory cell is lost.

FIG. 26 is a circuit diagram showing one embodiment of the variable booster circuit according to the present invention. PS like above
In RAM, about 1.
It may be operated by a low battery voltage VCC of about 5V. At this time, the double booster circuit uses 2 VCC-
2Vth (where Vth is the threshold voltage of MOSFET)
And the condition of 2VCC-2Vth ≧ VCC + Vth cannot be satisfied. That is, the power supply voltage VCC is set to 1.5 V, and the threshold voltage V
Assuming that th is 0.6 V, the boosted voltage is 3-1.2 = 1.8.
V and the required boosted voltage becomes 1.5 + 0.6 = 2.1 V or less. Therefore, in this embodiment, the power supply voltage VC
C or the boost voltage VCH is detected by a sensor circuit, and 2
Switching between double boosting and triple boosting is performed.

The pulse generator CKG (or the oscillator OS)
The periodic pulse CK generated by C) forms an approximately double boosted voltage by the capacitor C1 and the diode-type MOSFET Q1. That is, the pulse C
When K is at the low level, the capacitor C1 is charged up from the power supply voltage VCC via the diode-type MOSFET Q1. Next, a boosted voltage of 2VCC + Vth is output from the output side of the capacitor C1 in which the pulse CK is changed from a low level to a high level (VCC). This boosted voltage 2VCC + Vth is a diode-type MOS
The signal is transmitted to the boost output terminal VCH via the FET Q2.
A voltage holding capacitor (not shown) is provided between the boosted output terminal VCH and the ground potential point of the circuit, and the boosted voltage VCH is set at 2VCC-2Vth as described above.

The pulse output and the sensor output A are supplied to an exclusive OR circuit EX. This exclusive OR circuit E
On the output side of X, a double boosting circuit including a capacitor C2 similar to the above and MOSFETs Q4 and Q5 in the form of diodes is provided. A diode-type MOSFET Q3 is provided between the two boosting circuits. That is,
The output voltage of the capacitor C1 is transmitted to the output electrode of the capacitor C2 via the MOSFET Q3 in the form of a diode.

The sensor output A is set to logic "0" when the power supply voltage VCC or the boosted voltage is relatively high. As a result, when the pulse CK is at the low level logic "0", a low level coincidence signal is output, and when the pulse CK is at the high level logic "1", a high level mismatch signal is output. In this manner, when the sensor output A is logic "0", a pulse in phase with the input pulse CK is output from the output side of the exclusive OR circuit EX. Therefore, the two double boosting circuits operate in the same manner to form the double boosted voltage 2VCC-2Vth as described above. At this time, the diode-type MOSFET Q3 is in the off state because the cathode side and the anode side are always at the same potential.

The sensor circuit detects that the power supply voltage VCC or the boosted voltage drops to the low voltage as described above, and changes the output signal from logic “0” to logic “1”. As a result, when the pulse CK is at the low-level logic "0", a high-level mismatch signal is output, and when the pulse CK is at the high-level logic "1", a low-level mismatch signal is output. When the sensor output A changes to logic "1", a pulse having a phase opposite to that of the input pulse CK is output from the output side of the exclusive OR circuit EX. Therefore, the pulse CK goes high and the capacitor C1
To output a double boosted voltage from the capacitor C
2 is charged up through a diode-type MOSFET Q3. When the pulse CK is set to the low level, the capacitor C1 is precharged in the same manner as described above, and a triple boosted voltage such as 3VCC-2Vth is formed from the capacitor C2 driven by the opposite-phase pulse. , To the output terminal VCH via the diode-type MOSFET Q5. In this way,
In the variable booster circuit of this embodiment, the boosted voltage VCH can be finally raised to 3VCC-3Vth.

For example, as described above, the power supply voltage VCC is set to 1.5 V, and the threshold voltage Vth of the MOSFET is set to 0.
When the voltage is 6 V, the boosted voltage can be increased to 4.5-1.8 = 2.7 V. The required boost voltage is
Since 1.5 + 0.6 = 2.1 V under the above conditions, it is necessary to provide a diode-type clamping MOSFET between the power supply voltage VCC and the boosted output VCH to increase the boosted voltage more than necessary. It may be prevented.

FIG. 27 is a block diagram showing another embodiment of the variable booster circuit. In this embodiment, N circuits are prepared from a single boost circuit (double boost circuit), a double boost circuit (triple boost circuit) to N boost circuits (N + 1-fold boost circuit) in order. The sensor outputs A1 to AN formed by the sensor circuits operate the necessary one of the N booster circuits corresponding to the power supply voltage VCC and the boosted voltage at that time to operate the boosted voltage V
CH is obtained.

The sensor circuit compares the absolute value of VCC or VCH with a predetermined reference voltage to form the sensor outputs A, A1 to AN as described above, and the relative value of the power supply voltage VCC and the boosted voltage VCH. The output signal may be formed such that the difference voltage becomes a desired voltage by inputting such a voltage difference.

FIG. 28 is a circuit diagram showing one embodiment of the substrate voltage generating circuit according to the present invention. In the PSRAM as in the above embodiment, the power supply voltage VCC during normal operation is set to a relatively high voltage of about 5 V or 3.5 V, and is set to a low voltage such as 1.5 V during battery backup. . In this case, the operating voltage of the PSRAM is
1.5V suddenly from a high voltage such as 5V or 3.5V
To be lowered. It is necessary to change the substrate bias voltage in accordance with such a power supply voltage change. This is because if the substrate voltage is kept at a relatively deep bias voltage formed under a high power supply voltage, the threshold voltage of the MOSFET is kept at a relatively high potential due to the substrate effect. Therefore, when only the operating voltage is set to the low voltage as described above, the MOSFET becomes inoperable, and the refresh operation may not be performed.

Therefore, it is conceivable to form a leakage current path between the substrate and the ground potential point of the circuit to change the substrate bias voltage in accordance with the change in the power supply voltage. In order to increase the response to the change, it is necessary to always supply a relatively large current value of the leak current, and the current consumption increases, and it is necessary to form a substrate voltage generating circuit having a large current supply capability. Therefore, it is necessary to use an element having a large size, and the circuit scale is correspondingly increased.

The substrate voltage generating circuit of this embodiment can change the substrate potential at high speed in response to a change in the power supply voltage without increasing the current consumption or the circuit scale. In this embodiment, a control voltage generation circuit VBBC that forms a control voltage VC (VBB ′) that changes following the power supply voltage VCC is newly added. That is, the control voltage generation circuit VBBC has basically the same circuit configuration as the substrate voltage generation circuit VBBG as described later, but has a small current supply capability because it forms only the control voltage VC. Although the number of elements is almost the same as that of the substrate voltage generation circuit VBBG, the circuit size (occupied area) is substantially small since the elements are formed of small-sized elements.

The inverted pulse formed by the oscillation circuit OSC is transmitted to one electrode of the capacitor CB1 via the inverter circuit N1. A diode type MO is connected between the other electrode of the capacitor CB1 and the ground potential point of the circuit.
An SFET Q1 is provided. A resistor R and a P-channel MOSFET Q2 having a relatively large resistance value for flowing a leakage current with respect to the power supply voltage VCC are connected in series to form the capacitor CB1 and a diode-type MOSFET Q1.
Is connected to the connection point. The inversion pulse of the oscillation circuit OSC is supplied to the gate of the MOSFET Q2.
The negative voltage formed by the capacitor CB1 is applied to a capacitor C2 (or a substrate voltage control MOSFET) for forming a control voltage VC via a diode-type MOSFET Q3.
(Gate capacitance of Q8).

The capacitor CB2 and the diode-type MOSFET also respond to the non-inversion pulse of the oscillation circuit OSC.
Q4, Q6 and high resistance R and P constituting a leakage current path
A channel MOSFET Q5 is provided. A switch MOSFET Q7 using a negative voltage formed by the inversion pulse as a control voltage is a diode type MOSFET.
It is provided in parallel with ETQ6. That is, when the control voltage VC decreases to a predetermined potential, the negative voltage formed by the capacitor CB2 becomes
The signal is output without level loss by the switch MOSFET Q7 instead of the ETQ6.

In a circuit in which a negative voltage is formed by a MOSFET Q3 in the form of a diode, such as a negative voltage generating circuit corresponding to an inversion pulse, the control voltage VC is-(VCC-2Vt).
h). On the other hand, MOSFET
When Q7 is used, the capacitor CB2 is connected to-(VCC
When a negative voltage such as -Vth) is formed, a precharge operation is performed on the capacitor CB1, and the voltage is +
Since the potential is set to a positive potential such as Vth, the MOSFET Q7 is turned on to transmit the negative voltage − (VCC−Vth) to the capacitor C2 without level loss. Therefore, a circuit for forming a negative voltage from the inversion pulse basically forms a control voltage for the switch MOSFET Q7,
The diode type MOSFET Q3 may be omitted.

In order to perform the negative voltage generation operation by the switch control as described above, the oscillation outputs formed by the oscillation circuit OSC are simply phases opposite to each other and are non-overlapping pulses as shown in FIG. You. That is, the non-inverting pulse OSC changes from the low level to the high level after a certain period of time as shown by the dotted line after the inverted output OSCB changes from the high level to the low level. Similarly, the inversion pulse OSCB changes from the low level to the high level at a certain time after the non-inversion output OSC changes from the high level to the low level.

Referring to FIG. 28, substrate voltage generating circuit VBB
G is configured by a circuit similar to the above. However, the above-described leak current circuit R and the corresponding P-channel MOSFET are omitted. In this embodiment, the substrate voltage generation circuit VBBG2 and the control voltage generation circuit VBB
The common oscillator circuit OSC may be used. Oscillation circuit OS included in reference voltage generation circuit VBBG1
C operates according to the control signal CE1B supplied from the timing generation circuit TG. Capacitor C1 is a parasitic capacitance between the substrate and the ground potential of the circuit. The reference voltage generation circuit VBBG2 is different from the substrate voltage generation circuit VBBG1 in that the control signal CE1B is not supplied to the oscillation circuit OSC, but the other circuit configuration is the same as the substrate voltage generation circuit VBBG1.
Same as BG1.

One substrate voltage generating circuit VBBG2 is a circuit which operates steadily and has only a small current supply capability to compensate for a leak current constantly generated between the substrate and the ground potential point of the circuit. . When the memory access (read / write or refresh) operation is performed on the PSRAM, the other substrate voltage generation circuit VBBG1 is started automatically or by the monitor output of the substrate voltage VBB, and receives a relatively large current. It is designed to have a supply capacity. The circuit which is operated intermittently in this manner is, for example, as shown in the figure, in which two inverter circuits which respectively receive inverted and non-inverted oscillation pulses are replaced with NAND (NAND) or NOR (NOR) gate circuits. What is necessary is just to control by an operation control signal.

The substrate voltage VBB formed by such substrate voltage generation circuits VBBG1 and VBBG2 can be supplied to the power supply voltage VC without providing a steady-state leak current circuit.
With respect to the above-described decrease of C, the voltage is rapidly pulled out according to the control voltage VC (VBB ') supplied to the gate of the MOSFET Q8.

As shown in FIG. 30, when the power supply voltage VCC is switched from a relatively high level as in the normal operation to a low battery backup voltage, the P-channel MOSFET Q5 Is in the ON state, the precharge voltage at the large voltage stored in the capacitor CB2 is leaked through the resistor R. At this time, since the MOSFET Q7 is turned on, the control voltage VC (VBB ') is extracted by charge sharing between the capacitors CB2 and C2.

As described above, the control voltage VC is changed to the power supply voltage VCC.
When it changes with the decrease of
When the gate voltage of Q8 rises and the difference voltage from the substrate voltage VBB becomes greater than the threshold voltage Vth of MOSFET Q8, MOSFET Q8 is turned on and the substrate voltage V
BB is pulled out. Thus, the substrate voltage VB
Without providing a direct leakage path for B, the substrate voltage VBB also decreases at high speed in response to the change in the control voltage VC. As a result, the self-refresh operation in the battery backup and the timer operation as described above are effectively operated.

Since the above-described leak resistance R is for extracting the excess charge of the capacitors CB1 and CB2 having a small capacitance value only for forming the control voltage VC, the current value is small. It does not increase the current. When the low-level period of the oscillation pulse is sufficiently large with respect to the time constant of the resistor R and the capacitor CB2, the extraction speed becomes equal to that of the capacitor C
Since it is determined only by the charge share of B2 and the capacitor C2, it is easy to control the leak speed.

FIG. 31 is a block diagram showing another embodiment of the substrate voltage generating circuit. The control voltage generation circuit VBBC of this embodiment includes a capacitor CB1, a diode-type MOSFET Q1, Q3, and a leakage current resistor R provided in parallel with a capacitor C2 holding the control voltage VC. Control voltage generation circuit VB
The BC capacitor C2 has only a small capacitance value such as the gate capacitance of the MOSFET Q8 for discharging the substrate voltage VBB. Therefore, an inverter circuit N1, a capacitor CB1, and a MOSFET for forming a negative voltage
Q1 and Q2 are composed of relatively small-sized elements,
Since the capacitance value of the capacitor C2 is small, it is possible to form the control voltage VC that follows the fluctuation of the power supply voltage VCC with a small current consumption. Since the MOSFET Q8 flows a discharge current between the substrate and the ground potential point of the circuit in accordance with the voltage difference between the voltage VC and the substrate voltage VBB, a change in the control voltage VC, that is, Thus, the substrate voltage VBB can be changed indirectly by following the fluctuation of the power supply voltage VCC.

The substrate voltage generation circuit VBBG is an inverter circuit like the control voltage generation circuit VBBC of FIG.
It may be composed of two MOSFETs in the form of a capacitor and a diode, or may use a circuit as shown in FIG.

FIG. 32 shows the pseudo static RA
A timing diagram of one embodiment of an M read cycle is shown. In the pseudo-static RAM of this embodiment, a read cycle is performed on condition that the write enable signal WEB is at a high level at the falling edge of the chip enable signal CEB. The output enable signal OEB is temporarily set to the low level at a predetermined timing that does not delay the output operation of the read data. An 11-bit X address signal and an 8-bit Y address signal are supplied to the address input terminals A0 to A10 and A11 to A18 in synchronization with the falling edge of the chip enable signal CEB. In the figure, one of these address signals is exemplarily shown as a representative.
The data input / output terminals IO0 to IO7 are normally set to a high impedance state, and when a predetermined access time has elapsed, 8-bit read data output from eight memory cells which are simultaneously selected is transmitted. .

FIG. 33 shows the pseudo static RA
A timing diagram of one embodiment of the M write cycle is shown. In the pseudo-static RAM, at the falling edge of the chip enable signal CEB, the write enable signal WEB is set to a low level prior to the chip enable signal CEB, or temporarily set to a low level at a predetermined timing later than the chip enable signal CEB. On the condition that the write cycle is performed, a write cycle is performed. X is applied to the address input terminals A0 to A10 and A11 to A18.
And the Y address signal are input, and the data input / output terminal IO
8-bit write data is supplied to 0 to IO7 at a predetermined timing that does not delay the write operation.

FIG. 34 shows the pseudo static RA
A timing diagram for one embodiment of an M read-modify-write cycle is shown. This operation cycle is
In other words, the operation cycle is a combination of the read cycle and the write cycle, and includes a chip enable signal CE.
Output enable signal OE at the falling edge of B
Since B and the write enable signal WEB are at a high level, a read cycle is first started. Then, the read data at the specified address is transferred to the data input / output terminal IO.
0 to IO7, then the write enable signal WE
When B is temporarily set to the low level, 8-bit write data supplied from the data input / output terminals IO0 to IO7 is written to the address.

FIG. 35 shows the pseudo static RA
A timing diagram for one embodiment of an M auto-refresh cycle is shown. In the pseudo-static RAM, the condition that the output enable signal OEB (refresh control signal RFSHB) is temporarily set to the low level for a relatively short time (t _FAP ) while the chip enable signal CEB is fixed to the high level is provided. Then, an auto refresh cycle is executed. At this time, a refresh address for designating a word line to be refreshed is supplied from a refresh counter RFC incorporated in the pseudo static RAM.

In the pseudo static RAM of this embodiment, unlike the self-refresh operation described above, a total of two word lines specified by the refresh counter RFC are simultaneously selected, and a corresponding total of 20 word lines are selected.
Refresh operations are performed simultaneously on the 48 memory cells. The refresh counter RFC is automatically updated at a point in time after the output signal, that is, the refresh address is taken into the X address buffer.

The representative ones of the access times shown in the timing charts of FIGS. 32 to 35 are as follows. t _RC is a random read / write cycle time, t _CEA is a chip enable access time, t _RWC is a read-modify-write cycle time, t _OEA is an output enable access time, and t _AH is an address. Hold time, t _AS is an address setup time, t _P is a chip enable precharge time, and t _FC is an auto refresh cycle time.

Pseudo-static RAM of this embodiment
Is guaranteed to operate in a voltage range of about 5 V or 3.6 V to 1.5 V as described above. For example, when the maximum value is 3.6 V, the voltage variation width is about 2 V, which is small in absolute value. However, from the viewpoint of the minimum operation voltage of 1.5 V, the maximum operation voltage of 3.6 V is about twice or more of that. The voltage becomes relatively large as shown in FIG. Under such a relatively large voltage range, the operating speed and the fluctuation range of the current consumption become relatively large. Then, since it is possible to operate at a plurality of types of battery voltages having different generated voltages as described above, AC characteristics such as access time and DC characteristics such as current consumption are respectively determined at a plurality of operating voltages according to the following. [Table 2]
And [Table 3].

[0117]

[Table 2]

[0118]

[Table 3]

The above Table 2 shows that the minimum voltage (1.6
V) min, a central voltage (2.6 V) type and a maximum voltage (3.6 V) max are shown. In this [Table 2], the unit is ns (nanosecond). In [Table 3] above,
Minimum voltage (1.6 V) min, center voltage (2.6 V) t
An example of a typical plurality of DC characteristics at yp and maximum voltage (3.6 V) max is shown. Where I
_CC1 is the current consumption at the time of memory access, and _ICC3 is the current consumption in the self-refresh mode.

The above minimum voltage of 1.6 V is based on the case where a lead battery is mainly used, the center voltage of 2.6 V is on the assumption that a nickel-cadmium battery and a lithium battery are used, and the maximum voltage is 3.6.
V assumes that a lithium battery is used.
By determining the AC and DC characteristics for each of the different battery voltages in this way, the convenience for the user is improved.
That is, if the worst-case AC characteristics and DC characteristics are determined as in the related art, a user who uses a nickel-cadmium battery or a lithium battery is forced to use a PSRAM with a performance lower than that of the PSRAM. As described above, in a CMOS integrated circuit which is intended to be used in which the relative voltage fluctuation width is large, the fluctuations in speed and current consumption due to the operating voltage are large, so that the AC and DC characteristics correspond to each power supply voltage. Thus, the user can construct an extremely rational system utilizing the performance of the CMOS integrated circuit. In particular,
When the battery voltage is used as the operating voltage as in this embodiment, since the battery capacity is limited, the DC characteristics as described above are displayed for each voltage, so that the user can consider the battery life and design the system. Therefore, the system does not stop due to unexpected battery discharge or the like.

When the operation of the CMOS circuit is performed in a relatively large voltage range with a relatively small voltage as described above, the conductance characteristics of the MOSFET vary relatively largely with the operating voltage. Therefore, if a CMOS inverter circuit is used as a delay circuit as in a conventional CMOS circuit, the voltage dependence of the delay time is large, and stable timing operation cannot be expected.

FIG. 36 is a circuit diagram showing one embodiment of a delay circuit suitable for a CMOS integrated circuit according to the present invention. In this embodiment, in order to eliminate the voltage dependence of the delay time, a delay circuit is configured using a time constant circuit including a resistor R1 made of a polysilicon layer and a MOS capacitor C1. FIG. 1 shows an example of a delay circuit that forms an output signal D that rises with a delay of time TD when the input signal A rises from a low level to a high level.

The input signal A is supplied to the CMOS inverter circuit N
1 is input to a time constant circuit composed of the resistor R1 and the capacitor C1. The delay signal B formed by the time constant circuits R1 and C1 is supplied to the CMOS inverter circuit N2
And transmitted to a time constant circuit composed of a similar resistor R2 and capacitor C2. Then, the delay signal C formed by the time constant circuits R2 and C2 is supplied to one input of the NAND gate circuit G1. The input signal A is supplied to the other input of the NAND gate circuit G1. The output signal of the NAND gate circuit G1 is output as a delay signal D through a CMOS inverter circuit N3 for output.

Although not particularly limited, the capacitor C1
Is connected to the ground potential point of the circuit by connecting the source and the drain of the N-channel MOSFET in common, and the capacitor C2
Is a circuit in which the source and the drain of the P-channel MOSFET are commonly connected and connected to the power supply voltage Vcc.

FIG. 37 is a waveform chart for explaining an example of the operation of the delay circuit. When the input signal A changes from the low level to the high level, the output signal of the inverter circuit N1 changes from the high level to the low level accordingly, and the signal B changes from the high level to the low level according to the time constant of the resistor R1 and the capacitor C1. . The output signal of the inverter circuit N2 which receives the change of the signal B changes from the low level to the high level, and the signal C changes from the low level to the high level according to the time constant of the resistor R2 and the capacitor C2.

The NAND gate G1 is connected to the input signal A
Is opened at a high level (logic "1"), and operates substantially as an inverter circuit. Therefore, when the level of the signal C changes from the low level to the high level and reaches the logic threshold voltage, the output signal changes from the high level to the low level. Thus, the delay signal D output through the inverter circuit N3 is equal to the time constant circuit R1,
It rises from a low level to a high level with a delay time TD corresponding to the time constants of C1, R2 and C2. In addition,
The inverter circuits N1 to N3 and the gate circuit G1 also have a signal propagation delay time. However, since the delay time TD is smaller than the above time constant, the delay time TD is almost the same as that of the time constant circuits R1, C1 and R2, C2. It is no exaggeration to say that it is determined by a constant.

When the input signal A changes from the high level to the low level, the output signal of the NAND gate circuit G1 changes to the high level accordingly. That is, even if the level of the signal C is still at the high level, the output signal is changed to the high level regardless of the level. As a result, the output signal D passing through the inverter circuit N3 immediately changes to the low level. Therefore, the delay circuit of this embodiment forms the output signal D delayed by the delay time TD with respect to only the rise of the input signal A as described above.

FIG. 38 shows the resistance R1 and the capacitor C
1 is a cross-sectional view of an element structure according to one embodiment. On the surface of the element formation region of the P ⁻ type semiconductor substrate 1, n is formed by the same manufacturing process as that for forming a normal N-channel MOSFET.
Source / drain regions SD of the ⁺ type diffusion layer are formed.
A thick field insulating film 7 is formed on the semiconductor substrate other than the element formation region. The above pair of sauces,
A thin gate insulating film 5 is formed in an element formation region including the substrate surface sandwiched between the drain regions SD. Then, a first polysilicon layer 8 is formed on the field insulating film 7 and the gate insulating film 5. Semiconductor impurities are introduced from the surface of the first polysilicon layer 8 into portions constituting the gate electrode, the resistor R1, etc. of the MOSFET, and the gate electrode G, the resistor R1, and the conductivity of the first layer used as a wiring layer. A conductive polysilicon layer 8 is formed.

An ohmic contact from which the gate oxide film and the polysilicon layer on the source and drain regions are selectively removed is provided, and an aluminum layer 1 for applying a ground potential is provided there. The resistor R1 and the gate electrode G acting as one electrode of the capacitor C1 are formed integrally, and the delay signal C formed by the gate electrode G is connected to an N-channel MOSFET and a P-channel MOSFET which constitute an inverter circuit N2 (not shown). As the wiring connected to the gate electrode of the channel MOSFET, an aluminum wiring formed by the same process as the aluminum wiring 11 for applying the ground potential to the capacitor C1 is used.

FIG. 39 is a characteristic diagram of the delay time of the delay circuit according to the present invention and the delay circuit using the conventional inverter circuit. In the figure, the solid line shows the delay characteristics of the delay circuit according to the present invention, and the broken line shows the delay characteristics of the delay circuit using the conventional inverter circuit.

The delay circuit of this embodiment utilizes a polysilicon resistance element having no power supply dependency and a MOS capacitor. As a result, 1 V is mainly attributable to the power supply dependency of the rarely inserted inverter circuit such as waveform shaping.
Although the voltage dependency is large in the following low voltage region, a substantially constant delay time can be obtained at a voltage higher than the minimum voltage of about 1.6 V which is to be guaranteed in the pseudo static RAM of this embodiment. On the other hand, when an inverter circuit is used as in the related art, the delay time rapidly increases from a voltage of 4.5 V or less, which is not guaranteed in the conventional RAM, and a stable delay time cannot be obtained. Therefore,
In a CMOS circuit that guarantees an operation voltage having a relatively large relative voltage range at a low voltage like the pseudo-static RAM according to the present invention, in order to perform a stable timing operation, the CMOS circuit shown in the above embodiment is used. It is no exaggeration to say that such a delay circuit using a polysilicon resistor and a MOS capacitor is indispensable.

The operation and effect obtained from the above embodiment are as follows. That is, (1) RAM 1 using a dynamic memory cell
A peripheral self-refresh operation is performed based on a periodic pulse formed by an oscillating circuit that has substantially no temperature dependency, and a time constant corresponding to the temperature dependency of information retention in the memory cell. By controlling the self-refresh cycle by a timer circuit using a circuit, a self-refresh operation in a long cycle suitable for the information storage amount of the memory cell can be performed, thereby reducing power consumption. The effect is obtained. (2) MO for address selection of a plurality of dummy cells
By connecting a capacitor about one digit lower than the SFET to form a time constant circuit, a time constant circuit equivalent to the worst-case information holding characteristic of the memory cells with high accuracy and one-to-one is obtained. The effect that it can be obtained is obtained.

(3) A differential amplifier circuit operated by a small current and a cascaded inverter circuit for amplifying the amplified output are used as a comparator for monitoring the holding voltage of the capacitor constituting the time constant circuit. As a result, it is possible to perform an accurate voltage monitor with low power consumption. (4) The oscillation circuit for self-refresh is operated steadily in the self-refresh mode, and the oscillation pulse is counted by the counter circuit to set the upper limit of the refresh cycle. The effect that the information holding operation can be compensated can be obtained.

(5) C backed up by battery
By using a pseudo-static RAM having an input / output interface compatible with the static RAM as the MOS-structured RAM, the refresh operation is simplified, and the memory access can be made similar to that of the static RAM. The effect that the device can be obtained is obtained. (6) LVC specified by JEDEC STANDARD No.8 as a technical standard for the low voltage CMOS circuit
MOS and LVBO and C of 74HC or AC series
By using the MOS logic IC, it is possible to obtain an effect that compatibility with an existing IC can be obtained.

(7) By incorporating a variable booster circuit that can be switched in response to a voltage change, an effect is obtained that a semiconductor integrated circuit device having a wide operating voltage range can be obtained. (8) In the substrate voltage generation circuit, a MOSFET controlled by a control voltage formed by a control voltage generation circuit having a leakage current path is provided between the substrate and the ground potential point of the circuit, thereby reducing current consumption. The effect is obtained that the substrate potential can be changed according to the fluctuation of the power supply voltage without increasing.

The invention made by the present inventor has been specifically described based on the embodiment. However, the invention of the present application is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the pseudo static RAM shown in FIGS.
The input / output interface may simply be compatible with the static RAM. That is, it is sufficient that at least the address signal and the control signal have the same configuration as that of the static RAM. In addition to the pseudo static RAM, the dynamic RAM may be operated by a plurality of types of battery voltages as in the above-described embodiment. The dynamic RAM has the self-refresh function as described above. It may be added. The variable booster circuit and the substrate voltage generation circuit can be widely used for various semiconductor integrated circuit devices requiring a boosted voltage and a substrate voltage, in addition to a dynamic RAM and a pseudo static RAM.

[0137]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. In other words, the self-refresh operation around the RAM using the dynamic memory cell is performed based on a periodic pulse formed by an oscillation circuit that has substantially no temperature dependency,
The self-refresh cycle is controlled by a timer circuit using a time constant circuit corresponding to the temperature dependency of information retention in the memory cell, so that self-refresh in a long cycle suitable for the information storage amount of the memory cell is performed. Since the refresh operation can be performed, low power consumption can be achieved. MOSF for address selection of a plurality of dummy cells
By connecting a capacitor approximately one digit lower than ET to form a time constant circuit, it is possible to obtain a time constant circuit equivalent to the worst-case information holding characteristic of the memory cells one-to-one with high accuracy. be able to. By incorporating a variable booster circuit that can be switched in response to a voltage change, a semiconductor integrated circuit device having a wide operating voltage range can be obtained. M is controlled by a control voltage generated by a control voltage generation circuit having a leakage current path.
By providing the OSFET between the substrate and the ground potential point of the circuit, the substrate potential can be changed in response to a change in the power supply voltage without increasing current consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a computer system using a memory device including a semiconductor memory RAM to which the present invention is applied.

FIG. 2 is an overall layout diagram showing one embodiment of a selection circuit, a timing generation circuit, and a voltage generation circuit of a pseudo static RAM used in the memory card MEC and the like.

FIG. 3 is a specific circuit diagram of an embodiment corresponding to the circuit block 1 of FIG. 2;

FIG. 4 is a specific circuit diagram of one embodiment corresponding to the circuit block 2 of FIG. 2;

FIG. 5 is a specific circuit diagram of one embodiment corresponding to the circuit block 3 of FIG. 2;

FIG. 6 is a specific circuit diagram of one embodiment corresponding to the circuit block 4 of FIG. 2;

FIG. 7 is an overall layout diagram showing an embodiment of the memory array of the pseudo static RAM.

FIG. 8 is a block diagram of one embodiment corresponding to the circuit block 1 of FIG. 7;

FIG. 9 is a block diagram of an embodiment corresponding to the circuit block 2 of FIG. 7;

FIG. 10 is a block diagram of one embodiment corresponding to the circuit block 3 of FIG. 7;

FIG. 11 is a block diagram of one embodiment corresponding to the circuit block 4 of FIG. 7;

FIG. 12 is an overall layout diagram showing one embodiment of a direct peripheral circuit and a data input / output circuit of the pseudo static RAM.

FIG. 13 is a circuit diagram of an embodiment corresponding to the circuit block 1 of FIG.

FIG. 14 is a circuit diagram of one embodiment corresponding to the circuit block 2 of FIG.

FIG. 15 is an overall layout diagram showing one embodiment of the pseudo static RAM on the semiconductor substrate surface.

FIG. 16 is a layout diagram of one embodiment corresponding to the circuit block 1 of FIG. 15;

FIG. 17 is a layout diagram of one embodiment corresponding to the circuit block 2 of FIG. 15;

FIG. 18 is a layout diagram of one embodiment corresponding to the circuit block 3 of FIG. 15;

FIG. 19 is a timing chart for explaining a self-refresh operation in the pseudo static RAM according to the present invention.

FIG. 20 is a circuit diagram showing one embodiment of a timer circuit used for a self-refresh operation according to the present invention.

FIG. 21 is a pattern diagram showing one embodiment of a dummy cell used in the timer circuit of FIG. 20;

FIG. 22 is a sectional view of an element structure showing an embodiment of a memory cell having a STC structure and a MOSFET constituting a CMOS circuit.

FIG. 23 is a circuit diagram showing one embodiment of an oscillation circuit for setting the self-refresh time.

24 is a sectional view of an element structure showing one embodiment of a main element used in the oscillation circuit of FIG. 23;

FIG. 25 is a circuit diagram showing one embodiment of a low temperature limiter circuit used for a self-refresh operation according to the present invention.

FIG. 26 is a circuit diagram showing one embodiment of a variable booster circuit according to the present invention.

FIG. 27 is a block diagram showing another embodiment of the variable booster circuit according to the present invention.

FIG. 28 is a circuit diagram showing one embodiment of a substrate voltage generating circuit according to the present invention.

FIG. 29 is a waveform diagram illustrating an example of an oscillation pulse used in the substrate voltage generation circuit of FIG. 28.

FIG. 30 is a characteristic diagram for explaining the operation of the substrate voltage generation circuit according to the present invention.

FIG. 31 is a circuit diagram showing another embodiment of the substrate voltage generating circuit according to the present invention.

FIG. 32 is a timing chart showing an example of a read cycle of the pseudo static RAM.

FIG. 33 is a timing chart showing an example of a write cycle of the pseudo static RAM.

FIG. 34 is a timing chart showing an example of a read-modify-write cycle of the pseudo static RAM.

FIG. 35 is a timing chart showing an example of an auto-refresh cycle of the pseudo static RAM.

FIG. 36 is a circuit diagram showing one embodiment of a delay circuit according to the present invention.

FIG. 37 is a waveform chart for describing an example of the operation of the delay circuit of FIG. 36.

FIG. 38 is a sectional view of an element structure showing one embodiment of a resistor and a capacitor used in the delay circuit of FIG. 36;

FIG. 39 is a characteristic diagram showing voltage dependence of a delay circuit according to the present invention and a delay circuit using a conventional inverter circuit.

FIG. 40 is a block diagram showing one embodiment of a refresh counter according to the present invention.

[Explanation of symbols]

MEC: memory card (memory device), MCS: microcomputer system, MPU: microprocessor, PMEM: program memory, DMEM: data memory, CB1 to CB3: control bus, AB1, A
B2: Address bus, DB1, DB2: Data bus, P
CKT: Power supply circuit, CONT: Control circuit, PW
R: power supply control circuit, BAT: battery, RAM: random
Access memory, PSRAM ... Pseudo-static type R
AM, TG: timing generation circuit, XAB: X address buffer, YAB: Y address buffer, PXD: X predecoder, RFC / refresh counter, XR0
~ XR3 ... X system redundant circuit, VCHG ... Boost circuit, PWD
... Word line selection drive signal generation circuit, PRWD. Redundant word line selection drive voltage generation circuit, SN, PN sense amplifier drive circuit, PYD Y predecoder, YRAC0 to YR.
AC7: Y-system redundant circuit, MALL to MARR: Main amplifier, DIB: Data input buffer, DTLL to DIR
R: Write circuit, WS: Write select circuit, DOB ...
Data output buffer, OSL ... output selection circuit, HVC,
VBB, VL ... voltage generation circuit, XDL0L to XD3R ...
X decoder, YD0 to YD3 ... Y decoder, MARY0
L to MARY3R: memory array, SA0L to SA3R
... Sense amplifiers, CS0L to CS3R ... Column switches, LOG1 to LOG3 ... Logic circuits, OC ... Oscillation circuits, LC ... Low temperature limiter circuits, TC ... Timer circuits, NAND1 to NAND3 ... Nand gate circuits, IN
V1 to INV3: inverter circuit, NOR1: NOR gate circuit, AND1: AND gate circuit, Q1 to Q9: M
OSFET, Qm: Address selection MOSFET, N1
... N15: CMOS inverter circuit, DC: Dummy cell, QP, QN: Constant current source MOSFET, DELAY ...
Delay circuit, CT0 to CT12 ... Counter circuit, G1 to G
8: gate circuit, CKG (OSC): pulse generation circuit (oscillation circuit), EX: exclusive OR circuit, VBBC: control voltage generation circuit, VBBG: substrate voltage generation circuit, Cs,
CB1, CB2, C1 to C2 ... capacitors, R, R1 to
R2: resistance, n: N-type diffusion layer region, p: P-type diffusion layer region. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... N-WELL, 4 ... n ⁺ type diffusion layer area, 5 ... Gate insulating film, 6 ... P ⁺ type diffusion layer area, 7 ...
Field insulating film, 8 first polysilicon layer, 9 second polysilicon layer, 10 third polysilicon layer, 1
1: first aluminum layer, 12: contact region,
13 ... ohmic contact region.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/406 G11C 11/4076

Claims (8)

(57) [Claims] 1. A memory array having a plurality of word lines, a plurality of data lines, and a plurality of memory cells each including one MOSFET and one capacitor, and a refresh for refreshing each of the plurality of memory cells. Refresh means for outputting an instruction signal; and control signal forming means for receiving the refresh instruction signal and forming a refresh control signal, wherein the refresh means refreshes at a constant cycle when a refresh mode is instructed. An oscillation circuit that outputs a timing signal and a MOSFET that is formed similarly to the MOSFET that constitutes the memory cell.
And a plurality of MOSs in a parallel form which are constantly turned off.
FETs and the same number of memory cells as the plurality of MOSFETs.
Cell having a capacitance value one order of magnitude smaller than the total capacitance value of the capacitors in the memory cell, and the dummy cell during a refresh operation of the memory cell.
The cell capacitor is connected to the high voltage of the information voltage of the memory cell.
A precharge circuit for precharging to a level, a comparison circuit for comparing a holding voltage held in a capacitor of the dummy cell with a predetermined reference voltage, and a counter for counting the refresh timing signal.
And the memory of the memory array is operated by the count output of the counter.
When the refresh operation of the memory cell is completed, the refresh
Output of the instruction signal and the precharge of the precharge circuit.
Is stopped, and the holding voltage value of the capacitor of the dummy cell becomes
A signal indicating that the voltage has become lower than the
When the comparison circuit outputs, the refresh instruction signal is output.
Output, reset the counter, and
A semiconductor memory for performing a precharge operation of a charge circuit . 2. The device according to claim 1, wherein the counter is configured to reset all memory cells of the memory array.
Perform a predetermined counting operation that exceeds the number of times of freshness
Wherein the holding voltage value of the capacitor is higher than the predetermined reference voltage.
The comparison circuit outputs a signal indicating that
When there is not, the count value of the counter is
Outputs the refresh instruction signal when the value reaches
To reset the counter and
A semiconductor memory for performing a precharge operation of a memory circuit. 3. The semiconductor memory according to claim 2, wherein said counter circuit comprises a plurality of flip-flops. 4. A group of first address terminals according to claim 1, wherein an address for selecting one word line from the plurality of word lines is supplied;
A semiconductor memory having a second address terminal group to which an address for selecting one data line from the plurality of data lines is supplied. 5. A plurality of semiconductor memories coupled by a data bus and an address bus, and a control circuit coupled to the plurality of semiconductor memories via a control bus are mounted on a common mounting board, Each have multiple word lines, multiple data lines and one MO
A memory array having a plurality of memory cells each including an SFET and a capacitor; a refresh unit for outputting a refresh instruction signal for refreshing each of the plurality of memory cells; Control signal forming means for forming a use signal, wherein the refresh means includes an oscillation circuit for outputting a refresh timing signal at a constant cycle when a refresh mode is instructed, and a MOSFET forming the memory cell. Formed
And a plurality of MOSs in a parallel form which are constantly turned off.
FETs and the same number of memory cells as the plurality of MOSFETs.
Cell having a capacitance value one order of magnitude smaller than the total capacitance value of the capacitors in the memory cell, and the dummy cell during a refresh operation of the memory cell.
The cell capacitor is connected to the high voltage of the information voltage of the memory cell.
A precharge circuit for precharging to a level, a comparison circuit for comparing a holding voltage held in a capacitor of the dummy cell with a predetermined reference voltage, and a counter for counting the refresh timing signal.
And the memory of the memory array is operated by the count output of the counter.
When the refresh operation of the memory cell is completed, the refresh
Output of the instruction signal and the precharge of the precharge circuit.
Is stopped, and the holding voltage value of the capacitor of the dummy cell becomes
A signal indicating that the voltage has become lower than the
When the comparison circuit outputs, the refresh instruction signal is output.
Output, reset the counter, and
A precharge operation of the charge circuit.
Semiconductor memory device. 6. The memory device according to claim 5, wherein the counter is configured to reset all memory cells of the memory array.
Perform a predetermined counting operation that exceeds the number of times of freshness
Wherein the holding voltage value of the capacitor is higher than the predetermined reference voltage.
The comparison circuit outputs a signal indicating that
When there is not, the count value of the counter is
Outputs the refresh instruction signal when the value reaches
To reset the counter and
Semiconductor device characterized by performing a precharge operation of the
Body memory device. 7. The semiconductor memory device according to claim 6, wherein said counter circuit comprises a plurality of flip-flops . 8. The first address terminal group according to claim 5, wherein an address for selecting one word line from the plurality of word lines is supplied,
A semiconductor memory device having a second address terminal group to which an address for selecting one data line from the plurality of data lines is supplied .