JP3134913B2 - Switching device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching device using a MOSFET, and more particularly to a switching device using a MOSFET as a switching element of a switching power supply.

[0002]

2. Description of the Related Art In recent years, MOSFs used as switching elements have been used in order to reduce the number of parts of a switching power supply, improve the space factor, or reduce the size and cost.
A switching device in which the ET and its control circuit are incorporated in a semiconductor integrated circuit on the same chip has been put to practical use.

In such a conventional switching device, for example, 20 or more pins are provided as external terminals. Therefore, it is difficult to mount this device on a printed circuit board. Since external parts corresponding to the number of terminals are required, there is a limitation in downsizing. In addition, the cost increases according to the number of external parts.

[0004] In order to solve such a problem, the present applicant has filed a Japanese Patent Application No. 5-218393, entitled "Switching Device Apparatus", in which a switching device in which the above problems are solved is filed. According to this application, the external terminal is composed of three terminals, the drain terminal and the source terminal of the MOSFET, and the power input terminal of the control circuit.
It has features that it can be easily mounted on a printed circuit board and requires few external components. However, the control method of the switching device of this application uses a voltage control method. In the case of the voltage control method, the control system has a second-order delay, and in such a second-order delay control system, the control is very unstable because the phase is inverted by 180 °.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and its purpose is to reduce the number of external terminals to three in the same manner as in the above-mentioned patent application. , And the built-in control circuit is of a current control type. In the current control method, the control system has a first-order delay, and stable control can be performed. Thus, according to the present invention, it is possible to obtain an inexpensive switching device that can be easily mounted on a printed circuit board and has improved reliability.

[0005]

According to the present invention, there is provided a switching device in which a MOSFET used as a switching element and a control circuit thereof are configured as a semiconductor integrated circuit on the same chip, and a current control for controlling ON / OFF of the MOSFET. And a drain terminal and a source terminal of a MOSFET controlled by the control circuit and a power input terminal of the control circuit are external terminals.

[0006]

According to the present invention, the MOSFET is controlled by the current control type control circuit, and the external terminals can be three terminals.

[0007]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a circuit diagram of a switching device according to an embodiment of the present invention. In the figure, reference numeral 10 denotes a package, and a multi-source MOSFET (hereinafter simply referred to as FET) 2 used as a switching element in the package.
0 and a current control type control circuit 3 for controlling this FET.
0 is incorporated as a semiconductor integrated circuit on the same chip. Reference numeral 40 denotes a terminal to which a voltage Vin from the outside is input as a power supply voltage. The package 10 is provided with three terminals: a drain terminal 21 and a source terminal 22 of the FET 20, and a power input terminal 40. That is, it is a three-terminal type package.

In the control circuit 30, 31 is an oscillation circuit,
32 is an OR gate, 32a is an inverter, and 33 is a latch circuit composed of an RS flip-flop. The oscillation circuit 31 generates a pulse (blanking pulse) having a constant period and outputs a sawtooth wave (or a triangular wave) for generating the pulse. The blanking pulse is applied to the OR gate 32 and input to the set terminal S of the latch circuit 33, and the output Q of the latch circuit 33 is applied to the OR gate 32. 34 is a power input terminal 4
A reference voltage generation circuit that receives the voltage Vin applied from 0 to generate a reference voltage Vr, 35 is a low voltage detection circuit that detects a case where the voltage Vin is lower than the reference value, and 36 is Vi.
a high-voltage detection circuit that detects when n is higher than a predetermined value;
The reference voltages of both detection circuits are both obtained from the reference voltage generation circuit 34. 36a is a switch, and 36b is a voltage dividing resistor. A power supply voltage Vin obtained through a switch 36a is divided by a voltage dividing resistor 36b and applied to the high voltage detecting circuit 36.

Reference numeral 37 denotes an abnormal heating detection circuit for detecting an abnormal temperature rise for chip protection.
And the outputs of the high voltage detection circuits 35 and 36 are added to the above-mentioned OR gate 32. The output of the OR gate 32 is applied to the gate electrode of the FET 20 via the inverter 32a.

38 is an error amplifier, 38a is a switch, 3
8b is a voltage dividing resistor. The error amplifier 38 has a switch 3
The voltage Vin applied from the power supply input terminal 40 obtained through the voltage divider 8a is divided by a voltage dividing resistor 38b and applied.
The error amplifier 38 compares the divided voltage with a reference value Vr,
The difference is amplified and output. This reference voltage Vr is also obtained from the reference voltage generation circuit 34 described above. The switch 38a and the switch 36a are both driven by the output of the low voltage detection circuit 35.

Reference numeral 39 denotes a current detection comparator for comparing the current proportional to the source current detected from the multi-source of the FET 20 with the output of the error amplifier 38. The output of the error amplifier 38 is applied to its inverting input terminal. I have. FET2 detected by the resistor 23 is connected to the non-inverting input terminal.
A voltage proportional to a source current of 0 is converted into a current and applied, and a saw-tooth wave output from the oscillation circuit 31 is applied as a bias. The output of this comparator is connected to the reset terminal R of the latch circuit 33. The reason why the sawtooth wave obtained from the oscillation circuit 31 is superimposed is to correct the system so that it does not become unstable when the duty becomes 50% or more. 39a is a constant voltage element for limiting the maximum value of the voltage applied to the inverting input terminal of the current detection comparator 39.
Is limited to the maximum value of the drain current.

The operation of the switching device according to the present invention shown in FIG. 1 will be described below with reference to the waveform diagram of FIG. FIG. 3 is a truth table of the latch circuit 33 used in FIG.

The voltage Vi input from the power input terminal 40
n is applied as a power supply voltage to each circuit constituting the control circuit 30 as described above, and as a result, the reference voltage generation circuit 34 generates the reference voltage Vr. In this case, the input voltage Vin gradually increases from the time when the power is turned on, and the switches 36a and 38a are turned off while the value is lower than the starting voltage determined by the reference value Vr of the low voltage detection circuit 35. Is reached, both switches are turned on by the output of the low voltage detection circuit 35, whereby the entire control circuit is brought into an operating state.

When the control circuit 30 is activated, the oscillation circuit 31
Outputs a sawtooth wave shown in FIG. 2 (a) and generates a blanking pulse having a constant period shown in FIG. 2 (b) obtained by the sawtooth wave. The sawtooth signal is applied to the non-inverting input terminal of the current detection comparator 39, and the blanking pulse is applied to the input terminal of the OR gate 32 and the set terminal S of the latch circuit 32. On the other hand, when the switch 38a is turned on, the input voltage Vin is applied to the voltage dividing circuit 38a via this switch and divided. This divided voltage is compared with the reference value Vr by the error amplifier 38,
The difference is amplified and applied to the inverting input terminal of the current detection comparator 39 as a threshold current Ith. The level of this threshold current is represented by Ith in FIG.
1 to Ith3. Ith1 indicates a case where the difference between the divided voltage of the voltage dividing circuit 38a and the reference value Vr is small, and Ith3 indicates a case where the difference is large.

Here, the FET 2 detected by the resistor 21
The waveform of the source current of 0 is shown in FIG. This detection current rises at the fall of the blanking pulse shown in FIG. For example, when the blanking pulse falls at the time t1, the detection current (source current) rises, and the current gradually increases. When the value reaches the threshold current Ith1 at the time t2, the current detection comparator 39 sets the current detection comparator 39 in FIG. This is detected as shown in (c). This detection output is applied to the reset terminal R of the latch circuit 33. The detection current is the threshold current It
The output Q bar of the latch circuit 33 is at the low level as shown in FIG. 2D during the period from t1 to t2 when the output does not reach the threshold value h1, but when the threshold current Ith1 is reached at the time t2, the Q bar output becomes the high level. Become. This high-level output becomes low at the rise of the next blanking pulse.

When the level of the input to the OR gate 32 is all low, the output of the OR gate 32 becomes a low level as shown in FIG.
The signal is inverted by 2a as shown in FIG. 2 (f), and the high level signal is applied to the gate of the FET 20. F
The ET 20 is turned on while the output of the inverter 32a applied to this gate is at a high level. That is, the FET 20 is turned on during the period from t1 to t2 in FIG.
During the period from t2 to t3, the signal level applied to the gate of the FET 20 is low, and as a result, the FET 20 is off.

When the next blanking pulse falls at time t3, the detection current shown in FIG. 2 (g) rises. In this case, the value of the power supply voltage Vin changes from time t1 to t3.
And the threshold current of the current detection comparator 39 becomes Ith2 as a result, the output of the error amplifier 38 becomes large and the detection current becomes Ith2.
, The Q-bar output of the latch circuit 33 does not go high. That is, the period from t3 to t4 when the Q bar output of the latch circuit 33 is low is longer than the period from t1 to t2, and the FET 20 is on during the period from t3 to t4. Further, the power supply voltage V starts from time t3 to time t5.
When the value of in is small and the threshold current of the current detection comparator 39 is Ith3, as shown by periods t5 to t6, t3 to t6
The FET 20 is on for longer than the period of t4. Thus, the voltage V applied to the power input terminal 40 is
in and the reference value Vr, if there is a difference,
The value of the input voltage Vin is controlled so that the on-time of T20 is controlled so that the detected current becomes a constant value.

In addition to the blanking pulse, a low voltage detection circuit 35 for detecting the case where the voltage Vin is lower than the reference value Vr, a high voltage detection circuit 36 for detecting when the voltage Vin becomes higher than the reference value, and a circuit are provided. The outputs of the abnormal heating detection circuit 37 for detecting abnormal heating are applied to the OR gate 32, respectively. When at least one of the outputs of these circuits goes high, the output of the OR gate 32 goes high, which is inverted by the inverter 32a and applied to the gate of the FET 20. As a result, the FET 20 is turned off.

As described above, in the present invention, there are three external terminals, and the built-in control circuit is configured as a current control system. As a result, the control system has a first-order delay, and a switching device capable of performing very stable control can be obtained.

FIG. 4 is a circuit diagram of an example of a switching power supply constructed using the device shown in FIG. 1 according to the present invention. In FIG. 4, reference numeral 10 denotes the package described with reference to FIG.
0 and a current control type control circuit 3 for controlling this FET.
0 is incorporated as a semiconductor integrated circuit on the same chip. Reference numeral 40 denotes a power input terminal. As described with reference to FIG. 1, the power supply input terminal 40 and the FET 20
And a drain terminal D and a source terminal S.

Reference numeral 50 denotes a commercial power supply input terminal, and 60 denotes a transformer, which comprises a primary winding 61, a secondary winding 62, and a bias winding 63.
Is made up of 51 is a full-wave rectifier circuit for full-wave rectification of the commercial power supply voltage, and 52 is a smoothing circuit. The output terminal of the rectified and smoothed commercial power supply voltage is connected to the power supply input terminal 40 of the package 10 via the starting resistor 53 and is applied to the drain terminal D of the FET 20 via the primary winding 61 of the transformer 60. I have. 62a and 63a are diodes, 62b and 63b are capacitors, respectively.
2a and the capacitor 62b are connected to the secondary winding 62 of the transformer 60.
The diode 63a and the capacitor 63b rectify and smooth the voltage induced in the bias winding 63. The DC voltage obtained from the bias winding 62 is applied to the power input terminal 40.

The AC voltage applied to the commercial power supply input terminal 50 is converted into a DC voltage by a full-wave rectifier circuit 51 and a smoothing circuit 52, and the DC voltage is applied to a primary winding 61 of a transformer 60 and used for starting. The power supply voltage Vin is applied to the control circuit 30 from the power supply input terminal 40 via the resistor 53, whereby the control circuit 30 is connected to the control circuit 30 as described with reference to FIG.
Starts. FET2 is connected to the primary winding 61 of the transformer 60.
A drain / source terminal DS of 0 is connected in series, and a current flowing through this source terminal S is detected by a resistor 21. As described with reference to FIG. 1, the ON time of the FET 20 is controlled so that the value of the detection current becomes constant. FE
When T20 is turned on and off, the current flowing through the primary winding 61 of the transformer 60 is turned on and off. Thereby, the secondary winding 62 and the bias winding 63 of the transformer 60 are formed.
, And rectified and smoothed by diodes 62a and 63a and capacitors 62b and 63b, respectively. The DC voltage obtained from the secondary winding 62 is taken out as an output voltage OUT, and the DC voltage obtained from the bias winding 63 is applied to the power supply input terminal 40 as the power supply voltage Vin.

The power supply voltage Vin is divided by the voltage dividing resistor 38b as described with reference to FIG. The divided voltage is compared with the reference value Vr in the error amplifier 38, and the power supply voltage Vin applied to the terminal 40 so that the difference becomes small, that is, the source current of the FET 20 flowing through the detection resistor 21 becomes constant. Is controlled to a constant value. In this case, since the value of the voltage Vin when the voltage is controlled to a constant value is substantially equal to the voltage generated in the bias winding 63 of the transformer 60, the turns ratio between the bias winding 63 and the secondary winding 62 must be set appropriately. Accordingly, a desired DC voltage OUT can be obtained from the rectifying and smoothing circuit of the secondary winding 62. As described above, in the power supply of FIG. 4 using the present invention, a DC voltage which is insulated from the commercial power supply and converted to a desired value can be obtained.

The voltage Vin is applied to the power input terminal 40 of the control circuit 30 via the starting resistor 53 shown in FIG. 4. In this case, as described with reference to FIG.
Are lower than the starting voltage, the switches 36a and 38a are off. When Vin reaches the start-up voltage, the output of the low-voltage malfunction prevention circuit 35 becomes high level, whereby the switches 36a and 38a are closed, and at the same time the entire circuit starts operating. That is, since the switch is in an open state below the starting voltage, no current flows through the voltage dividing resistors 36b and 38b.

As described above, in the present invention shown in FIG. 1, the switches 36a and 38a are used for detecting the power supply voltage Vin.
By providing a, the input current before the start of activation of the device can be reduced. This makes it possible to use a high resistance value for the starting resistor 53 shown in FIG. 4, and reduce the starting resistance loss. For example,
When the switches 36a and 38a are not provided, the current before the start of the start requires approximately 1 mA, and the start resistor 53 at that time is 1 mA.
00KΩ. In this case, the loss of the starting resistor 53 is 1.
6W. On the other hand, when the switch is provided, the current before the start of startup is approximately 0.1 mA, the value of the startup resistor 53 is 300 KΩ, and the loss at this time is reduced to 0.53 W.
That is, by providing the switches 36a and 38a,
The loss is reduced by a factor of three.

[0026]

According to the present invention, the external terminal is realized by three switching devices in the same manner as the content of the previously filed application, and the built-in control circuit is of the current control type, so that the control system is delayed by the first order. Thus, a very stable device can be realized. As a result, according to the present invention, an inexpensive switching device that can be easily mounted on a printed circuit board and has improved reliability can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a device according to the present invention.

FIG. 2 is a waveform chart for explaining the operation of FIG.

FIG. 3 is a truth table of the latch circuit used in FIG. 1;

FIG. 4 is a configuration diagram of an example of a switching power supply configured using the device of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Package 20 MOSFET 30 Current control circuit 31 Oscillation circuit 32 OR gate 33 Latch circuit 36a Switch 38 Error amplifier 38a Switch 39 Current detection comparator 40 Power input terminal 50 Commercial voltage input terminal 60 Transformer

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-2-211062 (JP, A) JP-A-3-145919 (JP, A) JP-A-4-142468 (JP, A) JP-A-63- 146614 (JP, A) JP-A-4-167813 (JP, A) JP-A-7-74315 (JP, A) JP-A-6-61432 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 17/00-17/70

Claims (2)

(57) [Claims] 1. A MOS used as a switching element
In a switching device in which an FET and its control circuit are configured as a semiconductor integrated circuit on the same chip, a voltage applied from a power input terminal is compared with a reference voltage, a current corresponding to the difference is set as a threshold current, and the threshold current is switched A current detection comparator for comparing a current corresponding to a current flowing to a source terminal of a MOSFET used as an element, an oscillation circuit for generating a pulse having a constant period, a gate to which an output of the oscillation circuit is added, An output is applied to the set terminal, and a reset circuit is provided with a latch circuit to which the output of the current detection comparator is applied and the output is applied to the gate. The output of the gate controls on / off of the MOSFET. Equipped with a current-controlled control circuit,
A switching device, wherein a drain terminal and a source terminal of the MOSFET and a power input terminal of a control circuit are external terminals. 2. A power supply voltage applied from the power input terminal is supplied to the voltage divider circuit via a switch, according to claim 1, wherein which is adapted to compare the voltage divided with the reference voltage at the voltage dividing circuit Switching device.